CN101154468A - Test method for embedded memory chip - Google Patents
Test method for embedded memory chip Download PDFInfo
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- CN101154468A CN101154468A CNA2006101165613A CN200610116561A CN101154468A CN 101154468 A CN101154468 A CN 101154468A CN A2006101165613 A CNA2006101165613 A CN A2006101165613A CN 200610116561 A CN200610116561 A CN 200610116561A CN 101154468 A CN101154468 A CN 101154468A
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Abstract
The invention discloses a test method for embedded memory chip, including the following steps: firstly, a primary test on chips is completed; secondly, the chips which are tested normal by the primary test and have eligible test results are written in with value different from the original numerical value in a memory, while other chips maintain the original value; thirdly, the chips which pass the test are excluded from a retest list and retest on other chips is completed; fourthly, the chips which are tested normal by the retest and have eligible test results are written in with value different from the original numerical value in a memory, while other chips maintain the original value. Through writing in specific value into the chips which are tested normal by the primary test and have eligible test results and reserving the test results of the normal chips, the invention avoids another test abnormity caused by retest; moreover, the invention saves test cost and improves production efficiency.
Description
Technical field
The present invention relates to a kind of integrated circuit chips field tests, especially a kind of test method for embedded memory chip.
Background technology
In the process of test chip,, must test again unusual chip in this case because the fault of test macro as tester fault, probe damage etc., can cause some chip testing results abnormity in the silicon chip.But, can only test again the chip of all tests in the silicon chip because present as broad as long test is normal or the method for unusual chip.
In this case, the method for testing of prior art can consume a lot of manpowers and time, causes the increase of production cost.
Summary of the invention
Technical matters to be solved by this invention provides a kind of test method for embedded memory chip, can distinguishing tests unusual chip and the normal chip of test, thereby when testing again,, reduce time and cost of labor that test is consumed as long as carry out repetition measurement to testing unusual chip.
For solving the problems of the technologies described above, the technical scheme that test method for embedded memory chip of the present invention adopted is may further comprise the steps: the first step, embedded memory chip is tested for the first time; Second step, judge The tested results, normal and test result is that the obsolete zone of client writes the value that is different from original numerical value in the storer in the embedded memory of qualified chip to preliminary test, and undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to preliminary test; In the 3rd step, read the value of embedded memory chip relevant position in the first step by tester, if this value then eliminates this chip the repetition measurement tabulation for the specific value that writes, if this value is not then carried out repetition measurement to this chip for the specific value that writes; The 4th step; normal and test result is that the obsolete zone of client writes the value that is different from original numerical value in the storer in the embedded memory of qualified chip to repetition measurement, and undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to repetition measurement.
The present invention writes specific value in the embedded memory of qualified chip, thereby reach the purpose of normal chip of differentiating measurement and the unusual chip of test, when repetition measurement, only need test testing unusual chip, reduce the needed time of test, reduce cost, enhance productivity.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is a schematic flow sheet of the present invention;
Fig. 2 is the hardware testing system structural representation;
Fig. 3 is that the chip under test of different test results changes synoptic diagram at the test background storage.
Embodiment
As shown in Figure 1, test method for embedded memory chip of the present invention may further comprise the steps: the first step, embedded memory chip is tested for the first time.As shown in Figure 2, the used hardware testing system of test comprises that the large-scale logic tester 50, automatic prober platform 30 that test macro is carried out whole control fixedly test by application specific probe card 10 and 40 pairs of chips of measuring head.Second step, as shown in Figure 3, judge The tested results, normal and test result is that the obsolete zone of client writes the value that is different from original numerical value in the storer in the embedded memory of qualified chip to preliminary test, as writing sexadecimal number 5a5a, undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to preliminary test; The 3rd step, read the value of embedded memory chip relevant position in the first step by tester, read 5a5a and successfully show the first test passes of this chip, then in the repetition measurement tabulation, reject this chip automatically, carry out repetition measurement for those chips that read the 5a5a failure; In the 4th step, normal and test result is that the obsolete zone of client writes 5a5a in the embedded memory of qualified chip to repetition measurement, and undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to repetition measurement.If also exist unusually in the repetition measurement process, then repeat the step in the 3rd step and the 4th step, normal up to all chip testings.
The present invention writes specific value in the embedded memory of qualified chip, the test result of testing normal chip is kept, no longer test, only to unusual chip repetition measurement, another time test of having avoided repetition measurement to cause is unusual.Utilize the inventive method not only can measure unusual chip, and can avoid the repeated test in the test process, save production cost, enhance productivity.
Claims (3)
1. a test method for embedded memory chip is characterized in that, may further comprise the steps: the first step, embedded memory chip is tested for the first time; Second step, judge The tested results, normal and test result is that the obsolete zone of client writes the value that is different from original numerical value in the storer in the embedded memory of qualified chip to preliminary test, and undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to preliminary test; In the 3rd step, read the value of embedded memory chip relevant position in the first step by tester, if this value then eliminates this chip the repetition measurement tabulation for the specific value that writes, if this value is not then carried out repetition measurement to this chip for the specific value that writes; The 4th step; normal and test result is that the obsolete zone of client writes the value that is different from original numerical value in the storer in the embedded memory of qualified chip to repetition measurement, and undesired or test result keeps original value for relevant position in the embedded memory of the chip that lost efficacy to repetition measurement.
2. test method for embedded memory chip as claimed in claim 1 is characterized in that, increases following steps after the 4th step: repeated for the 3rd step and the 4th step.
3. test method for embedded memory chip as claimed in claim 1 is characterized in that, in second step and the 4th step, test normally and test result be that the value that writes in the qualified chip embedded memory is sexadecimal number 5a5a.
Priority Applications (1)
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CNA2006101165613A CN101154468A (en) | 2006-09-27 | 2006-09-27 | Test method for embedded memory chip |
Applications Claiming Priority (1)
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CNA2006101165613A CN101154468A (en) | 2006-09-27 | 2006-09-27 | Test method for embedded memory chip |
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CN101154468A true CN101154468A (en) | 2008-04-02 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102116837A (en) * | 2010-12-27 | 2011-07-06 | 东莞易步机器人有限公司 | Method for secondarily and fully testing PCBA (Printed Circuit Board Assembly) |
CN104635138A (en) * | 2013-11-12 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Method for retesting integrated chips with memory units |
CN105676105A (en) * | 2014-11-19 | 2016-06-15 | 比亚迪股份有限公司 | Chip test method and chip test machine |
CN106443415A (en) * | 2016-11-03 | 2017-02-22 | 上海华虹集成电路有限责任公司 | Retesting method for integrated chip with storage unit |
CN113436670A (en) * | 2020-03-23 | 2021-09-24 | 美商矽成积体电路股份有限公司 | Memory detection method and memory detection system |
CN115314418A (en) * | 2022-08-12 | 2022-11-08 | 紫光展讯通信(惠州)有限公司 | Test method, device, equipment and storage medium |
-
2006
- 2006-09-27 CN CNA2006101165613A patent/CN101154468A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102116837A (en) * | 2010-12-27 | 2011-07-06 | 东莞易步机器人有限公司 | Method for secondarily and fully testing PCBA (Printed Circuit Board Assembly) |
CN104635138A (en) * | 2013-11-12 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Method for retesting integrated chips with memory units |
CN104635138B (en) * | 2013-11-12 | 2017-07-04 | 上海华虹集成电路有限责任公司 | The repetition measurement method of the integrated chip with memory cell |
CN105676105A (en) * | 2014-11-19 | 2016-06-15 | 比亚迪股份有限公司 | Chip test method and chip test machine |
CN106443415A (en) * | 2016-11-03 | 2017-02-22 | 上海华虹集成电路有限责任公司 | Retesting method for integrated chip with storage unit |
CN113436670A (en) * | 2020-03-23 | 2021-09-24 | 美商矽成积体电路股份有限公司 | Memory detection method and memory detection system |
CN113436670B (en) * | 2020-03-23 | 2024-03-26 | 美商矽成积体电路股份有限公司 | Memory detection method and memory detection system |
CN115314418A (en) * | 2022-08-12 | 2022-11-08 | 紫光展讯通信(惠州)有限公司 | Test method, device, equipment and storage medium |
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Open date: 20080402 |