CN109710472A - Memory automatic test and stage division - Google Patents
Memory automatic test and stage division Download PDFInfo
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- CN109710472A CN109710472A CN201811549868.1A CN201811549868A CN109710472A CN 109710472 A CN109710472 A CN 109710472A CN 201811549868 A CN201811549868 A CN 201811549868A CN 109710472 A CN109710472 A CN 109710472A
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Abstract
The present invention provides a kind of memory automatic test and stage division.The described method includes: measuring the memory parameters boundary value of memory to be tested using the Shmoo tool in memory test instrument；Influence according to the memory parameters to the internal memory performance to be tested makes multiple test templates, wherein the corresponding internal memory performance grade of each test template；The memory to be tested is successively passed through to the test of the multiple test template, to realize automatic test and the classification of the memory to be tested.The present invention can be improved the accuracy of memory test efficiency and failure memory positioning, and can be realized the automation of memory grade separation more accurately to be judged memory quality.
Description
Technical field
The present invention relates to memory test technical field more particularly to a kind of memory automatic tests and stage division.
Background technique
Memory is one of the ost important components in computer, it is the bridge linked up with CPU.With flying for information technology
Speed development, the online datas such as social networks, information retrieval and e-commerce intensive applications become the hot spot of research gradually, this
More stringent requirements are proposed for access performance (bandwidth, delay etc.) of a little applications to data.Along with information technology development in pluralism
It is commonly used with computer technology, the demand of every field also towards development in pluralism, how to be accurately positioned failure memory with
And deposit into row classification internally to meet the needs of different industries, become current problem to be solved.
Currently, memory detection technique mainly includes test method based on automated test device and carries out in the server
The test method of pressure test.Since the working principle of memory is complex, it is logical that a memory is tested with automated test device
It often needs in certain sequence to test each technical parameter repeatedly according to specific fault model repeatedly to obtain test template, so
Afterwards capable test is internally deposited into according to test template again, filters out failure memory.It can be seen that there is consumption in this internal storage testing method
Time-consuming length, low efficiency, the defect of fault location inaccuracy.When carrying out pressure test in the server, due to being deposited in the presence of part
Storing up space can be by the driving reserved space and test program of basic input-output system BIOS, operating system OS and carry equipment
Itself is occupied and leads to not be tested, and causes potential quality risk, and consuming time is long for test, code maintenance needs
More manpowers are put into, testing efficiency is low.In addition, existing internal storage testing method, which also lacks, internally deposits into row quality grading
Effective means.
Summary of the invention
Memory automatic test and stage division provided by the invention, can be improved memory test efficiency and failure memory
The accuracy of positioning, and can be realized the automation of memory grade separation more accurately to be judged memory quality.
The present invention provides a kind of memory automatic test and stage division, comprising:
The memory parameters boundary value of memory to be tested is measured using the Shmoo tool in memory test instrument；
Influence according to the memory parameters to the internal memory performance to be tested makes multiple test templates, wherein each
Test template corresponds to an internal memory performance grade；
The memory to be tested is successively passed through to the test of the multiple test template, to realize the memory to be tested
Automatic test and classification.
Optionally, the memory parameters include that delay time CL, the row address of column address strobe are transferred to column address
Delay time tRCD, the precharge time tRP of row address strobe, memory refresh order time interval Refresh
Time, static waiting time Delay write recovery delay seven tWR, row refresh cycle time tRFC time sequence parameters.
Optionally, the multiple test template includes the first test template, the second test module, third test template and the
Four test templates；
Wherein, first test template is that all memory parameters are all satisfied JEDEC standard；
Second test template is that Refresh Time, Delay and tWR are set as most stringent, remaining memory parameters is equal
Meet JEDEC standard；
The third test template is Refresh Time, Delay, tWR, CL, tRCD and tRP are set as most stringent,
Remaining memory parameters are all satisfied JEDEC standard；
The 4th group of test template is that all memory parameters are set as most stringent.
Optionally, described successively to include: by the test of the multiple test template by the memory to be tested
The memory to be tested is tested using first test template, if the memory to be tested does not meet
First test template, then determine it is described it is to be tested in save as failure memory, otherwise using second test template to institute
Memory to be tested is stated to carry out continuing to test；
If the memory to be tested does not meet second test template, determine it is described it is to be tested in save as non-faulting
Robustness is general in memory, otherwise carries out continuing to test to the memory to be tested using the third test template；
If the memory to be tested does not meet the third test template, determine it is described it is to be tested in save as non-faulting
Memory and memory robustness is medium, otherwise carries out continuing to test using the 4th test template to the memory to be tested；
If the memory to be tested does not meet the 4th test template, determine it is described it is to be tested in save as non-faulting
Memory and memory robustness is good, otherwise determine it is described it is to be measured in save as non-faulting memory and memory robustness is outstanding.
Memory automatic test and stage division provided in an embodiment of the present invention, which comprises utilize memory test
Shmoo tool in instrument measures the memory parameters boundary value of memory to be tested；According to the memory parameters to described to be tested
The influence of internal memory performance makes multiple test templates, wherein the corresponding internal memory performance grade of each test template；It will be described
Memory to be tested successively passes through the test of the multiple test template, to realize the automatic test of the memory to be tested and divide
Grade.Compared with prior art, the present invention can be improved the accuracy of memory test efficiency and failure memory positioning, and can
Realize the automation of memory grade separation more accurately to be judged memory quality.
Detailed description of the invention
Fig. 1 is the flow chart of one embodiment of the invention memory automatic test and stage division.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The present invention provides a kind of memory automatic test and stage division, as shown in Figure 1, which comprises
S11, the memory parameters boundary value that memory to be tested is measured using the Shmoo tool in memory test instrument.
S12, the influence according to the memory parameters to the internal memory performance to be tested make multiple test templates, wherein often
The corresponding internal memory performance grade of one test template；
S13, the test that the memory to be tested is successively passed through to the multiple test template, it is described to be tested interior to realize
The automatic test deposited and classification.
Memory automatic test and stage division provided in an embodiment of the present invention, which comprises utilize memory test
Shmoo tool in instrument measures the memory parameters boundary value of memory to be tested；According to the memory parameters to described to be tested
The influence of internal memory performance makes multiple test templates, wherein the corresponding internal memory performance grade of each test template；It will be described
Memory to be tested successively passes through the test of the multiple test template, to realize the automatic test of the memory to be tested and divide
Grade.Compared with prior art, the present invention can be improved the accuracy of memory test efficiency and failure memory positioning, and can
Realize the automation of memory grade separation more accurately to be judged memory quality.
Optionally, the memory parameters include that delay time CL, the row address of column address strobe are transferred to column address
Delay time tRCD, the precharge time tRP of row address strobe, memory refresh order time interval Refresh
Time, static waiting time Delay write recovery delay seven tWR, row refresh cycle time tRFC time sequence parameters.
Optionally, the multiple test template includes the first test template, the second test module, third test template and the
Four test templates；
Wherein, first test template is that all memory parameters are all satisfied JEDEC standard；
Second test template is that Refresh Time, Delay and tWR are set as most stringent, remaining memory parameters is equal
Meet JEDEC standard；
The third test template is Refresh Time, Delay, tWR, CL, tRCD and tRP are set as most stringent,
Remaining memory parameters are all satisfied JEDEC standard；
The 4th group of test template is that all memory parameters are set as most stringent.
Specifically, the step S13 is specifically included:
The memory to be tested is tested using first test template, if the memory to be tested does not meet
First test template, then determine it is described it is to be tested in save as failure memory, otherwise using second test template to institute
Memory to be tested is stated to carry out continuing to test；
If the memory to be tested does not meet second test template, determine it is described it is to be tested in save as non-faulting
Robustness is general in memory, otherwise carries out continuing to test to the memory to be tested using the third test template；
If the memory to be tested does not meet the third test template, determine it is described it is to be tested in save as non-faulting
Memory and memory robustness is medium, otherwise carries out continuing to test using the 4th test template to the memory to be tested；
If the memory to be tested does not meet the 4th test template, determine it is described it is to be tested in save as non-faulting
Memory and memory robustness is good, otherwise determine it is described it is to be measured in save as non-faulting memory and memory robustness is outstanding.
Here of the invention based on interior to illustrate for choosing 25 M393A4K0CB1-CRC DDR4 32G memories of Samsung
Deposit the memory automatic test and stage division of tester instrument, wherein test is by adjusting March C algorithm and Data
What the time sequence parameter in Retention algorithm was realized, specific experiment data are as follows:
Experimental data shows: by adjusting different parameters, the percent of pass of memory is also different, and tRFC is between 370 to 380
It is most sensitive to the influence of memory when variation, it may be implemented internally to deposit effective classification.
Experimental summary:
Adjust three timing core parameter CL, tRCD, tRP, percent of pass 80%；
Three timing core parameter CL, tRCD, tRP and Refresh Time, Delay, tWR are adjusted, percent of pass is
70%；
Adjust three timing core parameter CL, tRCD, tRP, Refresh Time, Delay, tWR and tRFC (370~
380), percent of pass is 0%~60%.
Through the invention, it not only can effectively detect that memory can also be carried out grade according to stability by failure memory
Classification, wants more acurrate to memory " good " and the judge of " bad " than before, avoids the general memory applications of some qualities to surely
The case where qualitative requirement high occasion, server failure rate after sale can also be further decreased；Resource is more saved, meeting can
Sustainable development strategy.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (4)
1. a kind of memory automatic test and stage division characterized by comprising
The memory parameters boundary value of memory to be tested is measured using the Shmoo tool in memory test instrument；
Influence according to the memory parameters to the internal memory performance to be tested makes multiple test templates, and wherein each is tested
Template corresponds to an internal memory performance grade；
The memory to be tested is successively passed through to the test of the multiple test template, to realize the automatic of the memory to be tested
Change test and classification.
2. the method according to claim 1, wherein the memory parameters include the delay of column address strobe
Time CL, row address are transferred to the delay time tRCD of column address, the precharge time tRP of row address strobe, memory brush
Time interval Refresh Time of newer command, static waiting time Delay write recovery delay tWR, row refresh cycle time
Seven time sequence parameters of tRFC.
3. the method according to claim 1, wherein the multiple test template includes the first test template, the
Two test modules, third test template and the 4th test template；
Wherein, first test template is that all memory parameters are all satisfied JEDEC standard；
Second test template is that Refresh Time, Delay and tWR are set as most stringent, remaining memory parameters is all satisfied
JEDEC standard；
The third test template is that Refresh Time, Delay, tWR, CL, tRCD and tRP are set as most stringent, in remaining
It deposits parameter and is all satisfied JEDEC standard；
The 4th group of test template is that all memory parameters are set as most stringent.
4. according to the method described in claim 3, it is characterized in that, it is described the memory to be tested is successively passed through it is the multiple
The test of test template includes:
The memory to be tested is tested using first test template, if the memory to be tested do not meet it is described
First test template, then determine it is described it is to be tested in save as failure memory, otherwise using second test template to it is described to
Test memory carries out continuing to test；
If the memory to be tested does not meet second test template, determine it is described it is to be tested in save as non-faulting memory
Interior robustness is general, otherwise carries out continuing to test to the memory to be tested using the third test template；
If the memory to be tested does not meet the third test template, determine it is described it is to be tested in save as non-faulting memory
And memory robustness is medium, otherwise carries out continuing to test to the memory to be tested using the 4th test template；
If the memory to be tested does not meet the 4th test template, determine it is described it is to be tested in save as non-faulting memory
And memory robustness is good, otherwise determine it is described it is to be measured in save as non-faulting memory and memory robustness is outstanding.
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| CN111367732A (en) * | 2020-02-23 | 2020-07-03 | 苏州浪潮智能科技有限公司 | Memory application grade prediction method, system, terminal and storage medium |
| CN112700817A (en) * | 2021-01-18 | 2021-04-23 | 皇虎测试科技(深圳)有限公司 | Memory device quality evaluation method and device and computer readable storage medium |
| CN112908400A (en) * | 2021-02-19 | 2021-06-04 | 山东英信计算机技术有限公司 | Method, device and equipment for testing double-rate synchronous dynamic random access memory |
| CN113129995A (en) * | 2021-04-14 | 2021-07-16 | 锐捷网络股份有限公司 | EEPROM performance grade testing method, device, electronic equipment and medium |
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Application publication date: 20190503 |