CN113129995A

CN113129995A - EEPROM performance grade testing method, device, electronic equipment and medium

Info

Publication number: CN113129995A
Application number: CN202110402079.0A
Authority: CN
Inventors: 林纬坤
Original assignee: Ruijie Networks Co Ltd
Current assignee: Ruijie Networks Co Ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2021-07-16
Anticipated expiration: 2041-04-14
Also published as: CN113129995B

Abstract

The embodiment of the invention provides a method and a device for testing EEPROM performance levels, electronic equipment and a medium. The method comprises the following steps: selecting M sample EEPROMs from N EEPROMs to be tested; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the plurality of test templates, and determining the performance grade corresponding to each EEPROM to be tested. The method for testing the performance grade of the EEPROM provided by the embodiment of the invention realizes the automatic test and grading of the EEPROM to be tested, saves the automatic test resources and is easy to realize, transplant and popularize.

Description

EEPROM performance grade testing method, device, electronic equipment and medium

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a method and a device for testing EEPROM performance grade, electronic equipment and a medium.

Background

An Electrically Erasable Programmable Read-Only Memory (EEPROM) is a Memory chip with no data loss after power failure, and plays an important role in the field of storage. The method reasonably and accurately positions the failure EEPROM and grades the EEPROM performance, thereby meeting the requirement of using a high-performance and high-reliability storage chip by a user and becoming the problem to be solved at present.

For the problem of EEPROM performance test, there is no accurate and uniform test method at present, and the main processing method is to test the maximum frequency read-write performance test of the EEPROM under the condition that the EEPROM meets the specification indexes and the critical values VCCMIN and VCCMAX of the power supply Voltage (VCC). However, the test vector of the test scheme is too single to effectively distinguish the application requirements of the EEPROM in different scenes.

Disclosure of Invention

Aiming at the defects in the prior art, the embodiment of the invention provides an EEPROM performance grade testing method, an EEPROM performance grade testing device, electronic equipment and a medium.

In a first aspect, an embodiment of the present invention provides a method for testing an EEPROM performance level, including:

selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N;

testing each test parameter of the M sample EEPROMs through reading and writing data;

determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different;

and sequentially inputting the N EEPROMs to be tested into the at least three test templates, and determining the performance grade corresponding to each EEPROM to be tested.

As above, optionally, the testing the test parameters of the M sample EEPROMs by reading and writing data includes:

and sequentially adjusting each test parameter by using a test tool, and determining critical value sample data of each test parameter and the average highest interface frequency of the M sample EEPROMs corresponding to each test parameter by taking the interface frequency of each sample EEPROM in the M sample EEPROMs as the highest value and the read-write data test as the critical judgment basis.

As in the above method, optionally, the determining, according to the test result, the L basic parameter vectors with the maximum sensitivity from the test parameters includes:

determining P test parameters which have the greatest influence on the interface frequency according to the critical value sample data and the corresponding average highest interface frequency;

and selecting L test parameters from the P test parameters as L basic parameter vectors, wherein the L test parameters meet preset adjustment conditions, and P is larger than L.

As above, optionally, constructing a plurality of test templates according to the L basic parameter vectors includes:

determining critical values corresponding to the L basic parameter vectors and a first read-write test method according to an EEPROM parameter manual to obtain a first test template;

determining a critical value outlier parameter line according to the critical value sample data, determining values of L basic parameter vectors according to the critical value outlier parameter line, and obtaining a second test template according to the values of the L basic parameter vectors and a second read-write test method;

and determining values of the L basic parameter vectors according to the conversion relation between the critical value of each of the P minus L test parameters and the L basic parameter vectors, and obtaining at least one third test template according to the values of the L basic parameter vectors and a third read-write test method.

As for the method, optionally, the sequentially inputting the N EEPROMs to be tested into the plurality of test templates, and determining the performance level corresponding to each EEPROM to be tested includes:

inputting the EEPROMs to be tested into the first test template aiming at each EEPROM to be tested in the N EEPROMs to be tested, and determining that the performance grade corresponding to the EEPROM to be tested is unqualified if the test is not passed;

otherwise, inputting the EEPROM to be tested into the second test template, and if the EEPROM does not pass the second test template, determining that the performance grade corresponding to the EEPROM to be tested is qualified;

otherwise, inputting the EEPROM to be tested into the third test template, and if the EEPROM does not pass the third test template, determining that the performance grade corresponding to the EEPROM to be tested is good;

otherwise, determining the performance grade corresponding to the EEPROM to be tested to be excellent.

In a second aspect, an embodiment of the present invention provides an EEPROM performance level testing apparatus, including:

the selection module is used for selecting M sample EEPROMs from N EEPROMs to be tested, wherein M is less than N;

the pre-test module is used for testing each test parameter of the M sample EEPROMs through reading and writing data;

the construction module is used for determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different;

and the test module is used for sequentially inputting the N EEPROMs to be tested into the at least three test templates and determining the performance grade corresponding to each EEPROM to be tested.

Optionally, the pretest module is specifically configured to:

Optionally, when the building module is configured to determine, according to the test result, the L basic parameter vectors with the maximum sensitivity from the test parameters, the building module is specifically configured to:

Optionally, when the constructing module is configured to construct a plurality of test templates according to the L basic parameter vectors, the constructing module is specifically configured to:

and determining values of the L basic parameter vectors according to the conversion relation between the critical value of each parameter in the P-L test parameters and the L basic parameter vectors, and obtaining at least one third test template according to the values of the L basic parameter vectors and a third read-write test method.

As with the apparatus described above, optionally, the test module is specifically configured to:

In a third aspect, an embodiment of the present invention provides an electronic device, including:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform a method comprising: selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the plurality of test templates, and determining the performance grade corresponding to each EEPROM to be tested.

In a fourth aspect, an embodiment of the present invention provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following method: selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the plurality of test templates, and determining the performance grade corresponding to each EEPROM to be tested.

The EEPROM performance grade testing method provided by the embodiment of the invention selects the parameters of the test sample from the EEPROM to be tested; determining a basic parameter vector according to a test result, and constructing a plurality of test templates with different performance levels through the basic parameter vector; the EEPROM to be tested is tested by a plurality of test templates in sequence, so that the automatic test and classification of the EEPROM to be tested are realized, the EEPROM test efficiency and the accuracy of positioning a fault EEPROM are improved, the critical frequency is used as a reference index of a critical experiment according to the characteristics of the EEPROM, the parameter stress which is difficult to implement, such as temperature stress and the like, can be converted into other modes which are easy to implement, such as voltage tightening and the like, the automatic test resources are saved, in the scheme design, the interface frequency, the size and the like of an operation unit are changed by a test tool interface controller, the code change is small, and the realization and the transplantation popularization are easy.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a flow chart of an EEPROM performance level testing method provided by the embodiment of the invention;

FIG. 2 is a schematic structural diagram of an EEPROM performance level test device provided in an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic flow chart of an EEPROM performance level testing method according to an embodiment of the present invention, as shown in fig. 1, the method includes:

s11, M sample EEPROMs are selected from N EEPROMs to be tested, wherein M is less than N;

specifically, when the performance level test needs to be performed on N EEPROMs to be tested, M sample EEPROMs are selected from the N EEPROMs to be tested, for example, when the performance level test needs to be performed on 100 EEPROMs, 10 EEPROMs are selected from the N sample EEPROMs as the sample EEPROMs, wherein the closer M is to N, the higher the confidence of the test value of the sample is.

Step S12, testing each test parameter of the M sample EEPROMs through reading and writing data;

specifically, each test parameter of the M sample EEPROMs is tested by using a test fixture, where the test fixture may be a programmer or an actually used development board, and the test fixture only needs to support an EEPROM communication Interface protocol, such as a Serial Peripheral Interface (SPI) I2C, a mirrow communication Interface, and the like, and support corresponding test parameter adjustment.

And sequentially adjusting each test parameter by using the test tool, and determining critical value sample data of each test parameter and the average highest interface frequency of the M sample EEPROMs corresponding to each test parameter by taking the interface frequency of each sample EEPROM in the M sample EEPROMs as the highest value and the read-write data test as the critical judgment basis.

Taking an example that the EEPROM is a 2Mb SPI interface and the model is ATMEL AT25M02, parameters for test adjustment include voltages, i.e., a supply voltage of the EEPROM, an SPI interface voltage, and the like, wherein a default supply voltage and the SPI interface voltage have the same value, and an SPI interface frequency, an SPI read-write operation unit size, i.e., a pagesize size, and the like. Selecting 10 ATMEL AT25M02 chips, testing the critical value of each parameter, taking the highest interface frequency which can be reached under the premise of normal reading and writing as the critical value judgment basis, and determining the critical value sample data of each test parameter and the average highest interface frequency of M sample EEPROMs corresponding to each test parameter. For example, when testing the SPI interface voltage, a maximum interface frequency is obtained by M sample EEPROMs, and then the average value of the maximum interface frequencies is taken as the average maximum interface frequency of the SPI interface voltage. Thus, the larger the number of sample EEPROMs, the closer the average highest interface frequency is to the real data. During specific implementation, the test parameters are more, only one test parameter needs to be adjusted each time, other test parameters are fixed, and the fixed values of the other test parameters can be the most severe values in the support range of the EEPROM parameter manual.

For example, when testing temperature parameters, the voltage may be set to a minimum of 1.7V within the manual support range and pagesize to a maximum of 256 bytes. The critical value sample data table shown in table 1 and the corresponding average highest interface frequency can be obtained through the test fixture:

TABLE 1 ATMEL AT25M02 exemplary table of critical sample data

1.8V 256byte	Critical frequency AVERAGE	5.88MHZ
			1.7V 256byte	Critical frequency AVERAGE	5.16MHZ
Tc value at25 DEG C	Critical frequency AVERAGE	5.18MHZ
			Tc value-40 deg.C	Critical frequency AVERAGE	4.47MHZ
Tc value at 85 DEG C	Critical frequency AVERAGE	5.32MHZ

Step S13, determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test results, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grades corresponding to each test template are different;

specifically, P test parameters having the greatest influence on the interface frequency are determined according to the critical value sample data and the corresponding average highest interface frequency, optionally, a graph of each parameter and the interface frequency may be determined according to the critical value sample data and the corresponding average highest interface frequency, a slope of the graph is used as the sensitivity, and the P test parameters having the greatest sensitivity are selected from the slope. Alternatively, a large amount of test data shows that the critical frequency of the EEPROM is also different, and AT25M02 has the following rule: 1) under the same frequency, the lower the read-write voltage of the EEPROM is, the higher the probability of read-write error is; 2) under the condition of the same read-write voltage, the higher the read-write frequency of the EEPROM is, the higher the read-write error probability is; 3) under the same read-write voltage and the same frequency, the lower the EEPROM temperature is, the higher the read-write error probability is; 4) under the conditions of the same reading voltage and frequency, the larger the pagesize read by the EEPROM is, the higher the reading error probability is, but the smaller the influence of 1-3 points is; therefore, the influence on the interface frequency when the voltage, the frequency and the temperature are changed can be determined to be most sensitive, and the effective grading of the EEPROM can be realized.

And then, selecting L test parameters from the P test parameters as L basic parameter vectors, wherein the L test parameters meet preset adjustment conditions, and P is larger than L. The preset adjustment condition means that each test parameter in the L test parameters is easy to adjust for the test tool, so that the difficulty of EEPROM test can be reduced. For example, in three sensitive test parameters of voltage, frequency and temperature, the requirement of applying temperature stress on the experiment duration and the experiment condition is high, so that the voltage and the frequency can be used as basic parameter vectors, and the temperature test data can convert the influence value of the temperature stress on the critical frequency of the EEPROM into the voltage and the frequency value through the critical test data in high and low temperature environments. Optionally, an approximate equivalent transformation is performed according to the average maximum interface frequency, and if the critical frequency of 1.8V is reduced to 4.8M at 55 ℃ and the critical frequency is reduced to 4.8M when the voltage is reduced to 1.7V at25 ℃, the stress at 1.7 step-down at normal temperature is approximately equivalent to the temperature stress at 55 ℃.

After the base test vectors are determined, a test template may be constructed from the base test vectors. The test templates are divided into three types, respectively:

(1) determining critical values corresponding to the L basic parameter vectors and a first read-write test method according to the EEPROM parameter manual to obtain a first test template;

specifically, threshold values of all test parameters and corresponding test methods are set in an EEPROM parameter manual, and the test methods can be directly applied, L basic parameter vectors are set as corresponding thresholds, and a first read-write test method is used for testing, so that a first test template can be obtained, where the first read-write test method is a walk 1 test, that is, read-write verification data is 0x00,0x01,0x02, and 0x04 …, and the walk 1 test can minimize the number of memory cells that are turned over by 1 in unit time, and has the highest detection difficulty, mainly aiming at testing the conventional sensitivity of the EEPROM.

(2) Determining a critical value outlier parameter line according to the critical value sample data, determining values of L basic parameter vectors according to the critical value outlier parameter line, and obtaining a second test template according to the values of the L basic parameter vectors and a second read-write test method;

specifically, a critical value outlier parameter line is determined through critical value sample data, a line judged to be outlier is drawn, and the parameter outlier is used for sorting out the EEPROM with weak robustness. The critical value outlier parameter line means that under a certain group of test parameter values, the interface frequency of each sample EEPROM is always kept above the interface frequency range indicated by the reference manual, namely under the group of test parameter values, the interface frequency of each sample EEPROM accords with the parameter manual indication standard, the group of test parameter values is defined as the critical value outlier parameter line, and therefore the EEPROM with weak robustness can be selected through the critical value outlier parameter line.

For example, the second test template is determined according to values of L basic parameter vectors and a second read-write test method, where the second read-write test method is as follows, and the SPI interface frequency, whether the SPI interface frequency is the highest value, the lowest value, or the average value, is above 5MHZ of the interface frequency indicated by the reference manual at a normal temperature of 25 ℃ and a voltage of 1.7V, pagesize with a size of 256 bytes, and therefore the SPI interface frequency can be taken as a critical value outlier parameter line at a temperature of 25 ℃ and a voltage of 1.7V, pagesize with a size of 256 bytes, and values of the L basic parameter vectors can be obtained through the parameter line, and the second test template is determined according to the values of: the read-write verification data is tested by a full-chip 0X5AA5-0XA55A, the second read-write testing method can enable the number of memory cell inversions (1- >0,0- >1) in unit time to be the highest, and whether the EEPROM can pass the test or not when the test meets the most severe state in the parameter manual range.

(3) And determining values of the L basic parameter vectors according to the conversion relation between the critical value of each of the P minus L test parameters and the L basic parameter vectors, and obtaining at least one third test template according to the values of the L basic parameter vectors and a third read-write test method.

Specifically, for other P-L test parameters with higher sensitivity but less adjustability, the critical values of the P-L test parameters can be represented by basic parameter vectors, such as temperature, read-write reference current, fast switching frequency or pagesize, and the like, which are not easily adjustable, and the critical values can be converted into voltage, interface frequency, and the like. For example, if the critical frequency of 1.8V is reduced to 4.8M at 55 deg.C and the critical frequency is reduced to 4.8M when the voltage is reduced to 1.7V at25 deg.C, the stress at 1.7 step-down at room temperature is approximately equivalent to the stress at 55 deg.C. Therefore, the parameter stress which is difficult to test can be tested through other basic parameter vectors which are easy to adjust, and the test resources in the automatic test are saved. The third read-write test method of the third test template comprises the following steps: the read-write verification data is a full-slice 0X55AA-0XAA55 test, the test aims at an EEPROM over-specification test, 55AA enables the maximum turnover number of the same bit line to be the highest, and the third test module shows that the data can be read and written normally when the parameters corresponding to the basic test vector and other converted test parameters of the EEPROM reach the most severe state, and the performance of the test is optimal.

And step S14, inputting the N EEPROMs to be tested into the plurality of test templates in sequence, and determining the performance grade corresponding to each EEPROM to be tested.

Specifically, inputting the to-be-tested EEPROMs into the first test template aiming at each of the N to-be-tested EEPROMs, and if the to-be-tested EEPROMs fail to pass the test, determining that the performance grade corresponding to the to-be-tested EEPROMs is unqualified;

Table 2 test template example table

As shown in table 2, the EEPROM passed the grade 1,2 test, which indicates that the EEPROM meets the manual range index, and as can be seen from the table, the pass rate is 99%; the EEPROM passes the grade 3 test, which shows that the EEPROM can be read and written normally under the conditions that the voltage, the frequency, the read-write operation unit and the temperature stress reach the severest condition, and the passing rate is 82 percent. By the method for testing the EEPROM performance grade, provided by the embodiment of the invention, the failure EEPROM can be effectively detected, the EEPROM can be graded and classified according to the stability, the method is more accurate compared with the conventional method for judging the good and bad EEPROM, the automation of EEPROM grade classification can be realized to accurately judge the quality of the EEPROM, the condition that some EEPROMs with general quality are applied to occasions with high stability requirements is avoided, the resources are saved, and the method conforms to the sustainable development strategy.

The EEPROM performance grade testing method provided by the embodiment of the invention selects the boundary value of each parameter of the test sample from the EEPROM to be tested; determining a basic parameter vector according to a test result, and constructing a plurality of test templates with different performance levels through the basic parameter vector; the EEPROM to be tested is tested by a plurality of test templates in sequence, so that the automatic test and classification of the EEPROM to be tested are realized, the EEPROM test efficiency and the accuracy of positioning a fault EEPROM are improved, the critical frequency is used as a reference index of a critical experiment according to the characteristics of the EEPROM, the parameter stress which is difficult to implement, such as temperature stress and the like, can be converted into other modes which are easy to implement, such as voltage tightening and the like, the automatic test resources are saved, in the scheme design, the interface frequency, the size and the like of an operation unit are changed by a test tool interface controller, the code change is small, and the realization and the transplantation popularization are easy.

Based on the same inventive concept, an embodiment of the present invention further provides an EEPROM performance level testing apparatus, as shown in fig. 2, including: a selection module 21, a pre-test module 22, a construction module 23 and a test module 24, wherein:

the selection module 21 is configured to select M sample EEPROMs from N EEPROMs to be tested, where M < N; the pre-test module 22 is used for testing each test parameter of the M sample EEPROMs by reading and writing data; the construction module 23 is configured to determine, according to the test result, L basic parameter vectors with the highest sensitivity from the test parameters, and construct a plurality of test templates according to the L basic parameter vectors, where the EEPROM performance level corresponding to each test template is different; the test module 24 is configured to sequentially input the N EEPROMs to be tested into the at least three test templates, and determine a performance level corresponding to each EEPROM to be tested.

As with the above apparatus, optionally, the pretest module 22 is specifically configured to:

As for the above apparatus, optionally, when the constructing module 23 is configured to determine, according to the test result, the L basic parameter vectors with the maximum sensitivity from the test parameters, specifically:

As in the above apparatus, optionally, when the constructing module 23 is configured to construct a plurality of test templates according to the L basic parameter vectors, it is specifically configured to:

As with the above apparatus, optionally, the test module 24 is specifically configured to:

The apparatus provided in the embodiment of the present invention is configured to implement the method, and its functions specifically refer to the method embodiment, which is not described herein again.

Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 3, the electronic device includes: a processor (processor)31, a memory (memory)32, and a bus 33;

wherein, the processor 31 and the memory 32 complete the communication with each other through the bus 33;

the processor 31 is configured to call program instructions in the memory 32 to perform the methods provided by the above-mentioned method embodiments, including, for example: selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the at least three test templates, and determining the performance grade corresponding to each EEPROM to be tested.

An embodiment of the present invention discloses a computer program product, which includes a computer program stored on a non-transitory computer readable storage medium, the computer program including program instructions, when the program instructions are executed by a computer, the computer can execute the methods provided by the above method embodiments, for example, the method includes: selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the at least three test templates, and determining the performance grade corresponding to each EEPROM to be tested.

Embodiments of the present invention provide a non-transitory computer-readable storage medium, which stores computer instructions, where the computer instructions cause the computer to perform the methods provided by the above method embodiments, for example, the methods include: selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N; testing each test parameter of the M sample EEPROMs through reading and writing data; determining L basic parameter vectors with the maximum sensitivity from the test parameters according to the test result, and constructing at least three test templates according to the L basic parameter vectors, wherein the EEPROM performance grade corresponding to each test template is different; and sequentially inputting the N EEPROMs to be tested into the at least three test templates, and determining the performance grade corresponding to each EEPROM to be tested.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above-described embodiments of the apparatuses and the like are merely illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An EEPROM performance grade testing method is characterized by comprising the following steps:

selecting M sample EEPROMs from N EEPROMs to be tested, wherein M < N;

2. The method according to claim 1, wherein said testing the respective test parameters of the M sample EEPROMs by reading and writing data comprises:

3. The method of claim 2, wherein the determining the L basic parameter vectors with the greatest sensitivity from the respective test parameters according to the test results comprises:

4. The method of claim 3, wherein constructing a plurality of test templates from the L basis parameter vectors comprises:

5. The method of claim 4, wherein said sequentially inputting said N EEPROMs to be tested into said plurality of test templates, and determining a performance level corresponding to each EEPROM to be tested, comprises:

6. An EEPROM performance level testing device, comprising:

7. The apparatus of claim 6, wherein the pretest module is specifically configured to:

8. The apparatus according to claim 7, wherein the constructing module, when determining, according to the test result, the L basic parameter vectors with the greatest sensitivity from the test parameters, is specifically configured to:

9. The apparatus according to claim 8, wherein the constructing module, when constructing the plurality of test templates according to the L basic parameter vectors, is specifically configured to:

10. The apparatus of claim 9, wherein the testing module is specifically configured to:

11. An electronic device, comprising:

the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1 to 5.

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1 to 5.