CN100568397C - A kind of production test method of internal memory performance - Google Patents
A kind of production test method of internal memory performance Download PDFInfo
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- CN100568397C CN100568397C CNB2006100988721A CN200610098872A CN100568397C CN 100568397 C CN100568397 C CN 100568397C CN B2006100988721 A CNB2006100988721 A CN B2006100988721A CN 200610098872 A CN200610098872 A CN 200610098872A CN 100568397 C CN100568397 C CN 100568397C
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Abstract
The invention discloses a kind of production test method of internal memory performance, it may further comprise the steps: comprise following any one performance test methods at least: the stability that test memory reads after band CACHE large tracts of land writes; The stability of test memory when band CACHE random address large span jump writing.The method of testing that the inventive method adopted is compared with memory pressure test (RAM Stress Test) mode that industry is used always, can save the test duration, improves testing efficiency, and more is applicable to production test; And compare with commonly used function test method in the production test, then can remedy its deficiency to internal memory performance (stability of internal memory particle) test aspect.
Description
Technical field
The present invention relates to a kind of internal storage testing method, the in particular a kind of production test of internal memory performance fast and efficiently method.
Background technology
In the computing machine and the communications field, the performance of various internal memories (comprising SRAM, SDRAM and DDRSDRAM) directly has influence on the stability of veneer and even system.How internally to deposit into quick, efficient, the comprehensive test of row is the problem of industry research always.
Industry mainly adopts the mode of memory pressure test (RAM Stress Test) internally to deposit into comprehensively test of row at present.Its advantage be test relatively comprehensively, reliable, but shortcoming is consuming time oversize, and need set up independently test environment to internal memory, is unwell to large batch of production test.
In production test, often memory device is adopted simple functional test, for example data line, address wire and the functional memory cell read-write capability of internal memory are tested, this mode speed is very fast, but internal memory performance is not tested, mainly refer to the stability of internal memory particle, tend to stay very big hidden danger of quality.
Is in " dynamic memory function test method " in China Patent No. for the CN01140560 patent name, the method of the RAM chip being carried out functional test is disclosed, comprise read-write capability test to data line, address wire and storage unit etc., but also internal memory performance is not tested.
Therefore, prior art has yet to be improved and developed.
Summary of the invention
The object of the present invention is to provide a kind of production test method of internal memory performance, for the contradiction of testing efficiency and testing reliability in the production test that solves internal memory designs, it is mainly used in the production test of internal memory, can realize comparatively comprehensively test to internal memory with the short time.
Technical scheme of the present invention comprises:
A kind of production test method of internal memory performance, it may further comprise the steps:
At least comprise following any one performance test methods:
The stability that A, test memory read after band CACHE large tracts of land writes;
B, the stability of test memory when band CACHE random address large span jump writing.
Described method, wherein, described method A specifically also comprises:
The memory headroom of the mode application maximum of A1, usefulness band Cache;
B1, to all memory headroom one-time write test datas of applying for;
C1, read data in each address one by one, compare, if inconsistent then end test and report failure message with the corresponding test data that writes;
The operation of D1, repeating step B1 → C1 is until the repeated test number of times that reaches setting;
E1, test the back and discharge the memory headroom applied for.
Described method, wherein, described method B also comprises:
The memory headroom of the mode application maximum of A2, usefulness band Cache;
B2, array of pointers of definition;
C2, give each pointer assignment in the array of pointers successively, the arbitrary address value in the address space that makes each pointer point at random to apply in the described steps A 2, the equal assignment of all pointer address in array finishes;
D2, in each pointer memory address pointed, write at random test data successively;
E2, read real data in each pointer memory address pointed successively, compare, if inconsistent then end test and report failure message with the test data that writes;
The operation of F2, repeating step C2 → E2 is until the repeated test number of times that reaches setting;
G2, test the back and discharge the memory headroom applied for.
Described method, wherein, the assignment of each pointer among the described step C2 does not repeat, if any one address value of the assignment of certain pointer address and front is identical, then to its assignment again.
Described method wherein, was carried out the conventional func test before described performance test, it comprises:
A3, to the test of the address space of internal memory;
B3, data line is opened circuit or short trouble test;
C3, address wire is opened circuit or short trouble test;
D3, to the internal storage data readwrite tests, all available memory space are carried out the traversal test of a reading and writing data.
Described method, wherein, described steps A 3 also comprises: the address space of application maximum as much as possible, whether the actual address space of checking internal memory conforms to design capacity.
Described method, wherein, described steps A 3 also comprises:
The memory headroom of the mode application maximum of A31, usefulness band Cache.
Described method, wherein, described step B3 and C3 also comprise:
Employing is walked " 0 " method or is walked " 1 " method address wire or data line are tested.
Described method, wherein, described step D3 also comprises:
D31, from the start address of application memory field, write test data, read the data in this address, detect whether consistently with the data that write, make mistakes and promptly report test result, otherwise continue test;
D32, test address pointer add 1 successively, repeat the testing procedure in second step, finish until all address tests;
D33, test the back and discharge the memory headroom applied for.
The production test method of a kind of internal memory performance provided by the present invention, the method for testing that is adopted is compared with memory pressure test (RAM Stress Test) mode that industry is used always, can save the test duration, improves testing efficiency, and more is applicable to production test; And compare with commonly used function test method in the production test, then can remedy its deficiency to internal memory performance (stability of internal memory particle) test aspect.
Description of drawings
Fig. 1 is the stability test schematic flow sheet that reads after the interior existence band CACHE large tracts of land of the inventive method writes;
Fig. 2 is the stability test schematic flow sheet of the interior existence band CACHE random address large span jump writing of the inventive method.
Embodiment
Below by concrete example also in conjunction with the accompanying drawings, will describe in further detail the present invention.
The production test method of internal memory performance of the present invention, its testing procedure comprise the steps: as shown in Figure 1
At first: internally deposit into capable conventional func test; Described conventional func test mainly comprises following each step:
The first, to the address space test of internal memory; The fundamental purpose of memory address space test is whether checking memory size size is correct.Its test mode is: the address space of application maximum as much as possible, whether the actual address space of checking internal memory conforms to design capacity.
The second, data line is opened circuit or the short trouble test: fundamental purpose is the phenomenon whether the test memory data line exists open circuit (rosin joint) and short circuit.Can adopt away " 0 " method or walk " 1 " method data line is tested.
The 3rd, address wire is opened circuit or the short trouble test: under the prerequisite that the data line test is passed through, carry out the address wire test.The fundamental purpose of this test is the phenomenon whether the test memory data line exists open circuit (rosin joint) and short circuit.With the data line test class seemingly, can adopt away " 0 " method or walk " 1 " method address wire is tested.
The 4th, to the internal storage data readwrite tests: all available memory space are carried out the traversal test of a reading and writing data.
In the present embodiment, for efficient and the reliability that improves test, the inventive method is made a bit the conventionally test method and being improved, and takes to carry out readwrite tests with the mode of Cache.Concrete testing procedure is:
A, with the memory headroom of mode application maximum of band Cache, why adopt the mode of the mode of band Cache, be to accelerate test speed on the one hand, improve testing efficiency; Also read-write has proposed higher rate requirement to internal storage data on the other hand, makes that test is more reliable.
B, from the start address of application memory field, write test data, read the data in this address then, detect whether consistently with the data that write, make mistakes and promptly report test result, otherwise continue test;
C, test address pointer add 1 successively, and the test among the repeating step B finishes until all address tests;
D, test the back and discharge the memory headroom applied for.
Secondly, internally deposit into capable performance test, the internal memory performance test mainly is that the granule stability of internal memory is tested, and as shown in Figure 2, its test comprises following any one method of testing at least:
One, the stability that test memory reads after band CACHE large tracts of land writes, this step comprises following each step:
The memory headroom of the mode application maximum of A1, usefulness band Cache.
B1, to all memory headroom one-time write test datas of applying for, " disposable " here is to point to the memory headroom applied for to write test data continuously in the address one by one, and do not carry out read operation.In addition,, should guarantee when writing data that the test data between each address has nothing in common with each other, for example: write data i to address i respectively, perhaps i+1, i+2 etc. for the reliability that guarantees to test.
C1, read data in each address one by one, compare, if inconsistent then end test and report failure message with the corresponding test data that writes; After having finished the write operation of all address spaces among the step B1 in the above, this step is promptly carried out read operation, and whether the real data that checking reads is consistent with the data that write originally, if it is inconsistent then illustrate that there is fault in internal memory, promptly withdraw from test this moment, carry out localization of fault according to fault address, and the report failure message.If the data of next address space are verified in consistent then continuation, all verify until all address spaces and pass through.
The operation of D1, repeating step B1 → C1 is until the repeated test number of times that reaches setting; Be the stability of test memory particle, this test need repeat repeatedly, and multiplicity can be adjusted according to test duration and the required test effect that reaches.Testing time is many more, tests strict more, but consuming time long more.In general, this test needs to repeat more than 5 times.
E1, test the back and discharge the memory headroom applied for.
Its two, the stability of test memory when band CACHE random address large span jump writing, this step comprises following each step:
The memory headroom of the mode application maximum of A2, usefulness band Cache.
B2, array of pointers of definition; The array of pointers here is generally one-dimension array, the type of array of pointers should be consistent with the data type that test memory is read and write, and the capacity of array (number of the pointer that is in the array to be comprised) can be adjusted according to the test duration and the required test effect that reaches of expectation.The array capacity is big more, tests strict more, but consuming time long more.In general, to save as example in the 512M capacity, the capacity of array can be got about 200.
C2, give each pointer assignment in the array of pointers successively, the arbitrary address value in the address space that makes each pointer point at random to apply in the A2 step of front, the equal assignment of all pointer address in array finishes.But must note: the assignment of each pointer must not repeat, if any one address value of the assignment of certain pointer address and front is identical, and then must be to its assignment again.
Here it is also to be noted that each pointer address pointed must be arbitrarily to distribute in the address space of being applied for, can not be by the order continuous dispensing of address space, otherwise do not have the effect that its large span of test is jumped over read-write stability.
D2, in each pointer memory address pointed, write at random test data successively; Equally, only in all pointers address space pointed, write test data successively here, and do not carry out read operation.
E2, read real data in each pointer memory address pointed successively, compare, if inconsistent then end test and report failure message with the test data that writes.
After having finished the write operation of all pointers in the D2 step in the above, this step is promptly carried out read operation, and whether the real data that checking reads is consistent with the data that write originally, if it is inconsistent then illustrate that there is fault in internal memory, withdraw from test this moment immediately, carry out localization of fault according to fault address, and the report failure message.If the data in the next pointer address space pointed are verified in consistent then continuation, all verify until all pointers and pass through.
The operation of F2, repetition C2 → E2 is until the repeated test number of times that reaches setting; Notice that be the stability of test memory particle, this test must repeat repeatedly! Multiplicity can be adjusted according to test duration and the required test effect that reaches.Testing time is many more, tests strict more, but consuming time long more.This multiplicity should be at 105 orders of magnitude in general.
G2, test the back and discharge the memory headroom applied for.
In a word, the inventive method can be in the short period of time, on the basis of internal memory basic function test, the performance of internal memory compared comprehensive test, extremely is applicable to internally to deposit into capable performance test in the large batch of production test.
But should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (7)
1, a kind of production test method of internal memory performance, this method comprise any one in first kind of performance test methods and the second kind of performance test methods at least:
Wherein, first kind of performance test methods comprises steps A 1-E1:
The memory headroom of the mode application maximum of A1, usefulness band Cache;
B1, to all memory headroom one-time write test datas of applying for, should guarantee when writing test data that the test data between each address has nothing in common with each other;
C1, read data in each address one by one, compare, if inconsistent then end test and report failure message with the corresponding test data that writes;
The operation of D1, repeating step B1 → C1 is until the repeated test number of times that reaches setting;
E1, test the back and discharge the memory headroom applied for;
Second kind of performance test methods comprises steps A 2-G2:
The memory headroom of the mode application maximum of A2, usefulness band Cache;
B2, array of pointers of definition;
C2, give each pointer assignment in the array of pointers successively, the arbitrary address value in the address space that makes each pointer point at random to apply in the described steps A 2, the equal assignment of all pointer address in array finishes;
D2, in each pointer memory address pointed, write at random test data successively;
E2, read real data in each pointer memory address pointed successively, compare, if inconsistent then end test and report failure message with the test data that writes;
The operation of F2, repeating step C2 → E2 is until the repeated test number of times that reaches setting;
G2, test the back and discharge the memory headroom applied for.
2, method according to claim 1 is characterized in that, the assignment of each pointer among the described step C2 does not repeat, if any one address value of the assignment of certain pointer address and front is identical, then to its assignment again.
3, method according to claim 1 is characterized in that, carries out the conventional func test before described performance test, and it comprises:
A3, to the test of the address space of internal memory;
B3, data line is opened circuit or short trouble test;
C3, address wire is opened circuit or short trouble test;
D3, to the internal storage data readwrite tests, all available memory space are carried out the traversal test of a reading and writing data.
4, method according to claim 3 is characterized in that, described steps A 3 also comprises: the address space that application is maximum, whether the actual address space of checking internal memory conforms to design capacity.
5, method according to claim 4 is characterized in that, described steps A 3 also comprises:
The memory headroom of the mode application maximum of A31, usefulness band Cache.
6, method according to claim 3 is characterized in that, described step B3 and C3 also comprise:
Employing is walked " 0 " method or is walked " 1 " method address wire or data line are tested.
7, method according to claim 3 is characterized in that, described step D3 also comprises:
D31, from the start address of application memory field, write test data, read the data in this address, detect whether consistently with the data that write, make mistakes and promptly report test result, otherwise continue test;
D32, test address pointer add 1 successively, repeat the testing procedure in second step, finish until all address tests;
D33, test the back and discharge the memory headroom applied for.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101945019A (en) * | 2010-09-09 | 2011-01-12 | 福建星网锐捷通讯股份有限公司 | Back-to-back cache testing method for equipment |
| CN102841831A (en) * | 2011-06-24 | 2012-12-26 | 鸿富锦精密工业（深圳）有限公司 | System and method for testing server memory |
| CN102567158B (en) * | 2011-12-31 | 2016-05-18 | 曙光信息产业股份有限公司 | The method of testing of memory bandwidth and device |
| CN103473160B (en) * | 2013-09-26 | 2015-02-04 | 杭州华为数字技术有限公司 | Testing device, CPU (central processing unit) chip and testing method for cache |
| CN104391753B (en) * | 2014-12-16 | 2017-12-05 | 浪潮电子信息产业股份有限公司 | A kind of server master board memory system failure-free operation method |
| CN107039085A (en) * | 2017-05-03 | 2017-08-11 | 郑州云海信息技术有限公司 | A kind of method and system for realizing the test of storage subsystem data integrity |
| CN109408301A (en) * | 2017-08-16 | 2019-03-01 | 中国兵器装备集团自动化研究所 | Internal storage testing method based on 64 bit processor of Godson under a kind of PMON |
| CN109739706A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of ram test method and test device |
| CN113129995B (en) * | 2021-04-14 | 2023-05-16 | 锐捷网络股份有限公司 | EEPROM performance level testing method and device, electronic equipment and medium |
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