CN113410289A - 半导体装置 - Google Patents
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- CN113410289A CN113410289A CN202010862567.5A CN202010862567A CN113410289A CN 113410289 A CN113410289 A CN 113410289A CN 202010862567 A CN202010862567 A CN 202010862567A CN 113410289 A CN113410289 A CN 113410289A
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Abstract
半导体装置。公开了一种包括一个或更多个晶体管的半导体装置。该半导体装置包括:第一有源区,其设置在基板的阱区上;多个虚设有源区,其围绕第一有源区设置;以及栅极,其设置成横穿第一有源区,其中栅极的一部分设置为与多个虚设有源区中的至少一个交叠,并且电联接到多个虚设有源区中的至少一个。
Description
技术领域
本文所公开的技术和实现方式总体涉及一种半导体装置,更具体地,涉及一种包括一个或更多个晶体管的半导体装置。
背景技术
近来,随着更轻、更薄、更短和更小的电子产品的不断发展,对高度集成的半导体装置的需求迅速增加。根据半导体装置缩小的趋势,可以在更小和更窄的区域中形成器件隔离结构,使得在更小的半导体装置中更容易发生电特性的变化。
因此,需要开发一种器件隔离结构,其中能够防止在更小和更窄的区域内发生电特性的变化或劣化。此外,越来越需要减小在构造半导体装置的单位单元中使用的一个或更多个晶体管的形成区域的尺寸。
发明内容
所公开技术的各种实施方式涉及一种用于改进至少一个晶体管的应力并且用于减小其中可以放置晶体管的整个区域的尺寸的半导体装置。
根据所公开技术的一个实施方式,一种半导体装置可以包括:第一有源区,其设置在基板的阱区上;多个虚设有源区,其围绕第一有源区设置;以及栅极,其被设置成横穿第一有源区,其中,栅极的一部分被设置为与多个虚设有源区中的至少一个交叠并且电联接到多个虚设有源区中的至少一个。
根据所公开技术的另一实施方式,一种半导体装置可以包括:第一有源区,其形成在基板的阱区上;多个虚设有源区,其形成在阱区上,并且与第一有源区隔开预定距离;栅极,其设置在所述多个虚设有源区中的一个虚设有源区上方;以及栅极硅通孔(gate-through-silicon via),其联接到所述一个虚设有源区并且穿过栅极,并且被配置为将所述一个虚设有源区联接到设置在栅极上方的第一金属层。
根据所公开技术的又一实施方式,一种半导体装置可以包括:第一晶体管区;以及第二晶体管区,其被布置为关于第一方向与第一晶体管区对称,其中,第一晶体管区和第二晶体管区各自包括:第一有源区,其设置在基板的阱区上;虚设有源区,其设置在阱区上,并且与第一有源区隔开预定距离;栅极,其形成在虚设有源区上方,栅极硅通孔,其联接到虚设有源区并且穿过栅极;以及第一金属层,其将虚设有源区联接到栅极。
应当理解,本文公开的技术的前述一般描述和以下详细描述都是例示性和解释性的,并且旨在向本领域技术人员提供对本公开的范围的进一步解释。
附图说明
参照结合附图考虑时的以下详细描述,所公开技术的上述和其它特征以及有益方面将变得显而易见。
图1是示出根据本公开的一个实施方式的半导体装置的布局结构的图。
图2是示出根据本公开的一个实施方式的沿着图1所示的线Y-Y’截取的半导体装置的示例的截面图。
图3A至图3D是示出根据本公开的实施方式的沿着图1所示的线Y-Y’截取的半导体装置的制造工序的示例的截面图。
图4A至图4D是示出根据本公开的实施方式的沿着图1所示的线X-X’截取的半导体装置的制造工序的示例的截面图。
图5是示出根据本公开的一个实施方式的半导体装置的布局结构的示例的图。
图6是示出根据本公开的一个实施方式的沿着图5所示的线C-C’截取的半导体装置的示例的截面图。
附图中各元件的符号:
DACT1至DACT6:多个虚设有源区
ACT1至ACT3:多个有源区
G:栅极
GTV:栅极硅通孔
具体实施方式
该专利文献提供了一种半导体装置的实现方式和示例,该半导体装置基本上解决了与相关技术的限制或缺点相关的一个或更多个问题。所公开技术的一些实现方式提出了一种半导体装置,其能够改善至少一个晶体管的应力,并且能够减小晶体管的整个区域的尺寸。
现在将详细参照所公开技术的方面,其实施方式和示例在附图中示出。在尽可能的情况下,在所有附图中使用相同的附图标记来表示相同或相似的部件。
结合所公开技术的实施方式,仅出于例示的目的公开了具体的结构描述和功能描述。这些实施方式代表有限数量的可能实施方式。然而,在不脱离所公开技术的范围或精神的情况下,所公开技术的实施方式可以以各种或不同的方式实现。
在描述所公开的技术时,术语“第一”和“第二”可以用来描述多个组件,但是这些组件在数量或顺序上不受这些术语的限制。这些术语可以用来区分一个组件和另一组件。例如,在不脱离本公开的范围的情况下,第一组件可以称为第二组件,并且第二组件可以称为第一组件。
本申请中使用的术语仅用于描述具体实施方式,而并不旨在限制所公开的技术。除非另有明确说明,否则单数表达形式可以包括复数表达形式。
除非另有定义,否则本文使用的所有术语(包括技术术语或科学术语)具有与本领域技术人员所理解的含义相同的含义。在通用词典中定义的术语可以被分析为具有与相关领域的上下文相同的含义,而不应分析为具有理想含义或过于正式的含义,除非在本申请中明确定义。在所公开的技术中使用的术语仅仅是为了描述特定实施方式的目的,而不意图限制本公开。
图1是示出根据本公开的一个实施方式的半导体装置的布局结构的图。
参照图1,多个晶体管区TR1和TR2在结构上可以基本彼此相同,从而将在下文中仅使用一个晶体管区TR1作为示例来描述以下实施方式。
晶体管区TR1可以实现为NMOS晶体管或PMOS晶体管,但不限于此。此外,晶体管区TR2可以实现为NMOS晶体管或PMOS晶体管,但不限于此。
第一方向(I)可以指垂直于第二方向(II)的方向。第三方向(III)可以指与在第一方向(I)和第二方向(II)上延伸的水平面垂直的方向。例如,第三方向(III)可以与第一方向(I)和第二方向(II)中的每一个垂直。
基板100可以包括例如诸如硅(Si)或锗(Ge)之类的半导体材料,或者诸如硅锗(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)之类的化合物半导体材料。基板100可以包括导电区域,例如掺杂有杂质的阱或者掺杂有杂质的结构。
可以在基板100的指定区域中形成阱区110。在这种情况下,基板100可以掺杂有杂质以具有P型或N型导电材料。
为了便于描述,假设基板100实现为P型基板。在一些实施方式中,阱区110可以掺杂有杂质以具有P型或N型导电材料。为了便于描述,假设阱区110实现为N型阱。
阱区110可以包括多个有源区ACT1至ACT3。多个有源区ACT1至ACT3可以是用于接收晶体管区的源极电压、漏极电压和体电压的区域。
多个有源区ACT1至ACT3可以掺杂有杂质以具有P型或N型导电性。在一些实现方式中,多个有源区ACT1至ACT3中的每一个可以实现为掺杂有P型杂质的P型区域。根据各种电路类型的使用,多个有源区ACT1至ACT3可以被配置为具有不同的尺寸和不同的形状。
有源区ACT1可以位于晶体管TR1的中心区域。有源区ACT1可以形成为矩形岛状。
有源区ACT2和ACT3可以相对于晶体管TR1的中心区域形成在第二方向(II)的两侧。也就是说,有源区ACT2可以在第二方向(II)上位于有源区ACT1的一侧。有源区ACT3可以在第二方向(II)上位于有源区ACT1的另一侧。有源区ACT2和ACT3中的每一个可以形成为在第一方向(I)上延伸的线形状。有源区ACT2和有源区ACT3可以在第二方向(II)上彼此隔开预定距离。有源区ACT2和ACT3可以在第一方向(I)上具有相同或基本相同的长度。
此外,可以在基板100上形成多个虚设有源区DACT1至DACT6。多个虚设有源区DACT1至DACT6可以各自形成在形成于中心区域的有源区ACT1的外壁附近。例如,当沿第三方向观察时,多个虚设有源区DACT1至DACT6可以在第一方向和第二方向上围绕有源区ACT1而布置在基板100上。
在一些实施方式中,可以设置多个虚设有源区DACT1至DACT6以防止应力施加到有源区ACT1中的晶体管。例如,虚设有源区DACT1至DACT6可以形成在有源区ACT1附近并且与之相邻。
在半导体装置中,在半导体基板上形成的单元元件(例如,晶体管、二极管、电阻器等)必须彼此电隔离。因此,可以利用在所有半导体制造工序中使用的初始阶段工序来完成这种器件隔离工序。初始阶段工序能够极大地影响每个有源区的尺寸和后续工序的制造余量。
例如,浅沟槽隔离(STI)工艺可以解决由制造工序导致的不稳定性,诸如,由半导体装置的设计规则导致的场氧化膜的劣化。近来,为了进一步提高高度集成的半导体存储器装置的集成度,已经将半导体存储器装置发展为具有较小尺寸的组成元件。由于浅沟槽隔离(STI)工艺中的应力,具有较小元件的半导体存储器装置可能具有侧壁弱化的沟槽。为了解决这种可能性,所公开技术的实施方式中的半导体装置可以在半导体装置中包括多个虚设有源区DACT1至DACT6,以减少或防止受浅沟槽隔离(STI)工艺影响而在一个或更多个晶体管中产生应力。
多个虚设有源区DACT1至DACT6中的每一个可以形成为掺杂有P型杂质的P型区。尽管在本文公开的实施方式中,为了便于描述,多个虚设有源区DACT1至DACT6中的每一个形成为P型区,但是所公开的技术的范围或精神不限于此。在其它实施方式中,多个虚设有源区DACT1至DACT6也可以根据需要而利用其它类型的材料形成。
参照图1,多个虚设有源区DACT1至DACT6当中的虚设有源区DACT1和DACT2可以相对于中心区域设置在有源区ACT1的两侧。虚设有源区DACT1和DACT2中的每一个可以形成为在第二方向(II)上延伸的线形状。与有源区ACT1相比,虚设有源区DACT1和DACT2中的每一个可以形成为在第二方向(II)上具有更长的长度。例如,虚设有源区DACT1可以从有源区ACT1沿第一方向设置,使得虚设有源区DACT1的边缘或侧面覆盖有源区ACT1的相邻边缘或侧面,或者与有源区ACT1的相邻边缘或侧面完全交叠。类似地,在有源区ACT1的与虚设有源区DACT1相对的一侧,虚设有源区DACT2可以从有源区ACT1沿第一方向设置,使得虚设有源区DACT2的边缘或侧面覆盖有源区ACT1的相邻边缘或侧面,或者与有源区ACT1的相邻边缘或侧面完全交叠。虚设有源区DACT1和虚设有源区DACT2可以在第一方向(I)上彼此隔开预定距离。有源区ACT1可以设置在虚设有源区DACT1和虚设有源区DACT2之间。
有源区ACT1和有源区ACT2可以在第二方向(II)上彼此隔开预定距离。虚设有源区DACT3可以形成在有源区ACT1和有源区ACT2之间。换句话说,虚设有源区DACT3可以定位成与有源区ACT2邻接或相邻。虚设有源区DACT3可以沿第一方向(I)设置在虚设有源区DACT1和DACT2之间。虚设有源区DACT3可以形成为矩形或线形。虚设有源区DACT3可以在第一方向(I)上具有与有源区ACT1相同或基本相同的宽度。
有源区ACT1和有源区ACT3可以在第二方向(II)上彼此间隔开预定距离,并且有源区ACT3位于有源区ACT1的与有源区ACT2相对的另一侧。多个虚设有源区DACT4至DACT6可以形成在有源区ACT1和有源区ACT3之间。多个虚设有源区DACT4至DACT6中的每一个可以形成为矩形或线形。
多个虚设有源区DACT4至DACT6可以分别从多个虚设有源区DACT1至DACT3的侧面(例如,下侧)沿第二方向(II)设置。多个虚设有源区DACT4至DACT6中的每一个可以与有源区ACT3邻接或相邻。虚设有源区DACT4至DACT6可以在第一方向(I)上彼此隔开,并且可以间隔开预定距离。
栅极(G)可以设置在有源区ACT1和虚设有源区DACT5上方。晶体管TR1和TR2可以通过各自具有其相应的栅极来彼此区分。
栅极(G)可以形成为在第二方向(II)上延伸,并且可以形成为角形或锤形。例如,锤形的把手可以在第二方向(II)上延伸,而栅极(G)的区域(A)对应于锤形的头部并且在第一方向(I)上突出或延伸。换句话说,栅极(G)可以在第二方向(II)上延伸,并且可以形成为栅极(G)的区域(A)在第一方向(I)上弯曲的L形结构。栅极(G)的区域(A)可以设置为与虚设有源区DAC5交叠。在这种情况下,栅极(G)的区域(A)可以被形成为向每个晶体管提供电压。
栅极(G)的区域(A)可以通过栅极硅通孔(GTV)电联接到虚设有源区DACT5。也就是说,栅极(G)的区域(A)和虚设有源区(DACT5)可以在第三方向(III)上设置在同一条线上。
栅极(G)的区域(A)和虚设有源区DACT5可以关于第一方向(I)和第二方向(II)中的每一个而具有相同的尺寸或者可以具有不同的尺寸。在一些实施方式中,栅极(G)的区域(A)可以关于第一方向(I)和第二方向(II)中的每一个而在尺寸上小于虚设有源区DACT5。
尽管将栅极(G)设置为在有源区ACT1的顶面处或顶面附近横穿有源区ACT1,但是栅极(G)可以不设置在晶体管TR1的外围区域中,诸如其中设置有虚设有源区DACT4和DACT6的区域中。因此,在任何特定区域中不存在栅极图案的情况下,图案密度存在差异,从而可能导致在曝光和蚀刻步骤中不均匀地实现栅极图案。
因此,可以形成虚设栅极DG,使得通过设置虚设栅极DG,能够减小栅极图案之间的分隔距离的任何差异。通过实现虚设栅极DG,栅极图案能够以距离相同或基本相同的、更均匀的间隔彼此隔开。在图1中,从第三方向观察,虚设栅极DG可以设置为与虚设有源区DACT1至DACT6的一些边缘相邻。虚设栅极DG可以形成为围绕虚设有源区DACT1和DACT2。虚设栅极DG可以形成为在第二方向(II)上横穿虚设有源区DACT3的中心区域。
栅极(G)的侧面或边缘可以在第一方向(I)上与虚设栅极(DG)隔开预定距离。虚设栅极DG的分段可以具有与区域(A)外部的栅极(G)基本相同或相同的宽度(例如,第一方向I的宽度)。
可以在有源区ACT1至ACT3上方形成多个金属接触件(M0C)。多个金属接触件(M0C)可以在有源区ACT2和ACT3的顶面处或顶面附近沿第一方向(I)彼此隔开预定距离。多个金属接触件(M0C)可以在有源区(ACT1)的顶面处或顶面附近沿第一方向(I)和第二方向(II)形成为晶格或栅格形状。
如上所述,可以在虚设有源区DACT5上方形成栅极硅通孔(GTV)。栅极硅通孔(GTV)可以电联接到栅极(G)的区域(A)。此外,栅极硅通孔(GTV)可以在穿过栅极(G)之后电联接到下虚设有源区DACT5。
此外,可以在基板100上方形成多个金属层(M0)。金属层(M0)中的每一个可以形成为在第二方向(II)上延伸的线形状。多个金属层(M0)可以形成为在第二方向(II)上具有不同的长度,并且可以相对于彼此交错。多个金属层(M0)可以在第一方向(I)上彼此隔开预定距离。多个金属层(M0)可以通过金属接触件(M0C)电联接到有源区ACT1至ACT3。
金属层(M0_1)可以设置在金属层(M0)的延长线上。金属层(M0_1)可以形成为在第二方向(II)上延伸的线形状。金属层(M0_1)可以通过栅极硅通孔(GTV)电联接到栅极(G)和虚设有源区DACT5。金属层(M0_1)可以将晶体管区TR1的栅极硅通孔(GTV)电联接到晶体管区TR2的栅极硅通孔(GTV)。也就是说,晶体管区TR1的栅极(G)锤区域(A)可以通过金属层(M0_1)电联接到晶体管区TR2的栅极(G)锤区域(A)。
多个金属层(M0)当中的金属层M2可以在第一方向(I)上与金属层(M0_1)隔开预定距离。金属层M2可以形成为在第二方向(II)上延伸的线形状。金属层(M2)可以将晶体管区TR1的有源区ACT1电联接到晶体管区TR2的有源区ACT1。
可以在金属层(M0)上方形成多个金属接触件(M1C)。多个金属接触件(M1C)可以在第一方向(I)上彼此隔开预定距离。
此外,可以在金属层(M0)上方形成多个金属层(M1)。每个金属层(M1)可以形成为在第一方向(I)上延伸的线形状。金属层(M1)可以通过金属接触件(M1C)电联接到有源区ACT1。
图2是示出根据本公开的一个实施方式的沿着图1所示的线Y-Y’截取的图1所示半导体装置的示例的截面图。
参照图2,可以在基板100中或基板100上形成阱区110。在这种情况下,基板100可以实现为掺杂有P型杂质的P型基板。
阱区110可以包括晶体管的有源区ACT1和虚设有源区DACT5。在这种情况下,有源区ACT1和虚设有源区DACT5中的每一个可形成为掺杂有P型杂质的P型区域。
晶体管的栅极(G)的区域(A)可以在第三方向(III)上形成在虚设有源区DACT5上方。栅极(G)可以形成在层间绝缘膜120中或层间绝缘膜120上。层间绝缘膜120可以形成为诸如氧化膜的绝缘层。栅极(G)可以通过栅极硅通孔(GTV)电联接到下虚设有源区DACT5。
在一些实施方式中,虚设有源区DACT5可以形成在栅极(G)下方,即,虚设有源区DACT5可以在第二方向(II)上偏离栅极(G)。在该示例中,如果虚设有源区DACT5在第三方向(III)上没有形成在栅极(G)下方,而是虚设有源区DACT5与栅极(G)的侧面隔开,则由线Y-Y’示出的横截面的宽度可以增加,以便包括虚设有源区DACT5。因此,在图2中,设置在栅极(G)下方的虚设有源区DACT5沿相同的垂直线形成,并且减小或消除了将有源区ACT1和虚设有源区DACT5分离的任何距离。线Y-Y’的较短宽度可以对应于设置在半导体装置中的较小或较窄区域中的器件隔离结构。
金属接触件(M0C)中的每一个可以形成在有源区ACT1的顶面和金属层(M0)的底面之间。栅极硅通孔(GTV)可以在穿过栅极(G)的同时形成在金属层(M0_1)的底面和虚设有源区DACT5的顶面之间。栅极硅通孔(GTV)可以使上金属层(M0_1)、下栅极(G)和虚设有源区DACT5彼此电联接。
在一些实施方式中,栅极(G)和虚设有源区DACT5可以通过栅极硅通孔(GTV)彼此电联接。结果,能够防止在需要保护器件隔离沟槽的侧壁的后续等离子体注入工艺中发生等离子体诱导损伤(PID)。
也就是说,栅极硅通孔(GTV)和电联接到栅极(G)的虚设有源区DACT5可以用作能够防止等离子体诱导损伤(PID)的二极管图案。结果,可以防止半导体装置的组成元件的电特性劣化。更具体地,可以认为晶体管的阈值电压的偏移是这种电特性劣化的一个示例。
此外,金属层(M0)和金属层(M0_1)可以关于第三方向(III)形成在相同层中,并且可以在第二方向(II)上彼此隔开预定距离。金属接触件(M1C)可以形成在金属层(M0)的顶面和金属层(M1)的底面之间。金属层(M1)可以形成在金属层(M0)上方。金属层(M1)可以通过金属接触件(M1C)电联接到金属层(M0)。
图3A至图3D是示出根据本公开的实施方式的沿着图1所示的线Y-Y’截取的半导体装置的制造工序的示例的截面图。图4A至图4D是示出根据本公开的实施方式的沿着图1所示的线X-X’截取的半导体装置的制造工序的示例的截面图。在图3A至图3D和图4A至图4D中,为了便于描述,本文将省略与图2的组成元件相同的一些组成元件。
参照图3A和图4A,可以执行杂质注入工序来调整基板100中的掺杂密度,从而形成阱区110。在这种情况下,阱区110可以用作装置(例如,晶体管)的主体。
可以在阱区110中形成晶体管的有源区ACT1和虚设有源区DACT5。在这种情况下,可以通过浅沟槽隔离(STI)、硅局部氧化(LOCOS)处理等形成有源区ACT1和虚设有源区DACT5。
此外,可以在虚设有源区DACT5上方形成晶体管的栅极(G)。也就是说,栅极(G)可以沿垂直方向或第三方向(III)形成在虚设有源区DACT5上方。在虚设有源区DACT5上方形成氧化膜(未示出)和导线之后,可以响应于对应晶体管的栅极长度而对导线进行蚀刻,从而形成栅极(G)的图案。栅极(G)可以对应于要联接到上金属线和下金属线(未示出)的锤区域(A)。
在这种情况下,栅极(G)可以由各种导电材料形成。例如,栅极(G)可以由选自金属、金属和多晶硅以及多晶硅中的任何一种形成。在一些实施方式中,栅极(G)可以由金属和多晶硅形成。
此后,如图3B和图4B所示,可以对沿垂直方向形成在虚设有源区DACT5上方的栅极(G)进行蚀刻,从而形成接触孔H1。在这种情况下,可以对接触孔H1进行蚀刻以使虚设有源区DACT5的顶面暴露。
随后,如图3C和图4C所示,可以在栅极(G)结构的整个表面上方沉积层间绝缘膜120。在这种情况下,层间绝缘膜120可以包括氮化物膜或氧化物膜。
可以蚀刻层间绝缘膜120以形成接触孔H2。在这种情况下,可以蚀刻接触孔H2以使有源区ACT1的顶面暴露。因此,下有源区ACT1与用于连接虚设有源区DACT5和上金属线的接触件可以彼此电隔离。当对层间绝缘膜120进行蚀刻时,可以打开或重新打开栅极(G)的孔H1。
此后,如图3D和图4D所示,接触孔H1和H2可以利用接触插塞材料掩埋,从而能够形成金属接触件(M0C)和栅极硅通孔(GTV)。因此,栅极硅通孔(GTV)、栅极(G)和虚设有源区DACT5可以彼此物理接触。在这种情况下,埋入在接触孔H1中以形成栅极硅通孔(GTV)的材料可以与埋入在接触孔H2中以形成金属接触件(M0C)的材料相同。
在一些实施方式中,为了改进电特性,可以用特定材料附加掩埋其中接触孔H1与栅极(G)和虚设有源区DACT5接触的边界区域。
掩埋在其中接触孔H1与栅极(G)和虚设有源区DACT5接触的边界区域中的特定材料应当电联接到栅极(G)和虚设有源区DACT5,使得特定材料可以由导电材料形成。在这种情况下,导电材料可以包括诸如钨(W)、钛(Ti)和氮化钛(TiN)之类的金属材料,可以包括多晶硅,或者可以包括金属和多晶硅。
此后,可以在金属接触件(M0C)上方沉积金属层(M0),并且可以在栅极硅通孔(GTV)上方沉积金属层(M0_1)。
图5是示出根据本公开的一个实施方式的半导体装置的布局结构的示例的图。图6是示出根据本公开的一个实施方式的沿着图5所示的线C-C’截取的半导体装置的示例的截面图。在图5和图6中,用相同的附图标记表示与图1和图2中组成元件相同的组成元件,因此为了便于描述,这里将省略其详细描述。
参照图5和图6,晶体管区TR1和晶体管TR2可以在沿第一方向(I)跨过其间的线上彼此对称。也就是说,晶体管区TR1和晶体管区TR2可以布置成彼此面对,同时相对于第一方向(I)具有镜像对称结构。
在图6中,晶体管区TR1的栅极硅通孔(GTV)和晶体管区TR2的栅极硅通孔(GTV)可以通过金属层(M0_1)彼此电联接。也就是说,晶体管区TR1的栅极(G)、晶体管区TR2的栅极(G)以及每个晶体管的虚设有源区DACT5可以通过金属层(M0_1)彼此电联接。
从以上描述显而易见,基于所公开技术的实施方式的半导体装置可以改进至少一个晶体管的应力,并且可以减小将被占据的区域的整体尺寸。
所公开技术的实施方式可以提供能够通过上述专利文献直接或间接地识别的各种效果。
本领域的技术人员应当理解,在不脱离本公开的精神和本质特征的情况下,可以以除了本文阐述的方式之外的其它特定方式来实现实施方式。因此,上述实施方式在所有方面都应被解释为例示性而非限制性的。本公开的范围应当由所附权利要求及其法律等同物来确定,而不是由以上描述来确定。此外,在所附权利要求的含义和等效范围内的所有变化都被认为包含在本申请中。此外,本领域技术人员应当理解,在所附权利要求中没有彼此明确引用的权利要求可以作为实施方式而组合呈现,或者在提交申请后通过后续修改而被包括为新的权利要求。
尽管已经描述了多个例示性实施方式,但是应当理解,本领域技术人员能够设计出将落入本公开的原理的精神和范围内的许多其它变型和实施方式。具体地说,可以对本公开、附图和所附权利要求的范围内的组成部分和/或布置进行多种更改和变型。除了组成部分和/或布置的更改和变型之外,替代使用对于本领域技术人员来说也是显而易见的。
相关申请的交叉引用
本专利文献要求于2020年3月17日提交的韩国专利申请No.10-2020-0032699的优先权和利益,该韩国专利申请的全部内容通过引用结合于本文中。
Claims (22)
1.一种半导体装置,该半导体装置包括:
第一有源区,该第一有源区被设置在基板的阱区上;
多个虚设有源区,所述多个虚设有源区围绕所述第一有源区设置;以及
栅极,该栅极被设置成横穿所述第一有源区;
其中,所述栅极的一部分被设置为与所述多个虚设有源区中的至少一个交叠,并且电联接到所述多个虚设有源区中的至少一个。
2.根据权利要求1所述的半导体装置,其中,所述第一有源区被设置在所述阱区的中心区域中,并且具有矩形形状。
3.根据权利要求1所述的半导体装置,该半导体装置还包括:
第二有源区,该第二有源区关于第二方向设置在所述第一有源区的一侧;以及
第三有源区,该第三有源区关于所述第二方向设置在所述第一有源区的另一侧。
4.根据权利要求3所述的半导体装置,其中,
所述第二有源区和所述第三有源区各自具有在第一方向上延伸的线形状,并且所述第二有源区和所述第三有源区在所述第二方向上彼此隔开预定距离。
5.根据权利要求1所述的半导体装置,其中,所述多个虚设有源区包括:
第一虚设有源区,该第一虚设有源区关于第一方向设置在所述第一有源区的一侧;
第二虚设有源区,该第二虚设有源区关于所述第一方向设置在所述第一有源区的另一侧;
第三虚设有源区,该第三虚设有源区关于第二方向设置在所述第一有源区的一侧;以及
第四虚设有源区、第五虚设有源区和第六虚设有源区,该第四虚设有源区、该第五虚设有源区和该第六虚设有源区关于所述第二方向设置在所述第一有源区的另一侧,其中所述第四虚设有源区、所述第五虚设有源区和所述第六虚设有源区在所述第一方向上彼此隔开预定距离。
6.根据权利要求5所述的半导体装置,其中,
所述第一虚设有源区和所述第二虚设有源区各自具有在所述第二方向上延伸的线形状,并且在所述第二方向上比所述第一有源区更长。
7.根据权利要求5所述的半导体装置,其中,所述第一虚设有源区和所述第二虚设有源区在所述第一方向上彼此隔开预定距离。
8.根据权利要求5所述的半导体装置,其中,
所述第三虚设有源区在所述第一方向上设置在所述第一虚设有源区和所述第二虚设有源区之间。
9.根据权利要求5所述的半导体装置,其中,所述第三虚设有源区在所述第一方向上具有与所述第一有源区相同的宽度。
10.根据权利要求5所述的半导体装置,其中,所述第五虚设有源区电联接到所述栅极。
11.根据权利要求10所述的半导体装置,该半导体装置还包括:
栅极硅通孔,该栅极硅通孔穿过所述栅极并且联接到所述第五虚设有源区,并且被配置为使得所述第五虚设有源区能够联接到第一金属层。
12.根据权利要求11所述的半导体装置,该半导体装置还包括:
包括所述第一金属层的多个金属层,所述多个金属层形成在所述基板上方,
其中,所述第一金属层通过所述栅极硅通孔联接到所述栅极和所述第五虚设有源区,并且
所述多个金属层中的第二金属层通过接触件联接到所述第一有源区。
13.根据权利要求12所述的半导体装置,其中,
所述第一金属层沿垂直方向设置在所述栅极和所述第五虚设有源区上方;并且
所述第二金属层沿所述垂直方向设置在所述第一有源区上方。
14.根据权利要求13所述的半导体装置,该半导体装置还包括:
第三金属层,该第三金属层沿所述垂直方向形成在所述第二金属层上方。
15.根据权利要求5所述的半导体装置,其中,所述栅极具有锤形状,该锤形状具有在所述第二方向上延伸的把手和在所述第一方向上突出的头部。
16.根据权利要求15所述的半导体装置,其中,所述栅极的在所述第一方向上突出的锤头区域沿垂直方向设置在所述第五虚设有源区上方。
17.根据权利要求5所述的半导体装置,该半导体装置还包括:
虚设栅极,当在垂直方向上观察时,该虚设栅极围绕所述多个虚设有源区的边缘设置,
其中,所述虚设栅极的一部分在所述第二方向上横穿所述第三虚设有源区。
18.一种半导体装置,该半导体装置包括:
第一有源区,该第一有源区形成在基板的阱区上;
多个虚设有源区,所述多个虚设有源区形成在所述阱区上,并且与所述第一有源区隔开预定距离;
栅极,该栅极被设置在所述多个虚设有源区中的一个虚设有源区上方;以及
栅极硅通孔,该栅极硅通孔联接到所述一个虚设有源区并且穿过所述栅极,并且被配置为将所述一个虚设有源区联接到设置在所述栅极上方的第一金属层。
19.根据权利要求18所述的半导体装置,该半导体装置还包括:
接触件,该接触件被配置为将所述第一有源区联接到设置在所述第一有源区上方的第二金属层。
20.根据权利要求18所述的半导体装置,其中,所述栅极沿垂直方向形成在与所述虚设有源区相同的线上,并且电联接到所述栅极硅通孔。
21.一种半导体装置,该半导体装置包括:
第一晶体管区;以及
第二晶体管区,该第二晶体管区被布置为关于第一方向与所述第一晶体管区对称;
其中,所述第一晶体管区和所述第二晶体管区各自包括:
第一有源区,该第一有源区被设置在基板的阱区上;
虚设有源区,该虚设有源区被设置在所述阱区上,并且与所述第一有源区隔开预定距离;
栅极,该栅极形成在所述虚设有源区上方,
栅极硅通孔,该栅极硅通孔联接到所述虚设有源区并且穿过所述栅极;以及
第一金属层,该第一金属层将所述虚设有源区联接到所述栅极。
22.根据权利要求21所述的半导体装置,其中,所述第一晶体管区和所述第二晶体管区共享所述第一金属层,所述第一金属层将所述第一晶体管区的栅极硅通孔电联接到所述第二晶体管区的栅极硅通孔。
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