CN113410268A - Display panel, manufacturing method of display panel and display device - Google Patents

Display panel, manufacturing method of display panel and display device Download PDF

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Publication number
CN113410268A
CN113410268A CN202110616796.3A CN202110616796A CN113410268A CN 113410268 A CN113410268 A CN 113410268A CN 202110616796 A CN202110616796 A CN 202110616796A CN 113410268 A CN113410268 A CN 113410268A
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opening
layer
isolation
substrate
display panel
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CN113410268B (en
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朱正勇
孙光远
贾溪洋
段培
马志丽
王宏宇
逄辉
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/122Pixel-defining structures or layers, e.g. banks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/84Passivation; Containers; Encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The embodiment of the invention provides a display panel, a manufacturing method of the display panel and a display device, wherein the display panel comprises: a substrate; the functional layer, at least, including the opening layer and be located the pixel definition layer that the opening layer deviates from substrate one side, pixel definition layer includes this somatic part and runs through the pixel opening of this somatic part, set up the isolation through-hole that runs through the setting on the functional layer, and keep apart the through-hole including the first isolation opening that is located the opening layer, be located the first second isolation opening that keeps apart the opening and deviate from substrate one side and the first communication port that communicates first isolation opening and second isolation opening, wherein, the first orthographic projection of first isolation opening on the substrate and the orthographic projection dislocation set of pixel opening on the substrate, the size of first orthographic projection is greater than the size of the orthographic projection of first communication port on the substrate, have in the first isolation opening with the isolation clearance of first communication port dislocation set. The invention can improve the low gray scale color cast of the display picture caused by current crosstalk and improve the display effect of the display panel.

Description

Display panel, manufacturing method of display panel and display device
Technical Field
The invention relates to the technical field of display equipment, in particular to a display panel, a manufacturing method of the display panel and a display device.
Background
Flat Display panels, such as Liquid Crystal Display (LCD) panels, Organic Light Emitting Diode (OLED) panels, and Display panels using Light Emitting Diode (LED) devices, have advantages of high image quality, power saving, thin body, and wide application range, and are widely used in various consumer electronics products, such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
In the display panel, because the lighting voltages of the red sub-pixel, the green sub-pixel and the blue sub-pixel are different, when the sub-pixel with high lighting voltage is lighted, current flows transversely through the current carrier layer, so that the sub-pixel with low lighting voltage is lightly lighted, a display picture has low gray scale color cast, and display abnormity occurs.
Therefore, a display panel, a method for manufacturing the display panel, and a display device are needed.
Disclosure of Invention
The embodiment of the application provides a display panel, a manufacturing method of the display panel and a display device, and aims to improve the display effect of the display panel.
An embodiment of a first aspect of the present application provides a display panel, including: a substrate; the functional layer, at least, including the opening layer and be located the pixel definition layer that the opening layer deviates from substrate one side, pixel definition layer includes this somatic part and runs through the pixel opening of this somatic part, set up the isolation through-hole that runs through the setting on the functional layer, and keep apart the through-hole including the first isolation opening that is located the opening layer, be located the first second isolation opening that keeps apart the opening and deviate from substrate one side and the first communication port that communicates first isolation opening and second isolation opening, wherein, the first orthographic projection of first isolation opening on the substrate and the orthographic projection dislocation set of pixel opening on the substrate, the size of first orthographic projection is greater than the size of the orthographic projection of first communication port on the substrate, have in the first isolation opening with the isolation clearance of first communication port dislocation set.
According to an embodiment of the first aspect of the present application, the isolation gap is disposed around a circumferential side of the first communication port.
According to any one of the preceding embodiments of the first aspect of the present application, the center of the first forward projection overlaps the center of the second forward projection.
According to any one of the embodiments of the first aspect of the present application, the number of the second isolation openings is plural, and the plural second isolation openings are distributed at intervals on the peripheral side of each pixel opening; the number of the first isolation openings is multiple, and each first isolation opening and each second isolation opening are correspondingly arranged in the thickness direction of the display panel.
According to an embodiment of the first aspect of the present application, the second isolation opening opens in the pixel definition layer, and the opening is located in the planarization layer on a side of the pixel definition layer facing the substrate layer.
According to any one of the preceding embodiments of the first aspect of the present application, the functional layer further comprises: and the spacing layer is positioned between the opening layer and the pixel defining layer, and the second isolation opening extends from the pixel defining layer to the spacing layer.
According to one embodiment of the first aspect of the present application, the display panel has an opening area and a display area surrounding the opening area,
the opening area is internally provided with a sealing through hole penetrating through the functional layer, the sealing through hole comprises a first sealing opening positioned on the opening layer, a second sealing opening positioned on one side of the first sealing opening, which is far away from the substrate, and a second communication opening communicating the first sealing opening and the second sealing opening,
the third orthographic projection of the first sealing opening on the substrate and the orthographic projection of the pixel opening on the substrate are arranged in a staggered mode, the size of the third orthographic projection is larger than that of the orthographic projection of the second communication opening on the substrate, and a sealing gap arranged in a staggered mode with the second communication opening is formed in the first sealing opening.
According to any of the preceding embodiments of the first aspect of the present application, the opening layer is located on the signal line layer on the side of the pixel defining layer facing the substrate, the functional layer further comprises a planarization layer located between the signal line layer and the pixel defining layer, and the second isolation opening and the second sealing opening are disposed through the pixel defining layer and the planarization layer.
According to an embodiment of the first aspect of the present application, the display panel further includes: a current carrier layer located at one side of the pixel defining layer away from the opening layer and having a first thickness d1(ii) a The opening layer has a second thickness d2A second thickness d2And a first thickness d1Satisfies the following conditions: d2≥d1
According to any of the preceding embodiments of the first aspect of the present application, the second thickness d2And a first thickness d1Satisfies the following conditions: d2≥3d1
According to any of the preceding embodiments of the first aspect of the application, the second thickness
Figure BDA0003098002820000031
According to any of the preceding embodiments of the first aspect of the present application, the edge of the first isolation opening has a maximum distance H from the edge of the second isolation opening, a maximum distance H and a first thickness d1Satisfies the following conditions: h is not less than d1
According to any of the preceding embodiments of the first aspect of the present application, the maximum distance H and the first thickness d1Satisfies the following conditions: h is more than or equal to 3d1
Embodiments of the second aspect of the present application provide a display device, including the display panel described above.
Embodiments of a third aspect of the present application provide a method for manufacturing a display panel, the method including:
providing a substrate;
arranging a functional material layer on the substrate, wherein the functional material layer at least comprises an opening material layer and a pixel definition material layer positioned on one side of the opening material layer, which is far away from the substrate;
patterning the pixel defining material layer to form a body portion and a pixel opening penetrating the body portion;
patterning the functional layer to form a transition through hole extending from the pixel definition material layer to the opening material layer;
carry out the etching to the opening material layer and handle, increase transition open-ended size is in order to form first isolation opening, make transition through-hole form be located first isolation opening and keep apart the second isolation opening that deviates from substrate one side and communicate first isolation opening and second isolation open-ended first intercommunication mouth, first orthographic projection of first isolation opening on the substrate and the orthographic projection dislocation set of pixel opening on the substrate, the size of first orthographic projection is greater than the size of the orthographic projection of first intercommunication mouth on the substrate, have in the first isolation mouth with the isolation clearance of first intercommunication mouth dislocation set.
In the display panel provided in the embodiment of the present invention, the display panel includes a substrate and a functional layer that are sequentially stacked, an isolation through hole is formed in the functional layer, the isolation through hole includes a first isolation opening and a second isolation opening, and when a carrier layer is disposed on the pixel defining layer, a material of the carrier layer enters the first isolation opening through the second isolation opening. The first orthographic projection of the first isolation opening on the substrate and the orthographic projection of the pixel opening on the substrate are arranged in a staggered mode, namely the first isolation opening and the pixel opening are arranged in a staggered mode in the thickness direction of the display panel, and therefore the first isolation opening cannot influence the forming of the pixel opening. In addition, the first isolating opening is internally provided with an isolating gap which is arranged in a staggered mode with the first communication opening, when a carrier layer is formed on the pixel defining layer, at least part of the material of the carrier layer can not enter the isolating gap, the carrier layer is disconnected at the isolating gap, the communication area of the carrier layer can be reduced, the transverse current is reduced, the low gray scale color cast of a display picture caused by current crosstalk is improved, and the display effect of the display panel is improved.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings in which like or similar reference characters refer to the same or similar parts.
Fig. 1 is a top view of a display panel according to an embodiment of the first aspect of the present invention;
FIG. 2 is an enlarged partial schematic view of the structure at P in FIG. 1;
FIG. 3 is an enlarged partial schematic view taken at A-A in FIG. 2;
FIG. 4 is a cross-sectional view taken at A-A of FIG. 2 in another embodiment;
FIG. 5 is a cross-sectional view taken at A-A of FIG. 2 in a further embodiment;
FIG. 6 is a cross-sectional view taken at B-B of FIG. 1;
FIG. 7 is a cross-sectional view taken at B-B of FIG. 1 in accordance with yet another embodiment;
FIG. 8 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the third aspect of the present invention;
fig. 9 to 15 are process diagrams of a display panel according to an embodiment of the invention.
Description of reference numerals:
11. a first sub-pixel; 12. a second sub-pixel; 13. a third sub-pixel;
100. a substrate;
200. a functional layer; 210. a pixel defining layer; 211. a body portion; 212. a pixel opening; 220. an opening layer; 230. isolating the through holes; 231. a first isolation opening; 232. a second isolation opening; 233. a first communication port; 234. a third isolation opening; 235. isolating the gap; 240. a spacer layer; 250. sealing the through hole; 251. a first sealed opening; 252. a second sealed opening; 253. a second communication port; 254. a third sealed opening; 255. sealing the gap; 260. a signal line layer; 261. a first delamination; 262. second layering; 263. third layering; 270. a planarization layer;
310. a first insulating layer; 320. a first conductive layer; 330. a second insulating layer; 340. a second conductive layer;
400. a charge carrier layer;
500. a light emitting structure;
600. common electrode
700. A sealing layer; 710. a first inorganic layer; 720. a second organic layer; 730. a third inorganic layer;
800. a dam;
AA. A display area; KA; an opening area; NA, non-display area.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present invention; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the description of the present invention, it is to be noted that, unless otherwise specified, "a plurality" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated for convenience in describing the invention and to simplify description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The directional terms appearing in the following description are intended to be illustrative in all directions, and are not intended to limit the specific construction of embodiments of the present invention. In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as either a fixed connection, a removable connection, or an integral connection; can be directly connected or indirectly connected. The specific meaning of the above terms in the present invention can be understood as appropriate to those of ordinary skill in the art.
The light emitting layer in the OLED display panel includes light emitting layers of different color sub-pixels, and the electron injection layer, the electron transport layer, the hole injection layer and the hole transport layer corresponding to the light emitting layers of the different color sub-pixels are usually common layers. This results in the possibility of lateral electron transport to adjacent sub-pixels during use, and common layer leakage causes cross talk, resulting in the problem of poor brightness and inaccurate color display for adjacent sub-pixels.
The present invention has been made to alleviate or solve, at least to some extent, the above-mentioned technical problems. For better understanding of the present invention, the display panel, the method for manufacturing the display panel, and the display device according to the embodiments of the present invention are described in detail below with reference to fig. 1 to 15.
Fig. 1 and fig. 2 are schematic structural diagrams of a display panel according to an embodiment of the invention.
According to the display panel provided by the embodiment of the first aspect of the present invention, the display panel has a display area AA. Optionally, the display panel may further have a non-display area NA. In some optional embodiments, in order to facilitate the under-screen integration of the photosensitive component, the display panel further has an opening area KA, and a through hole may be formed in the opening area KA, so that the photosensitive component obtains the optical information through the through hole.
Referring to fig. 2 and 3 together, fig. 2 is a schematic view of a portion of the enlarged structure at P in fig. 1, and fig. 3 is a cross-sectional view at a-a in fig. 2.
As shown in fig. 2, the display panel includes a plurality of sub-pixels, for example, a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13, wherein the first sub-pixel 11 is, for example, a red sub-pixel, the second sub-pixel 12 is, for example, a green sub-pixel, and the third sub-pixel 13 is, for example, a blue sub-pixel. Only three sub-pixels are illustrated in fig. 2.
As shown in fig. 3, an embodiment of the first aspect of the present invention provides a display panel including: a substrate 100; the functional layer 200 at least comprises an opening layer 220 and a pixel defining layer 210 located on one side of the opening layer 220, which is far away from the substrate 100, wherein the pixel defining layer 210 comprises a body portion 211 and a pixel opening 212 which penetrates through the body portion 211, the functional layer 200 is provided with an isolation through hole 230 which is arranged in a penetrating manner, the isolation through hole 230 comprises a first isolation opening 231 located on the opening layer 220, a second isolation opening 232 located on one side of the first isolation opening 231, which is far away from the substrate 100, and a first communication hole 233 which communicates the first isolation opening 231 with the second isolation opening 232, wherein a first orthographic projection of the first isolation opening 231 on the substrate 100 and an orthographic projection of the pixel opening 212 on the substrate 100 are arranged in a staggered manner, the size of the first orthographic projection is larger than that of the first communication hole 233 on the substrate 100, and an isolation gap 235 which is arranged in a staggered manner with the first communication hole 233 is arranged in the first isolation opening 231.
The present invention is illustrated in fig. 2 as the location and size of the isolation gap 235 in a top view. The position of the first communication opening 233 is indicated by a chain line in fig. 3, and the chain line does not limit the structure of the embodiment of the present invention.
Optionally, the display panel further includes a charge carrier layer 400, and the charge carrier layer 400 is located on a side of the pixel defining layer 210 facing away from the opening layer 220.
Optionally, the pixel opening 212 on the pixel defining layer 210 and the plurality of sub-pixels are disposed correspondingly, and each pixel opening 212 is disposed correspondingly to each sub-pixel.
In the display panel provided in the embodiment of the present invention, the display panel includes the substrate 100 and the functional layer 200 that are sequentially stacked, the functional layer 200 is provided with the isolation through hole 230, the isolation through hole 230 includes the first isolation opening 231 and the second isolation opening 232, and when the charge carrier layer 400 is disposed on the pixel defining layer 210, the material of the charge carrier layer 400 enters the first isolation opening 231 from the second isolation opening 232. The first orthographic projection of the first isolation opening 231 on the substrate 100 is offset from the orthographic projection of the pixel opening 212 on the substrate 100, that is, the first isolation opening 231 and the pixel opening 212 are offset in the thickness direction (Z direction in fig. 3) of the display panel, so that the first isolation opening 231 does not affect the formation of the pixel opening 212.
The first orthogonal projection is larger than the orthogonal projection of the first communication port 233 on the substrate 100, and the first isolation opening 231 can have an isolation gap 235 provided offset from the first communication port 233. When carrier layer 400 is formed on pixel defining layer 210, at least a portion of the material of carrier layer 400 may not enter into isolation gap 235. As shown in fig. 3, the carrier layer 400 is disconnected at the isolation gap 235, so that the connection area of the carrier layer 400 can be reduced, the lateral current is reduced, the low gray level color shift of the display screen caused by the current crosstalk is improved, and the display effect of the display panel is improved.
In the present invention, a horizontal current is opposite to a vertical current, which is a current flowing in the thickness direction of the display panel and capable of driving the display panel to emit light. Lateral current refers to current flowing within carrier layer 400.
The substrate 100 may be made of a light-transmitting material such as glass or Polyimide (PI).
There are various ways of disposing the functional layer 200, and the optional functional layer 200 further includes a pixel electrode layer disposed between the pixel defining layer 210 and the opening layer 220, where the pixel electrode layer includes, for example, a plurality of first electrodes, and each first electrode is disposed corresponding to each pixel opening 212. So that one sub-pixel can be driven to emit light when one of the first electrodes is energized.
The carrier layer 400 can be disposed in various ways, and the carrier layer 400 includes, but is not limited to, at least one of an electron injection layer, an electron transport layer, an electron blocking layer, a hole injection layer, and a hole transport layer. Alternatively, when the charge carrier layer 400 includes a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, which are sequentially stacked in the direction from the opening layer 220 to the pixel defining layer 210, the layer separated in the separation gap 235 may be the hole injection layer. In these embodiments, the hole injection layer is disconnected at the isolation gap 235, so that the lateral flow of electrons can be effectively blocked, the lateral current can be reduced, the low gray scale color cast of the display screen caused by current crosstalk can be avoided, and the display effect of the display panel can be improved.
In other embodiments, what is broken off at the separation gap 235 may be a hole injection layer and a hole transport layer, or a hole injection layer, a hole transport layer, and an electron transport layer, or a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, all of which are broken off at the separation gap 235. I.e., at least the hole injection layer is open at the isolation gap 235.
In some alternative embodiments, the isolation gap 235 is disposed around the periphery of the first communication opening 233. The size of the isolation gap 235 can be increased, the communication area of the carrier layer 400 is further reduced, the transverse current is further reduced, the low gray scale color cast of a display picture caused by current crosstalk is improved, and the display effect of the display panel is improved.
Optionally, the center of the first orthographic projection overlaps with the center of the second orthographic projection of the second isolation opening 232 on the substrate 100.
In these alternative embodiments, when the center of the first orthographic projection overlaps the center of the second orthographic projection, the isolation gap 235 can be formed on the peripheral side of the second orthographic projection, the area of the isolation gap 235 is increased, the communication area of the carrier layer 400 is reduced, the lateral current is reduced, the low gray scale color cast of the display screen caused by the current crosstalk is improved, and the display effect of the display panel is improved.
The isolation gap 235 may be disposed in various shapes, and the isolation gap 235 is, for example, a stripe shape and disposed around the periphery of the pixel opening 212.
The number of the second isolation openings 232 may be provided with one or more.
Alternatively, when the number of the second isolation openings 232 is plural, as shown in fig. 2, the plural second isolation openings 232 are distributed at intervals on the peripheral side of each pixel opening 212; the number of the first isolation openings 231 is plural, and each of the first isolation openings 231 and each of the second isolation openings 232 are provided corresponding to each other in the thickness direction of the display panel.
In these alternative embodiments, the plurality of second isolation openings 232 are distributed at intervals on the peripheral side of each pixel opening 212, that is, a gap is left between two adjacent second isolation openings 232, and the carrier layer 400 and the common electrode are not disconnected between two adjacent second isolation openings 232, so that the common electrodes at different positions are ensured to be connected with each other.
The arrangement of the first isolation openings 231 and the second isolation openings 232 is: the first isolation opening 231 is provided on a side of each second isolation opening 232 facing the substrate 100, and each first isolation opening 231 is communicated with each second isolation opening 232. So that an isolation gap 235 can be formed in each first isolation opening 231, and the carrier layer 400 is disconnected in the isolation gap 235 corresponding to the second isolation opening 232. The area of the isolation gap 235 can be increased, the communication area of the carrier layer 400 is reduced, the transverse current is reduced, the low gray scale color cast of a display picture caused by current crosstalk is improved, and the display effect of the display panel is improved.
Referring to fig. 4, fig. 4 is a cross-sectional view taken along a line a in another embodiment of the second aspect of the present invention.
In the embodiment shown in fig. 4, the opening layer 220 is disposed in direct contact with the pixel defining layer 210.
Such as the opening layer 220, is located on the planarization layer 270 of the pixel defining layer 210 on the side facing the substrate 100. When the opening layer 220 is located on the planarization layer 270, the opening layer 220 is formed on the entire planarization layer 270, and the first isolation opening 231 is disposed through the planarization layer 270; or the opening layer 220 is formed on the planarization layer 270 partially adjacent to the pixel defining layer 210, the first isolation opening 231 is recessed on the planarization layer 270, and the first isolation opening 231 is not disposed through the planarization layer 270.
In these alternative embodiments, the planarization layer 270 has a first isolation opening 231 formed thereon, the side of the body portion 211 of the pixel defining layer 210 facing the planarization layer 270 forms an isolation gap 235, and the carrier layer 400 is disconnected at the isolation gap 235.
In other alternative embodiments, as shown in FIG. 3, functional layer 200 further comprises: the spacer layer 240 and the second isolation opening 232 extend from the pixel defining layer 210 to the spacer layer 240.
In these alternative embodiments, a spacer layer 240 is further disposed between the opening layer 220 and the pixel defining layer 210, and the second isolation opening 232 extends from the pixel defining layer 210 to the spacer layer 240, so that an isolation gap 235 can be formed in the opening layer 220.
There are various positions for disposing the spacing layer 240 and the opening layer 220, and in some alternative embodiments, the display panel further includes: a planarization layer 270 between the substrate 100 and the pixel defining layer 210; the signal line layer 260 is located on a side of the planarization layer 270 away from the pixel defining layer 210, the opening layer 220 is located on the signal line layer 260, and the spacer layer 240 is the planarization layer 270.
In these alternative embodiments, the opening layer 220 is located on the signal line layer 260, the spacer layer 240 is a planarization layer 270, a first isolation opening 231 is formed on the signal line layer 260, a third isolation opening 234 is formed on the planarization layer 270, and a first isolation opening 231 is formed on the pixel defining layer 210. An isolation gap 235 is formed on a side of the planarization layer 270 facing away from the pixel defining layer 210, and the carrier layer 400 is disconnected within the isolation gap 235.
When the opening layer 220 is located on the signal line layer 260, the entire signal line layer 260 forms the opening layer 220, and the first isolation opening 231 is disposed through the signal line layer 260; or a portion of the signal line layer 260 forms the opening layer 220, and the first isolation opening 231 forms a groove on the signal line layer 260; alternatively, the signal line layer 260 has a through-hole, the isolation gap 235 is provided near the signal line layer 260 toward the center of the hole wall of the through-hole in the thickness direction, and the first isolation opening 231 is provided near the signal line layer 260 toward the center of the hole wall of the through-hole in the thickness direction.
Referring to fig. 5, fig. 5 is a cross-sectional view taken along line a-a in yet another embodiment of the first aspect of the present invention.
In some alternative embodiments, the signal line layer 260 includes a plurality of layers, and the isolation gap 235 is located on a layer of the plurality of layers that is near a middle of the signal line layer 260 in a thickness direction.
For example, the signal line layer 260 includes a first sub-layer 261, a second sub-layer 262, and a third sub-layer 263 sequentially stacked under the planarization layer 270, the second isolation opening 232 is disposed through the first sub-layer 261, and the second isolation opening 232 is disposed through the second sub-layer 262. The second layered layer 262 is an opening layer 220. The isolation via 230 further includes a third isolation opening 234 located on a side of the first isolation opening 231 facing away from the second isolation opening 232, and the third isolation opening 234 is disposed through the third layered layer 263. The size of the third isolation opening 234 is smaller than the size of the first isolation opening 231 to form an isolation gap 235 at the second delamination layer 262.
For example, when the signal line layer 260 is a metal layer and the signal line layer 260 includes a plurality of metal layers, for example, the signal line layer 260 includes a titanium layer, an aluminum layer, and a titanium layer sequentially stacked. A via may be formed on the signal line layer 260 first and then the signal line layer 260 is subjected to an etching process to etch a portion of the aluminum material to form the isolation gap 235 on the aluminum layer.
There are various types of display panels, and an alternative display panel is, for example, a full-screen display panel.
In other optional embodiments, the display panel is an open-cell display panel, the display panel has an open-cell area KA and a display area AA surrounding the open-cell area KA, and the open-cell area KA is provided with a through hole, so that sensors such as a camera can acquire information through the through hole.
Referring to fig. 6, fig. 6 is a cross-sectional view taken along line B-B of fig. 1.
In some alternative embodiments, a sealing through hole 250 penetrating through the functional layer 200 is formed in the aperture area KA, and the sealing through hole 250 includes a first sealing opening 251 located in the opening layer 220, a second sealing opening 252 located on a side of the first sealing opening 251 facing away from the substrate 100, and a second communication port 253 communicating the first sealing opening 251 and the second sealing opening 252, wherein a third orthographic projection of the first sealing opening 251 on the substrate 100 is offset from an orthographic projection of the pixel opening 212 on the substrate 100, a size of the third orthographic projection is larger than a size of an orthographic projection of the second communication port 253 on the substrate 100, and a sealing gap 255 is formed in the first sealing opening 251 and offset from the second communication port 253.
In these alternative embodiments, when the sealing layer 700 is formed by performing a sealing process on the display panel, the sealing layer 700 may be formed in the sealing gap 255 to achieve a complete sealing of the display panel and improve the sealing effect of the display panel.
When the display panel includes the pixel defining layer 210, the planarization layer 270 on the side of the pixel defining layer 210 facing the substrate 100, and the signal line layer 260 on the side of the planarization layer 270 facing the substrate 100, the sealing via 250 generally penetrates through the pixel defining layer 210, the planarization layer 270, and the signal line layer 260. Optionally, the opening layer 220 is located on the signal line layer 260, the functional layer 200 further includes a planarization layer 270 located between the signal line layer 260 and the pixel defining layer 210, and the second isolation opening 232 and the second sealing opening 252 are disposed through the pixel defining layer 210 and the planarization layer 270.
In the display panel provided in these alternative embodiments, the isolation gap 235 and the sealing gap 255 may be formed by using the same process flow or in the same process step, which can simplify the forming process of the display panel and improve the forming efficiency of the display panel.
As shown in fig. 6, the signal line layer 260 includes a first sub-layer 261, a second sub-layer 262, and a third sub-layer 263, the second sealing opening 252 is disposed through the first sub-layer 261, and the second sealing opening 252 is disposed through the second sub-layer 262. The second layered layer 262 is an open layer 220, and the sealed via 250 further includes a third sealed opening 254 on a side of the first sealed opening 251 facing away from the second sealed opening 252, the third sealed opening 254 being disposed through the third layered layer 263. The third seal opening 254 is smaller in size than the first seal opening 251 to form a seal gap 255 in the second split layer 262.
Optionally, a dam 800 is further disposed in the opening area KA to improve the sealing effect of the display panel.
Alternatively, a part of the signal line layer 260 is exposed at a side of the dam 800 facing away from the display area AA. The pixel defining layer 210 and the planarization layer 270 are not disposed on the portion of the signal line layer 260 so that the sealing layer 700 can directly contact the signal line layer 260.
Fig. 7 is a cross-sectional view taken at B-B of fig. 1 in another embodiment, as shown in fig. 7.
The display panel further includes a carrier layer 400, a light emitting structure 500, and a common electrode 600, and when the light emitting structure 500 is deposited, a portion of the material of the light emitting structure 500 is deposited on the signal line layer 260 in the opening area KA.
Optionally, the display panel further includes a sealing layer 700, and the sealing layer 700 includes a first inorganic layer 710, a second organic layer 720, and a third inorganic layer 730 sequentially stacked on the common electrode 600. Optionally, the second organic layer 720 is not disposed on a side of the bank 800 facing the opening area KA. The first inorganic layer 710 and the third inorganic layer 730 can be deposited on the isolation gap 235 and the sealing gap 255 to secure a sealing effect, and the second organic layer 720 can fill pits that occur due to the provision of the isolation through-hole 230 and the sealing through-hole 250.
In other alternative embodiments, the layer structure of the display panel may further include: a first insulating layer 310 on a side of the signal line layer 260 facing away from the planarization layer 270; a first conductive line layer on a side of the first insulating layer 310 away from the signal line layer 260; a second insulating layer 330 on a side of the first wire layer facing away from the first insulating layer 310; and a second conductive line layer on a side of the second insulating layer 330 away from the first conductive line layer.
The second conductive line layer may be, for example, a capacitor gate layer, or the second conductive line layer may be a gate layer. The first wiring layer is, for example, a source/drain electrode layer, and the first insulating layer 310 may also serve as a planarization layer.
In other alternative embodiments, the opening layer 220 may also be on one of the first insulating layer 310, the first wire layer, and the second insulating layer 330. For example, when the opening layer 220 is the first insulating layer 310, the signal line layer 260 and the planarization layer 270 are the spacer layer 240, and the third isolation opening 234 is formed on both the signal line layer 260 and the planarization layer 270. For example, when the opening layer 220 is a first conductive line layer, the first insulating layer 310, the signal line layer 260 and the planarization layer 270 are the spacer layer 240, and third isolation openings 234 are formed on the first insulating layer 310, the signal line layer 260 and the planarization layer 270. When the second insulating layer 330 is the opening layer 220, the first wire layer, the first insulating layer 310, the signal line layer 260 and the planarization layer 270 are the spacing layer 240, and the first wire layer, the first insulating layer 310, the signal line layer 260 and the planarization layer 270 are all provided with third isolation openings 234.
In some alternative embodiments, charge carrier layer 400 has first thickness d1(ii) a The opening layer 220 has a second thickness d2A second thickness d2And a first thickness d1Satisfies the following conditions: d2≥d1
In these alternative embodiments, the first and second electrodes are,second thickness d of opening layer 2202Larger, it can avoid carrier layer 400 from blocking at the side of isolation gap 235 facing into third isolation opening 234, and ensure that carrier layer 400 can be disconnected at isolation gap 235.
Alternatively, when carrier layer 400 includes at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer, carrier layer 400 may include only the hole injection layer, and then the thickness of carrier layer 400 is the thickness of the hole injection layer, or carrier layer 400 includes the hole transport layer and the hole injection layer, and the thickness of carrier layer 400 is the total thickness of the hole transport layer and the hole injection layer.
Optionally, a second thickness d2And a first thickness d1Satisfies the following conditions: d2≥3d1Further ensuring that carrier layer 400 can be broken at isolation gap 235.
Optionally, a second thickness
Figure BDA0003098002820000131
Second thickness d2Larger, further ensuring that carrier layer 400 can break at isolation gap 235.
In some alternative embodiments, the edge of the first isolation opening 231 has a maximum distance H from the edge of the second isolation opening 232, the maximum distance H and the first thickness d1Satisfies the following conditions: h is not less than d1
In these alternative embodiments, the maximum distance H between the edge of the first isolation opening 231 and the edge of the second isolation opening 232 is larger, that is, the extension of the isolation gap 235 in the plane is larger, so that the carrier layer 400 can be disconnected at the isolation gap 235.
Optionally, the maximum distance H and the first thickness d1Satisfies the following conditions: h is more than or equal to 3d1Further ensuring that carrier layer 400 can be broken at isolation gap 235.
Embodiments of the second aspect of the present invention further provide a display device, including the display panel of any one of the embodiments of the first aspect. Since the display device of the embodiment of the invention includes the display panel, the display device of the embodiment of the invention has the beneficial effects of the display panel, and the description is omitted here.
The display device in the embodiment of the present invention includes, but is not limited to, a mobile phone, a Personal Digital Assistant (PDA), a tablet computer, an electronic book, a television, a door lock, a smart phone, a console, and other devices having a display function.
Referring to fig. 8, fig. 8 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the third aspect of the present invention. The display panel may be the display panel of any of the embodiments of the first aspect described above.
As shown in fig. 8, the preparation method includes:
step S01: a substrate 100 is provided.
Step S02: a layer of functional material is provided on the substrate 100, the layer of functional material comprising at least a layer of opening material and a layer of pixel defining material on a side of the layer of opening material facing away from the substrate 100.
Step S03: the pixel defining material layer is patterned to form a body portion 211 and a pixel opening 212 penetrating the body portion 211.
Step S04: the functional layer 200 is patterned to form a transitional via extending from the pixel defining material layer to the opening material layer.
Step S05: and etching the opening material layer, increasing the size of the transition opening to form a first isolation opening 231, and forming a second isolation opening 232 positioned on one side of the first isolation opening 231, which is far away from the substrate 100, and a first communication port 233 for communicating the first isolation opening 231 and the second isolation opening 232 by the transition through hole.
The first orthographic projection of the first isolation opening 231 on the substrate 100 is offset from the orthographic projection of the pixel opening 212 on the substrate 100, the size of the first orthographic projection is larger than the size of the orthographic projection of the first communication opening 233 on the substrate 100, and an isolation gap 235 offset from the first communication opening 233 is arranged in the first isolation opening 231.
The display panel formed by the preparation method of the present invention can form the isolation gap 235. When the carrier layer 400 is formed on the pixel defining layer 210, the material of the carrier layer 400 may not enter the isolation gap 235, so that the carrier layer 400 is disconnected at the isolation gap 235, the connection area of the carrier layer 400 can be reduced, the lateral current is reduced, the low gray scale color cast of the display screen caused by the current crosstalk is improved, and the display effect of the display panel is improved.
Optionally, the layer where the first isolation opening 231 is located is an opening layer 220, the opening layer 220 is, for example, a planarization layer 270 located on a side of the pixel defining layer 210 facing the substrate 100 and at least partially contacting the pixel defining layer 210, the display panel further includes an array substrate located on a side of the planarization layer 270 facing away from the pixel defining layer 210, and then forming the array substrate on the substrate 100 may be further included before step S02.
Optionally, the array substrate includes a signal line layer 260, a first insulating layer 310 on a side of the signal line layer 260 facing away from the planarization, a first wire layer on the first insulating layer 310 facing away from the signal line layer 260, a second insulating layer 330 on a side of the first wire layer facing away from the first insulating layer 310, and the like.
Optionally, when the opening layer 220 is the signal line layer 260 and the like and is located on the side of the planarization layer 270 away from the pixel defining layer 210, a spacing layer 240 is further disposed between the opening layer 220 and the pixel defining layer 210, and after step S02, the method further includes: a spacer material layer is formed on the side of the opening material layer facing away from the substrate 100. Then in step S04, the opening material layer, the spacer material layer, and the pixel definition layer 210 are patterned to form a transitional via extending from the pixel definition material layer to the opening material layer.
In some alternative embodiments, the display panel has an opening area KA and a display area AA surrounding the opening area KA, a sealing through hole 250 penetrating through the functional layer 200 is formed in the opening area KA, and the sealing through hole 250 includes a first sealing opening 251 located in the opening layer 220, a second sealing opening 252 located on a side of the first sealing opening 251 facing away from the substrate 100, and a second communication opening 253 communicating with the first sealing opening 251 and the second sealing opening 252, wherein a third orthographic projection of the first sealing opening 251 on the substrate 100 is offset from an orthographic projection of the pixel opening 212 on the substrate 100, a size of the third orthographic projection is larger than a size of an orthographic projection of the second communication opening 253 on the substrate 100, and a sealing gap 255 offset from the second communication opening 253 is formed in the first sealing opening 251.
Then, when the opening layer 220 is located on the signal line layer 260, the signal line layer 260 has the first isolation opening 231, and the planarization layer 270 and the pixel definition layer 210 have the second isolation opening 232, in step S4: the opening material layer (i.e., the signal line layer 260), the spacer material layer (i.e., the planarization layer 270), and the pixel defining layer 210 are patterned to form a first isolation opening 231 and a first sealing opening 251 on the opening material layer, and a second isolation opening 232 and a second sealing opening 252 on the spacer material layer and the pixel defining layer 210.
Referring to fig. 9 to 15, a method for manufacturing a display panel will be described below by taking the display panel structure shown in fig. 7 as an example. The manufacturing method of the display panel comprises the following steps:
the method comprises the following steps: as shown in fig. 9, a substrate 100 is provided, and a second conductive layer 340, a second insulating layer 330, a first conductive layer 320, and a first insulating layer 310 are formed over the substrate 100.
Step two: as shown in fig. 10, a signal line material layer is formed on a side of the first insulating layer 310 facing away from the first conductive layer 320.
Optionally, when the signal line layer 260 needs to be connected to a conductive line of the first conductive layer 320, a patterning process may be performed on the first insulating layer 310 to form a via hole in the first step, so that at least a portion of the first conductive layer 320 is exposed by the via hole. In step two, the signal material may enter the via and connect with the conductive line of the first conductive layer 320.
Optionally, when the signal line layer 260 includes a signal line, the signal line material layer may be patterned in the second step to form a signal line.
Step three: as shown in fig. 11, a planarization material layer is formed on a side of the signal line material layer facing away from the first insulating layer 310.
Optionally, when the pixel electrode in the pixel electrode layer needs to pass through the planarization layer 270 and be connected to the signal line layer 260, the planarization material layer may be patterned in step three to form a via hole corresponding to the pixel electrode. The planarization material partially located in the open region may also form part of the bank 800 when the planarization material is processed.
Step four: as shown in fig. 12, a pixel electrode material layer is formed on the planarization material layer, and a patterning process is performed on the pixel electrode material layer to form a pixel electrode.
Step five: as shown in fig. 13, a pixel defining material layer is disposed on a side of the pixel electrode material layer facing away from the substrate 100, and the pixel defining material layer is patterned to form a body portion 211 and a pixel opening 212 penetrating the body portion 211.
Optionally, the pixel defining layer 210 may be patterned to form a part of the dam 800.
Step six: as shown in fig. 14, the signal line material layer, the planarization material layer, and the pixel defining material layer are subjected to a hole opening process to form a first transition opening and a second transition opening on the signal line material layer, and to form a second isolation opening 232 and a second sealing opening 252 on the planarization material layer and the pixel defining layer 210.
Step seven: as shown in fig. 15, the signal line material layer is etched to increase the size of the first and second transition openings to form a first isolation opening 231 and a first sealing opening 251, so as to form an isolation gap 235 and a sealing gap 255 on a side of the planarization layer 270 facing away from the pixel defining layer 210.
After the separation gap 235 and the sealing gap 255 are formed, the carrier layer 400, the light emitting material layer, the common electrode 600, the first sealing layer 700, the second sealing layer 700, and the third sealing layer 700 are continuously disposed on the pixel defining layer 210 to form the display panel as shown in fig. 7.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (10)

1. A display panel, comprising:
a substrate;
the functional layer at least comprises an opening layer and a pixel defining layer positioned on one side of the opening layer, which is far away from the substrate, wherein the pixel defining layer comprises a body part and a pixel opening which penetrates through the body part;
the first orthographic projection of the first isolation opening on the substrate and the orthographic projection of the pixel opening on the substrate are arranged in a staggered mode, the size of the first orthographic projection is larger than that of the orthographic projection of the first communication opening on the substrate, and an isolation gap arranged in a staggered mode with the first communication opening is formed in the first isolation opening.
2. The display panel according to claim 1,
the isolation gap is arranged around the periphery of the first communication port;
preferably, a center of the first orthographic projection overlaps a center of a second orthographic projection of the second isolation opening on the substrate.
3. The display panel according to claim 1,
the number of the second isolation openings is multiple, and the second isolation openings are distributed at intervals on the peripheral side of each pixel opening;
the number of the first isolation openings is multiple, and each first isolation opening and each second isolation opening are correspondingly arranged in the thickness direction of the display panel.
4. The display panel according to claim 1, wherein the second isolation opening is opened in the pixel definition layer, and the opening layer is located in a planarization layer on a side of the pixel definition layer facing the substrate layer.
5. The display panel according to claim 1, wherein the functional layer further comprises: a spacer layer between the opening layer and the pixel defining layer, the second isolation opening extending from the pixel defining layer to the spacer layer.
6. The display panel according to claim 5, wherein the display panel has an opening area and a display area surrounding the opening area,
the opening area is internally provided with a sealing through hole penetrating through the functional layer, the sealing through hole comprises a first sealing opening positioned on the opening layer, a second sealing opening positioned on one side of the first sealing opening, which is far away from the substrate, and a second communication opening communicated with the first sealing opening and the second sealing opening,
and a third orthographic projection of the first sealing opening on the substrate and an orthographic projection of the pixel opening on the substrate are arranged in a staggered mode, the size of the third orthographic projection is larger than that of the orthographic projection of the second communication opening on the substrate, and a sealing gap arranged in a staggered mode with the second communication opening is formed in the first sealing opening.
7. The display panel according to claim 1, further comprising:
a charge carrier layer located on a side of the pixel defining layer facing away from the opening layer, the charge carrier layer having a first thickness d1
The opening layer has a second thickness d2Said second thickness d2And the first thickness d1Satisfies the following conditions: d2≥d1
Preferably, the second thickness d2And the first thickness d1Satisfies the following conditions: d2≥3d1
Preferably, the second thickness
Figure FDA0003098002810000021
8. The display panel according to claim 7, wherein the edge of the first isolation opening and the edge of the second isolation opening have a maximum distance H therebetween, and the maximum distance H and the first thickness d are1Satisfies the following conditions: h is not less than d1
Preferably, the maximum distance H and the first thickness d1Satisfies the following conditions: h is more than or equal to 3d1
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
10. A method for manufacturing a display panel, comprising:
providing a substrate;
arranging a functional material layer on the substrate, wherein the functional material layer at least comprises an opening material layer and a pixel definition material layer positioned on one side of the opening material layer, which is far away from the substrate;
patterning the pixel defining material layer to form a body portion and a pixel opening penetrating through the body portion;
patterning the functional layer to form a transition through hole extending from the pixel definition material layer to the opening material layer;
etching the opening material layer, increasing the size of the transition opening to form a first isolation opening, enabling the transition through hole to form a second isolation opening which is positioned on one side of the first isolation opening and a first communication opening which is communicated with the first isolation opening and the second isolation opening, enabling a first orthographic projection of the first isolation opening on the substrate and an orthographic projection of the pixel opening on the substrate to be arranged in a staggered mode, enabling the size of the first orthographic projection to be larger than that of the orthographic projection of the first communication opening on the substrate, and enabling an isolation gap which is arranged in a staggered mode with the first communication opening to be arranged in the first isolation opening.
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