CN216213464U

CN216213464U - Display substrate and display device

Info

Publication number: CN216213464U
Application number: CN202122078591.2U
Authority: CN
Inventors: 刘肖楠; 李军; 池昶恂; 尚庭华; 徐倩
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2022-04-05
Anticipated expiration: 2031-08-31

Abstract

The present disclosure provides a display substrate and a display device, which belong to the technical field of display and can at least partially solve one of the existing technical problems. The display substrate comprises a substrate and a plurality of sub-pixels arranged on the substrate at intervals in an array; a spacer region is arranged between the adjacent sub-pixels; the spacer region comprises a first spacer region with functional bits and a second spacer region without functional bits; at least part of the function positions are provided with function parts; the width of the first interval region between two adjacent sub-pixels arranged along the first direction or the second direction is larger than the width of the second interval region between two adjacent sub-pixels arranged along the same direction; the width of the interval area is equal to the shortest distance between the boundaries of the two sub-pixels corresponding to the interval area.

Description

Display substrate and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display device.

Background

Organic Light Emitting Diode (OLED) Display is an important Display mode, and compared with Liquid Crystal Display (LCD), OLED Display has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle, fast response speed, and the like, so that OLED Display is widely applied to the fields of mobile phones, tablet computers, digital cameras, and the like.

The OLED display substrate mainly includes a substrate, and a plurality of sub-pixels (or pixel units) arranged in an array (e.g., a matrix) on the substrate, where each sub-pixel includes an OLED device. The OLED device is formed by an evaporation process, that is, organic materials are controlled to pass through an opening on a high-definition Metal Mask (FMM) to form a structure such as an emission layer (EML) of the OLED device.

SUMMERY OF THE UTILITY MODEL

The present disclosure at least partially solves one of the problems of the prior art, and provides a display substrate and a display device.

In a first aspect, an embodiment of the present disclosure provides a display substrate, which includes a substrate, and a plurality of sub-pixels arranged on the substrate at intervals in an array;

a spacer region is arranged between the adjacent sub-pixels; the spacer region comprises a first spacer region with functional bits and a second spacer region without functional bits;

at least part of the function positions are provided with function parts;

the width of the first interval region between two adjacent sub-pixels arranged along the first direction or the second direction is larger than the width of the second interval region between two adjacent sub-pixels arranged along the same direction; the width of the interval area is equal to the shortest distance between the boundaries of the two sub-pixels corresponding to the interval area.

In some embodiments, the first spacer has a width greater than or equal to 20 μm.

In some embodiments, the distance between the boundary of the function and the boundary of the closest sub-pixel is greater than or equal to 3 μm.

In some embodiments, the width of the second spacer region is less than or equal to 19 μm.

In some embodiments, at least a part of the shortest connecting line between the boundaries of two sub-pixels corresponding to the first spacing area passes through the functional element in the first spacing area.

In some embodiments, in a cross section passing through the shortest connecting line and perpendicular to the substrate base plate, a distance between boundaries of two sub-pixels corresponding to the first spacer is greater than or equal to 20 μm, and a distance between the functional element in the first spacer and the sub-pixel is greater than or equal to 3 μm.

In some embodiments, at least a portion of a line connecting geometric centers of two sub-pixels corresponding to the first spacer passes through the functional element in the first spacer.

In some embodiments, at least a portion of a connection line between the geometric centers of the two sub-pixels corresponding to the first spacer passes through the geometric center of the functional element in the first spacer.

In some embodiments, at least a portion of the first spacers extend in the third direction;

at least a portion of the first spacer region extends in a fourth direction; the fourth direction intersects the third direction;

the first spacers extending at least partially in the third direction and the first spacers extending in the fourth direction have an overlap region, and at least part of the functional element at least partially overlaps the overlap region.

In some embodiments, the distance between adjacent said features is between 100 μm and 300 μm.

In some embodiments, the number of functional bits provided with said function is at least 15% of the total number of functions.

In some embodiments, the display substrate further comprises a pixel defining layer;

the pixel definition layer comprises pixel definition layer openings and pixel definition parts positioned between the pixel definition layer openings;

the pixel defining layer opening defines a light emitting area of the sub-pixel;

the functional part is arranged on one side of the pixel defining part, which is far away from the substrate base plate.

In some embodiments, the functional element is a unitary structure with the pixel defining part.

In some embodiments, among the plurality of sub-pixels adjacent to at least part of the functional element, at least one of the sub-pixels has a geometric center that is offset from a straight line extending in the first direction, and geometric centers of at least two sub-pixels that are in the same row as the sub-pixel in the first direction are located on the straight line;

and/or the presence of a gas in the gas,

among a plurality of sub-pixels adjacent to at least a part of the functional element, at least one of the sub-pixels has a geometric center that is offset from a straight line extending in the second direction, and geometric centers of at least two sub-pixels located in the same row as the sub-pixel in the second direction are located on the straight line; the second direction intersects the first direction.

In some embodiments, the sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel;

the first sub-pixels and the third sub-pixels are alternately arranged along a first direction to form a first pixel group, and are alternately arranged along a second direction to form a third pixel group; the second direction intersects the first direction;

the second sub-pixels are arranged along the first direction to form a second pixel group, and are arranged along the second direction to form a fourth pixel group;

wherein the first pixel groups and the second pixel groups are alternately arranged along the second direction; the third pixel groups and the fourth pixel groups are alternately arranged along the first direction.

In some embodiments, among the spacers between the first sub-pixel and the third sub-pixel adjacent in the third pixel group, at least a part of the spacers is the first spacers;

the spacer between the first sub-pixel and the third sub-pixel adjacent to each other in the first pixel group is the second spacer.

In some embodiments, the spacers between the first sub-pixel and the third sub-pixel adjacent in the third pixel group alternate into the first spacer and the second spacer along the second direction;

in two adjacent third pixel groups, one of the first spacer regions in one of the third pixel groups and one of the second spacer regions in the other of the third pixel groups are located between two rows of sub-pixels arranged along the first direction.

In some embodiments, the sequential connection line of the geometric centers of the two first sub-pixels and the two third sub-pixels arranged in an array forms a virtual trapezoid;

the spacer between the first sub-pixel and the third sub-pixel corresponding to the bottom side of the virtual trapezoid is the first spacer, and the spacer between the first sub-pixel and the third sub-pixel corresponding to the top side of the virtual trapezoid is the second spacer.

In some embodiments, a base of the virtual trapezoid is parallel to the second direction.

In some embodiments, the virtual trapezoid is a virtual isosceles trapezoid.

In some embodiments, in the first spacer at least partially located between the adjacent first sub-pixel and the third sub-pixel, the geometric center of the functional element is located on a line between the geometric center of the first sub-pixel and the geometric center of the third sub-pixel corresponding to the first spacer.

In some embodiments, in the first spacer at least partially located between the adjacent first sub-pixel and the third sub-pixel, along the second direction, a distance between a geometric center of the functional element and a geometric center of the first sub-pixel corresponding to the first spacer is smaller than a distance between a geometric center of the functional bit and a geometric center of the third sub-pixel corresponding to the first spacer.

In some embodiments, in the first spacer at least partially located between the adjacent first sub-pixel and the third sub-pixel, along the second direction, the geometric center of the functional element is located on a side of the reference line corresponding to the functional element, which is close to the first sub-pixel corresponding to the first spacer; and the reference line of the functional bit is a connecting line between the geometric centers of the two second sub-pixels positioned at two sides of the functional bit in the first direction.

In some embodiments, the shape of the first sub-pixel comprises a square or rounded square, one diagonal of the square or rounded square being parallel to the first direction and the other diagonal being parallel to the second direction;

the shape of the third sub-pixel comprises a square or a rounded square, one diagonal of the square or the rounded square is parallel to the first direction, and the other diagonal is parallel to the second direction.

In some embodiments, at least a portion of the third sub-pixels are divided into asymmetric first and second portions along a line passing through the geometric center thereof and parallel to the first direction, and the maximum dimension of the first portion is smaller than the maximum dimension of the second portion along the second direction;

among the first spacers located between the first sub-pixel and the third sub-pixel adjacent in the second direction, at least a part of the first spacers is a spacer between the first part of the third sub-pixel and the adjacent first sub-pixel.

the first sub-pixel pairs and the third sub-pixels are alternately arranged along the first direction to form a fifth pixel group; the first sub-pixel pair includes one first sub-pixel and one second sub-pixel arranged in a second direction; the second direction intersects the first direction;

the first sub-pixels and the second sub-pixels are alternately arranged along a second direction to form a sixth pixel group;

the third sub-pixels are arranged along a second direction to form a seventh pixel group;

wherein the sixth pixel group and the seventh pixel group are alternately arranged along the first direction; the plurality of fifth pixel groups are arranged along the second direction.

In some embodiments, among the spacers between the adjacent third sub-pixels in the seventh pixel group, at least a part of the spacers is the first spacer;

the spacer between the first sub-pixel and the third sub-pixel adjacent to each other in the fifth pixel group and the spacer between the second sub-pixel and the third sub-pixel adjacent to each other are the second spacer;

the second pixel group is formed by a second pixel group, and the second pixel group is formed by a second pixel group.

In some embodiments, at least some of the spacers between the adjacent third sub-pixels in the seventh pixel group alternate between the first spacers and the second spacers along the second direction.

among the first spacers located between the third sub-pixels adjacent in the second direction, at least a part of the first spacers is a spacer between the first parts of the third sub-pixels.

the second sub-pixel pairs, the first sub-pixels and the third sub-pixels are alternately arranged along the first direction to form an eighth pixel group; the second sub-pixel pair comprises two second sub-pixels arranged along the second direction; the second direction intersects the first direction;

a plurality of the eighth pixel groups are arranged in the second direction;

in two adjacent eighth pixel groups, one of the second sub-pixel pairs of one of the eighth pixel groups is located between one of the first sub-pixels and one of the third sub-pixels of the other of the eighth pixel groups along the first direction.

In some embodiments, the spacers are located between two adjacent eighth pixel groups and the adjacent first sub-pixel and the adjacent third sub-pixel, and at least a part of the spacers are the first spacers.

In some embodiments, the spacers are located between two adjacent eighth pixel groups and the first sub-pixel and the second sub-pixel, and at least a part of the spacers is the first spacers.

In some embodiments, two second sub-pixels of the second sub-pixel pair are symmetrically distributed with respect to a line parallel to the first direction.

In some embodiments, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

In some embodiments, the function is to include a spacer, and the function includes a spacer.

In a second aspect, an embodiment of the present disclosure further provides a display device, which includes any one of the display substrates described above.

Drawings

FIG. 1 is a schematic cross-sectional view of a display substrate supporting a high-definition metal mask during deposition in accordance with the related art;

FIG. 2 is a schematic cross-sectional view of a display substrate separated from a high-definition metal mask during deposition according to some related art;

fig. 3 is a circuit diagram of a pixel circuit in a sub-pixel of a display substrate according to an embodiment of the disclosure;

fig. 4 is a schematic partial cross-sectional structure diagram of a display substrate according to an embodiment of the disclosure;

fig. 5 is a schematic diagram illustrating a relationship between a sub-pixel and a light emitting region of the sub-pixel in a display substrate according to an embodiment of the disclosure;

fig. 6 is a schematic view of a local distribution position of a partial structure in a display substrate according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram illustrating the position of a portion of the structure in a cross-section along line XX' in the display substrate of FIG. 6;

fig. 8 is a schematic view illustrating a local distribution position of a partial structure in a display substrate according to an embodiment of the disclosure;

FIG. 9 is an enlarged partial schematic view of FIG. 8;

FIG. 10 is an enlarged, fragmentary, schematic view of another version of FIG. 8;

fig. 11 is a schematic view illustrating distribution positions of a portion of a structure in another display substrate according to an embodiment of the disclosure;

fig. 12 is a schematic view of a local distribution position of a partial structure in another display substrate provided in the embodiment of the present disclosure;

FIG. 13 is an enlarged partial schematic view of FIG. 12;

fig. 14 is a schematic view of a local distribution position of a partial structure in another display substrate provided in the embodiment of the present disclosure;

FIG. 15 is a schematic view of a partial distribution of structures in a display substrate according to an embodiment of the present disclosure;

FIG. 16 is an enlarged partial schematic view of one form of FIG. 15;

FIG. 17 is an enlarged, fragmentary, schematic view of another version of FIG. 15;

fig. 18 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be understood that the specific embodiments and figures described herein are merely illustrative of the disclosure and are not limiting of the disclosure.

It is to be understood that the embodiments of the present disclosure and various features of the embodiments may be combined with each other without conflict.

It is to be understood that, for the convenience of description, only portions related to embodiments of the present disclosure are shown in the drawings of the present disclosure, and portions not related to embodiments of the present disclosure are not shown in the drawings.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. Wherein "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another; similarly, the terms "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one; the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalent, but does not exclude other elements or items; the terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect; "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Before describing aspects of embodiments of the present disclosure in detail, some concepts involved therein are exemplified below.

In the embodiments of the present disclosure, the display substrate refers to a plate-shaped structure with a display structure used in a display device, and more specifically, refers to an Array (Array) substrate with a thin film transistor Array, and further refers to an Array substrate of an Organic Light Emitting Diode (OLED) display.

In the embodiments of the present disclosure, the display substrate includes a substrate base (or referred to as a substrate or a base), which is a basis for carrying other display structures in the display substrate, that is, the other display structures of the display substrate are "disposed" on the substrate base. The substrate base plate can be rigid, such as a rigid material including glass; alternatively, the substrate may be flexible, such as a flexible material including a polymer, and thus may be used in a bendable display device (e.g., a flexible display device, a folding display device, etc.).

In the embodiments of the present disclosure, each "sub-pixel (or pixel unit)" refers to a minimum structure that can be independently controlled to emit light with a desired brightness. Specifically, the sub-pixel may be an organic electroluminescent device (OLED). An organic electroluminescent device is a device composed of a Cathode (Cathode), a light emitting layer, and an Anode (Anode) which are stacked, and the light emitting layer can emit light of different brightness according to the magnitude of current flowing therethrough. The light emitting layer may specifically include a plurality of stacked sub-layers, such as a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an organic light emitting layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

In the embodiment of the present disclosure, the first sub-pixel, the second sub-pixel, and the third sub-pixel represent three sub-pixels with different colors, that is, three sub-pixels capable of emitting light with different colors. The three colors of the first sub-pixel, the second sub-pixel and the third sub-pixel can be three colors of a three-primary color combination, and further can be a red sub-pixel, a green sub-pixel and a blue sub-pixel. In part of the content of the embodiments of the present disclosure, the first sub-pixel is taken as a red sub-pixel, the second sub-pixel is taken as a green sub-pixel, and the third sub-pixel is taken as a blue sub-pixel for illustration; it should be understood, however, that the above description of the first sub-pixel being a red sub-pixel, the second sub-pixel being a green sub-pixel, and the third sub-pixel being a blue sub-pixel does not limit the scope of the embodiments of the present disclosure. The specific manner of making the different types of sub-pixels emit light with different colors is various, for example, the materials of the light emitting layers of the organic electroluminescent devices of the different types of sub-pixels are different, or Color Filters (CF) with different colors are disposed at the different types of sub-pixels, and so on, which will not be described in detail herein.

In the embodiment of the present disclosure, each sub-pixel is configured to be disposed on the substrate, and there are spaces between positions of different sub-pixels, where the spaces are used for disposing pixel circuits for driving the sub-pixels, and various leads, electrodes, and the like for providing driving signals for the pixel circuits. For example, referring to fig. 3, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst, and drives the organic electroluminescent device (OLED) of the corresponding sub-pixel to operate to emit light of a desired luminance under the control of driving signals such as a positive driving signal (VDD), a negative driving signal (VSS), a gate driving signal (Gtae), a Data driving signal (Data), a Reset driving signal (Reset'), an initialization driving signal (Vinit), and a switching driving signal (EM). Since the pixel circuit has seven transistors and one capacitor, it is referred to as a 7T1C pixel circuit. It should be understood that the pixel circuit may be in other specific forms, such as a 2T1C pixel circuit, a 3T1C pixel circuit, etc.

In the embodiments of the present disclosure, a part of the layers of the organic electrode light emitting device of the sub-pixel may exceed the range of the sub-pixel, for example, the cathodes of all the sub-pixels in the whole display substrate may form an integral cathode layer, and the light emitting layer of each sub-pixel may cover the range of the sub-pixel. Therefore, in the embodiment of the present disclosure, the range of the sub-pixel is determined by directly contacting and stacking the cathode, the light emitting layer and the anode to form a region capable of emitting light.

In the embodiment of the present disclosure, a Pixel Definition Layer (PDL) is used to define the range of the above sub-pixels. The pixel definition layer comprises a plurality of pixel definition layer openings, a pixel definition part is arranged between the pixel definition layer openings, the cathode, the light-emitting layer and the anode can be contacted only at the pixel definition layer openings to form the organic electroluminescent device, and even if the cathode, the light-emitting layer and the anode exist at the pixel definition part at the same time, one (such as the anode) is separated from the other two (such as the light-emitting layer and the cathode) by the pixel definition part, so that the organic electroluminescent device cannot be contacted and formed. Therefore, each sub-pixel is located in the pixel defining layer opening of the pixel defining layer, i.e. the range of the pixel defining layer opening is the range of the sub-pixel, and the pixel defining part corresponds to the interval between the sub-pixels.

In the embodiments of the present disclosure, the first direction and the second direction are two directions intersecting each other and parallel to the substrate base plate, i.e., an included angle between the first direction and the second direction may be any angle other than 0. Among them, as one mode of the embodiment of the present disclosure, the first direction and the second direction may further be perpendicular to each other, for example, one of the first direction and the second direction is a row direction and the other is a column direction. In some of the contents of the embodiments of the present disclosure, the first direction is taken as a row direction, and the second direction is taken as a column direction. It should be understood that the up-row direction and the column direction are just two opposite directions in the display substrate, and do not have any necessary relationship with the shape, the placement manner, and the like of the display substrate.

To further explain the structure of the display substrate according to the embodiment of the disclosure, the following describes an exemplary structure of a portion of a film layer in the display substrate according to the embodiment of the disclosure, with reference to the manufacturing method of the display substrate, where fig. 1 is a schematic view of a partial cross-sectional structure of a display substrate according to an embodiment of the disclosure.

As shown in fig. 1 to 17, the method for manufacturing a display substrate according to the embodiment of the present disclosure may specifically include the following steps:

s001, preparing a substrate base plate on the glass carrier plate.

As a mode of the embodiment of the present disclosure, the substrate board 010 of the display substrate may be a flexible substrate board.

For example, the substrate 010 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are sequentially stacked. The first flexible material layer and the second flexible material layer can be made of Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) for improving the water and oxygen resistance of the substrate 010, and thus are referred to as Barrier (Barrier) layers. Amorphous silicon (a-si) can be used as the material of the semiconductor layer.

For example, taking the material of each laminated structure of the substrate 010 as PI1/Barrier1/a-si/PI2/Barrier2 as an example, the preparation process may include: coating a layer of polyimide on a glass carrier plate, and forming a first material layer (PI1) after curing and film-forming; subsequently, depositing a layer of inorganic material on the first layer of flexible material, forming a first Barrier (Barrier1) layer overlying the first layer of material; then, depositing a layer of amorphous silicon on the first barrier layer to form an amorphous silicon layer (a-si) covering the first barrier layer; then, coating a layer of polyimide on the amorphous silicon layer, and forming a second material layer (PI2) after curing and film forming; then, depositing a layer of inorganic material on the second flexible material layer to form a second Barrier layer (Barrier2) covering the second flexible material layer; finally, the first flexible material layer is separated from the glass carrier plate by means of laser lift-off and the like, so that the substrate base plate 010 is obtained.

And S002, preparing a driving structure layer on the substrate base plate 010 with the structure.

The driving structure layer includes a plurality of pixel circuits, and leads and the like for supplying various driving signals to the pixel circuits. Here, each pixel circuit may include a plurality of transistors and at least one storage capacitor Cst, such as the above 7T1C pixel circuit, 2T1C pixel circuit, 3T1C pixel circuit, and the like.

In fig. 1 and the following description, for the pixel circuit of each sub-pixel P, only the structure of one transistor (e.g., the sixth transistor T6 in fig. 3) is shown as an example for explanation, but it should be understood that it does not represent the entire structure in the pixel circuit. Accordingly, the preparation process of the driving structure layer may include:

a first insulating film and a semiconductor film are sequentially deposited on the substrate base 010, and the semiconductor film is patterned by a patterning process to form a first insulating layer 011 covering the entire substrate base 010 and an active layer pattern provided on the first insulating layer 011. The active layer pattern may include an active region of each transistor, and may further include a partially conductive semiconductor structure as a lead line or the like for connecting different active regions.

Subsequently, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 012 covering the active layer pattern and a first gate metal layer pattern disposed on the second insulating layer 012. The first gate metal layer pattern includes a gate electrode of a portion of the transistor and a first electrode of the storage capacitor Cst.

Subsequently, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 013 covering the first gate metal layer and a second gate metal layer pattern disposed on the third insulating layer 013. The second gate metal layer pattern includes a second electrode of the storage capacitor Cst, and the like, which is opposite to the first electrode of the storage capacitor Cst.

Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 014 covering the second gate metal layer, wherein at least two first via holes are formed on the fourth insulating layer 014, and the fourth insulating layer 014, the third insulating layer 013 and the second insulating layer 012 in the two first via holes are etched away to expose the surface of the active region.

Subsequently, a third metal film is deposited, and the third metal film is patterned through a patterning process, so as to form a source-drain metal layer pattern on the fourth insulating layer 014, where the source-drain metal layer includes a source electrode and a drain electrode of a partial transistor (e.g., the sixth transistor T6 in fig. 3), and the source electrode and the drain electrode may be respectively connected to the corresponding active regions through the first via holes.

As one mode of the embodiment of the present disclosure, the first insulating layer 011, the second insulating layer 012, the third insulating layer 013, and the fourth insulating layer 014 may be formed using an inorganic insulating material, such as any one or a combination of more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Wherein each insulating layer may be a single-layer structure, or a multi-layer composite structure, etc.

The first insulating layer 011, also referred to as a Buffer layer (Buffer), is used to improve the resistance of the substrate 010 to water and oxygen and to improve the adhesion of a subsequent structure to the substrate 010. The second insulating layer 012 and the third insulating layer 013 isolate a Gate electrode and an active region of the transistor, and are also referred to as Gate insulating layers (GI). The fourth insulating layer 014 is also called an Interlayer Insulating Layer (ILD) for isolating a portion of the conductive structure disposed in a different layer.

The first metal film, the second metal film, and the third metal film are made of a conductive metal material, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or a combination (alloy) of multiple metals, such as aluminum neodymium (AlNd), molybdenum niobium (MoNb), and the like. Wherein each metal thin film can be a single-layer structure or a multi-layer composite structure, such as a Ti/Al/Ti multi-layer composite structure.

The active layer thin film is made of a semiconductor material, for example, a metal Oxide semiconductor material such as an amorphous indium gallium zinc Oxide material (a-IGZO), zinc oxynitride (ZnON), or Indium Zinc Tin Oxide (IZTO), a silicon-based semiconductor material such as amorphous silicon (a-Si) or polycrystalline silicon (p-Si), or an organic semiconductor material such as hexathiophene or polythiophene.

S003, a Planarization Layer (PLN) is formed on the substrate 010 on which the above-described structure is formed.

As one mode of the embodiment of the present disclosure, a flat film of an organic material is coated on the base substrate 010 on which the foregoing structure is formed, a planarization layer 015 covering the entire base substrate 010 is formed, and a plurality of second via holes are formed on the planarization layer 015 through processes of masking, exposing, developing, and the like, to expose surfaces of drain electrodes of transistors (e.g., the sixth transistor T6 in fig. 3) of the respective sub-pixels P, respectively.

The flat layer 015 has a large thickness and a good leveling property, and is used to eliminate a step (undulation) of a lower structure, so that a subsequent organic electroluminescent device (OLED) can be formed on the basis of being relatively flat, and the light emitting effect of the OLED is improved.

S004, a first electrode pattern is formed on the base substrate 010 on which the above-described structure is formed.

As a mode of the embodiment of the present disclosure, a conductive thin film is deposited on the substrate 010 on which the foregoing structure is formed, and the conductive thin film is patterned through a patterning process to form a first electrode pattern, where the first electrode pattern includes first electrodes of the organic electroluminescent devices of the respective sub-pixels P, and the respective first electrodes are respectively connected to drain electrodes of transistors (e.g., a sixth transistor T6 in fig. 3) through second vias.

In some examples, the first electrode is an anode 213, further a reflective anode.

In some examples, the anode 213 may employ a metallic material, such as a combination (alloy) of any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb); the anode 213 may be a single layer structure, or a multi-layer composite structure such as a Ti/Al/Ti multi-layer composite structure; alternatively, the anode 213 may be a stack structure formed by reflective metal and transparent conductive material, such as a stack structure of ITO/Ag/ITO, Mo/AlNd/ITO, and the like.

S005, a pixel defining layer pattern is formed on the base substrate 010 on which the above-described structure is formed.

As one mode of the embodiment of the present disclosure, a Pixel Definition film is coated on the substrate 010 on which the foregoing structure is formed, and the Pixel Definition film at a partial position is removed through a mask, exposure, and development process to form a Pixel Definition Layer (PDL).

The pixel defining layer 30 includes a plurality of pixel defining layer openings 301 corresponding to the positions where the above pixel defining films are removed, and pixel defining portions 302 located between the pixel defining layer openings 301; the pixel defining layer opening 301 exposes at least a portion of the surface of the anode electrode 213 of each sub-pixel P. Thus, the light emitting layer 216 formed later can be in contact with the anode electrode 213 of the corresponding sub-pixel P only at the pixel defining layer opening 301, so that the pixel defining layer opening 301 defines the position of the sub-pixel P and the pixel defining part 302 is the space between the sub-pixels P.

In some examples, the pixel defining layer 30 may be formed of polyimide, acryl, or polyethylene terephthalate.

As a mode of the embodiment of the present disclosure, a Spacer 34(PS, Post Spacer, or Pixel sub port) may be formed at the same time as the Pixel defining layer 30 is formed.

The spacer 34 is located at the pixel defining portion 302, i.e. at the interval between the sub-pixels P, and protrudes from the pixel defining portion 302, so as to support a high-definition Metal Mask (FMM) in the subsequent evaporation process.

In the masking and exposing processes of the pixel definition film, different positions of the pixel definition film may be exposed to different degrees by using a "halftone mask" or a "gray-scale mask", so that after the developing process, a portion of the pixel definition film (corresponding to the opening 301 of the pixel definition layer) is removed, a portion of the pixel definition film (corresponding to the individual pixel definition portion 302) remains a thinner pixel definition film, and a portion of the pixel definition film (corresponding to the pixel definition portion 302 having the spacer 34) remains a thicker pixel definition film, that is, the spacer 34 having an "integral structure" with the pixel definition portion 302 is obtained, so that the material of the spacer 34 is also the same as that of the pixel definition layer 30.

Wherein the spacers 34 may be distributed only at intervals between some of the sub-pixels P, for example, referring to three sub-pixels P in fig. 1, only one spacer 34 is provided.

It should be understood, of course, that it is also possible to form the spacers 34 separately from the pixel defining layer 30, if by a separate process.

Referring to fig. 7, the edge portions of the various solid structures (e.g., the spacers 34 and the pixel defining portions 302) that are actually formed are generally structures that gradually thicken from the boundaries thereof toward the inside, or have "gradient angles", due to the limitations of the manufacturing process.

Therefore, in the embodiments of the present disclosure, the boundaries of various solid structures all refer to the maximum position occupied by the structure when the structure includes the "slope angle" portion, or the boundaries of the orthographic projection of the structure "on the substrate 010" as a whole ". For example, the region of the pixel defining part 302 is the region marked d1 in fig. 7, and the region of the spacer 34 is the region between two regions marked d2 in fig. 7.

Accordingly, the boundary of the non-solid region is defined by the boundary of the corresponding solid structure, for example, the region of the pixel defining layer opening 301 (i.e., the sub-pixel P) is the region outside the region of the pixel defining part 302 (the region labeled d1 in fig. 7).

When the spacer 34 and the pixel defining portion 302 are integrally formed, they are made of the same material and have no distinct dividing interface therebetween. Since the pixel defining portion 302 has a substantially flat surface on the upper side, and the spacer 34 is disposed on the substantially flat surface, referring to fig. 7, a portion where the included angle between the surface and the flat surface starts to exceed a threshold (for example, the threshold may be 20 degrees, 25 degrees, 30 degrees, etc.) is used as the boundary (i.e., "slope angle" portion) of the spacer 34.

S006, a light-emitting layer and a second electrode of the organic electroluminescent device are sequentially formed on the base substrate 010 on which the above structure is formed.

In some examples, the first electrode is a cathode 218, further a transparent cathode.

The organic electroluminescent device may emit light from a side far from the substrate 010 through the transparent cathode, thereby realizing top emission. Thus, a transparent material such as Indium Tin Oxide (ITO) may be used for the cathode 218.

In some examples, the light emitting layer of the organic electroluminescent device includes a plurality of stacked sub-layers, such as in a direction gradually away from the substrate 010, the light emitting layer sequentially includes: a Hole Injection Layer (HIL)214, a Hole Transport Layer (HTL)215, an organic emission layer (EML)216, and an Electron Transport Layer (ETL) 217.

The hole injection layer 214, the hole transport layer 215, the electron transport layer 217, and the cathode 218 of the organic electroluminescent device of each sub-pixel P may be an integrated structure, so that they may be sequentially formed on the substrate 010 forming the above structure by evaporation using an Open Mask.

Referring to fig. 1, the organic light emitting layers 216 corresponding to different sub-pixels P may be made of different materials, so that the organic light emitting layers 216 of different sub-pixels P (e.g., the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P03) may be sequentially formed on the substrate 010 forming the structure by a patterning process.

Referring to fig. 1, the organic light emitting layer 216 corresponding to each sub-pixel P may be beyond the range of the sub-pixel P (organic electroluminescent device) itself, so that one sub-pixel P (or a plurality of adjacent sub-pixels P of the same color) may correspond to a larger organic light emitting layer 216, and the area where the organic light emitting layer 216 is located is referred to as "light emitting area P99" of the sub-pixel P.

For example, referring to fig. 5, the actual areas of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P03 may be smaller, and the areas of the light-emitting regions P99 corresponding to the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P03 may exceed their own areas, for example, the ratio of the actual area of the sub-pixel P to the area of the corresponding light-emitting region P99 may be 1: 1 (1.01-10.5), and further may be 1: 1 (1.1-1.3).

The shape and size of the light-emitting region P99 substantially correspond to the opening on the high-definition metal mask used for forming the organic light-emitting layer of the sub-pixel P.

In terms of process, the positions of the openings on the high-definition metal masks used for forming the organic light-emitting layer may be connected or overlapped, that is, although the different sub-pixels P are arranged at intervals, referring to fig. 5, the light-emitting regions P99 of the different sub-pixels P may be connected or overlapped.

In some examples, the cathode 218 may be a transflective cathode, such that a "resonant microcavity" may be formed between the transflective cathode and the reflective anode to enhance the purity and brightness of the light output.

Thus, the light emitting layer may further include: a microcavity adjusting layer between the hole transport layer 215 and the organic light emitting layer 216 to adjust the thickness of the "resonant microcavity" between different sub-pixels P.

In some exemplary embodiments, the cathode 218 may employ a combination (alloy) of any one or more of magnesium (Mg), silver (Ag), and aluminum (Al), or the cathode 218 may employ a transparent conductive material, such as Indium Tin Oxide (ITO), or the cathode 218 may employ a multi-layer composite structure of metal and transparent conductive material.

In some examples, a light coupling layer may be further formed on the side of the cathode 244 away from the substrate 010, and the light coupling layer may be a common layer of the plurality of sub-pixels P. The optical coupling layer may cooperate with the transparent cathode to provide an increased light output. For example, the material of the optical coupling layer may be a semiconductor material.

S007, an encapsulation layer is formed on the substrate 010 on which the above structure is formed.

As a way of the embodiment of the present disclosure, an encapsulation layer may be continuously formed on the substrate 010 forming the foregoing structure, so as to seal various structures located therebelow, and prevent them (especially, the light emitting layer) from being corroded by moisture and oxygen in the environment.

In some examples, the encapsulation layer may include a first encapsulation layer 41, a second encapsulation layer 42, and a third encapsulation layer 43 stacked in this order, the first encapsulation layer 41 may employ an inorganic material, the second encapsulation layer 42 employs an organic material, and the third encapsulation layer 43 employs an inorganic material, that is, the encapsulation layer may employ a three-layer stack structure of inorganic layer/organic layer/inorganic layer. Of course, the specific form of the encapsulation layer is not limited thereto, and for example, in other examples, the encapsulation layer may also adopt a five-layer stacked structure of inorganic layer/organic layer/inorganic layer.

In some related art, referring to fig. 1, after the spacers 34 are formed, the high-definition metal mask FMM needs to be in contact with the spacers 34 to be supported thereby while continuing to form the subsequent structures through the evaporation process.

The substrate 010 is subjected to gravity and an adsorption magnetic force (gauss force) for attaching the high-precision metal mask FMM, so that certain deformation and stress exist, and the transmission of the stress causes slight friction between the spacer 34 and the high-precision metal mask FMM, so that a material (such as a material of the hole injection layer 214) on the spacer 34, which is in contact with the high-precision metal mask FMM, falls off, and particles pt (particle) are generated.

Referring to fig. 2, after the high-definition metal mask FMM is separated from the display substrate, the particles PT may adhere to the high-definition metal mask FMM or fall into the region of the sub-pixel P of the display substrate, thereby causing defects such as dark spots and dead spots, reducing the display effect, and causing reliability and yield problems.

In a first aspect, referring to fig. 1 to 17, an embodiment of the present disclosure provides a display substrate.

The display substrate of the embodiment of the disclosure may be an Array substrate, and further may be an Array substrate of an Organic Light Emitting Diode (OLED) display.

The display substrate of the embodiment of the present disclosure includes a substrate 010, and a plurality of sub-pixels P arranged in an array at intervals on the substrate 010; wherein,

a spacer is arranged between the adjacent sub-pixels P; the spacer regions include a first spacer region 91 having functional bits, and a second spacer region 92 having non-functional bits;

at least part of the function positions are provided with function parts;

the width of the first spacing region 91 is greater than the width of the second spacing region 92; wherein, the width of the spacing region is equal to the shortest distance between the boundaries of the two sub-pixels P corresponding to the spacing region.

Here, each of the spacers (e.g., the first spacer 91 and the second spacer 92) is located between two sub-pixels P, so that the width of one spacer, i.e., the distance between two sub-pixels P on both sides thereof (i.e., the interval between two sub-pixels P in the arrangement direction), is, for example, the distance between the nearest boundaries of the two sub-pixels P on the line connecting the geometric centers of the two sub-pixels P, and thus, the extending direction of the above line (or the arrangement direction of the two sub-pixels P), i.e., the width direction of the spacer.

Further, the two sub-pixels P on both sides of each spacer area are necessarily arranged in a certain direction (e.g., a row direction or a column direction), so that the width contrast of the different spacer areas (the first spacer area 91 and the second spacer area 92) should be the width contrast of the spacer area between the sub-pixels P arranged in the same direction (or in substantially the same direction), or the widths of the two spacer areas should be comparable when the width directions of the two spacer areas are the same (or substantially the same) (i.e., when the two spacer areas are located between the sub-pixels P arranged in the same directions).

Here, the "function bit" refers to a position in a spacer region between the sub-pixels P, at which a function can be disposed. And "functional element" means a structure provided in the above spacer region for realizing a certain function.

For example, the above function may be a sensor such as an infrared sensor, a fingerprint sensor, or the like; or, the functional element may also be an auxiliary conductive column for connecting with the cathode to perform an auxiliary conductive function; alternatively, the functional element may be a blocking structure or the like that performs an optical or electrical blocking function, for example, a blocking structure for blocking some film layers such as a common layer (an electron transport layer, a hole transport layer, a cathode, and the like) to reduce crosstalk; alternatively, the functional member may be a lens structure, a reflective structure, or the like for enhancing light extraction efficiency.

In some embodiments, although the projection of the functional element on the substrate is located between two sub-pixels P (e.g., pixel definition layer openings), the functional element is not necessarily located at the same layer as at least some of the layers of the sub-pixels P, e.g., may be located above the pixel definition layer; alternatively, the functional element may be located on the same layer as the pixel defining layer (for example, the pixel defining layer has a functional opening other than the sub-pixel opening for displaying, and the functional element is located in the functional opening of the pixel defining layer); alternatively, the features may also be located on the side of the pixel defining layer adjacent to the substrate base (e.g., in the anode spaces of the subpixels, or in the openings of the flat layer on the side of the anode adjacent to the substrate base, etc.).

In some embodiments, the functional site is a spacer site 911 for positioning a spacer and the functional element is a spacer 34 (PS).

As a way of the embodiment of the present disclosure, the functional component is a spacer 34 for supporting, and the corresponding functional position is a spacer position 911 for disposing the above spacer. Of course, other functional devices (such as the above sensor, the auxiliary conductive column, the partition structure, the lens structure, etc.) may be provided for the spacer locations 911 for providing the spacers 34.

In the following part of the embodiment of the present disclosure, a spacer 911 is used as an example of a function bit, and a spacer 34 is used as an example of a function element. It should be understood that the spacer 911 in the following description can be replaced by a functional position, and the spacer 34 can be replaced by a functional element, but the functional position and the functional element are not limited to the above spacer 911 and the spacer 34.

In the embodiment of the present disclosure, referring to fig. 6, the spacing regions between the sub-pixels P are divided into two types, wherein one type of the spacing regions has a larger width (larger than the spacing in the related art) and is a first spacing region 91 having the spacing position 911, and the other type of the spacing regions has a smaller width (unchanged from the spacing in the related art) and is a second spacing region 92, and the spacers 34(PS) are only disposed in the spacing position 911 (but not all the spacing positions 911 need to be disposed with the spacers 34).

That is, in the embodiment of the present disclosure, the spacers 34 are disposed only in the first spacing regions 91 having the larger width, and it is impossible to dispose the spacers in the second spacing regions 92.

Therefore, in the display substrate according to the embodiment of the present disclosure, it is equivalent to "enlarge" the space (the first spacer 91) between some of the sub-pixels P, and the spacer 34 is disposed in the "enlarged" space, so that the distance between the spacer 34 and the sub-pixels P is increased, the generation of the particles PT in the evaporation process is reduced, the defects of dark spots, dead spots, and the like caused by the particles PT are reduced, the product yield and reliability are improved, the passing rate of the display substrate product for 500h (hours) and 1000h 8585 tests (tests at 85 ℃ and 85% relative humidity) is increased, and the display quality is improved.

Meanwhile, in the display substrate according to the embodiment of the present disclosure, only the first spacers 91 that may be provided with the spacers 34 are "pulled up", and the second spacers 92 between the other sub-Pixels P have a constant size, so that the overall distribution of the sub-Pixels P is constant, that is, the resolution (PI, Pixels Per inc) of the display substrate is not changed (certainly, the aperture ratio may be reduced to some extent), the display effect is not significantly affected, and the requirement of high resolution can be satisfied.

In some embodiments, the width of the first spacer 91 is greater than or equal to 20 μm.

In some embodiments, the distance between the boundary of the spacer 34 (spacer bit 911) and the boundary of the closest subpixel P is greater than or equal to 3 μm.

In some embodiments, the width of the second spacer region 92 is less than or equal to 19 μm.

The applicant has studied and created findings, and referring to fig. 6 and 7, when the width d1 of the first spacer region 91 having the spacer 34 (i.e., the width of the entire pixel defining part 302) is greater than or equal to 20 μm, and the distance d2 between the spacer 34 and the boundary of the closest sub-pixel P (i.e., the distance between the boundary of the spacer 34 and the boundary of the pixel defining part 302 where the spacer 34 is located) is greater than or equal to 3 μm, the effect of preventing the generation of the particles PT can be achieved.

When the spacer is provided with the pixel defining portion 302, the pixel defining portion 302 is located in the spacer. However, due to process limitations, referring to fig. 7, the edge portion of the pixel defining part 302 generally has a structure that gradually thickens from the boundary to the inside, or has a "gradient angle", so the cross section of the pixel defining part 302 is approximately trapezoidal, and thus, the spacer should correspond to the whole area of the pixel defining part 302, i.e. the size of the "widest" part of the trapezoid bottom side of the pixel defining part 302, for example, the spacer generally covers the edge of the anode 213.

Here, one spacer 34 (that is, it may be adjacent to a plurality of sub-pixels P), and in this case, there may be a plurality of distances between the spacer 34 and the plurality of adjacent sub-pixels P, and these distances may be all the same, or all the different (that is, any two distances are different), or may be partially the same, or partially different.

In contrast, the width of the second spacer region 92 (or the width of the space between the sub-pixels P in the related art) without the spacer may be less than or equal to 19 μm.

Wherein the width d1 of the first spacer region 91 having the spacer 34 may further be greater than or equal to 21 μm, greater than or equal to 22 μm, greater than or equal to 24 μm, greater than or equal to 26 μm, greater than or equal to 28 μm, greater than or equal to 30 μm, and the like.

The distance d2 between the spacer 911 and the boundary of the nearest sub-pixel P may be greater than or equal to 4 μm, greater than or equal to 5 μm, greater than or equal to 6 μm, greater than or equal to 7 μm, greater than or equal to 8 μm, etc.

Wherein the width d1 of the second spacer region 92 without spacers may further be less than or equal to 18 μm, less than or equal to 16 μm, etc.

For example, as shown in table 1 below, when the size and the spacing size of the spacer 34 between two sub-pixels P are different, the corresponding spacer shape (Profile) determination is also different, and the size meeting the above requirements of the embodiment of the present disclosure can ensure that the spacer shape determination is qualified.

TABLE 1 shape of spacer under different sizes

In some embodiments, at least a portion of the shortest connection line between the boundaries of the two sub-pixels P corresponding to the first spacer region 91 passes through the spacer 34 in the first spacer region 91.

In some embodiments, in a cross section passing through the shortest connecting line and perpendicular to the substrate 010, a distance between boundaries of two sub-pixels P corresponding to the first spacer 91 is greater than or equal to 20 μm, and a distance between the spacer 911 and the sub-pixel P in the first spacer 91 is greater than or equal to 3 μm.

As an aspect of the embodiment of the present disclosure, referring to fig. 6, at least some of the spacer locations 911 may pass through the shortest position between adjacent sub-pixels P, so that if the spacer 34 is disposed on the spacer locations 911, the shortest connecting line between the boundaries of two corresponding sub-pixels P also passes through the spacer 34 on the spacer location 911, and referring to fig. 7, in this case, in the cross section of the shortest position, the sizes of the spacer locations 911 and the spaces also meet the above requirements.

In some embodiments, a connection line between the geometric centers of the two sub-pixels P corresponding to at least a portion of the first spacer region 91 passes through the spacer 34 in the first spacer region 91.

In some embodiments, a connection line between the geometric centers of two sub-pixels P corresponding to at least a portion of the first spacer area 91 passes through the geometric center of the spacer 34 in the first spacer area 91.

As another way of the embodiment of the present disclosure, referring to fig. 6, at least a portion of the spacer 911 (and the spacer 34 thereon) may pass through a connection line between the geometric centers of the adjacent sub-pixels P, and further, the geometric center of the spacer 911 (and the spacer 34 thereon) itself may be located on the connection line between the geometric centers of the adjacent sub-pixels P.

The pattern of the spacers 34 in the cross section perpendicular to the base board 010 and passing through any of the connecting lines may be symmetrical, for example, a trapezoid as shown in fig. 7.

In some embodiments, at least a portion of the first spacers 91 extend in the third direction; at least part of the first spacers 91 extend in the fourth direction; the fourth direction intersects the third direction; the first spacers 91 extending at least partially in the third direction and the first spacers 91 extending in the fourth direction have an overlapping area, and at least a part of the spacer 34 overlaps at least a part of the overlapping area.

Referring to fig. 6, spacers may be disposed between any adjacent sub-pixels P, and the sub-pixels P may be adjacent in different directions, so that there may be spacers extending in different directions between the sub-pixels P adjacent in different directions, for example, in fig. 6, there are "laterally extending" spacers between the "laterally adjacent" sub-pixels P, and "longitudinally extending" spacers between the "longitudinally adjacent" sub-pixels P. Also, the above different spacers may also have an overlapping area.

Thus, if there are two first spacers 91 extending in different directions having an overlap region, there may be spacers 34 (spacers 911) at least partially located in the overlap region, or completely located in the overlap region. That is, referring to fig. 6, the above spacers 34 (spacer locations 911) are simultaneously located between a plurality of "pairs" of different adjacent sub-pixels P, so that they may also belong "to" a plurality of first spacer areas 91 at the same time.

It should be understood that, when the spacer 34 (spacer location 911) is located in a plurality of spacer regions, any one of the spacer regions should be the above first spacer region 91, and should meet the above width requirement.

The third direction and the fourth direction only indicate two different directions, and do not necessarily indicate that the two directions are perpendicular, and the like.

The extending direction of the spacer may also be the direction in which the width of the spacer is located, for example, the extending direction of a connecting line between the geometric centers of the two sub-pixels P on both sides of the spacer.

The specific shape of the spacer is various and is determined according to the shape of the region between the two sub-pixels P where the spacer is located, for example, the spacer may be in the shape of a strip (or a rectangle), or may be in the shape of a circle, an ellipse, or the like; for another example, the spacers may be relatively regular symmetrical shapes having an axis of symmetry, or may be other irregular shapes, etc.

It should be understood that the spacer 34 (spacer sites 911) may be provided regardless of the specific shape of the spacer as long as its dimension in the width direction meets the above requirements, belonging to the above first spacer 91.

In some embodiments, the distance between adjacent spacers 34 is between 100 μm and 300 μm.

As mentioned above, the spacer 911 is a position where the spacer 34 may be disposed, but it does not mean that each spacer 911 is actually disposed with the spacer 34, and the density of the spacer 34 is sufficient to support the high-precision metal mask FMM. The distance between the spacers 34 satisfying the above support requirements may be in the range of 100 μm to 300 μm, further 120 μm to 280 μm, or 150 μm to 250 μm.

In some embodiments, the number of dunnage sites 911 at which the dunnage 34 is provided is at least 15% of the total number of dunnage 34.

In the disclosed embodiment, at least 15% of the spacer locations 911 may be provided with spacers 34. Of course, it is also possible that the ratio of the spacer locations 911 provided with the spacers 34 is at least 25%, 50%, 75%, etc., or all of the spacer locations 911 are provided with the spacers 34.

Thus, if the interval between adjacent first spacers 91 is smaller than the above range, referring to fig. 6, only one spacer 911 among the plurality of first spacers 91 may be actually provided with the spacer 34.

In some embodiments, the display substrate further comprises a pixel defining layer 30;

the pixel defining layer 30 includes pixel defining layer openings 301, and pixel defining portions 302 located between the pixel defining layer openings 301;

the pixel defining layer opening 301 defines a light emitting region of the sub-pixel P;

the spacers 34 are disposed on a side of the pixel defining portion 302 facing away from the substrate 010.

In some embodiments, the spacer 34 and the pixel defining portion 302 are a unitary structure.

As a way of the embodiment of the present disclosure, the area where the sub-Pixel P can actually emit light (i.e., the sub-Pixel P) may correspond to the Pixel Definition Layer opening 301 of the Pixel Definition Layer (PDL) 30, the interval of the sub-Pixel P corresponds to the Pixel Definition portion 302 of the Pixel Definition Layer 30, and the spacer 34 is disposed above the Pixel Definition portion 302.

As a way of the embodiment of the present disclosure, the spacer 34 may be integrated with the pixel defining part 302, i.e., formed by one material layer in one patterning process.

Of course, it is also possible to form the independent structures on the pixel defining parts 302 with separate material layers if the spacers 34 are formed by independent patterning processes.

Of course, if the functional element is not the spacer 34 but other structure, it may be formed by a separate patterning process, or it may be disposed in the same layer as the other structure (e.g., formed in a single patterning process), and the functional element and the other structure disposed in the same layer may be connected to each other as a whole, or may be independent of each other.

The following description will exemplarily describe the arrangement of some specific sub-pixels P adopted by the display substrate, and the arrangement of the corresponding first spacing region 91 (and the spacing position 911 therein) and the second spacing region 92.

In some embodiments, among the plurality of sub-pixels P adjacent to at least a part of the spacers 34, at least one geometric center of the sub-pixel P is offset from a straight line extending along the first direction, and geometric centers of at least two sub-pixels P located in the same row as the sub-pixel P in the first direction are located on the straight line;

and/or the presence of a gas in the gas,

among the plurality of sub-pixels P adjacent to at least a part of the spacers 34, at least one of the sub-pixels P has a geometric center that is offset from a straight line extending in the second direction, and at least two of the sub-pixels P located in the same row as the sub-pixel P in the second direction have geometric centers located on the straight line; the second direction intersects the first direction.

In the following description, the first direction is taken as a row direction, and the second direction is taken as a column direction as an example for explanation. It should be understood that the above direction is not intended as a limitation on the scope of the present disclosure.

That is, each subpixel P1 may be arranged in a plurality of rows and columns in the row direction (first direction) and the column direction (second direction). Among the plurality of sub-pixels P1 in the same row, those sub-pixels P1 adjacent to the spacer 34 (spacer 911) may be "offset" from the other sub-pixels P1 in the row (in terms of the position of the geometric center), for example, in a direction away from the spacer 34 adjacent thereto; in the plurality of sub-pixels P1 in the same column, the sub-pixel P1 adjacent to the spacer 34 (spacer 911) may also be "offset" from the other sub-pixels P1 in the column (in terms of the position of the geometric center), for example, in a direction away from the spacer 34 adjacent thereto.

Thus, a sufficient space can be left for the spacer area provided with the spacer 34 (spacer position 911) to satisfy the width requirement of the first spacer area 91.

In some embodiments, the first sub-pixel P01 is a red sub-pixel, the second sub-pixel P02 is a green sub-pixel, and the third sub-pixel P03 is a blue sub-pixel.

As a way of the embodiment of the present disclosure, the light emitting efficiency of the organic electroluminescent devices (OLEDs) of different colors and the sensitivity of human eyes to light of different colors are considered together, and the colors of different subpixels P may be the above way. It should be understood, however, that the color of the sub-pixel P corresponds to the above case, and is not a limitation to the scope of the present disclosure.

For example, referring to fig. 8, the subpixels P are arranged in an array, the array column includes a plurality of rows of first pixel rows and a plurality of rows of second pixel rows, and the first pixel rows and the second pixel rows are alternately arranged. The first pixel row is formed by red sub-pixels and blue sub-pixels which are alternately arranged, and the red sub-pixels and the blue sub-pixels which are positioned in the same column in the plurality of rows of the first pixel row are also alternately arranged. The second pixel row is formed by arranging a plurality of green sub-pixels side by side, and the green sub-pixels are arranged in a staggered mode with the red sub-pixels and the blue sub-pixels in the adjacent rows. For the pixel arrangement, the pixel array can be divided into repeating units arranged in an array, each repeating unit comprises two rows and four columns of sub-pixels, namely each repeating unit comprises one red sub-pixel, one blue sub-pixel and two green sub-pixels, the red sub-pixel and the blue sub-pixel are shared sub-pixels, and the four sub-pixels can realize the display of two virtual pixel units through a virtual algorithm. For example: the red sub-pixel in the first row second repeating unit, the blue sub-pixel in the first row first repeating unit and the green sub-pixel closest to the blue sub-pixel form a virtual pixel unit, and the red sub-pixel in the first row second repeating unit, the blue sub-pixel in the repeating unit and the green sub-pixel closest to the blue sub-pixel form a virtual pixel unit; in addition, the blue sub-pixel in the second repeating unit in the first row and the other green sub-pixel in the repeating unit and the closest red sub-pixel in the third repeating unit in the first row form a virtual pixel unit, so that the resolution of a display panel applying the pixel array can be effectively improved.

In some embodiments, the sub-pixel P includes a first sub-pixel P01, a second sub-pixel P02, a third sub-pixel P03;

the first and third sub-pixels P01 and P03 are alternately arranged in a first direction to form a first pixel group a01 and in a second direction to form a third pixel group a 03; the second direction intersects the first direction;

the second sub-pixels P02 are arranged along the first direction to form a second pixel group a02, and arranged along the second direction to form a fourth pixel group a 04;

wherein the first pixel group a01 and the second pixel group a02 are alternately arranged along the second direction; the third pixel group a03 and the fourth pixel group a04 are alternately arranged along the first direction.

Referring to fig. 8 and 9, in the display substrate, as a manner of the embodiment of the present disclosure, the first sub-pixel P01 and the third sub-pixel P03 may be alternately arranged in a plurality of rows of the first pixel group a01, the second sub-pixel P02 is arranged in a plurality of rows of the second pixel group a02, and in the column direction, the first pixel group a01 and the second pixel group a02 are alternately arranged; meanwhile, the first and third subpixels P01 and P03 are alternately arranged in a plurality of columns of the third pixel group a03, the second subpixel P02 is arranged in a plurality of columns of the fourth pixel group a04, and the third pixel group a03 and the fourth pixel group a04 are alternately arranged in the row direction.

In some embodiments, among the spacers between the first sub-pixel P01 and the third sub-pixel P03 adjacent in the third pixel group a03, at least a part of the spacers are the first spacers 91;

the spacer between the first sub-pixel P01 and the third sub-pixel P03 adjacent in the first pixel group a01 is the second spacer 92.

As a manner of the embodiment of the present disclosure, referring to fig. 8 and 9, the spacer regions between the first subpixel P01 and the third subpixel P03 adjacent in the row direction are the second spacer regions 92 without spacer regions; and a first spacer 91 at least partially provided with a spacer 911 (spacer 34) is provided in a spacer between the first subpixel P01 and the third subpixel P03 adjacent in the column direction.

The widths of the second spacing regions 92 in the same row (i.e. the second spacing regions 92 between two adjacent rows of sub-pixels P) should be the same or substantially the same. For example, if the width of the second spacer region 92 having the smallest width among the plurality of second spacer regions 92 in the same row is 0.8, the relative width of the second spacer region 92 having the largest width among the plurality of second spacer regions 92 should not exceed 1.2.

In some embodiments, the spaced regions between the first sub-pixel P01 and the third sub-pixel P03 adjacent in the third pixel group a03 alternate as the first spaced regions 91 and the second spaced regions 92 along the second direction;

in two adjacent third pixel groups a03, one of the first spacer regions 91 in one of the third pixel groups a03 and one of the second spacer regions 92 in the other of the third pixel groups a03 are located between the same two rows of sub-pixels P arranged in the first direction.

As a manner of the embodiment of the present disclosure, referring to fig. 8 and 9, in the spacer between the first sub-pixel P01 and the third sub-pixel P03 in each column, the first spacer 91 and the second spacer 92 are alternately arranged; and also the first and

second spacer regions

91 and 92 are alternately arranged among the plurality of spacer regions positioned between two adjacent third pixel groups a 03. For example, referring to fig. 8 and 9, in the spacer region between the first sub-pixel P01 and the third sub-pixel P03 located at any column, the spacer region where the third sub-pixel P03 is above and the first sub-pixel P01 is below is the first spacer region 91, and correspondingly, the spacer region where the third sub-pixel P03 is below and the first sub-pixel P01 is above is the second spacer region 92. Thus, the first spacing region 91 and the second spacing region 92 (which are necessarily adjacent to each other) in the same row in the two adjacent third pixel groups a03 are located between two adjacent rows of sub-pixels P, for example, between two rows of sub-pixels P labeled with H in fig. 8.

Therefore, the spacer locations 911 (spacers 34) are also relatively uniformly distributed in the display substrate, which facilitates the arrangement of the spacer locations 911 (spacers 34).

The widths of the first spacers 91 in the same row (i.e., the first spacers 91 between two adjacent rows of sub-pixels P) may be equal, and the widths of the second spacers 92 in the same row (i.e., the second spacers 92 between two adjacent rows of sub-pixels P) may be equal, so as to achieve regular arrangement of the sub-pixels P.

In some embodiments, a sequential connection line of the geometric centers of the two first sub-pixels P01 and the two third sub-pixels P03 arranged in an array forms a virtual trapezoid;

the spacer between the first sub-pixel P01 and the third sub-pixel P03 corresponding to the bottom side of the virtual trapezoid is the first spacer 91, and the spacer between the first sub-pixel P01 and the third sub-pixel P03 corresponding to the top side of the virtual trapezoid is the second spacer 92.

As a way of implementing the embodiment of the present disclosure, referring to fig. 9, the virtual "quadrangle" formed by connecting the geometric centers of every four first sub-pixels P01 and third sub-pixels P03 is "trapezoid", and the spacer 911 (first spacing region 91) is located at a position corresponding to the bottom side (longer side) of the virtual trapezoid, and the top side (shorter side) of the virtual trapezoid corresponds to the second spacing region 92.

Alternatively, for each column of the first sub-pixel P01 and the third sub-pixel P03, the distance between a part of the first sub-pixel P01 and the third sub-pixel P03 (the distance between the other first sub-pixel P01 and the third sub-pixel P03 is obviously correspondingly reduced) may be "enlarged", and the spacer 911 (the first spacer 91) may be disposed at the position where the distance is "enlarged", so as to increase the distance between the spacer 34 and the sub-pixel P, reduce the generation of the particles PT, and improve the reliability and yield.

In some embodiments, the virtual trapezoid is a virtual isosceles trapezoid.

Further, the bottom side of the virtual trapezoid may be parallel to the column direction, and further may be a virtual isosceles trapezoid (i.e., the first sub-pixel P01 and the third sub-pixel P03 move by the same distance).

In some embodiments, in the first spacer region 91 at least partially located between the adjacent first sub-pixel P01 and the third sub-pixel P03, the geometric center of the spacer 34 is located on a connecting line between the geometric center of the first sub-pixel P01 and the geometric center of the third sub-pixel P03 corresponding to the first spacer region 91.

As one mode of the embodiment of the present disclosure, referring to fig. 9, the geometric center of at least some of the spacers 911 and the spacers 34 located thereon may be located on a connecting line (e.g., the bottom side of the above virtual trapezoid) between the geometric centers of the corresponding first sub-pixel P01 and third sub-pixel P03.

In some embodiments, in the first spacer region 91 at least partially located between the adjacent first sub-pixel P01 and the third sub-pixel P03, along the second direction, a distance between a geometric center of the spacer 34 and a geometric center of the first sub-pixel P01 corresponding to the first spacer region 91 is smaller than a distance between a geometric center of the spacer 911 and a geometric center of the third sub-pixel P03 corresponding to the first spacer region 91.

As a way of the embodiment of the present disclosure, referring to fig. 9, the spacers 34 disposed on the spacer 911 in at least a part of the first spacers 91 are not located "in the middle" of their corresponding first sub-pixel P01 and third sub-pixel P03 in the column direction, but are closer to their corresponding first sub-pixel P01 and farther from their corresponding third sub-pixel P03; alternatively, the spacer 911 is "biased down".

In some embodiments, in the first spacer region 91 at least partially located between the adjacent first sub-pixel P01 and the third sub-pixel P03, along the second direction, the geometric center of the spacer 34 is located on a side of the reference line 9111 corresponding thereto close to the first sub-pixel P01 corresponding thereto of the first spacer region 91; the reference line 9111 of the spacer 911 is a connecting line between the geometric centers of the two second sub-pixels P02 located at two sides of the spacer 911 in the first direction.

As a mode of the embodiment of the present disclosure, referring to fig. 9, the spacers 34 disposed on the spacer 911 in at least the first spacer area 91 may be closer to the corresponding first sub-pixel P01 than the second sub-pixel P2 in the same row in the column direction. For example, the geometric center (reference line 9111) of the second sub-pixel P2, which may be in the same row, is located on the connection line between the midpoint of the fixed side and the midpoint of the bottom side of the corresponding virtual trapezoid, i.e., the second sub-pixel P2 may be located between the first sub-pixel P01 and the third sub-pixel P03, and the second sub-pixel P2 is relatively close to (lower than) the first sub-pixel P01.

In some embodiments, the shape of the first subpixel P01 includes a square or rounded square having one diagonal parallel to the first direction and the other diagonal parallel to the second direction;

the shape of the third sub-pixel P03 includes a square or rounded square having one diagonal parallel to the first direction and the other diagonal parallel to the second direction.

As one mode of the embodiment of the present disclosure, referring to fig. 8 and 9, the shape of the first sub-pixel P01 and the third sub-pixel P03 may be a square, or a rounded square (i.e., a shape obtained by rounding each corner of the square), and two diagonal lines of the square (or rounded square) are respectively arranged along the row direction and the column direction.

Of course, the second sub-pixel P02 may also be a square or rounded square, or a non-square rectangle or rounded rectangle, or a rectangle or rounded rectangle "missing" a part of the shape, and will not be described in detail herein.

In some embodiments, at least a portion of the third sub-pixel P03 is divided into asymmetric first and second portions along a line passing through its geometric center and parallel to the first direction, the maximum dimension of the first portion being smaller than the maximum dimension of the second portion along the second direction; among the first spacers 91 located between the first sub-pixel P01 and the third sub-pixel P03 adjacent in the second direction, at least a part of the first spacers 91 are spacers between the first portion of the third sub-pixel P03 and the adjacent first sub-pixel P01.

As another form of the embodiment of the present disclosure, referring to fig. 10 and 11 as well, at least a part of the third subpixel P03 may be "asymmetrical" in shape with respect to an axis parallel to the first direction, one side (the first portion, such as a lower side in fig. 10) of which is "missing" a part with respect to the other side (the second portion, an upper side in fig. 10), so that the size of the first portion thereof in the second direction is "shorter". Thus, the first spacer region 91 may be disposed between the first sub-pixel P01 and the side of the first portion of the third sub-pixel P03 being "shorter". That is, the third subpixel P03 may not necessarily be "moved", but satisfy the requirement of the width of the first space area 91 by the change of the shape thereof (of course, it is also possible if a part of one side thereof is "absent" while the third subpixel P03 is "moved").

Further, referring to fig. 11, when the spacer 34 is disposed at only a partial position, the first portion of the different third sub-pixel P03 is oriented differently to form a position where the spacer 34 is disposed.

In some embodiments, the area of the second subpixel P02 is less than the area of the first subpixel P01;

the area of the second subpixel P02 is smaller than that of the third subpixel P03.

As a manner of the embodiment of the present disclosure, referring to fig. 8 and 9, the area of the above second sub-pixel P02 (e.g., green sub-pixel) may be the smallest, for example, the area of the third sub-pixel P03 (e.g., blue sub-pixel) is the largest, the area of the second sub-pixel P02 (e.g., green sub-pixel) is the smallest, and the area of the first sub-pixel P01 (e.g., red sub-pixel) is the middle, etc.

the first sub-pixel pair P91 and the third sub-pixel P03 are alternately arranged in the first direction to form a fifth pixel group a 05; the first sub-pixel pair P91 includes one of the first sub-pixels P01 and one of the second sub-pixels P02 arranged in a second direction; the second direction intersects the first direction;

the first and second sub-pixels P01 and P02 are alternately arranged in the second direction to form a sixth pixel group a 06;

the third sub-pixel P03 is arranged along the second direction to form a seventh pixel group a 07;

wherein the sixth pixel group a06 and the seventh pixel group a07 are alternately arranged along the first direction; a plurality of the fifth pixel group a05 is arranged along the second direction.

As another mode of the embodiment of the present disclosure, referring to fig. 12 and 13, one first subpixel P01 and one second subpixel P02 which are adjacent in the column direction may form a "first subpixel pair P91", and the first subpixel pair P91 and the third subpixel P03 are alternately arranged in a plurality of rows of the fifth pixel group a 05; the first sub-pixel pair P91 is further arranged in a plurality of columns of a sixth pixel group a06, the third sub-pixel P03 is arranged in a plurality of columns of a seventh pixel group a07, and the seventh pixel group a07 and the sixth pixel group a06 are alternately arranged in the row direction.

In some embodiments, among the spacers between the adjacent third sub-pixels P03 in the seventh pixel group a07, at least a part of the spacers is the first spacers 91;

the spacer region between the first sub-pixel P01 and the third sub-pixel P03 adjacent in the fifth pixel group a05, and the spacer region between the second sub-pixel P02 and the third sub-pixel P03 adjacent in the fifth pixel group a05 are the second spacer region 92;

the spacing region between the first sub-pixel P01 and the second sub-pixel P02 adjacent to each other in the fifth pixel group a05 is the second spacing region 92.

As another way of the embodiment of the present disclosure, referring to fig. 12, 13, the first spacer region 91 is located between the third subpixels P03 adjacent in the column direction; the second spacing region 92 is a spacing region between the third sub-pixel P03 and the first sub-pixel P01 adjacent to each other in the row direction, a spacing region between the third sub-pixel P03 and the second sub-pixel P02 adjacent to each other in the row direction, and a spacing region between the first sub-pixel P01 and the second sub-pixel P02 adjacent to each other in the column direction.

That is, the spacing between the third sub-pixel P03 of at least part of the same column may be "pulled up" to increase the distance between the spacer 911 and the sub-pixel P (e.g., increase d3 in FIG. 13 from 5 μm to 10 μm).

In some embodiments, at least some of the spacers between the adjacent third sub-pixels P03 in the seventh pixel group a07 alternate between the first spacers 91 and the second spacers 92 along the second direction.

Referring to fig. 12 and 13, the spacer regions in at least a portion of the seventh pixel group a07 may be alternately the first spacer region 91 and the second spacer region 92, so as to make the distribution of the spacer locations 911 more uniform.

In some embodiments, the area of the third subpixel P03 is greater than the area of the first subpixel P01;

the area of the third subpixel P03 is greater than that of the second subpixel P02.

As a manner of the embodiment of the present disclosure, referring to fig. 12 and 13, the area of the above third sub-pixel P03 (e.g., blue sub-pixel) may be the largest, for example, the area of the third sub-pixel P03 (e.g., blue sub-pixel) is the largest, the area of the second sub-pixel P02 (e.g., green sub-pixel) is the middle, and the area of the first sub-pixel P01 (e.g., red sub-pixel) is the smallest.

The shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 may also be various, for example, referring to fig. 12 and 13, the shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 are all rectangles or rounded rectangles, and two sides of the rectangle (or rounded rectangle) are parallel to the row direction and the column direction, respectively.

In some embodiments, at least a portion of the third sub-pixel P03 is divided into asymmetric first and second portions along a line passing through its geometric center and parallel to the first direction, the maximum dimension of the first portion being smaller than the maximum dimension of the second portion along the second direction;

among the first spacers 91 positioned between the third sub-pixels P03 adjacent in the second direction, at least a part of the first spacers 91 is a spacer between the first portions of the third sub-pixels P03.

As another form of the embodiment of the present disclosure, referring also to fig. 14, at least a part of the third sub-pixel P03 may be in a shape "asymmetrical" with respect to an axis parallel to the first direction, one side of which is "missing" a part with respect to the other side (a lower side of the third sub-pixel P03 at the upper side in fig. 14, and an upper side of the third sub-pixel P03 at the lower side), so that the size of the first part thereof in the second direction is "shorter". Thus, the first spacer region 91 may be disposed between the first portions of the two third sub-pixels P03 that are "shorter" to meet the width requirement of the first spacer region 91.

It should be understood that the above scheme of "lacking" a part of the third sub-pixel P03 and disposing the first spacer 91 on the "lacking" side of the third sub-pixel P03 is a specific shape of the sub-pixel P, so that it is not necessarily related to the position of each sub-pixel P itself and the position of each spacer, and therefore, the above scheme is "compatible" with other arrangement schemes of the sub-pixels P and the spacers.

Here, it should be understood that, in addition to the third sub-pixel P03 being "absent" a portion on one side, other sub-pixels P are also "absent" a portion corresponding to the first spacer region 91 to meet the requirement of the width of the first spacer region 91.

the second sub-pixel pair P92, the first sub-pixel P01 and the third sub-pixel P03 are alternately arranged along the first direction to form an eighth pixel group a 08; the second sub-pixel pair P92 includes two second sub-pixels P02 arranged along the second direction; the second direction intersects the first direction;

a plurality of the eighth pixel group a08 are arranged along the second direction;

in two adjacent eighth pixel groups a08, one of the second sub-pixel pairs P92 of one of the eighth pixel groups a08 is located between one of the first sub-pixels P01 and one of the third sub-pixels P03 of the other of the eighth pixel groups a08 along the first direction.

As one mode of the embodiment of the present disclosure, referring to fig. 15, 16, and 17, two second subpixels P02 adjacent in the column direction may form a second subpixel pair P92, and the second subpixel pair P92, the first subpixel P01, and the third subpixel P03 are alternately arranged to form a plurality of rows and an eighth pixel group a08, and the eighth pixel groups a08 of adjacent rows are staggered by "one and a half columns".

In some embodiments, at least some of the spacers between the first sub-pixel P01 and the third sub-pixel P03, which are located between two adjacent eighth pixel groups a08, are the first spacers 91.

As a way of the embodiment of the present disclosure, referring to fig. 16, it may be possible to "pull-in" the distance between two second sub-pixels P02 in the second sub-pixel pair P92, so as to increase the distance between the second sub-pixel P02 and the third sub-pixel P03, which are diagonally adjacent, in the adjacent eighth pixel group a08 (adjacent row), so that the spacer 911 (first spacer region 91) may be disposed between the second sub-pixel P02 and the third sub-pixel P03. Of course, the spacer 911 is also located in the adjacent eighth pixel group a08 and is inclined between two adjacent first sub-pixels P01.

In some embodiments, at least some of the spacers between the first sub-pixel P01 and the second sub-pixel P02 that are adjacent to the eighth pixel group a08 are the first spacers 91.

As another way of the embodiment of the present disclosure, referring to fig. 17, the first sub-pixel P01 and the third sub-pixel P03 may also be "compressed" along the column direction, so as to increase the distance between the first sub-pixel P01 and the third sub-pixel P03, which are diagonally adjacent, in the adjacent eighth pixel group a08 (adjacent row), so that the spacer 911 (first spacer region 91) may be disposed between the first sub-pixel P01 and the third sub-pixel P03. Of course, the spacer 911 is also located in the adjacent eighth pixel group a08 and is inclined between two adjacent second sub-pixels P02.

In this way, the first sub-pixels P01 located at the upper and lower sides, respectively, of the adjacent eighth pixel group a08 are located closer to the "same row", so that a better display effect can be achieved.

In some embodiments, two second sub-pixels P02 of the second sub-pixel pair P92 are symmetrically distributed with respect to a line parallel to the first direction.

Referring to fig. 15, 16, and 17, the two second subpixels P02 of each second subpixel pair P92 may be vertically symmetric to improve the uniformity of the distribution of the second subpixel pairs P92.

The shapes of the first sub-pixel P01, the second sub-pixel P02, and the third sub-pixel P02 may be various. For example, referring to fig. 15, 16, and 17, the first and third sub-pixels P01 and P02 may be each a hexagon, and each hexagon may be divided into two parts that are vertically symmetrical; each second sub-pixel P02 may be a pentagon, that is, a hexagon is formed by splicing two second sub-pixels P02 of each second sub-pixel pair P92.

As a manner of the embodiment of the present disclosure, referring to fig. 15, 16, and 17, the area of the above second sub-pixel P02 (e.g., green sub-pixel) may be the smallest, for example, the area of the third sub-pixel P03 (e.g., blue sub-pixel) is the largest, the area of the second sub-pixel P02 (e.g., green sub-pixel) is the smallest, and the area of the first sub-pixel P01 (e.g., red sub-pixel) is the middle, etc.

In some embodiments, the resolution of the display substrate is less than or equal to 1000 PPI.

The display substrate of the embodiment of the disclosure is suitable for the case of low resolution, for example, resolution is not more than 1000PPI (pixels per inch), further not more than 800PPI, further not more than 600PPI, and the like. When the resolution of the display substrate is too high, the theoretically possible spacing between the sub-pixels P is too small, and it is difficult to achieve the above spacing condition.

In a second aspect, referring to fig. 18, an embodiment of the present disclosure further provides a display device including any one of the display substrates described above.

The display substrate described above may be assembled with other structures (e.g., a pair of case substrates, a driver, a power module, a housing, etc.) to form a display device which is a separate product having a display function.

Specifically, the display device may be any product or component having a display function, such as an Organic Light Emitting Diode (OLED) display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims

1. A display substrate comprises a substrate base plate and a plurality of sub-pixels arranged on the substrate base plate at intervals in an array; it is characterized in that the preparation method is characterized in that,

at least part of the function positions are provided with function parts;

2. The display substrate of claim 1,

the width of the first spacer is greater than or equal to 20 μm.

3. The display substrate of claim 1,

the distance between the boundary of the function and the boundary of the nearest sub-pixel is greater than or equal to 3 μm.

4. The display substrate of claim 1,

the width of the second spacer region is less than or equal to 19 μm.

5. The display substrate of claim 1,

at least part of the shortest connecting line between the boundaries of the two sub-pixels corresponding to the first interval area passes through the functional element in the first interval area.

6. The display substrate of claim 5,

in a cross section which passes through the shortest connecting line and is vertical to the substrate, the distance between the boundaries of two sub-pixels corresponding to the first interval area is greater than or equal to 20 μm, and the distance between the functional element in the first interval area and the sub-pixels is greater than or equal to 3 μm.

7. The display substrate of claim 1,

at least part of the connecting line between the geometric centers of the two sub-pixels corresponding to the first interval area passes through the functional element in the first interval area.

8. The display substrate of claim 7,

at least part of the connecting line between the geometric centers of the two sub-pixels corresponding to the first interval area passes through the geometric center of the functional element in the first interval area.

9. The display substrate of claim 1,

at least a portion of the first spacer region extends in the third direction;

10. The display substrate of claim 1,

the distance between adjacent functional elements is between 100 μm and 300 μm.

11. The display substrate of claim 1,

the number of function bits provided with said functions is at least 15% of the total number of functions.

12. The display substrate according to claim 1, further comprising a pixel defining layer;

13. The display substrate of claim 12,

the functional element and the pixel defining part are of an integral structure.

14. The display substrate of claim 1,

among a plurality of sub-pixels adjacent to at least part of the functional element, at least one geometric center of the sub-pixel is deviated from a straight line extending along the first direction, and geometric centers of at least two sub-pixels in the same row as the sub-pixel in the first direction are located on the straight line;

and/or the presence of a gas in the gas,

15. The display substrate of claim 1, wherein the sub-pixels comprise a first sub-pixel, a second sub-pixel, a third sub-pixel;

16. The display substrate of claim 15,

in the spacer between the first sub-pixel and the third sub-pixel adjacent to each other in the third pixel group, at least a part of the spacer is the first spacer;

17. The display substrate of claim 16,

the first and second spacing regions alternate along the second direction between the adjacent first and third sub-pixels in the third pixel group;

18. The display substrate of claim 17,

the geometric centers of the two first sub-pixels and the geometric centers of the two third sub-pixels which are arranged in an array form a sequential connection line to form a virtual trapezoid;

19. The display substrate of claim 18,

the base of the virtual trapezoid is parallel to the second direction.

20. The display substrate of claim 18,

the virtual trapezoid is a virtual isosceles trapezoid.

21. The display substrate of claim 16,

in the first spacing area at least partially located between the adjacent first sub-pixel and the third sub-pixel, the geometric center of the functional element is located on a connecting line between the geometric center of the first sub-pixel and the geometric center of the third sub-pixel corresponding to the first spacing area.

22. The display substrate of claim 16,

in the first spacing area at least partially located between the adjacent first sub-pixel and the third sub-pixel, along the second direction, a distance between a geometric center of the functional element and a geometric center of the first sub-pixel corresponding to the first spacing area is smaller than a distance between a geometric center of the functional bit and a geometric center of the third sub-pixel corresponding to the first spacing area.

23. The display substrate of claim 22,

in the first spacing area at least partially located between the adjacent first sub-pixel and the third sub-pixel, along the second direction, the geometric center of the functional element is located on one side of the reference line corresponding to the functional element, which is close to the first sub-pixel corresponding to the first spacing area; and the reference line of the functional bit is a connecting line between the geometric centers of the two second sub-pixels positioned at two sides of the functional bit in the first direction.

24. The display substrate of claim 15,

the shape of the first sub-pixel comprises a square or a rounded square, one diagonal of the square or the rounded square is parallel to the first direction, and the other diagonal of the square or the rounded square is parallel to the second direction;

25. The display substrate of claim 15,

at least part of the third sub-pixels are divided into a first part and a second part which are asymmetric along a straight line which passes through the geometric center of the third sub-pixels and is parallel to the first direction, and the maximum size of the first part is smaller than that of the second part along the second direction;

26. The display substrate of claim 1, wherein the sub-pixels comprise a first sub-pixel, a second sub-pixel, a third sub-pixel;

27. The display substrate of claim 26,

among the spacers between the adjacent third sub-pixels in the seventh pixel group, at least a part of the spacers is the first spacers;

28. The display substrate of claim 27,

at least a part of the spacing regions between the adjacent third sub-pixels in the seventh pixel group are the first spacing regions and the second spacing regions alternately along the second direction.

29. The display substrate of claim 26,

30. The display substrate of claim 1, wherein the sub-pixels comprise a first sub-pixel, a second sub-pixel, a third sub-pixel;

a plurality of the eighth pixel groups are arranged in the second direction;

31. The display substrate of claim 30,

and the spacers are respectively positioned in two adjacent eighth pixel groups, and at least part of the spacers are the first spacers in the spacers between the adjacent first sub-pixels and the adjacent third sub-pixels.

32. The display substrate of claim 30,

and the spacers are respectively positioned in two adjacent eighth pixel groups, and at least part of the spacers are the first spacers in the spacers between the adjacent first sub-pixels and the adjacent second sub-pixels.

33. The display substrate of claim 30,

two second sub-pixels in the second sub-pixel pair are symmetrically distributed relative to a line parallel to the first direction.

34. The display substrate of any one of claims 15 to 33,

the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

35. The display substrate of claim 1,

the function is to include the spacer position, the function piece includes the spacer.

36. A display device, comprising:

the display substrate of any one of claims 1 to 35.