CN113396452A

CN113396452A - Display panel and driving method of display panel

Info

Publication number: CN113396452A
Application number: CN202080012789.6A
Authority: CN
Inventors: 金珍浩; 申相旻; 丁英基
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-03-29
Filing date: 2020-03-27
Publication date: 2021-09-14
Anticipated expiration: 2040-03-27
Also published as: EP3871211A1; CN113396452B; KR20200115003A; EP3871211B1; EP3871211A4; KR102657371B1; KR20200114980A

Abstract

A display panel including a plurality of pixels is provided. The display panel includes: a plurality of light emitting elements configured to constitute each of a plurality of pixels; and a plurality of pixel circuits respectively corresponding to the plurality of light emitting elements and configured to drive the plurality of light emitting elements, wherein the plurality of pixel circuits includes a first pixel circuit for Pulse Width Modulation (PWM) driving a first light emitting element of the plurality of light emitting elements and a second pixel circuit for Pulse Amplitude Modulation (PAM) driving a second light emitting element of the plurality of light emitting elements.

Description

Display panel and driving method of display panel

Technical Field

The present disclosure relates to a display panel and a driving method of the display panel, and more particularly to a display panel in which light emitting elements constitute pixels and a driving method of the display panel.

Background

In recent years, display panels that display images by light emitting elements such as red Light Emitting Diodes (LEDs), green LEDs, and blue LEDs have been developed. Each pixel of such a display panel may include a plurality of sub-pixels, and each sub-pixel includes a light emitting element. In this case, the light emitting element may be implemented as a micro LED.

In such a display panel, when the gray scale of the sub-pixel is expressed by a Pulse Amplitude Modulation (PAM) driving method, since the wavelength of light emitted according to the amplitude of the driving current is changed together with the gray scale, there is a problem in that the color reproducibility of an image is lowered. Fig. 1 illustrates a variation in wavelength according to the magnitude (or amplitude) of a driving current flowing through a blue LED, a green LED, and a red LED.

In addition, when the sub-pixels are implemented by light emitting elements, each light emitting element requires a pixel circuit for driving the sub-pixel. In this case, if the pixel circuit occupies a large area in the display panel, there is a problem that a high-resolution display panel cannot be provided.

Disclosure of Invention

[ problem ] to provide a method for producing a semiconductor device

A display panel and a driving method thereof are provided, which can provide a high resolution display panel while improving color reproducibility by optimizing the design of a driving circuit for driving LEDs (which are inorganic light emitting elements) mounted on a substrate with respect to an input image signal.

Further, a display panel and a driving method thereof capable of securing a range of a PWM data voltage capable of stably representing a gray scale are provided.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[ technical solution ] A

According to an aspect of the present disclosure, a display panel including a plurality of pixels includes: a plurality of light emitting elements configured to constitute each of a plurality of pixels; and a plurality of pixel circuits respectively corresponding to the plurality of light emitting elements and configured to drive the plurality of light emitting elements, wherein the plurality of pixel circuits includes a first pixel circuit for Pulse Width Modulation (PWM) driving a first light emitting element of the plurality of light emitting elements and a second pixel circuit for Pulse Amplitude Modulation (PAM) driving a second light emitting element of the plurality of light emitting elements.

The plurality of light emitting elements may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element; the first light emitting element may correspond to a green light emitting element; and the second light emitting element may correspond to a red light emitting element and a blue light emitting element.

The size of the first pixel circuit may be larger than the size of the second pixel circuit.

Each of the plurality of light emitting elements may be configured to: emitting light based on a driving current supplied from a corresponding pixel circuit of the plurality of pixel circuits; the first pixel circuit may be configured to: supplying a first driving current to the first light emitting element for a time corresponding to the PWM data voltage applied to the first pixel circuit, the first driving current having a magnitude corresponding to the first PAM data voltage applied to the first pixel circuit; and the second pixel circuit may be configured to: a second driving current is supplied to the second light emitting element, the second driving current having a magnitude corresponding to a second PAM data voltage applied to the second pixel circuit.

The gray scale of light emitted from the first light emitting element is controlled by a time for which the first driving current is supplied to the first light emitting element according to the magnitude of the PWM data voltage. The gray scale of light emitted from the second light emitting element is controlled by the magnitude of the second driving current according to the magnitude of the second PAM data voltage.

Each of the plurality of light emitting elements may be a micro Light Emitting Diode (LED).

The first pixel circuit may be configured to: changing a voltage of a terminal of the first pixel circuit according to a sweep voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to the PWM data voltage to the first light emitting element; and the swept voltage may be a voltage that varies linearly from the second voltage after varying from the first voltage to the second voltage.

The first pixel circuit may include a transistor and may be configured to control a pulse width of the driving current by performing a switching operation of the transistor based on a voltage of a gate terminal of the transistor, which varies according to the swept voltage.

The swept voltage may be a voltage that rises from a first voltage to a second voltage before an emission time of the first light emitting element and then decreases from the second voltage over time during the emission time.

The voltage of the gate terminal of the transistor may increase with increasing swept frequency voltage by a difference between the second voltage and the first voltage, and may decrease with decreasing swept frequency voltage from the increasing voltage; and the pulse width of the driving current may be determined based on a time until the reduced voltage of the gate terminal reaches a certain voltage.

The specific voltage may be a voltage determined based on a driving voltage for driving the first pixel circuit.

The difference between the first voltage and the second voltage may correspond to a range of PWM data voltages for representing gray scales of light emitted from the first inorganic light emitting element.

The first pixel circuit may be configured to: the transistor connected in parallel with the first inorganic light emitting element is turned on for a period including a point of time when a switching operation of the transistor is performed to discharge a leakage current.

According to another aspect of the present disclosure, a driving method of a display panel in which each of a plurality of pixels includes a plurality of light emitting elements and includes a plurality of pixel circuits for driving the plurality of light emitting elements respectively corresponding to the plurality of light emitting elements, the driving method includes: driving a first light emitting element of the plurality of light emitting elements by a first pixel circuit Pulse Width Modulation (PWM); and driving a second light emitting element of the plurality of light emitting elements by a second pixel circuit Pulse Amplitude Modulation (PAM).

Each of the plurality of light emitting elements may emit light based on a driving current supplied from a corresponding pixel circuit of the plurality of pixel circuits; the PWM driving may include: supplying, by the first pixel circuit, a first driving current to the first light emitting element for a time corresponding to the PWM data voltage applied to the first pixel circuit, the first driving current having a magnitude corresponding to a first PAM data voltage applied to the first pixel circuit; and the PAM driving may include: a second drive current is provided by the second pixel circuit to the second light emitting element, the second drive current having a magnitude corresponding to a second PAM data voltage applied to the second pixel circuit.

The gray scale of light emitted from the first light emitting element is controlled by a time for which the first driving current is supplied to the first light emitting element according to the magnitude of the PWM data voltage. The gray scale of light emitted from the second light emitting element is controlled by the magnitude of the second driving current according to the magnitude of the second PWM data voltage.

Each of the plurality of light emitting elements may be a micro LED.

The PWM driving may include: changing, by the first pixel circuit, a voltage of a terminal of the first pixel circuit according to a sweep voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to the PWM data voltage to the first light emitting element; and the swept voltage may be a voltage that varies linearly from the second voltage after varying from the first voltage to the second voltage.

The PWM driving may further include: the pulse width of the drive current is controlled by the first pixel circuit by performing a switching operation of a transistor based on a voltage of a gate terminal of the transistor of the first pixel circuit, the voltage of the gate terminal of the transistor varying according to the sweep voltage.

The voltage of the gate terminal of the transistor may increase the difference between the second voltage and the first voltage as the swept frequency voltage increases and decrease from the increased voltage as the swept frequency voltage decreases; and the pulse width of the driving current may be determined based on a time until the reduced voltage of the gate terminal reaches a certain voltage.

The PWM driving may include: in a period including a point of time when a switching operation of the transistor is performed, the transistor connected in parallel with the first inorganic light emitting element is turned on by the first pixel circuit to discharge a leakage current.

According to another aspect of the present disclosure, a plurality of pixel circuits respectively corresponding to a plurality of light emitting elements constituting a pixel includes: a first pixel circuit configured to Pulse Width Modulation (PWM) drive a first light emitting element of a plurality of light emitting elements; and a second pixel circuit configured to Pulse Amplitude Modulation (PAM) drive a second light emitting element of the plurality of light emitting elements.

The first pixel circuit may be configured to PWM-drive the green light emitting element; and the second pixel circuit may be configured to PAM drive the red light emitting element and the blue light emitting element.

The first pixel circuit may be configured to: supplying a first driving current to the first light emitting element for a time corresponding to the PWM data voltage applied to the first pixel circuit, the first driving current having a magnitude corresponding to the first PAM data voltage applied to the first pixel circuit; and the second pixel circuit may be configured to: a second driving current is supplied to the second light emitting element, the second driving current having a magnitude corresponding to a second PAM data voltage applied to the second pixel circuit.

[ PROBLEMS ] the present invention

As described above, according to the different embodiments of the present disclosure, it is possible to prevent the wavelength of light emitted from the inorganic light emitting elements included in the display panel from varying according to the gray scale.

Further, color difference (mura) or color of inorganic light emitting elements constituting the display panel can be corrected, and even when a display panel having a large area is configured by combining module type display panels, luminance or color difference between the display panel modules can be corrected.

In addition, a more optimized pixel circuit can be designed, thereby providing a high resolution display panel.

Further, a range of the PWM data voltage capable of stably representing the gradation can be secured.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a graph showing a change in wavelength according to the magnitude of a driving current flowing through a blue LED, a green LED, and a red LED;

fig. 2 is a diagram for describing a pixel structure of a display panel according to an embodiment;

fig. 3 is a diagram for describing a pixel structure of a display panel according to an embodiment;

fig. 4 is a cross-sectional view of a display panel according to an embodiment;

fig. 5 is a block diagram showing a configuration of a display panel according to the embodiment;

fig. 6 is a block diagram showing a configuration of a display panel according to the embodiment;

fig. 7 is a block diagram showing a configuration of a pixel circuit according to the embodiment;

fig. 8 is a block diagram showing a configuration of a pixel circuit according to the embodiment;

fig. 9 to 11 are circuit diagrams of a pixel circuit according to an embodiment;

fig. 12 is a diagram for describing a method for determining a pulse width of a driving current according to an embodiment;

fig. 13 is a block diagram showing a configuration of a pixel circuit according to the embodiment;

FIG. 14 is a circuit diagram of an internal compensation circuit according to an embodiment;

fig. 15 is a diagram for describing ranges of the sweep voltage and the PWM data voltage according to the embodiment;

fig. 16 is a detailed circuit diagram of a pixel circuit according to an embodiment;

FIG. 17 is a timing diagram of various signals used to drive the pixel circuit of FIG. 16, according to an embodiment;

fig. 18 is a detailed circuit diagram of a pixel circuit according to an embodiment;

FIG. 19 is a timing diagram of various signals used to drive the pixel circuit of FIG. 18, according to an embodiment;

fig. 20 is a configuration diagram of a display device according to an embodiment; and

fig. 21 is a flowchart illustrating a driving method of a display panel according to an embodiment.

Detailed Description

[ embodiment ]

Hereinafter, detailed descriptions of known components or operations related to the embodiments may be omitted. In addition, redundant descriptions of the same or similar structures or operations may be omitted.

The suffix of a component used in the following description ". The device" may be provided for each description and may not have a different meaning or effect per se.

The terminology used in the description is for the purpose of describing the embodiments and is not intended to be limiting and/or restrictive of the disclosure. Unless the context clearly dictates otherwise, singular expressions include plural expressions.

It will be further understood that the terms "comprises" and "comprising," when used in this disclosure, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

The expressions "first", "second", etc. used in the present disclosure may indicate various components regardless of the order and/or importance of the components, and will be used to distinguish one component from other components, and do not limit the corresponding components.

When it is mentioned that any component (e.g., a first component) is (operatively or communicatively) coupled/coupled to another component (e.g., a second component) or connected to another component, it is to be understood that the component is directly coupled/coupled to the other component or may be coupled/coupled to the other component through an intermediate component (e.g., a third component). On the other hand, when it is referred to that any component (e.g., a first component) is "directly coupled"/"directly coupled to" or "directly connected" to another component (e.g., a second component), it is understood that there is no intermediate component (e.g., a third component) between the component and the other component.

Unless otherwise defined, terms used in the detailed description may be construed as meanings well known to those skilled in the art.

It should be understood that as used herein, expressions such as "at least one of" modify the entire list of elements after the list of elements rather than modifying individual elements in the list. For example, the expression "at least one of [ a ], [ B ] and [ C ] or" at least one of [ a ], [ B ] or [ C "means only a, only B, only C, A and B, B and C, A and C, or A, B and C.

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

Fig. 2 is a diagram for describing a pixel structure of a display panel (or display module) 1000 according to an embodiment.

Here, the display panel according to the embodiment may be applied to a wearable device, a portable device, a handheld device, and an electronic product or an electronic device including various displays in a single unit.

In addition, the display panel according to the embodiment may be applied to a display apparatus through a plurality of assembly arrangements in a matrix form. In this case, for example, the display panel includes a monitor for a personal computer, (high definition) Television (TV), a large display device such as a sign, an electronic display, and the like.

As shown in fig. 2, the display panel 1000 may include a plurality of pixels 10 arranged in a matrix form.

In this case, each pixel 10 may include a plurality of sub-pixels 10-1 to 10-3. For example, one pixel 10 of the display panel 1000 may include three types of sub-pixels, for example, a red (R) sub-pixel 10-1, a green (G) sub-pixel 10-2, and a blue (B) sub-pixel 10-3. That is, one set of the R, G, and B sub-pixels may constitute one unit pixel of the display panel 1000.

Each sub-pixel may include a light emitting element. Here, the light emitting element may be an inorganic light emitting element manufactured using an inorganic material, which is different from an Organic Light Emitting Diode (OLED) manufactured using an organic material. In particular, the light-emitting element may be a light-emitting diode (LED), in particular a micro-LED (u-LED or micro-LED). Micro LEDs refer to subminiature inorganic light emitting elements having a size of 100 micrometers (μm) or less, which emit light by themselves without a backlight or a color filter.

Accordingly, the R sub-pixel may include the R micro LED, the G sub-pixel may include the G micro LED, and the B sub-pixel may include the B micro LED.

Referring to fig. 2, the R, G, and B sub-pixels 10-1 to 10-3 are shown to be arranged in an inverted L shape in one pixel 10, but this is merely an example. It should be understood that in various embodiments, the sub-pixels 10-1 to 10-3 may be arranged in various forms.

For example, as shown in fig. 3, according to another embodiment, the R, G, and B sub-pixels 10-1 to 10-3 may be arranged in a row in the pixel 10. However, such an arrangement of the sub-pixels is also merely an example, and a plurality of sub-pixels may be arranged in various forms within each pixel according to various embodiments.

Further, in the above example, the pixel is described as including three types of sub-pixels, i.e., the R sub-pixel, the G sub-pixel, and the B sub-pixel. However, it is to be understood that one or more other embodiments are not so limited. For example, the pixels may be implemented as four types of sub-pixels, e.g., R, G, B and W (white), or may also include any other kind of sub-pixels.

Further, referring to fig. 2, in the display panel 1000, one pixel region 20 may include a region 10 occupied by a pixel and the remaining region 11 around the pixel.

In this case, the region 10 occupied by the pixel may be regarded as a region occupied by a plurality of sub-pixels constituting the pixel and a driving circuit for driving each sub-pixel.

That is, the region 10 occupied by the pixels may include an R light emitting element and a pixel circuit for driving the R light emitting element, a G light emitting element and a pixel circuit for driving the G light emitting element, a B light emitting element, and a pixel circuit for driving the B light emitting element. Meanwhile, the remaining region 11 may include various circuits for driving the pixel circuits.

The pixel circuit may be formed on a substrate of the display panel 1000. Specifically, fig. 4 is a cross-sectional view of a display panel according to an embodiment. In fig. 4, for convenience of description, only one pixel included in the display panel 1000 is illustrated, and sub-pixels in the pixel are illustrated to be arranged in a row.

Referring to fig. 4, the display panel 1000 may include a substrate 30, a driving circuit layer 40, and R, G, and B light emitting elements 50-1 to 50-3.

In this case, the pixel circuit for driving the light emitting elements 50-1, 50-2, 50-3 may be implemented with a Thin Film Transistor (TFT) and a capacitor, and may be included in the driving circuit layer 40 formed on the substrate 30. That is, the driving circuit layer 40 may include a pixel circuit for driving the R light emitting element 50-1, a pixel circuit for driving the G light emitting element 50-2, and a pixel circuit for driving the B light emitting element 50-3.

In addition, the substrate 30 may be implemented with glass, and the display panel 1000 in which the driving circuit layer 40 and the light emitting elements 50-1 to 50-3 are formed on the glass may be referred to as a Chip On Glass (COG) type display panel. In this case, the glass and the driver circuit layer 40 formed on the glass may be collectively referred to as a TFT panel or a glass substrate. However, this is merely an example, and the substrate may be implemented with various materials in various embodiments.

The TFTs of the TFT layer (or backplane) are not limited to a particular structure or type. In other words, the TFT of the present disclosure may be implemented as an oxide TFT and a Si TFT (polycrystalline silicon, amorphous silicon (a-silicon)), an organic TFT, a graphene TFT, etc., in addition to the LTPS TFT, and only a P-type (or N-type) MOSFET may be fabricated and applied in a Si wafer CMOS process.

In addition, the R, G, and B light emitting elements 50-1 to 50-3 may be disposed on the driving circuit layer 40. In this case, the light emitting element may be mounted or disposed on the driving circuit layer 40 to be electrically connected to the pixel circuit.

For example, the R light emitting element 50-1 may be electrically connected to an electrode 1 for driving the R light emitting element 50-1 formed or disposed on the pixel circuit, the G light emitting element 50-2 may be electrically connected to an electrode 2 for driving the G light emitting element 50-2 formed or disposed on the pixel circuit, and the B light emitting element 50-3 may be electrically connected to an electrode 3 for driving the B light emitting element 50-3 formed or disposed on the pixel circuit.

Meanwhile, the light emitting elements 50-1 to 50-3 may be implemented as flip-chip type micro LEDs. However, the light emitting elements 50-1 to 50-3 are not limited thereto, and in some embodiments, the light emitting elements 50-1 to 50-3 may be lateral type or longitudinal type micro LEDs.

Further, according to an embodiment, the display panel 1000 may further include at least one of: a multiplexing circuit for selecting any one of a plurality of sub-pixels 10-1 to 10-3 constituting the pixel 10, an electrostatic discharge circuit (ESD) for preventing static electricity generated in the display panel 1000, at least one gate driver for driving the pixels arranged in a matrix form on the display panel 1000 in a horizontal line unit (or a row unit), a data driver (or a source driver) for supplying a data voltage (e.g., a Pulse Amplitude Modulation (PAM) data voltage, a Pulse Width Modulation (PWM) data voltage, etc.) to each pixel or each sub-pixel, and the like.

Fig. 5 is a block diagram showing a configuration of the display panel 1000 according to the embodiment.

Referring to fig. 5, the display panel 1000 may include the light emitting element 100 and the pixel circuit 200.

The light emitting element 100 constitutes a sub-pixel of the display panel 1000. Specifically, the display panel 1000 may include a plurality of pixels arranged in a matrix form, and each pixel may include a plurality of sub-pixels. Therefore, for each pixel, a plurality of light emitting elements 100 may be included.

In this case, the display panel 1000 may include a plurality of types of light emitting elements 100, and the type of the sub-pixel may be determined according to the type of the light emitting element 100.

Specifically, the display panel 1000 may include red (R) light emitting elements for emitting red light, green (G) light emitting elements for emitting green light, and blue (B) light emitting elements for emitting blue light. In this case, the pixels of the display panel 1000 include an R sub-pixel, a G sub-pixel, and a B sub-pixel. The R light emitting element may constitute an R sub-pixel, the G light emitting element may constitute a G sub-pixel, and the B light emitting element may constitute a B sub-pixel.

On the other hand, the light emitting element 100 may be a micro LED. In this case, the R sub-pixel may include an R micro LED, the G sub-pixel may include a G micro LED, and the B sub-pixel may include a B micro LED.

In addition, the light emitting element 100 can emit light according to the driving current supplied from the pixel circuit 200.

Specifically, the light emitting element 100 may emit light of different brightness according to the magnitude or pulse width of the driving current supplied from the pixel circuit 200. Here, the pulse width of the drive current may also be expressed as a duty ratio of the drive current or a drive time (or duration) of the drive current.

For example, the light emitting element 100 may emit light with high luminance when the amplitude of the driving current is large, and may emit light with high luminance when the pulse width is long (i.e., the duty ratio is high or the driving time is long), but is not limited thereto.

The pixel circuit 200 can drive the light emitting element 100. Specifically, the pixel circuit 200 can drive the light emitting element 100 to control the gradation of light emitted from the light emitting element 100. In this case, according to the embodiment, depending on the type of the light emitting element, a specific type of the light emitting element may be driven by the pixel circuit for PWM driving, and other types of the light emitting element may be driven by the pixel circuit for PAM driving. Details thereof are described below.

Meanwhile, according to an embodiment, the pixel circuit 200 may drive the light emitting element 100 for rendering a gray scale in a unit of a sub-pixel. As described above, since the display panel 1000 has sub-pixels configured in units of the light emitting elements 100, the pixel circuit 200 can drive the light emitting elements 100 for rendering (express) gradation in units of sub-pixels, unlike a Liquid Crystal Display (LCD) panel using a plurality of LEDs that emit the same monochromatic light as a backlight.

To this end, each sub-pixel of the display panel 1000 may include a light emitting element 100 and a pixel circuit 200 for driving the light emitting element 100. That is, for each light emitting element 100, there may be a pixel circuit 200 for driving the light emitting element 100. Specifically, the display panel 1000 may include, for each pixel, a pixel circuit for driving an R light emitting element, a pixel circuit for driving a G light emitting element, and a pixel circuit for driving a B light emitting element.

Therefore, according to the embodiment shown in fig. 6, the display panel 1000 may include a plurality of pixels, and each pixel 10 may include a plurality of sub-pixels 10-1 to 10-3. Specifically, each pixel 10 may include a plurality of light emitting elements 100-1 to 100-3 and a plurality of pixel circuits 200-1 to 200-3 for driving the plurality of light emitting elements 100-1 to 100-3. In this case, the plurality of light emitting elements 100-1 to 100-3 may include an R light emitting element 100-1, a G light emitting element 100-2, and a B light emitting element 100-3.

In addition, each of the plurality of light emitting elements 100-1 to 100-3 may emit light based on a driving current supplied by a pixel circuit for driving each light emitting element among the plurality of pixel circuits 200-1 to 200-3. That is, the light emitting element 100-1 may emit light based on the driving current supplied from the pixel circuit 200-1, the light emitting element 100-2 may emit light based on the driving current supplied from the pixel circuit 200-2, and the light emitting element 100-3 may emit light based on the driving current supplied from the pixel circuit 200-3.

Meanwhile, according to an embodiment, the display panel 1000 may drive the light emitting elements in different manners according to the types of the light emitting elements. For example, the display panel 1000 may drive a specific type of light emitting element in a PAM manner, and may drive another specific type of light emitting element in a PWM manner. For this, the display panel 1000 may include a pixel circuit capable of driving the light emitting elements in the PAM manner and a pixel circuit capable of driving the light emitting elements in the PWM manner.

Specifically, the plurality of pixel circuits 200-1 to 200-3 may include: a first pixel circuit for PWM-driving a first light emitting element among the plurality of light emitting elements 100-1 to 100-3, and a second pixel circuit for PAM-driving a second light emitting element among the plurality of light emitting elements 100-1 to 100-3. In this case, the size of the first pixel circuit may be larger than the size of the second pixel circuit.

Further, the first light emitting element may include a G light emitting element, and the second light emitting element may include an R light emitting element or a B light emitting element.

Specifically, the first pixel circuit may supply the first driving current having a magnitude corresponding to the PAM data voltage applied to the first pixel circuit to the first light emitting element for a time corresponding to the PWM data voltage applied to the first pixel circuit. In this case, the gray scale of light emitted from the first light emitting element may be controlled by the time for which the first driving current is supplied to the first light emitting element according to the magnitude of the PWM data voltage.

In addition, the second pixel circuit may supply the second light emitting element with a second driving current having a magnitude corresponding to the PAM data voltage applied to the second pixel circuit. In this case, the gray scale of light emitted from the second light emitting element may be controlled by the magnitude of the second driving current according to the magnitude of the PAM data voltage.

That is, the first pixel circuit may drive G light emitting elements among the light emitting elements included in the display panel 1000 using a PWM driving method. In this case, for each G light emitting element, a first pixel circuit for driving the G light emitting element may be included in the display panel 1000.

In addition, the second pixel circuit may drive the R light emitting element and the B light emitting element among the light emitting elements included in the display panel 1000 using a PAM driving method. In this case, for each R light emitting element, a second pixel circuit for driving the R light emitting element may be included in the display panel 1000, and for each B light emitting element, a second pixel circuit for driving the B light emitting element may be included in the display panel 1000.

The pixel circuit as described above will be described in more detail below.

Fig. 7 and 8 are diagrams for describing

pixel circuits

700 and 800 according to an embodiment.

First, as shown in fig. 7, the first pixel circuit 700 may supply a driving current to the light emitting element 100. Here, the light emitting element 100 may include a G light emitting element.

In this case, the first pixel circuit 700 may control the amplitude and pulse width of the driving current for driving the light emitting element 100 together, for example, by receiving the PAM data voltage and the PWM data voltage from the data driver, and may drive the light emitting element 100 by supplying the driving current controlled in both the amplitude and pulse width to the light emitting element 100.

For this, as shown in fig. 7, the first pixel circuit 700 may include a PWM driving circuit 710 and a PAM driving circuit 720.

Here, controlling the amplitude and pulse width of the driving current "together" does not require the first pixel circuit 700 to simultaneously control the amplitude and pulse width of the driving current at the same time, but indicates that the PWM driving and the PAM driving are used together for gray scale representation.

That is, the PAM drive circuit 720 may control the amplitude of the drive current supplied to the light emitting element 100 based on the PAM data voltage. In addition, the PWM driving circuit 710 may control a pulse width of the driving current supplied to the light emitting element 100 based on the PWM data voltage.

Specifically, the PAM drive circuit 720 supplies a drive current having a magnitude corresponding to the PAM data voltage to the light emitting element 100. In this case, the PWM driving circuit 710 controls the pulse width of the driving current by controlling the driving time of the driving current (i.e., the driving current having the amplitude corresponding to the PAM data voltage) supplied to the light emitting element 100 by the PAM driving circuit 720 based on the PWM data voltage.

In this case, according to an embodiment, the PAM data voltage may be commonly applied to all pixels (or all sub-pixels) included in the display panel 1000, and the commonly applied PAM data voltage may be a voltage of the same magnitude.

The first pixel circuit 700 controls the gray scale of light emitted from the light emitting element 100 by the PWM driving method. That is, the PWM driving method is a method for displaying a gray scale in accordance with the light emission time of the light emitting element 100. Therefore, when the light emitting element 100 is driven by the PWM driving method, various gradations can be expressed by changing the light emitting time even if the magnitude of the driving current is the same.

Specifically, the data driver may supply the PWM data voltage to the first pixel circuit 700 to represent the gray scale by the PWM driving, and the first pixel circuit 700 may control the gray scale of the light emitted from the light emitting element 100 by controlling the driving time of the driving current according to the PWM data voltage.

In this case, the first pixel circuit 700 may also be referred to as a PWM pixel circuit because it represents the gradation of the light emitting element 100 by a PWM driving method.

As such, according to the embodiment, the first pixel circuit 700 drives the light emitting element 100 by the PWM driving method. Thus, as described above with reference to fig. 1, the following problems can be solved: the LED is driven by the PAM driving method and the wavelength of light emitted from the LED (particularly, a micro LED) is changed according to the gray scale, thereby reducing color reproducibility.

However, the first pixel circuit 700 may have a larger size because it includes the PWM driving circuit 710 and the PAM driving circuit 720.

Accordingly, when the first pixel circuit 700 is used to drive each of the light emitting elements included in all the pixels of the display panel 1000, a per-inch pixel (PPI) is reduced, which is not suitable for high resolution (e.g., 8K).

Therefore, according to the embodiment, the G light emitting elements having a relatively large wavelength variation (or wavelength shift) according to the driving current are PWM-driven through the first pixel circuit 700, and the R and B light emitting elements having a relatively small wavelength variation are PAM-driven as described below.

As shown in fig. 8, the second pixel circuit 800 can supply a driving current to the light emitting element 100. Here, the light emitting element 100 may include an R light emitting element and a B light emitting element.

In this case, the second pixel circuit 800 may control the magnitude of the driving current for driving the light emitting element 100, for example, by receiving the PAM data voltage from the data driver, and may drive the light emitting element 100 by supplying the driving current having the controlled magnitude to the light emitting element 100.

To this end, as shown in fig. 8, the second pixel circuit 800 may include a PAM driving circuit 810.

That is, the PAM drive circuit 810 may control the amplitude of the drive current supplied to the light emitting element 100 based on the PAM data voltage. Specifically, the PAM drive circuit 810 may supply a drive current having a magnitude corresponding to the PAM data voltage to the light emitting element 100.

That is, the data driver may supply the PAM data voltage to the second pixel circuit 800 to represent the gray scale by PAM driving, and the second pixel circuit 800 may control the gray scale of light emitted from the light emitting element 100 by controlling the magnitude of the driving current according to the PAM data voltage.

In this case, the second pixel circuit 800 may also be referred to as a PAM pixel circuit because it represents the gray scale of the light emitting element 100 by a PAM driving method.

According to the embodiment, the G light emitting elements included in the display panel 1000 are driven by the PWM pixel circuit, and the R light emitting elements and the B light emitting elements included in the display panel 1000 are driven by the PAM pixel circuit. Accordingly, it is possible to provide the display panel 1000 of high resolution because the entire area occupied by the pixel circuits is smaller than the case where all the light emitting circuits are driven by the PWM pixel circuits, while solving the problem of the color reproducibility being reduced when the wavelength of light is changed according to the gray scale.

Fig. 9 to 11 show circuit diagrams of a pixel circuit according to an embodiment.

First, fig. 9 and 10 show examples of the first pixel circuit (i.e., PWM pixel circuits 900 and 1100). The

PWM pixel circuits

900 and 1100 may include

PWM driving circuits

910 and 1110 and

PAM driving circuits

920 and 1120, and may supply driving currents to the light emitting elements 100 through these driving circuits.

Specifically, the

PAM drive circuits

920 and 1120 may control the amplitude of the drive current supplied to the light emitting element 100 based on the applied PAM data voltage Sig. In addition, the

PWM driving circuits

910 and 1110 may control the driving time of the driving current supplied to the light emitting element 100 by the

PAM driving circuits

920 and 1120 based on the applied PWM data voltage Sig. That is, the

PWM driving circuits

910 and 1110 control the pulse width of the driving current based on the applied PWM data voltage Sig.

In this case, the PAM data voltage and the PWM data voltage may be applied to the PAM driving circuit and the PWM driving circuit, respectively, in a time-division manner.

Accordingly, the

PWM pixel circuits

900 and 1100 may supply the driving current having the pulse width corresponding to the PWM data voltage for gradation representation of each pixel to the light emitting element 100, and the light emitting element 100 may emit light according to the driving current supplied from the

PWM pixel circuits

900 and 1100.

Fig. 11 shows an example of a second pixel circuit, i.e., a PAM pixel circuit 1200. The PAM pixel circuit 1200 may include a PAM driving circuit 1210, and a driving current may be supplied to the light emitting element 100 through the PAM driving circuit 1210.

Specifically, the PAM drive circuit 1210 may control the amplitude of the drive current supplied to the light emitting element 100 based on the PAM data voltage Sig applied.

Accordingly, the PAM pixel circuit 1200 may supply the light emitting element 100 with a driving current having a magnitude corresponding to a PAM data voltage for grayscale representation of each pixel, and the light emitting element 100 may emit light according to the driving current supplied from the PAM pixel circuit 1200.

Referring to fig. 9 and 10, the

PWM pixel circuits

900 and 1100 may be implemented with thirteen transistors (i.e., T1 to T13) and two capacitors (i.e., C1 and C2) because the

PWM pixel circuits

900 and 1100 include

PWM driving circuits

910 and 1110 and

PAM driving circuits

920 and 1120. Meanwhile, referring to fig. 11, the PAM pixel circuit 1200 may be implemented with seven transistors (i.e., T1 through T7) and one capacitor (i.e., C2) because it includes only the PAM driving circuit 1210. As such, the PAM pixel circuit 1200 may be implemented in a smaller size than the

PWM pixel circuits

900 and 1100.

Therefore, the case where the pixel circuit for driving the G light emitting element is formed or implemented by the

PWM pixel circuits

900 and 1100 and the pixel circuit for driving the R light emitting element and the B light emitting element is formed or implemented by the PAM pixel circuit 1200 occupies a smaller area in the display panel 1000 than the case where all the pixel circuits are formed by the

PWM pixel circuits

900 and 1100. For example, PW is used for all pixel circuitsIn the case where the

M pixel circuits

900 and 1100 are formed, the area of the entire pixel circuit is 48000 μ M²Whereas, in the case where the pixel circuit for driving the R light emitting element and the B light emitting element according to the embodiment is formed of the PAM pixel circuit 1200 and the pixel circuit for driving the G light emitting element is formed of the

PWM pixel circuits

900 and 1100, the area of the entire pixel circuit is 29000 μm²And can be relatively reduced by 40%.

Therefore, according to the embodiment, it is possible to provide the high resolution display panel 1000 while solving the problem that the wavelength varies according to the gray scale to reduce the color reproducibility.

It should be understood that the circuits shown in fig. 9-11 are merely examples, and that one or more other embodiments are not limited thereto. That is, the PWM pixel circuit may be implemented in various types of circuits and circuit arrangements including a PWM drive circuit and a PAM drive circuit. In addition, the PAM pixel circuit may be implemented in various types of circuits and circuit arrangements including a PAM drive circuit.

In the above example, it has been described that the pixel includes three kinds of sub-pixels (i.e., the R sub-pixel, the G sub-pixel, and the B sub-pixel), and in this case, the pixel circuit for driving the G light emitting element is implemented with the PWM pixel circuit, and the pixel circuits for driving the R light emitting element and the B light emitting element are implemented with the PAM pixel circuit. It is to be understood that one or more other embodiments are not limited thereto.

For example, according to one or more other embodiments, even in the case where a pixel includes four kinds of sub-pixels (e.g., an R sub-pixel, a G sub-pixel, a B sub-pixel, and a W sub-pixel), a pixel circuit for driving a G light emitting element may be implemented with a PWM pixel circuit, and pixel circuits for driving an R light emitting element and a B light emitting element may be implemented with a PAM pixel circuit. In this case, the pixel circuit for driving the W light emitting element can be realized by a PWM pixel circuit.

According to another aspect of the present disclosure, a plurality of pixel circuits respectively corresponding to a plurality of light emitting elements constituting a pixel includes a first pixel circuit configured to Pulse Width Modulation (PWM) drive a first light emitting element of the plurality of light emitting elements and a second pixel circuit configured to Pulse Amplitude Modulation (PAM) drive a second light emitting element of the plurality of light emitting elements.

The first pixel circuit may PWM-drive the green light emitting element, and the second pixel circuit may PAM-drive the red light emitting element and the blue light emitting element. The size of the first pixel circuit may be larger than the size of the second pixel circuit.

The first pixel circuit may supply a first driving current having a magnitude corresponding to a first PAM data voltage applied to the first pixel circuit to the first light emitting element for a time corresponding to the PWM data voltage applied to the first pixel circuit, and the second pixel circuit may supply a second driving current having a magnitude corresponding to a second PAM data voltage applied to the second pixel circuit to the second light emitting element.

The first pixel circuit may change a voltage of a terminal of the first pixel circuit according to a sweep voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to the PWM data voltage to the first light emitting element, and the sweep voltage may be a voltage linearly changed from the second voltage after changing from the first voltage to the second voltage.

Meanwhile, the first pixel circuit (i.e., the PWM pixel circuit) according to the embodiment may change a voltage of a terminal of the first pixel circuit according to a sweep voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to the PWM data voltage to the first light emitting element.

Here, the first pixel circuit may include a transistor, and the terminal of the first pixel circuit may be a gate terminal of the transistor. In this case, the first pixel circuit can control the pulse width of the drive current by performing the switching operation of the transistor based on the voltage of the gate terminal of the transistor which varies according to the sweep voltage.

The swept voltage is an externally applied voltage that is used to change the voltage of the gate terminal of the transistor. Further, the swept voltage may be a voltage that rises from a first voltage to a second voltage before an emission time of the first light emitting element and then decreases from the second voltage over time during the emission time. In this case, the swept frequency voltage may be reduced from the second voltage to the first voltage during the transmit time.

Thus, the voltage of the gate terminal of the transistor may increase the difference between the second voltage and the first voltage as the swept frequency voltage increases and may decrease from the increased voltage as the swept frequency voltage decreases.

In this case, the pulse width of the driving current may be determined based on the time until the reduced voltage of the gate terminal becomes a certain voltage. Here, the specific voltage may be a voltage determined based on a driving voltage for driving the first pixel circuit.

Specifically, when the PWM data voltage is applied, the first pixel circuit may apply a voltage based on the PWM data voltage to the gate terminal of the transistor. Then, if a step-up sweep voltage is applied to the first pixel circuit before the start of the light emission time, the voltage of the gate terminal of the transistor may increase by the step-up voltage value due to the coupling effect.

For example, referring to fig. 12, if the sweep voltage rises (e.g.,) the voltage applied to the gate terminal of the transistor rises according to the sweep voltage (e.g.,) thereof.

The first pixel circuit may supply a driving current to the first light emitting element according to a voltage of a gate terminal of the transistor if the emission time starts. For example, as shown in fig. 12, when the voltage of the gate terminal increased according to the voltage of the sweep frequency is greater than a certain voltage V₁At this time, the first pixel circuit can supply a driving current to the first light emitting element by using a transistor in an off state (off state).

On the other hand, if the emission time starts, a sweep voltage gradually decreasing with time may be applied to the first pixel circuit. Even in this case, the voltage of the gate terminal of the transistor varies according to the sweep voltage. That is, if a decreasing sweep voltage is applied, the voltage of the gate terminal of the transistor gradually decreases according to the sweep voltage.

For example, referring to fig. 12, if the swept voltage decreases in the form of a triangular wave (e.g., (c)), the increased voltage of the gate terminal decreases in the form of a triangular wave according to the swept voltage (e.g., (r)).

In this case, if the reduced voltage of the gate terminal of the transistor reaches a certain voltage V₁The first pixel circuit may perform a switching operation of the transistor. For example, the first pixel circuit may turn on a transistor in an off state. As such, if the switching operation of the transistor is performed, the first pixel circuit may stop supplying the driving current to the first light emitting element.

Therefore, as shown in fig. 12, the pulse width of the drive current can be determined.

Meanwhile, the difference between the first voltage and the second voltage may correspond to a range of PWM data voltages for representing a gray scale of light emitted from the first light emitting element, and is described in detail below in connection with a driving method of the first pixel circuit.

Fig. 13 shows a block diagram of a first pixel circuit 700 according to an embodiment.

The first pixel circuit 700 may include a PAM driving circuit 720 and a PWM driving circuit 710. The PAM driving circuit 720 and the PWM driving circuit 710 include a transistor and an internal compensation circuit for compensating a threshold voltage of the transistor, respectively.

For example, as shown in fig. 13, the PAM driving circuit 720 may include a transistor T8 and a second internal compensation circuit 72.

The transistor T8 can supply driving currents having different magnitudes to the light emitting element 100 according to the magnitude of the voltage applied to the gate terminal C. Specifically, the PAM drive circuit 720 may supply a drive current having a magnitude corresponding to the applied PAM data voltage to the light emitting element 100 through the transistor T8.

At this time, the threshold voltage of the transistor T8 may be a problem. Specifically, the display panel 1000 has a plurality of sub-pixels, and each sub-pixel has a transistor T8. Theoretically, transistors manufactured under the same condition should have the same threshold voltage, but an actual transistor may have a different threshold voltage even when manufactured under the same condition, and the transistors T8 included in the display panel 1000 are the same.

As such, when there is a difference between the threshold voltages of the transistor T8 corresponding to each sub-pixel, even when the same PAM data voltage is applied to the gate terminal, the transistor T8 supplies a driving current having a different magnitude to each light emitting element 100 through the difference in threshold voltage, which may be represented as a stripe of an image.

Therefore, according to the embodiment, the threshold voltage deviation between the transistors T8 included in the display panel 1000 is compensated.

The second internal compensation circuit 72 is a component for compensating the threshold voltage of the transistor T8. Specifically, when the PAM data voltage is applied, the PAM driving circuit 720 may apply a voltage based on the applied PAM data voltage and the threshold voltage of the transistor T8 to the gate terminal C of the transistor T8 through the second internal compensation circuit 72. Accordingly, the transistor T8 may supply the light emitting element 100 with a driving current having a magnitude corresponding to the magnitude of the applied PAM data voltage regardless of the threshold voltage of the transistor T8.

Accordingly, a problem caused by a threshold voltage deviation between the transistors T8 included in the display panel 1000 may be overcome.

As shown in fig. 13, meanwhile, the PWM driving circuit 710 may further include a transistor T3 and the first internal compensation circuit 71.

The transistor T3 may be connected to the gate terminal C of the transistor T8 to control the voltage of the gate terminal of the transistor T8, thereby controlling the pulse width of the driving current. Specifically, if a time corresponding to the PWM data voltage elapses after the light emitting element 100 starts emitting light according to the driving current supplied through the transistor T8, the transistor T3 may control the pulse width of the driving current by turning off the transistor T8.

Further, the transistor T3 present in each sub-pixel of the display panel 1000 also has a threshold voltage deviation, and even if the same PWM data voltage is applied to the transistor T3, there is a problem in that driving currents having different pulse widths are supplied to each light emitting element 100 by the threshold voltage deviation, if the threshold voltage deviation is not compensated for.

The first internal compensation circuit 71 is a component for compensating the threshold voltage of the transistor T3. Specifically, when the PWM data voltage is applied, the PWM driving circuit 710 may apply a voltage based on the applied PWM data voltage and the threshold voltage of the transistor T3 to the gate terminal a of the transistor T3 through the first internal compensation circuit 71. Accordingly, the transistor T3 may supply the light emitting element 100 with a driving current having a pulse width corresponding to the magnitude of the applied PWM data voltage regardless of the threshold voltage of the transistor T3.

Hereinafter, the operation of the internal compensation circuit will be described in more detail with reference to fig. 14.

Fig. 14 is a circuit diagram of the

internal compensation circuit

71 or 72 according to the embodiment.

As described above, the PWM driving circuit 710 may include the first internal compensation circuit 71 for compensating the threshold voltage of the transistor T3.

When the PWM data voltage is applied, the first internal compensation circuit 71 compensates the threshold voltage of the transistor T3 by applying a voltage corresponding to the sum of the applied PWM data voltage and the threshold voltage of the transistor T3 to the gate terminal C of the transistor T3.

For this purpose, as shown in fig. 14, the first internal compensation circuit 71 includes: a transistor T4 connected between the gate terminal and the drain terminal of the transistor T3; and a transistor T2 having a drain terminal connected to the source terminal of the transistor T3 and a gate terminal connected to the gate terminal of the transistor T4.

Specifically, if (e.g., based on) the transistors T2 and T4 are turned on according to the control signal SPWM [ n ] applied to the gate terminals of the transistors T2 and T4, the PWM data voltage applied to the source terminal of the transistor T2 is input to the first internal compensation circuit 71.

At this time, when (e.g., based on) the voltage of the gate terminal a of the transistor T3 is in a low state, the transistor T3 is fully turned on. Accordingly, the input PWM data voltage is applied to the gate terminal a of the transistor T3 while sequentially passing through the transistor T2, the transistor T3, and the transistor T4. In this case, the voltage of the gate terminal a of the transistor T3 is not increased to the inputted PWM data voltage, but is increased to a voltage corresponding to the sum of the PWM data voltage and the threshold voltage of the transistor T3.

The reason is that when the PWM data voltage is applied to the first internal compensation circuit 71 for the first time, since the voltage of the gate terminal a of the transistor T3 is in a low state and the transistor T3 is thus fully turned on, a current flows sufficiently to smoothly increase the voltage of the gate terminal a of the transistor T3. However, as the voltage of the gate terminal a of the transistor T3 increases, the voltage difference between the gate terminal and the source terminal of the transistor T3 decreases, thereby reducing the flow of current. Therefore, if the voltage difference between the gate terminal and the source terminal of the transistor T3 reaches the threshold voltage of the transistor T3, the transistor T3 is turned off to stop the flow of current.

That is, since the PWM data voltage is applied to the source terminal of the transistor T3, the voltage of the gate terminal a of the transistor T3 is increased to a voltage obtained by adding the PWM data voltage to the threshold voltage of the transistor T3. As such, the threshold voltage of the transistor T3 can be compensated by the first internal compensation circuit 71.

Meanwhile, the second internal compensation circuit 72 is similar in configuration and operation to the first internal compensation circuit 71.

That is, as shown in fig. 14, the second internal compensation circuit 72 includes: a transistor T9 connected between the gate terminal and the drain terminal of the transistor T8; and a transistor T7 having a drain terminal connected to the source terminal of the transistor T8 and a gate terminal connected to the gate terminal of the transistor T9.

In addition, the second internal compensation circuit 72 also operates in the same or similar manner as the first internal compensation circuit 71, so that a voltage corresponding to the sum of the PAM data voltage and the threshold voltage of the transistor T8 may be applied to the gate terminal C of the transistor T8.

According to the embodiment as described above, the PWM driving circuit 710 internally and automatically performs the internal compensation for the threshold voltage of the transistor T3 while setting (or applying) the applied PWM data voltage to the gate terminal a of the transistor T3, which is the same as or similar to the PAM driving circuit 720.

The term "internal compensation" indicates that the threshold voltage of the transistor is self-compensated within the driver circuit during operation of the driver circuit. This internal compensation scheme is different from an external compensation scheme that compensates for the threshold voltage of the transistor by correcting the data voltage itself to be applied to the driving circuit outside the driving circuit.

As described above, since the threshold voltages of the transistors T3 and T8 are internally compensated, according to the embodiment, when the PAM data voltage is set to the pixels included in the display panel 1000 to display one image frame, the PAM data voltage may be commonly applied to the pixels. Therefore, a light emission period (light emitting section) in which the light emitting element 100 emits light in the entire period for displaying one image frame can be sufficiently ensured.

Further, according to the above-described embodiment, the PWM data voltages are sequentially applied to the pixels included in the display panel 1000 row by row to represent the gray scale of each pixel.

Hereinafter, the operation of the first pixel circuit 700 according to the swept voltage is described in more detail.

Specifically, when the PWM data voltage is applied, the first driving circuit 710 may apply a voltage based on the PWM data voltage and the threshold voltage of the transistor T3 to the gate terminal a of the transistor T3. Here, the voltage applied to the gate terminal a may be a voltage obtained by adding (or corresponding to the sum of) the PWM data voltage and the threshold voltage of the transistor T3.

In addition, when the PAM data voltage is applied, the PAM driving circuit 720 may apply a voltage based on the PAM data voltage and the threshold voltage of the transistor T8 to the gate terminal C of the transistor T8. Here, the voltage applied to the gate terminal C may be a voltage obtained by adding (or corresponding to the sum of) the PAM data voltage and the threshold voltage of the transistor T8.

Thereafter, when the boosted swept frequency voltage is applied to the PWM driving circuit 710, the voltage applied to the gate terminal a of the transistor T3 is boosted by the voltage value by which the swept frequency voltage is increased. In this case, the magnitude of the sweep voltage applied to the PWM driving circuit 710 may be maintained at the boosted voltage value until the start of the lighting period.

Thereafter, if the light emitting period starts, the PAM drive circuit 720 supplies a drive current having a magnitude corresponding to the PAM data voltage to the light emitting element 100 through the transistor T8 in an on state, and the light emitting element 100 starts emitting light.

At this time, the sweep voltage applied to the PWM driving circuit 710 is gradually decreased from the boosting voltage value to the initial voltage value. Therefore, the voltage of the gate terminal a of the transistor T3 gradually decreases according to the sweep voltage.

On the other hand, when (for example, based on) the voltage of the gate terminal a of the transistor T3 increased according to the sweep voltage is larger than a value obtained by adding the driving voltage VDD applied to the source terminal of the transistor T3 and the threshold voltage of the transistor T3, the transistor T3 is in an off state. Therefore, the transistor T3 in the off state remains in the off state until the voltage of the gate terminal a decreased according to the sweep voltage is a value obtained by adding the voltage of the source terminal and the threshold voltage of the transistor T3 (i.e., the driving voltage VDD + the threshold voltage of the transistor T3) (as a reference, in the case of a PMOSFET, the threshold voltage may have a negative value).

Thereafter, if the voltage of the gate terminal a of the transistor T3 reaches a value obtained by adding the driving voltage VDD and the threshold voltage of the transistor T3, the transistor T3 is turned on, and accordingly, the driving voltage VDD applied to the source terminal of the transistor T3 is applied to the gate terminal C of the transistor T8 through the drain terminal.

On the other hand, since the driving voltage VDD is applied to the source terminal of the transistor T8, if (for example, based on) the driving voltage VDD is applied to the gate terminal C of the transistor T8, the voltage of the gate terminal C of the transistor T8 exceeds a value obtained by adding the voltage of the source terminal and the threshold voltage of the transistor T8 (i.e., the driving voltage VDD + the threshold voltage of the transistor T8), so that the transistor T8 in an on state may be turned off (as a reference, the threshold voltage may have a negative value in the case of a PMOSFET). Therefore, if the transistor T8 is turned off, the drive current no longer flows, and the light emitting element 100 stops emitting light.

As such, the first pixel circuit 700 can control the pulse width of the driving current by controlling the voltage of the gate terminal a of the transistor according to the swept voltage.

Meanwhile, fig. 13 described above illustrates that the driving voltage VDD is applied to the PWM driving circuit 710 and the PAM driving circuit 720 through one line, but this is merely an example, and it is to be understood that one or more other embodiments are not limited thereto. For example, according to another embodiment, the driving voltage VDD may be applied to the PWM driving circuit 710 and the PAM driving circuit 720 through separate lines. That is, the PWM driving voltage VDD _ PWM may be applied to the PWM driving circuit 710 through one line, and the PAM driving voltage VDD _ PAM may be applied to the PAM driving circuit 720 through another line.

According to the embodiment, by controlling the pulse width of the driving current using the sweep voltage as described above, a range of the PWM data voltage capable of stably representing the gray scale can be secured.

Specifically, when the PWM data voltage is applied, a voltage having a value obtained by adding the PWM data voltage and the threshold voltage of the transistor T3 is applied to the gate terminal a of the transistor T3. In addition, when the sweep voltage is applied, the voltage of the gate terminal a increases according to the rise of the sweep voltage, and then the increased voltage of the gate terminal a gradually decreases as the sweep voltage decreases.

In this case, the driving current may be supplied to the light emitting element 100 during a period in which the voltage of the gate terminal a of the transistor T3, which varies according to the sweep voltage, is greater than a value obtained by adding the source terminal of the transistor T3 (i.e., the driving voltage VDD) and the threshold voltage of the transistor T3.

Accordingly, the PWM data voltage at which the voltage of the gate terminal a of the transistor T3 becomes a value obtained by adding the driving voltage VDD and the threshold voltage of the transistor T3 at the time of rising (step-up) may be set as the PWM data voltage for representing the minimum gray (e.g., black). Further, the PWM data voltage at which the voltage of the gate terminal a of the transistor T3 before rising (step-up) becomes a value obtained by adding the driving voltage VDD and the threshold voltage of the transistor T3 may be set as the PWM data voltage for representing the maximum gray, for example, full gray (i.e., white).

In this case, the difference between the PWM data voltage for representing the minimum gray scale and the PWM data voltage for representing the maximum gray scale (i.e., the range of the PWM data voltages) may be a voltage value at which the sweep voltage is increased.

Therefore, when the voltage value of the sweep voltage rise is appropriately set according to the gray scale range to be presented, the inverse gamma does not occur, and each gray scale can be presented by the stable PWM data voltage.

For example, it is assumed that the driving voltage VDD or VDD _ PAM is 12.4V and the maximum voltage value of the PWM data voltage provided by the data driver is 15V.

Meanwhile, due to the fact that the range of the PWM data voltage may be 6V or more in order to represent the gray scale of 1024, according to an embodiment, as shown in fig. 15, the voltage value of the sweep voltage rise may be set to 6V. For example, the swept voltage may have a voltage waveform that rises from an initial voltage of 0V to 6V, and then gradually decreases from 6V to 0V.

Accordingly, the range of the PWM data voltage may be 6V, the PWM data voltage for the minimum gray (i.e., black) may be 6.4V, and the PWM data voltage for the maximum gray (i.e., full gray) may be 12.4V.

Meanwhile, phi in fig. 15 shows a voltage waveform of the gate terminal a of the transistor T3 according to the swept voltage when the PWM data voltage of 6.4V is applied to the first pixel circuit.

Specifically, referring to (r) in fig. 15, the voltage of the gate terminal a is from 6.4V + V_THIncrease 6V to 12.4V + V_THThen gradually decreases to 6.4V + V_TH。

In this case, since the voltage of the gate terminal a does not exceed the voltage across the source terminal of the transistor T3 (i.e., since the driving voltage is applied to the source terminal, the voltage of the source terminal is 12.4V) and the threshold voltage V of the transistor T3_THVoltage value obtained by addition (12.4V + V)_TH) Thus drivingThe current is not supplied to the light emitting element 100, and therefore, the light emitting element 100 does not emit light.

Meanwhile, ② of fig. 15 shows a voltage waveform of the gate terminal a of the transistor T3 according to the sweep voltage when the PWM data voltage of 12.4V is applied to the first pixel circuit.

Specifically, referring to (2) of fig. 15, the voltage of the gate terminal a is from 12.4V + V_THIncrease 6V to 18.4V + V_THThen gradually decreases to 12.4V + V_TH。

In this case, during the entire emission time, the voltage of the gate terminal a is greater than the threshold voltage V of the transistor T3 by comparing the voltage of the source terminal of the transistor T3 with the voltage of the source terminal of the transistor T3_THAdditive (i.e., 12.4V + V)_TH) And the voltage value obtained. Therefore, the driving current is supplied to the light emitting element 100 during the entire emission time, and the light emitting element 100 can exhibit the maximum gray scale.

As such, according to the embodiment, a range of PWM data voltages that stably represent gray scales can be ensured by the sweep voltage having a specific waveform.

Fig. 15 depicts a sweep voltage rise of 6V, but this is merely an example, and it is to be understood that one or more other embodiments are not limited thereto. For example, according to another embodiment, by setting the sweep voltage to be raised by 6V or more, the PWM data voltage for representing the minimum gray scale and the maximum gray scale may have a range of 6V or more.

Hereinafter, the configuration and operation of the pixel circuit according to the embodiment are described in more detail with reference to fig. 16 to 19.

Fig. 16 is a detailed circuit diagram of the pixel circuit 900 according to the embodiment. First, elements constituting the first pixel circuit 900 and a connection relationship between the elements are described with reference to fig. 16. For reference, the pixel circuit 900 shown in fig. 16 is the same as the pixel circuit 900 shown in fig. 9.

Fig. 16 shows a circuit associated with one sub-pixel, that is, one light emitting element 100 and a PWM pixel circuit 900 for driving one light emitting element 100.

Referring to fig. 16, the PWM pixel circuit 900 may include a PWM driving circuit 910 and a PAM driving circuit 920.

Specifically, the PAM driving circuit 920 includes: a first transistor T8; a second transistor T9 connected between the drain terminal and the gate terminal of the first transistor T8; and a third transistor T7 having a drain terminal connected to the source terminal of the first transistor T8 and a gate terminal connected to the gate terminal of the second transistor T9, the third transistor T7 receiving the data signal Sig (i.e., PAM data voltage) through the source terminal.

If (e.g., based on) the PAM data voltage is applied through the source terminal of the third transistor T7 while the second transistor T9 and the third transistor T7 are turned on according to the control signal SPAM, the PAM drive circuit 920 applies a voltage equal to the sum of the applied PAM data voltage and the threshold voltage of the first transistor T8 to the gate terminal of the first transistor T8 through the turned-on first transistor T8 and second transistor T9.

Meanwhile, the PWM driving circuit 910 includes: a fourth transistor T3; a fifth transistor T4 connected between the drain terminal and the gate terminal of the fourth transistor T3; and a sixth transistor T2 having a drain terminal connected to the source terminal of the fourth transistor T3 and a gate terminal connected to the gate terminal of the fifth transistor T4, the sixth transistor T2 receiving the data signal Sig (i.e., the PWM data voltage) through the source terminal.

If (for example, based on) the PWM data voltage is applied through the source terminal of the sixth transistor T2 while the fifth and sixth transistors T4 and T2 are turned on according to the control signal spwm (n), the PWM driving circuit 910 applies a voltage equal to the sum of the applied PWM data voltage and the threshold voltage of the fourth transistor T3 to the gate terminal a of the fourth transistor T3 through the turned-on fourth and fifth transistors T3 and T4.

The seventh transistor T1 has a source terminal connected to the driving voltage terminal (or driving voltage signal) VDD of the PWM pixel circuit 900, and a drain terminal commonly connected to the drain terminal of the sixth transistor T2 and the source terminal of the fourth transistor T3.

The seventh transistor T1 is turned on/off according to the control signal Emi to electrically connect or disconnect the driving voltage terminal VDD to the PWM driving circuit 910.

The eighth transistor T5 has a source terminal connected to the drain terminal of the fourth transistor T3 and a drain terminal connected to the gate terminal of the first transistor T8.

The ninth transistor T6 has: a source terminal commonly connected to a source terminal of the fourth transistor T3, a drain terminal of the sixth transistor T2, and a drain terminal of the seventh transistor T1; and a drain terminal commonly connected to the source terminal of the first transistor T8 and the drain terminal of the third transistor T7.

The eighth transistor T5 and the ninth transistor T6 are turned on/off according to the control signal Emi to electrically connect or disconnect the PWM driving circuit 910 and the PAM driving circuit 920.

The tenth transistor T10 has a source terminal connected to the drain terminal of the first transistor T8 and a drain terminal connected to the anode terminal of the light emitting element 100. The tenth transistor T10 is turned on/off according to the control signal Emi to electrically connect or disconnect the PAM driving circuit 920 to or from the light emitting element 100.

One end of the first capacitor C1 is commonly connected to the gate terminal of the fourth transistor T3 and the drain terminal of the fifth transistor T4, and the other end of the first capacitor C1 is applied with a swept-frequency voltage (i.e., Vsweep).

The eleventh transistor T11 has a drain terminal commonly connected to the gate terminal of the first transistor T8 and the drain terminal of the second transistor T9, and a source terminal to which the initial voltage Vini is applied.

The twelfth transistor T12 has a source terminal connected to one end of the first capacitor C1 and a drain terminal connected to the source terminal of the eleventh transistor T11.

One end of the second capacitor C2 is connected to the driving voltage terminal VDD, and the other end of the second capacitor C2 is commonly connected to the gate terminal of the first transistor T8, the drain terminal of the second transistor T9, the drain terminal of the eleventh transistor T11, and the drain terminal of the eighth transistor T5.

The eleventh and twelfth transistors T11 and T12 are turned on according to the control signal VST to apply the initial voltage Vini to the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3.

In order to prevent the driving voltage VDD from being coupled to the gate terminal C of the first transistor T8 through the second capacitor C2 after the voltages of the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3 are initialized, the eleventh transistor T11 and the twelfth transistor T12 are maintained in a turned-on state for a predetermined time according to the control signal VST to apply the initial voltage Vini to the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3 even after the driving voltage VDD is applied to one end of the second capacitor C2.

The thirteenth transistor T13 is connected between the anode terminal and the cathode terminal of the light emitting element 100.

Before the light emitting element 100 is mounted on the driving circuit layer 40 (i.e., the TFT layer) and electrically connected to the PWM pixel circuit 900, the thirteenth transistor T13 may be turned on according to the control signal Test to check whether the PWM pixel circuit 900 is abnormal. In addition, after the light emitting element 100 is mounted on the TFT layer and electrically connected to the PWM pixel circuit 900, the thirteenth transistor T13 may be turned on according to the control signal Discharging to discharge the charges remaining in the light emitting element 100.

The cathode terminal of the light emitting element 100 is connected to a ground voltage VSS terminal.

Hereinafter, the operation of the PWM pixel circuit 900 will be described in more detail with reference to fig. 17.

Fig. 17 shows a timing diagram of various signals used to drive the pixel circuit 900 of fig. 16, according to an embodiment.

Referring to fig. 17, to display one image frame, the PWM pixel circuit 900 may be driven in the order of an initialization period (initialization), a holding period (hold), a data voltage setting and threshold voltage Vth compensation period, an emission period (emission), and a discharge period (LED discharge).

In this case, as an example shown in fig. 17, the data voltage setting and threshold voltage Vth compensation period may include a PAM data voltage setting and threshold voltage compensation period (PWM data + Vth compensation) of the transistor T3 and a PAM data voltage setting and threshold voltage compensation period (PAM data + Vth compensation) of the transistor T8.

The initialization period is a period for initializing the voltages of the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3. The PWM pixel circuit 900 initializes the voltages of the terminal C and the terminal a to the initial voltage Vini in the initialization period.

Specifically, in the initialization period, since the eleventh transistor T11 and the twelfth transistor T12 are turned on according to the control signal VST, the initial voltage Vini is applied to the gate terminal C of the first transistor T8 through the eleventh transistor T11 and is applied to the gate terminal a of the fourth transistor T3 through the twelfth transistor T12.

The holding period is a period for continuously holding the voltages of the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3 in a low state (i.e., an initialization state). This is because the first transistor T8 and the fourth transistor T3 should be turned on when the data voltage setting and threshold voltage Vth compensation period starts.

The data voltage setting and threshold voltage compensation periods are periods in which the data voltages in the PWM driving circuit 910 and the PAM driving circuit 920 are respectively set and the threshold voltages Vth of the first transistor T8 and the fourth transistor T3 are compensated.

According to an embodiment, as shown in fig. 17, the PWM data voltage setting and the threshold voltage compensation of the fourth transistor T3 may be performed first, and then the PAM data voltage setting and the threshold voltage compensation of the first transistor T8 may be performed. However, it should be understood that another embodiment is not limited thereto and the order may be changed.

Meanwhile, during the data voltage setting and threshold voltage compensation periods, the seventh to tenth transistors T1, T5, T6 and T10 are all turned off according to the control signal Emi, and thus, the PWM driving circuit 910 and the PAM driving circuit 920 are each independently configured to perform data voltage setting and threshold voltage compensation.

First, the PWM data voltage setting and threshold voltage compensation period (PWM data + Vth compensation) of the fourth transistor T3 is a period in which the PWM data voltage transmitted through the data line (Sig wiring) is applied to the gate terminal a of the fourth transistor T3.

Specifically, if the fifth transistor T4 and the sixth transistor T2 are turned on according to the control signal spwm (n), the PWM data voltage sequentially passes through the sixth transistor T2, the fourth transistor T3, and the fifth transistor T4, and the compensation voltage (voltage equal to the sum of the PWM data voltage and the threshold voltage of the fourth transistor T3) is input to the node a. Therefore, the compensated voltage is stored in the first capacitor C1, and the node a maintains a floating state.

The control signal spwm (n) may be a signal output from a gate driver inside or outside the display panel 1000. In spwm (n), n refers to the number of pixel rows included in the display panel 1000. Accordingly, the PWM data voltages are sequentially applied to the pixels (or sub-pixels) for each row of the plurality of pixels arranged in a matrix form.

The PAM data voltage setting and the threshold voltage compensation period (PAM data + Vth compensation) of the first transistor T8 are periods in which a PAM data voltage transmitted through the data line (Sig wiring) is applied to the gate terminal C of the first transistor T8.

Specifically, during the PAM data voltage setting and threshold voltage compensation period of the first transistor T8, because the control signal SPAM is low, the second transistor T9 and the third transistor T7 are turned on.

In this case, similar to the internal compensation principle of the PWM driving circuit 910 described above, since the PAM data voltage is input to the node C through the third transistor T7, the first transistor T8, and the second transistor T9, a voltage equal to the sum of the PAM data voltage and the threshold voltage of the first transistor T8 is input to the node C. The compensated voltage is stored in the second capacitor C2, and the node C maintains a floating state.

The control signal SPAM may be a signal output from a gate driver inside or outside the display panel 1000. According to an embodiment, the control signal SPAM may be commonly applied to pixels (or sub-pixels) included in the display panel 1000, unlike the control signal spwm (n). In this case, according to an embodiment, the PAM data voltages commonly applied to the sub-pixels included in the display panel 1000 may be voltages of the same magnitude. However, the PAM data voltage is not limited thereto.

The emission cycle (emission) is a period in which the light emitting element 100 emits light. During the emission period, the light emitting element 100 emits light according to the amplitude and pulse width of the driving current supplied from the PWM driving circuit 900, thereby exhibiting gray scales corresponding to the PAM data voltage and PWM data voltage applied.

Specifically, during the emission period, since the seventh to tenth transistors T1, T5, T6, and T10 are turned on according to the control signal Emi, the PWM driving circuit 910 and the PAM driving circuit 920 are electrically connected to each other, and also to the driving voltage terminal and the light emitting element 100.

In the case where the emission period starts, since the driving voltage VDD is transmitted to the light emitting element 100 through the seventh transistor T1, the ninth transistor T6, the first transistor T8, and the tenth transistor T10, a potential difference is generated across the light emitting element 100, so that the light emitting element 100 starts emitting light. In this case, the driving current for light emission has a magnitude corresponding to the PAM data voltage.

Further, before the emission period (specifically, a period before the seventh to tenth transistors T1, T5, T6, and T10 are turned on according to the control signal Emi after the PAM data voltage is completely applied), the sweep voltage Vsweep that is increased from the initial voltage value by a certain voltage value is applied to the first capacitor C1. In this case, a coupling voltage is generated at the gate terminal a of the fourth transistor T3 in a floating state by the first capacitor C1. Therefore, the voltage of the node a is increased by the boosted swept voltage from the voltage equal to the sum of the PWM data voltage and the threshold voltage of the fourth transistor T3.

Then, when the transmit period begins, the swept voltage is gradually reduced to the initial voltage value, and accordingly, the voltage of node a is also reduced according to the swept voltage. When the voltage of the node a, which has been reduced, reaches a voltage value obtained by adding the threshold voltage of the fourth transistor T3 to the driving voltage VDD applied to the source terminal of the fourth transistor T3 through the turned-on seventh transistor T1, the fourth transistor T3 is turned on from the off state.

When the fourth transistor T3 is turned on, the driving voltage VDD is transmitted to the gate terminal C of the first transistor T8 through the seventh transistor T1, the fourth transistor T3, and the eighth transistor T5. When the driving voltage VDD is applied to the gate terminal C of the first transistor T8, the first transistor T8 is turned off. When the first transistor T8 is turned off, the driving voltage VDD does not reach the light emitting element 100, and thus, light emission of the light emitting element 100 is terminated.

In this manner, the PWM drive circuit 910 supplies the drive current to the light emitting element 100 since the drive voltage VDD is applied to the light emitting element 100 until the voltage applied to the gate terminal a of the fourth transistor T3 changes to a voltage value obtained by adding the drive voltage VDD and the threshold voltage of the fourth transistor T3 according to the change in the sweep voltage Vsweep. That is, the driving current has a pulse width corresponding to the PWM data voltage.

According to an embodiment, in order to discharge the leakage current, the first pixel circuit 900 may turn on a transistor connected in parallel with the first inorganic light emitting element in a period including a point of time when a switching operation of the transistor is performed.

Specifically, the thirteenth transistor T13 may be turned on according to the control signal discharge during a period from a preset time point before to a predetermined time point after a time point at which the seventh to tenth transistors T1, T5, T6 and T10 are turned on according to the control signal Emi.

This is to make the luminance of the light emitting element 1000 nit when the leakage current is discharged to the ground voltage VSS terminal through the thirteenth transistor T13 to drive the light emitting element 100 to assume a low gray (particularly, black).

Specifically, in the case of rendering black using the light emitting element 100, if the seventh to tenth transistors T1, T5, T6, and T10 are turned on by the control signal Emi, the fourth transistor T3 is turned on, and accordingly, the first transistor T8 is turned off, so that the driving current does not flow through the light emitting element 100 during the emission period.

In this case, however, since the node C lacks a discharging capability, a time difference occurs between a point of time when the fourth transistor T3 is turned on and a point of time when the first transistor T8 is turned off, and the input resistance of the circuit applying the driving voltage VDD and the internal resistance of the PWM pixel circuit 900 are high. Therefore, a leakage current occurring between a time point when the fourth transistor T3 is turned on and a time point when the first transistor T8 is turned off may flow through the light emitting element 100.

In this case, since the light emitting element 100 weakly emits light (i.e., light leakage occurs), there may occur a problem that black (i.e., complete black) cannot be reproduced using the light emitting element 100.

Therefore, according to an embodiment, during a period from a preset time point before to a predetermined time point after a time point at which the seventh to tenth transistors T1, T5, T6 and T10 are turned on according to the control signal Emi, the thirteenth transistor T13 may be turned on using the control signal decharging to discharge a leakage current through the thirteenth transistor T13. As such, a leakage current can be prevented from flowing through the light emitting element 100, and black can be presented using the light emitting element 100.

That is, according to the embodiment, when black is presented by the light emitting element 100, the luminance of the light emitting element 100 may be 0 nit when black is presented by discharging the leakage current, which is generated by the RC load of the circuit to which the driving voltage VDD is applied and the variation of the transistor characteristics due to the process variation of the transistors, through the thirteenth transistor T13.

Further, even after the light emission of the light emitting element 100 is terminated, electric charges may remain in the light emitting element 100. This may cause a problem that the light emitting element 100 emits light weakly after the light emission is terminated, which may be particularly problematic when a low gray (e.g., black) is presented.

Therefore, the discharge period (LED discharge) is a period for Discharging the electric charges remaining in the light emitting element 100 after the light emitting period is terminated, and the PWM pixel circuit 900 can solve the above-described problem by turning on the thirteenth transistor T13 to completely discharge the electric charges remaining in the light emitting element 100 to the ground voltage VSS terminal according to the control signal discharge.

As described above, before the light emitting element 100 is mounted on the TFT layer and electrically connected to the PWM pixel circuit 900, it may be checked whether the PWM pixel circuit 900 is abnormal using the thirteenth transistor T13. For example, a developer or a manufacturer of a product may check whether the PWM pixel circuit 900 is abnormal (e.g., a short circuit or an open circuit) by turning on the eleventh transistor T11 through the control signal Test during the emission period, and then check a current flowing through the eleventh transistor T11.

Further, the various data signals Sig, the driving voltage VDD, the ground voltage VSS, and the control signals (Vsweep, Emi, SPWM (n), SPAM, Vini, VST, and Test/distributing) shown in fig. 17 may be received from at least one of an external Timing Controller (TCON), a processor, a power supply circuit, a sweep signal supply circuit, a driver circuit (e.g., a data driver, a gate driver), and the like.

Fig. 18 is a detailed circuit diagram of the pixel circuit 1100 according to the embodiment. First, elements constituting the first pixel circuit 1100 and a connection relationship between the elements will be described with reference to fig. 18. For reference, the pixel circuit 1100 shown in fig. 18 is the same as the pixel circuit 1100 shown in fig. 10.

Fig. 18 shows a circuit associated with one sub-pixel, that is, one light emitting element 100 and a PWM pixel circuit 1100 for driving one light emitting element 100.

Referring to fig. 18, the PWM pixel circuit 1100 may include a PWM driving circuit 1110 and a PAM driving circuit 1120.

Specifically, the PAM driving circuit 1120 includes: a first transistor T8; a second transistor T9 connected between the drain terminal and the gate terminal of the first transistor T8; and a third transistor T7 having a drain terminal connected to the source terminal of the first transistor T8 and a gate terminal connected to the gate terminal of the second transistor T9, the third transistor T7 receiving the data signal Sig (i.e., PAM data voltage) through the source terminal.

If (e.g., based on) the PAM data voltage is applied through the source terminal of the third transistor T7 while the second transistor T9 and the third transistor T7 are turned on according to the control signal SPAM, the PAM drive circuit 1120 applies a voltage equal to the sum of the applied PAM data voltage and the threshold voltage of the first transistor T8 to the gate terminal of the first transistor T8 through the turned-on first transistor T8 and second transistor T9.

Meanwhile, the PWM driving circuit 1110 includes: a fourth transistor T3; a fifth transistor T4 connected between the drain terminal and the gate terminal of the fourth transistor T3; and a sixth transistor T2 having a drain terminal connected to the source terminal of the fourth transistor T3 and a gate terminal connected to the gate terminal of the fifth transistor T4, the sixth transistor T2 receiving the data signal Sig (i.e., the PWM data voltage) through the source terminal.

If (for example, based on) the PWM data voltage is applied through the source terminal of the sixth transistor T2 while the fifth and sixth transistors T4 and T2 are turned on according to the control signal spwm (n), the PWM driving circuit 1110 applies a voltage equal to the sum of the applied PWM data voltage and the threshold voltage of the fourth transistor T3 to the gate terminal a of the fourth transistor T3 through the turned-on fourth and fifth transistors T3 and T4.

The seventh transistor T1 has a source terminal connected to the PWM driving voltage terminal (or driving voltage signal) VDD _ PWM of the PWM pixel circuit 1100, and a drain terminal commonly connected to the drain terminal of the sixth transistor T2 and the source terminal of the fourth transistor T3. The seventh transistor T1 is turned on/off by the control signal Emi to electrically connect or disconnect the PWM driving voltage terminal VDD _ PWM to the PWM driving circuit 1110.

The eighth transistor T5 has a source terminal connected to the drain terminal of the fourth transistor T3 and a drain terminal connected to the gate terminal of the first transistor T8. The eighth transistor T5 is turned on/off according to the control signal Emi to electrically connect or disconnect the PWM driving circuit 1110 and the PAM driving circuit 1120.

The ninth transistor T6 has a source terminal connected to the PAM drive voltage terminal VDD _ PAM of the PWM pixel circuit 1100, and a drain terminal commonly connected to the source terminal of the first transistor T8 and the drain terminal of the third transistor T7. The ninth transistor T6 is turned on/off by the control signal Emi to electrically connect or disconnect the PAM drive voltage terminal VDD _ PAM and the PAM drive circuit 1120.

The tenth transistor T10 has a source terminal connected to the drain terminal of the first transistor T8 and a drain terminal connected to the anode terminal of the light emitting element 100. The tenth transistor T10 is turned on/off according to the control signal Emi to electrically connect or disconnect the PAM driving circuit 1120 and the light emitting element 100.

One end of the second capacitor C2 is connected to the PWM driving voltage terminal VDD _ PWM, and the other end of the second capacitor C2 is commonly connected to the gate terminal of the first transistor T8, the drain terminal of the second transistor T9, the drain terminal of the eleventh transistor T11, and the drain terminal of the eighth transistor T5.

In order to prevent the PWM driving voltage VDD _ PWM from being coupled to the gate terminal C of the first transistor T8 through the second capacitor C2 after the voltages of the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3 are initialized, the eleventh transistor T11 and the twelfth transistor T12 remain in a turn-on state according to the control signal VST for a predetermined time even after the PWM driving voltage VDD _ PWM is applied to one end of the second capacitor C2 to apply the initial voltage Vini to the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3.

Before the light emitting element 100 is mounted on the TFT layer and electrically connected to the PWM pixel circuit 900, the thirteenth transistor T13 may be turned on according to the control signal Test to check whether the PWM pixel circuit 900 is abnormal. In addition, after the light emitting element 100 is mounted on the TFT layer and electrically connected to the PWM pixel circuit 900, the thirteenth transistor T13 may be turned on according to the control signal Discharging to discharge the charges remaining in the light emitting element 100.

Further, the cathode terminal of the light emitting element 100 is connected to a ground voltage VSS terminal.

Hereinafter, the operation of the PWM pixel circuit 1100 will be described in more detail with reference to fig. 19.

Fig. 19 shows a timing diagram of various signals used to drive the pixel circuit 1100 of fig. 18, in accordance with an embodiment.

Referring to fig. 19, in order to display one image frame, the PWM pixel circuit 1100 may be driven in the order of an initialization period (initialization), a holding period (hold), a data voltage setting and threshold voltage Vth compensation period, an emission period (emission), and a discharge period (LED discharge).

In this case, as an example shown in fig. 19, the data voltage setting and threshold voltage Vth compensation period may include a PAM data voltage setting and threshold voltage compensation period (PWM data + Vth compensation) of the transistor T3 and a PAM data voltage setting and threshold voltage compensation period (PAM data + Vth compensation) of the transistor T8.

The initialization period is a period for initializing the voltages of the gate terminal C of the first transistor T8 and the gate terminal a of the fourth transistor T3. The PWM pixel circuit 1100 initializes the voltages of the terminal C and the terminal a to the initial voltage Vini in the initialization period.

The data voltage setting and threshold voltage compensation periods are periods in which the data voltages in the PWM driving circuit 1110 and the PAM driving circuit 1120 are set, respectively, and the threshold voltages Vth of the first transistor T8 and the fourth transistor T3 are compensated.

According to an embodiment, as shown in fig. 19, the PWM data voltage setting and the threshold voltage compensation of the fourth transistor T3 may be performed first, and then the PAM data voltage setting and the threshold voltage compensation of the first transistor T8 may be performed. However, it is to be understood that one or more other embodiments are not so limited and may change order.

Meanwhile, during the data voltage setting and threshold voltage compensation periods, the seventh to tenth transistors T1, T5, T6 and T10 are all turned off according to the control signal Emi, and thus, the PWM driving circuit 1110 and the PAM driving circuit 1120 are each independently configured to perform data voltage setting and threshold voltage compensation.

Specifically, during the PAM data voltage setting and threshold voltage compensation period of the first transistor T8, the second transistor T9 and the third transistor T7 are turned on because the control signal SPAM is low.

In addition, the control signal SPAM may be a signal output from a gate driver inside or outside the display panel 1000. According to an embodiment, the control signal SPAM may be commonly applied to pixels (or sub-pixels) included in the display panel 1000, unlike the control signal spwm (n). In this case, according to an embodiment, the PAM data voltages commonly applied to the sub-pixels included in the display panel 1000 may be voltages of the same magnitude. However, the PAM data voltage is not limited thereto.

The emission period is a period in which the light emitting element 100 emits light. During the emission period, the light emitting element 100 emits light according to the amplitude and pulse width of the driving current supplied from the PWM pixel circuit 1100, thereby exhibiting gray scales corresponding to the PAM data voltage and PWM data voltage applied.

Specifically, during the emission period, since the seventh to tenth transistors T1, T5, T6 and T10 are turned on according to the control signal Emi, the PWM driving circuit 1110 and the PAM driving circuit 1120 are electrically connected to each other, and also to the driving voltage terminals VDD _ PWM and VDD _ PAM and the light emitting element 100.

In the case where the emission period starts, since the PAM driving voltage VDD _ PAM is transmitted to the light emitting element 100 through the ninth transistor T6, the first transistor T8, and the tenth transistor T10, a potential difference is generated across the light emitting element 100, so that the light emitting element 100 starts emitting light. In this case, the driving current for light emission has a magnitude corresponding to the PAM data voltage.

Before the emission period (specifically, a period before the seventh to tenth transistors T1, T5, T6, and T10 are turned on according to the control signal Emi after the PAM data voltage is completely applied), the sweep voltage Vsweep increased by a certain voltage value from the initial voltage value is applied to the first capacitor C1. In this case, a coupling voltage is generated at the gate terminal a of the fourth transistor T3 in a floating state by the first capacitor C1. Therefore, the voltage of the node a is increased by the boosted swept voltage from the voltage equal to the sum of the PWM data voltage and the threshold voltage of the fourth transistor T3.

Then, when the transmit period begins, the swept voltage is gradually reduced to the initial voltage value, and accordingly, the voltage of node a is also reduced according to the swept voltage. When the voltage of the node a, which has been reduced, reaches a voltage value obtained by adding the threshold voltage of the fourth transistor T3 to the PWM driving voltage VDD _ PWM applied to the source terminal of the fourth transistor T3 through the turned-on seventh transistor T1, the fourth transistor T3 is turned on from the off state.

When the fourth transistor T3 is turned on, the PWM driving voltage VDD _ PWM is transmitted to the gate terminal C of the first transistor T8 through the seventh transistor T1, the fourth transistor T3, and the eighth transistor T5. When the PWM driving voltage VDD _ PWM is applied to the gate terminal C of the first transistor T8, the first transistor T8 is turned off. When the first transistor T8 is turned off, the driving voltage VDD does not reach the light emitting element 100, and thus, light emission of the light emitting element 100 is terminated.

As such, the PWM driving circuit 1110 supplies the driving current to the light emitting element 100 since the PWM driving voltage VDD _ PWM is applied to the light emitting element 100 until the voltage applied to the gate terminal a of the fourth transistor T3 changes to a voltage value obtained by adding the PWM driving voltage VDD _ PWM and the threshold voltage of the fourth transistor T3 according to the sweep voltage Vsweep. That is, the driving current has a pulse width corresponding to the PWM data voltage.

According to an embodiment, the first pixel circuit 1100 may turn on a transistor connected in parallel with the first inorganic light emitting element in a period including a point of time when a switching operation of the transistor is performed to discharge a leakage current.

In this case, however, since the node C lacks a discharging capability, a time difference occurs between a point of time when the fourth transistor T3 is turned on and a point of time when the first transistor T8 is turned off, and the input resistance of the circuit applying the PWM driving voltage VDD _ PWM and the internal resistance of the PWM pixel circuit 1100 are high. Therefore, a leakage current occurring between a time point when the fourth transistor T3 is turned on and a time point when the first transistor T8 is turned off may flow through the light emitting element 100.

According to an embodiment, during a period from a preset time point before to a predetermined time point after a time point at which the seventh to tenth transistors T1, T5, T6 and T10 are turned on according to the control signal Emi, the thirteenth transistor T13 may be turned on using the control signal decharging to discharge a leakage current through the thirteenth transistor T13. Therefore, a leakage current can be prevented from flowing through the light emitting element 100, and black can be presented using the light emitting element 100.

As such, according to the embodiment, when black is presented by the light emitting element 100, the luminance of the light emitting element 100 may be 0 nit when black is presented by discharging the leakage current, which is generated by the RC load of the circuit to which the PWM driving voltage VDD _ PWM is applied and the variation of the transistor characteristics due to the process variation of the transistor, through the thirteenth transistor T13.

Even after the light emission of the light emitting element 100 is terminated, electric charges may remain in the light emitting element 100. This may cause a problem that the light emitting element 100 emits light weakly after the light emission is terminated, which may be particularly problematic when a low gray (e.g., black) is presented.

Therefore, the discharge period (LED discharge) is a period for Discharging the electric charges remaining in the light emitting element 100 after the light emitting period is terminated, and the PWM pixel circuit 1100 can solve the above-described problem by completely Discharging the electric charges remaining in the light emitting element 100 to the ground voltage VSS terminal by turning on the thirteenth transistor T13 according to the control signal Discharging.

Further, as described above, before the light emitting element 100 is mounted on the TFT layer and electrically connected to the PWM pixel circuit 1100, it may be checked whether the PWM pixel circuit 1100 is abnormal using the thirteenth transistor T13. For example, a developer or a manufacturer of a product may check whether the PWM pixel circuit 1100 is abnormal (e.g., a short circuit or an open circuit) by turning on the thirteenth transistor T13 through the control signal Test during the emission period, and then check a current flowing through the thirteenth transistor T13.

Further, the various data signals Sig, PWM driving voltages VDD _ PWM, PAM driving voltages VDD _ PAM, ground voltage VSS, and control signals (Vsweep, Emi, SPWM (n), SPAM, Vini, VST, and Test/distributing) shown in fig. 19 may be received from at least one of an external Timing Controller (TCON), a processor, a power supply circuit, a sweep signal supply circuit, a driver circuit (e.g., a data driver, a gate driver), and the like.

Fig. 20 is a configuration diagram of a display device 2000 according to an embodiment. Referring to fig. 20, a display device 2000 includes a display panel 1000, a panel driver 2010, and a processor 2020 (e.g., at least one processor).

The display panel 1000 may include a plurality of pixels, and each pixel may include a plurality of sub-pixels. In this case, each sub-pixel may include the light emitting element 100 and the pixel circuit 200.

In addition, the display panel 1000 may be formed or disposed such that the gate lines G1 to Gn and the data lines D1 to Dm cross each other, and the pixel circuits 200 may be formed or disposed in regions disposed to cross each other. In this case, a light emitting element may be formed or disposed on each pixel circuit. Specifically, an R light emitting element may be formed on a pixel circuit for driving the R light emitting element, a G light emitting element may be formed on a pixel circuit for driving the G light emitting element, and a B light emitting element may be formed on a pixel circuit for driving the B light emitting element.

The panel driver 2010 drives the display panel 1000 under the control of the processor 2020, and may include a timing controller 2011, a data driver 2012, and a gate driver 2013.

The timing controller 2011 may receive an input signal IS, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a main clock signal MCLK, and the like from the outside to generate an image data signal, a scan control signal, a data control signal, a light emission control signal, and the like, and supply them to the display panel 1000, the data driver 2012, the gate driver 2013, the power supply circuit, the sweep signal supply circuit, and the like.

In addition, the timing controller 2011 may apply various control signals to the pixel circuit 200 according to different embodiments. In addition, in some embodiments, the timing controller 2011 may also apply a control signal for selecting one of the R, G, and B sub-pixels to the pixel circuit 200 through the multiplexing circuit.

The data driver 2012 generates a data signal and receives image data of the R/G/B component from the processor 2020 and generates data voltages (e.g., a PWM data voltage and a PAM data voltage). In addition, the data driver 2012 may apply the generated data signals to the display panel 1000.

The gate driver 2013 generates various control signals (e.g., SPAM, SPWM [ m ], etc.) and transmits the generated various control signals to a specific row (or a specific horizontal line) of the display panel 1000 or the entire row thereof.

The power supply circuit may supply the driving voltage VDD to the pixel circuits 200 included in the display panel 1000. In the case of the PWM pixel circuit, in some embodiments, the power supply circuit may supply the driving voltage VDD to the PWM pixel circuit through one line, or supply the PWM driving voltage VDD _ PWM to the PWM driving circuit through one line, and may supply the PAM driving voltage VDD _ PAM to the PAM driving circuit through another line.

The sweep signal supply circuit may supply a sweep voltage to the pixel circuit 200 (specifically, a PWM pixel circuit) included in the display panel 1000. In this case, the swept voltage may have a voltage waveform that rises from the initial voltage and decreases in the form of a triangular wave.

Further, as described above, the data driver 2012 and the gate driver 2013 may be implemented such that all or a portion of the data driver 2012 and the gate driver 2013 are included in the driving circuit layer 40 formed or disposed on one surface of the substrate 30 of the display panel 1000, or may be implemented as a separate semiconductor IC and disposed on the other surface of the substrate 30. The sweep signal supply circuit and the power supply circuit may be implemented in the form of a chip, and mounted on an external Printed Circuit Board (PCB) together with the processor 2020 or the timing controller 2011, and may be connected to the pixel circuit by wiring.

However, this is merely an example, and it is to be understood that one or more other embodiments are not limited thereto. For example, at least one of the sweep signal supply circuit, the power supply circuit, and the data driver 2012 may be mounted on an external PCB, and the gate driver 2013 may be included in a TFT layer of the display panel 1000.

The processor 2020 controls the overall operation of the display device 2000. Specifically, the processor 2020 may drive the display panel 1000 by controlling the panel driver 2010 to allow the pixel circuit 200 to perform the above-described operations.

To this end, the processor 2020 may be implemented as one or more of a Central Processing Unit (CPU), a microcontroller, an Application Processor (AP), a Communication Processor (CP), and an ARM processor.

Although in fig. 20, the processor 2020 and the timing controller 2011 are described as separate components, it should be appreciated that one or more other embodiments are not so limited. For example, according to another embodiment, the timing controller 2011 may perform the functions of the processor 2020 without the processor 2020.

Fig. 21 is a flowchart for describing a driving method of a display panel according to an embodiment.

First, in the display panel, each of the plurality of pixels may include a plurality of light emitting elements, and may include a plurality of pixel circuits for driving the plurality of light emitting elements.

A first light emitting element of the plurality of light emitting elements is Pulse Width Modulated (PWM) driven through the first pixel circuit (operation S2110).

A second light emitting element of the plurality of light emitting elements is Pulse Amplitude Modulation (PAM) driven through the second pixel circuit (operation S2120).

In this case, the plurality of light emitting elements may include a red (R) light emitting element, a green (G) light emitting element, and a blue (B) light emitting element. Further, the first light emitting element may include a green light emitting element, and the second light emitting element may include a red light emitting element and a blue light emitting element.

Meanwhile, the size of the first pixel circuit may be larger than that of the second pixel circuit.

Each of the plurality of light emitting elements may emit light based on a driving current supplied from a pixel circuit for driving each light emitting element among the plurality of pixel circuits, the first pixel circuit may supply a first driving current having a magnitude corresponding to a PAM data voltage applied to the first pixel circuit to the first light emitting element for a time corresponding to a PWM data voltage applied to the first pixel circuit, and the second pixel circuit may supply a second driving current having a magnitude corresponding to a PAM data voltage applied to the second pixel circuit to the second light emitting element.

In this case, the gray scale of light emitted from the first light emitting element may be controlled by the time when the first driving current is supplied to the first light emitting element according to the magnitude of the PWM data voltage, and the gray scale of light emitted from the second light emitting element may be controlled by the magnitude of the second driving current according to the magnitude of the PAM data voltage.

Each of the plurality of light emitting elements may be a micro LED.

The first pixel circuit may change a voltage of a terminal of the first pixel circuit according to a swept voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to the PWM data voltage to the first light emitting element. The swept voltage may be a voltage that varies linearly from a second voltage after changing from a first voltage to the second voltage.

Specifically, the first pixel circuit may include a transistor, and control the pulse width of the drive current by performing a switching operation of the transistor based on a voltage of a gate terminal of the transistor, which varies according to the sweep voltage.

Here, the swept voltage may be a voltage that rises from a first voltage to a second voltage before an emission time of the first light emitting element and then decreases from the second voltage with time during the emission time.

In this case, the voltage of the gate terminal of the transistor may increase the difference between the second voltage and the first voltage as the swept frequency voltage increases and decrease from the increased voltage as the swept frequency voltage decreases. Further, the pulse width of the driving current may be determined based on a time until the reduced voltage of the gate terminal reaches a certain voltage.

Here, the specific voltage may be a voltage determined based on a driving voltage for driving the first pixel circuit.

In addition, a difference between the first voltage and the second voltage may correspond to a range of PWM data voltages for representing gray scales of light emitted from the first inorganic light emitting element.

Meanwhile, one or more embodiments may be implemented by software including instructions stored in a machine-readable storage medium (e.g., a computer). The machine is an apparatus that calls stored instructions from a storage medium and is operable according to the called instructions, and may include a display device 2000 in accordance with the disclosed embodiments.

When the instructions are executed by the processor, the processor may directly perform the functions corresponding to the instructions, or may use other components to perform the functions corresponding to the instructions under the control of the processor. The instructions may include code generated or executed by a compiler or interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory" means that the storage medium does not include a signal and is tangible, but does not distinguish whether data is semi-permanently or temporarily stored in the storage medium.

Methods according to various embodiments may be included and provided in a computer program product. The computer program product may be used as a product for conducting transactions between sellers and buyers. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or through an application store (e.g., PlayStore)^TM) And (4) online distribution. In case of online distribution, at least a part of the computer program product may be at least temporarily stored in a storage medium (e.g. a memory of a manufacturer's server, a server of an application store or a relay server) or temporarily generated.

Each of the components (e.g., modules or programs) according to various embodiments may include a single entity or multiple entities, and some of the above-described sub-components may be omitted, or other sub-components may also be included. Alternatively or additionally, some components (e.g., modules or programs) may be integrated into one entity to perform the same or similar functions as those performed by the respective components prior to integration. Operations performed by modules, programs, or other components according to various embodiments may be performed in a sequential, parallel, iterative, or heuristic manner, or at least some operations may be performed in a different order or omitted, or other operations may be added.

The above description is merely illustrative of the technical spirit of the present disclosure, and various modifications and changes can be made by those skilled in the art without departing from the essential characteristics of the present disclosure. In addition, the above-described embodiments are not intended to limit the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, the scope of the present disclosure is defined at least by the appended claims, and all technical spirit within the scope equivalent thereto should be construed as being included in the scope of the present disclosure.

Claims

1. A display panel comprising a plurality of pixels, the display panel comprising:

a plurality of light emitting elements configured to constitute each of the plurality of pixels; and

a plurality of pixel circuits respectively corresponding to the plurality of light emitting elements and configured to drive the plurality of light emitting elements,

wherein the plurality of pixel circuits includes a first pixel circuit for Pulse Width Modulation (PWM) driving a first light emitting element of the plurality of light emitting elements and a second pixel circuit for Pulse Amplitude Modulation (PAM) driving a second light emitting element of the plurality of light emitting elements.

2. The display panel of claim 1, wherein:

the plurality of light emitting elements include a red R light emitting element, a green G light emitting element, and a blue B light emitting element;

the first light emitting element corresponds to the green light emitting element; and is

The second light emitting element corresponds to the red light emitting element and the blue light emitting element.

3. The display panel of claim 1, wherein a size of the first pixel circuit is larger than a size of the second pixel circuit.

4. The display panel of claim 1, wherein:

each of the plurality of light-emitting elements is configured to: emitting light based on a driving current supplied from a corresponding pixel circuit of the plurality of pixel circuits;

the first pixel circuit is configured to: supplying a first driving current to the first light emitting element for a time corresponding to a PWM data voltage applied to the first pixel circuit, the first driving current having a magnitude corresponding to a first PAM data voltage applied to the first pixel circuit; and is

The second pixel circuit is configured to: providing a second drive current to the second light emitting element, the second drive current having a magnitude corresponding to a second PAM data voltage applied to the second pixel circuit.

5. The display panel of claim 4, wherein:

a gradation of light emitted from the first light emitting element is controlled by a time for which the first driving current is supplied to the first light emitting element according to a magnitude of the PWM data voltage; and is

A gradation of light emitted from the second light emitting element is controlled by a magnitude of the second driving current according to a magnitude of the second PAM data voltage.

6. The display panel of claim 1, wherein each of the plurality of light-emitting elements is a micro light-emitting diode (LED).

7. The display panel of claim 1, wherein:

the first pixel circuit is configured to: changing a voltage of a terminal of the first pixel circuit according to a swept voltage applied to the first pixel circuit to supply a driving current having a pulse width corresponding to a PWM data voltage to the first light emitting element; and is

The swept voltage is a voltage that varies linearly from a second voltage after changing from a first voltage to the second voltage.

8. The display panel according to claim 7, wherein the first pixel circuit includes a transistor and is configured to control a pulse width of the drive current by performing a switching operation of the transistor based on a voltage of a gate terminal of the transistor, the voltage of the gate terminal of the transistor being varied in accordance with the sweep voltage.

9. The display panel of claim 8, wherein the swept voltage is a voltage that rises from the first voltage to the second voltage before an emission time of the first light emitting element and then decreases from the second voltage over time during the emission time.

10. The display panel of claim 9, wherein:

the voltage of the gate terminal of the transistor increases with increasing swept voltage by the difference between the second voltage and the first voltage and decreases with decreasing swept voltage from the increasing voltage; and is

Determining a pulse width of the driving current based on a time until the reduced voltage of the gate terminal reaches a certain voltage.

11. The display panel according to claim 10, wherein the specific voltage is a voltage determined based on a driving voltage for driving the first pixel circuit.

12. The display panel according to claim 7, wherein a difference between the first voltage and the second voltage corresponds to a range of the PWM data voltage for representing a gray scale of light emitted from the first inorganic light emitting element.

13. The display panel of claim 7, wherein the first pixel circuit is configured to: the transistor connected in parallel with the first inorganic light emitting element is turned on for a period including a point of time when a switching operation of the transistor is performed to discharge a leakage current.

14. A driving method of a display panel in which each of a plurality of pixels includes a plurality of light emitting elements and includes a plurality of pixel circuits for driving the plurality of light emitting elements corresponding to the plurality of light emitting elements, respectively, the driving method comprising:

driving a first light emitting element of the plurality of light emitting elements by a first pixel circuit Pulse Width Modulation (PWM); and

driving a second light emitting element of the plurality of light emitting elements by a second pixel circuit pulse amplitude modulation, PAM.

15. The driving method according to claim 14, wherein: