CN1808549A - Electro-optical device, drive circuit, driving method, and electronic apparatus - Google Patents

Abstract

A drive circuit of an electro-optical device comprising electro-optical elements of which each gray scale is controlled in accordance with a data signal output to a data line includes a reference current that generates unit generating reference current and a signal output unit that generates the data signal corresponding to a current value of the reference current generated by the reference current generating unit on the basis of gray-scale data and outputs the generated data signal to the data line. The reference current generating unit performs a refresh operation of setting the current value of the reference current to a predetermined value plural times.

Description

Electro-optical device, driving circuit, driving method and e-machine

Technical field

The present invention relates to the technology of various electrooptic elements such as a kind of control Organic Light Emitting Diode (below be called " OLED (OrganicLight Emitting Diode) ") element.

Background technology

The electro-optical device that possesses this electrooptic element, have and correspond respectively to many data lines and be arranged in planar a plurality of electrooptic elements, with generate data-signal according to the numerical data of the gray scale of specifying electrooptic element (below be called " gradation data "), export to a plurality of current output circuits of digital line.Each current output circuit, for including the D/A transducer of a plurality of transistors as current source (below be called " current supply transistor "), by will flow into these current supplies with in the transistor corresponding to gradation data selected transistor in electric current add up, generate data-signal.

But a plurality of current supplies that contained in each current output circuit are with characteristics of transistor (particularly threshold voltage), particularly owing on making, produce error sometimes.Like this,, just can't generate data-signal corresponding to the desired current value of gradation data in case each current supply produces deviation with characteristics of transistor, consequently, the problem that exists display quality to reduce.

In order to address this problem, for example in the patent documentation 1, announced a kind of formation that each current supply of compensation is set with the circuit of characteristics of transistor deviation (below be called " compensating circuit ") in each current output circuit.This compensating circuit has the transistor that is connected with drain terminal and gate terminal (below be called " compensation transistor "), with the capacitor of the voltage of this gate terminal of maintenance.Compensation has and each current supply roughly the same characteristic of transistor with transistor.Like this, to allow the voltage of the gate terminal of compensation after temporarily becoming conducting state with transistor (below be called " reference voltage "), load and give each current supply, just can compensate the error of each current supply with characteristics of transistor with after the transistorized gate terminal.

Patent documentation 1: the spy opens 2004-88158 (the 0053rd section and Fig. 3).

Summary of the invention

But in case reference voltage changes because of noise etc., then compensation just is maintained level after this change with the voltage of transistorized gate terminal.So, can't give the reference voltage of each current supply with the desired level of transistorized gate terminal loading, result's existence is controlled to desired current value with data-signal and has been subjected to the problem that hinders.Under such background, a mode of the present invention, purpose are to solve this problem of data-signal that stably generates.

In order to address this problem, the driving circuit of associated electrical optical devices of the present invention, be a kind ofly to have corresponding to the data-signal of exporting to data line, the driving circuit of the electro-optical device of the electrooptic element of control gray scale separately possesses: the reference current that generates reference current generates mechanism; And signal output mechanism, it is according to gradation data, generation generates the data-signal of the current value of the reference current that mechanism generated corresponding to the said reference electric current, export to above-mentioned data line, the said reference electric current generates mechanism, repeatedly carries out the more new element that the current value of said reference electric current is made as set-point.

By adopting this formation, owing to repeatedly carry out more new element, therefore even hypothesis the reference current change also can be made as desired value with reference current by more new element next time because of noise etc. causes, therefore can high precision and stably generate data-signal corresponding to gradation data.In addition, signal output mechanism among the present invention " generates the data-signal corresponding to the current value of reference current ", except the formation of the data-signal that generates the current value directly reflect reference current, also comprise the formation that generates with according to the corresponding data-signal of the voltage that current value generated (reference voltage) of reference current.

In first mode of the present invention, the said reference electric current generates mechanism and comprises: the first terminal is loaded voltage, and (for example the compensation of Fig. 3 is used transistor T a) with transistor in the compensation that is electrically connected between second terminal and the gate terminal; Keep the capacitance part (for example capacitor C1 of Fig. 3) of above-mentioned compensation with the voltage of transistorized gate terminal; And voltage load maintainer (for example voltage supply line 27 and on-off element SW of Fig. 3), it is repeatedly carried out and will make above-mentioned compensation load to the above-mentioned more new element of above-mentioned compensation with transistorized gate terminal with the forward voltage that transistor is in conducting state, generates the said reference electric current (for example reference current Ir0 of Fig. 3) corresponding to the voltage that above-mentioned capacitance part kept.In this mode, load forward voltage by giving compensation with transistorized gate terminal, and reference current is set at desired current value.In addition, the object lesson of first mode will be as the first embodiment aftermentioned.

In the driving circuit of relevant first mode, be provided with the mapping device of generation corresponding to the reference voltage (for example reference voltage V ref1 of Fig. 3) of said reference electric current; The said reference electric current generates mechanism, comprises by the voltage that will be kept in the above-mentioned capacitance part loading to gate terminal, and the electric current that generates the said reference electric current generates with transistor (for example the electric current of Fig. 3 generates and uses transistor T b); Above-mentioned signal output mechanism according to gradation data, generates the data-signal corresponding to the reference voltage that above-mentioned mapping device generated, and exports to above-mentioned data line.Mapping device in this mode, for example comprise generating generating current mirror circuit with the corresponding image current of the reference current that transistor generated (for example image current Ir1 of Fig. 3) with above-mentioned electric current, and the mechanism (for example generation of the voltage among Fig. 3 transistor T d) of the corresponding said reference voltage of image current that generated of generation and above-mentioned current mirror circuit.By this mode,, therefore can make the reference voltage stabilization that offers the signal output mechanism reliably because electric current generates with the transistor AND gate mapping device between compensation is with transistorized gate terminal and signal output mechanism.In addition, during this constitutes,, preferably allow electric current generate and compensate have roughly the same characteristic with transistor with transistor AND gate for offset current reliably generates deviation with transistorized threshold voltage.But, even above-mentioned characteristics of transistor and consistent imprecisely also can effectively be brought into play effect of the present invention.

In the driving circuit of relevant first mode, be provided with the comparison mechanism that above-mentioned compensation is compared with the voltage and the given voltage of transistorized gate terminal; Above-mentioned voltage load maintainer, with corresponding moment of comparative result based on above-mentioned relatively mechanism, give above-mentioned compensation with transistorized gate terminal loading forward voltage.Given voltage for example is set as to load and gives the voltage of compensation with transistorized the first terminal, and with this voltage with compensate with the transistorized threshold voltage addition voltage between the resultant voltage (for example voltage Va in first embodiment) afterwards.By this mode, can only take place under the situation of change at the voltage of compensation with transistorized gate terminal, load forward voltage just for this gate terminal, therefore compare with the mode that transistorized gate terminal loads forward voltage, reduced consumed power with regularly giving compensation.In addition, the object lesson of this mode as shown in Figure 7.

In second mode of the present invention, the said reference electric current generates mechanism to have: the electric current that comprises gate terminal and the first terminal, second terminal generates with transistor (for example the electric current of Figure 11 generates and uses transistor Tr A); And keep above-mentioned electric current to generate capacitance part (for example capacitor C1 of Figure 11) with the voltage of transistorized gate terminal; Above-mentioned more new element comprises: compensating movement, it is by under the state that is electrically connected at above-mentioned gate terminal and above-mentioned the first terminal (being drain terminal among Figure 11), load first voltage (for example voltage Vref of Figure 11) for above-mentioned second terminal (being source terminal among Figure 11), generate with transistorized threshold voltage according value and the voltage of this gate terminal is set at corresponding to above-mentioned first voltage and above-mentioned electric current, and keep by above-mentioned capacitance part; And generation action, it is by under the state of above-mentioned gate terminal and the disconnection of above-mentioned the first terminal electricity, load second voltage (for example voltage Vdd of Figure 11) different for above-mentioned second terminal, and between above-mentioned the first terminal and above-mentioned second terminal, produce and the corresponding said reference electric current of voltage (for example electric current I r1 of Figure 11) that in above-mentioned capacitance part, is kept by above-mentioned compensating movement with above-mentioned first voltage.

By this mode, can be set at compensating movement by electric current being generated voltage with transistorized gate terminal corresponding to its threshold voltage according value, compensate the error of threshold voltage.For example, generate with the reference current that transistor generated,, and do not rely on threshold voltage by the difference decision of its gain coefficient or first voltage and second voltage by electric current.So, can pass through repeatedly more new element, stably generate given current value has been carried out the reference current that high precision is adjusted.In addition, the object lesson of this mode is as the second embodiment aftermentioned.

In the associated driver circuitry of second mode, above-mentioned compensating movement comprises: between the first phase in (for example Figure 12 during A), by under above-mentioned gate terminal and state that above-mentioned the first terminal is electrically connected, load above-mentioned first voltage for above-mentioned second terminal, load first action of given voltage for simultaneously above-mentioned gate terminal, and following in second phase between the above-mentioned first phase (for example Figure 12 during B), keep being electrically connected of above-mentioned gate terminal and above-mentioned the first terminal, stop to load above-mentioned given voltage to above-mentioned gate terminal, by like this, the voltage of this gate terminal is set at corresponding to above-mentioned first voltage and above-mentioned electric current generates with transistorized threshold voltage according value, and by second moving that above-mentioned capacitance part keeps; Above-mentioned generation action comprises: in following between the third phase of the above-mentioned second phase (for example Figure 12 during C), with the 3rd moving that above-mentioned gate terminal and above-mentioned the first terminal electricity disconnect; And between through the fourth phase after between the above-mentioned third phase in (for example Figure 12 during D), by loading above-mentioned second voltage for above-mentioned second terminal, and between above-mentioned the first terminal and above-mentioned second terminal, by four action of described the 2nd action generation with the corresponding said reference electric current of voltage that in above-mentioned capacitance part, is kept.By this mode, also can serve the same role and effect.

In the associated driver circuitry of second mode, the said reference electric current generates mechanism, comprises that a plurality of above-mentioned electric current that each gate terminal is connected in the above-mentioned capacitance part jointly generates with transistor (for example the electric current of Figure 21 generates with transistor Tr A1 to TrA4); Above-mentioned signal output mechanism (for example transistor Tr D1 to TrD4 of Figure 21), select above-mentioned a plurality of electric current to generate corresponding to gradation data with the electric current generation transistor more than 1 in the transistor, with the summation of this electric current generation more than 1, export as data-signal with the electric current that is flowed between the first terminal in the transistor and second terminal.By this mode, a plurality of electric currents are generated with reference current that transistor generated each, export as data-signal selectively corresponding to gradation data.In addition, the object lesson of this mode as shown in figure 21.

The said reference electric current generates mechanism, comprise that voltage generates with transistor (for example the voltage of Figure 11 generates and uses transistor Tr B), it is corresponding to the first terminal that has been loaded tertiary voltage (for example earthing potential Gnd of Figure 11) and be connected the said reference electric current that is flowed between second terminal on the gate terminal, and the voltage of this gate terminal is set at reference voltage; Above-mentioned signal output mechanism according to gradation data, generates corresponding to the data-signal of above-mentioned voltage generation with the reference voltage of transistorized gate terminal, exports to above-mentioned data line; Above-mentioned first action, comprise by above-mentioned electric current being generated and being electrically connected with transistorized second terminal with above-mentioned voltage generation with transistorized the first terminal, with the voltage of above-mentioned electric current generation with transistorized gate terminal, be set at and above-mentioned electric current generation ratio and above-mentioned first voltage of the above-mentioned voltage generation of transistor AND gate with the conducting resistance between the transistor, the action of the corresponding above-mentioned given voltage of above-mentioned tertiary voltage (also promptly, the voltage Vref with Figure 11 generates with resulting voltage after the resistance ratio dividing potential drop of transistor Tr B with transistor Tr A and voltage corresponding to the electric current generation); Above-mentioned second action comprises by above-mentioned electric current being generated with transistorized the first terminal and above-mentioned voltage generating with the disconnection of transistorized second terminal electricity, stops the action of the loading of above-mentioned given voltage.By this formation, also can pass through repeatedly more new element, stably generate given current value has been carried out the reference current that high precision is adjusted.

In addition, the above-mentioned second phase in second mode, be than the voltage of above-mentioned electric current generation with transistorized gate terminal, the above-mentioned given voltage that sets between the above-mentioned first phase, change to above-mentioned first voltage and above-mentioned electric current generate with till the difference between the transistorized threshold voltage the time length during.By this mode, can shorten electric current and generate with the needed time of the compensating movement of transistorized threshold voltage.

In other modes, the above-mentioned second phase, be than the voltage of above-mentioned electric current generation with transistorized gate terminal, the above-mentioned given voltage that sets between the above-mentioned first phase, change to above-mentioned first voltage and above-mentioned electric current generate with till the difference between the transistorized threshold voltage the time long during.By this mode, offset current generates and uses transistorized threshold voltage reliably.

In the Third Way of the present invention, comprising: comprise gate terminal and the first terminal, and the electric current generation transistor (for example the electric current of Figure 22 generates and uses transistor Tr A) that is loaded second terminal of given voltage (for example power supply potential Vdd of Figure 22); And have first electrode (for example first electrode E1 of Figure 22) and generate the capacitance part (for example capacitor C2 of Figure 22) of second electrode (for example second electrode E2 of Figure 22) that is connected with transistorized gate terminal with above-mentioned electric current; Above-mentioned more new element comprises: compensating movement, it is by having loaded under the state of first voltage (for example voltage VINI of Figure 22) for above-mentioned first electrode, above-mentioned electric current generation is electrically connected with the first terminal (being drain terminal among Figure 22) with transistorized gate terminal, loads corresponding to above-mentioned given voltage and the transistorized threshold voltage according of above-mentioned electric current generation for above-mentioned second electrode; And generation action, it is by generating at above-mentioned electric current under the state that disconnects with transistorized gate terminal and the first terminal electricity, make the change in voltage of above-mentioned first electrode become second voltage (for example voltage Vref of Figure 22) different with above-mentioned first voltage, make the voltage of above-mentioned second electrode, begin to change from the voltage that above-mentioned compensating movement, sets, at the said reference electric current (the reference current Ir0 of Figure 22) that produces between above-mentioned the first terminal and above-mentioned second terminal corresponding to the voltage after this variation corresponding to the difference (Δ V) between above-mentioned first voltage and above-mentioned second voltage.

In this mode,, can be set at compensating movement, compensate the error of threshold voltage by electric current being generated voltage with transistorized gate terminal corresponding to its threshold voltage according value by this mode.In addition, if the voltage of first electrode from first change in voltage to second voltage, then by the capacitive coupling in the capacitance part, allow electric current generate and change with the voltage of transistorized gate terminal difference corresponding to first voltage and second voltage.Therefore, can pass through repeatedly more new element, stably generate corresponding to first voltage and second voltage expectation current value has been carried out the reference current that high precision is adjusted.In addition, the object lesson of this mode is as the 3rd embodiment aftermentioned.

In the driving circuit of relevant Third Way, above-mentioned compensating movement comprises: between the first phase in (for example period P 0 of Figure 26), by generating under the state that disconnects with transistorized gate terminal electricity at above-mentioned second electrode and above-mentioned electric current, load above-mentioned first voltage for above-mentioned first electrode, load first action of tertiary voltage (for example earthing potential Gnd of Figure 25) for simultaneously above-mentioned second electrode; In the second phase of following between the above-mentioned first phase (for example period P 1 of Figure 26), stop to load after the above-mentioned tertiary voltage to above-mentioned second electrode, above-mentioned second electrode and above-mentioned electric current are generated with second moving that transistorized gate terminal is connected; And following between the third phase of the above-mentioned second phase in (for example period P 2 of Figure 26), couple together with transistorized gate terminal and the first terminal by above-mentioned electric current is generated, the voltage of above-mentioned second electrode is made as to generate with the 3rd of the corresponding voltage of transistorized threshold voltage (being voltage " Vdd-Vth " in the illustration of Figure 26) with above-mentioned given voltage and above-mentioned electric current moves; Above-mentioned generation action comprises: in (for example period P 3 of Figure 26), above-mentioned electric current is generated the 4th action that disconnects (also promptly removing diode is connected) with transistorized gate terminal and the first terminal electricity between the fourth phase of following between the third phase; And between the fifth phase of following between the above-mentioned fourth phase, in (for example period P 4 of Figure 26), be above-mentioned second voltage by the change in voltage that makes above-mentioned first electrode, and between above-mentioned the first terminal and above-mentioned second terminal, produce the 5th action of said reference electric current.By this mode, because before the compensation of threshold voltage, the voltage that electric current generates with transistorized gate terminal can not be reduced to tertiary voltage, therefore can reduce electric current and generate with the consumed power in the transistor, the voltage that can shorten gate terminal simultaneously arrives the time before the magnitude of voltage of the compensation that is used for threshold voltage.

In the associated driver circuitry of first to the 3rd each mode, be provided with a plurality of unit circuits (reference example such as Fig. 3 and Figure 11) that comprise said reference electric current generation mechanism and above-mentioned signal output mechanism respectively.By adopting this formation, can in each signal output mechanism, generate reference current accurately.In addition, also can adopt the formation with a plurality of above-mentioned signal output mechanisms, this mechanism generates respectively with 1 said reference electric current and generates the corresponding data-signal of reference voltage (reference example such as Fig. 5 and Figure 17) that mechanism generated.By this formation, because shared 1 electric current of a plurality of signal output mechanisms generates mechanism, therefore with in each unit circuit include reference current and generate mechanism and compare with the formation of signal output mechanism, dwindled circuit scale.

In the associated driver circuitry of first to the 3rd each mode, a plurality of said reference electric currents are set generate mechanism, and select above-mentioned a plurality of reference current to generate certain selection mechanism (for example selection circuit 29 among Fig. 8 and Figure 18) in the mechanism; Above-mentioned signal output mechanism according to gradation data, generates corresponding to the data-signal that generates the reference current that mechanism generated by the selected reference current of above-mentioned selection mechanism, exports to above-mentioned data line.By this mode,, generate the reference current that mechanism generated and adopt by certain reference current in order to generate data-signal selectively.For example, when generating the positive earthquake of reference current that mechanism generated, generate the reference current that mechanism generated, generate data-signal according to other reference currents by certain reference current.So, can stably supply with reference voltage to the signal output mechanism.In addition, the object lesson of this mode such as Fig. 8 and shown in Figure 180.

In the even more ideal mode, above-mentioned a plurality of reference currents generate each of mechanism, carry out more new element in the mutually different moment respectively.By this mode, when certain reference current generated mechanism and carries out more new element, selection mechanism selected other reference currents to generate the reference current of mechanisms, by like this, can more stably generate data-signal.

In addition, if the specific associated driver circuitry that turns to the first party formula of this mode, the voltage that certain generated that a plurality of voltages that then have a formation voltage generate mechanism's (for example reference voltage generating circuit 21 of Fig. 8), generate mechanism with a plurality of voltages is chosen as the selection mechanism (for example selection circuit 29 of Fig. 8) of reference voltage and generates data-signal corresponding to the selected reference voltage of selection mechanism according to gradation data, exports to the electric current output mechanism of data line; Each voltage generates mechanism, have the first terminal and be loaded voltage, the compensation that is connected between second terminal and the gate terminal simultaneously with transistor, keep compensation with the capacitance part (voltage maintaining body) of the voltage of transistorized gate terminal and will make that repeatedly compensating the forward voltage that is in conducting state with transistor loads to the voltage load maintainer that compensates with transistorized gate terminal; Voltage or voltage corresponding with it that capacitance part kept are exported as reference voltage.In more detail, each voltage that is contained in 1 unit circuit generates the voltage load maintainer of mechanism, the compensation of generating mechanism for this voltage in the mutually different moment loads forward voltage with transistorized gate terminal, and selection mechanism is selected in turn to compensate with the voltage that has been loaded forward voltage in the transistor and generated the reference voltage that mechanism generated.

In the associated driver circuitry of first to the 3rd each mode of the present invention, the said reference electric current generates mechanism, carries out more new element in during each is given.By this mode, even in reference current accidental fluctuation sometime, also can by the next one more new element revise reference current reliably.

In addition, also can adopt the said reference electric current to generate mechanism, the interim between horizontal scan period in succession, or in the interim between the vertical scanning period in succession, carry out the more formation of new element.By this formation, have and to avoid new element more (loading forward voltage with transistorized gate terminal for example in first mode compensation) to bring the advantage of influence to the gray scale of electrooptic element.

In the even more ideal formation, the said reference electric current generates mechanism, the moment between above-mentioned signal output mechanism begins to move, with begin to move after the moment in, carry out more new element.During this constitutes, owing to before the action of signal output mechanism begins, carry out more new element, therefore when the action of signal output mechanism has just begun, just can stablize and generate data-signal accurately.And, after the action based on the signal output mechanism begins, also carry out more new element, though therefore in the action of signal output mechanism reference current taken place also it to be modified to desired value under the situation of change.

Among the present invention, also specific electro-optical device with driving circuit of each mode discussed above.This electro-optical device has a plurality of electrooptic elements corresponding to the data-signal control gray scale separately of exporting to data line, and the associated driver circuitry of any mode illustrated above.According to driving circuit of the present invention, because the current value of stable maintenance reference current the magnitude of voltage of the reference voltage that reference current generated (or corresponding to), therefore for example in electro-optical device, can export high quality images as display device or image processing system (printing equipment).

Associated electrical optical devices of the present invention can be used in various e-machines.The exemplary of this e-machine is with the machine of electro-optical device as display device.This e-machine, for example a guy's computing machine and portable telephone etc.But the purposes of associated electrical optical devices of the present invention is not limited in the demonstration of image.For example, light-emitting device of the present invention also can be as the exposure device (photohead) that forms sub-image in the image carrier such as photoconductor drum that is radiated at by light.

The present invention can also specificly be used for driving the method for electro-optical device.Also promptly, this driving method is a kind ofly to have: corresponding to the data-signal of exporting to data line, and a plurality of electrooptic elements of control gray scale separately; The reference current that generates reference current generates mechanism; According to gradation data, generation generates the data-signal of the current value of the reference current that mechanism generated corresponding to the said reference electric current, and export to the driving method of electro-optical device of the signal output mechanism of above-mentioned data line, it is characterized in that: repeatedly carry out the more new element that the current value of said reference electric current is made as set-point.By this method, can by repeatedly more new element stably generate reference current (or corresponding to reference voltage that reference current generated).In addition, in the driving method of the present invention, equally also can adopt the illustrated variety of way of driving circuit.

In addition, if be conceived to be used for to prevent the formation of the error of reference current (or based on reference voltage that it generated) especially, then the present invention can specificly be the associated driver circuitry of following each mode.In addition, these driving circuits also can suitably adopt above each cited mode.

At first, first feature of associated driver circuitry of the present invention, have the voltage that generates reference voltage and generate mechanism's (for example reference voltage generating circuit 21 of Fig. 3 or Fig. 5), and according to gradation data, generation is exported to the signal output mechanism (for example current output circuit 23 of Fig. 3 or Fig. 5) of data line corresponding to the data-signal of the above-mentioned voltage generation reference voltage that mechanism generated; Above-mentioned voltage generates mechanism, have the first terminal and be loaded voltage, the compensation that is connected between second terminal and the gate terminal simultaneously with transistor, the above-mentioned compensation of maintenance with the capacitance part (for example capacitor C1 of Fig. 3 or Fig. 5) of the voltage of transistorized gate terminal and repeatedly will make above-mentioned compensation load to the voltage load maintainer (for example switch SW of Fig. 3 or Fig. 5) of above-mentioned compensation with transistorized gate terminal with the forward voltage that transistor is in conducting state; Voltage or voltage corresponding with it that above-mentioned capacitance part kept are exported as reference voltage.

In addition, second feature of associated driver circuitry of the present invention, be a kind of have by one in many data lines supply with and the driving circuit of the electro-optical device of a plurality of electrooptic elements that the data-signal of regulation gray scale is controlled, at least have the data current that becomes above-mentioned data-signal or generate and use transistor as the electric current of the reference current of the benchmark of above-mentioned data current, and keep above-mentioned electric current to generate capacitance part with the voltage of transistorized gate terminal, generate above-mentioned data current or said reference electric current if be made as, and load the voltage of generating with transistorized the first terminal for above-mentioned electric current is first voltage, being located at above-mentioned electric current generates with loading under transistorized gate terminal and the interconnected state of second terminal to the first terminal, decision is second voltage as the voltage that above-mentioned electric current generates with the grid voltage of the magnitude of voltage of transistorized gate terminal, then in generating with transistorized gate terminal, above-mentioned electric current maintaining under the state of above-mentioned grid voltage by above-mentioned capacitance part, above-mentioned electric current is generated with transistorized gate terminal and the disconnection of second terminal, switch to above-mentioned first voltage with loading the voltage of generating with transistorized the first terminal for above-mentioned electric current from above-mentioned second voltage, by like this, above-mentioned electric current generates uses transistorized gain coefficient, the above-mentioned data current that voltage difference determined by above-mentioned first voltage and above-mentioned second voltage, and the said reference electric current, generate with transistor by above-mentioned electric current generation.

In addition, the associated driver circuitry of another way, it is a kind of driving circuit of electro-optical device of controlling a plurality of electrooptic elements of gray scale separately corresponding to the data-signal of supplying with through data line that has, have the voltage that generates reference voltage and generate mechanism, and according to gradation data, generation is exported to the electric current output mechanism of data line corresponding to the data-signal of the above-mentioned voltage generation reference voltage that mechanism generated; Above-mentioned voltage generates mechanism, have the first terminal and be loaded voltage, the compensation that is connected between second terminal and the gate terminal simultaneously with transistor, keep above-mentioned compensation with the capacitance part of the voltage of transistorized gate terminal and repeatedly will make above-mentioned compensation be in the forward voltage of conducting state with transistor, the voltage load maintainer of the other end of the resistive element that loading is connected with transistorized gate terminal to an end and above-mentioned compensation; Voltage or voltage corresponding with it that above-mentioned capacitance part kept are exported as reference voltage.By this mode,, therefore can simplify the formation of drive unit owing to need load forward voltage with transistorized gate terminal for compensation in particular moment.In addition, the object lesson of this mode is open in Figure 10.In addition, also can adopt each formation discussed above in the driving circuit of this mode.

Description of drawings

Fig. 1 is the block diagram of the formation of the electro-optical device of relevant first embodiment of the present invention of expression.

Fig. 2 is the circuit diagram of the formation of an image element circuit of expression.

Fig. 3 is the circuit diagram of the formation of expression data line drive circuit.

Fig. 4 is the sequential chart that is used for illustrating the action of data line drive circuit.

Fig. 5 is the circuit diagram of the formation of the data line drive circuit of relevant first variation of expression.

Fig. 6 is the sequential chart of action that is used for illustrating the data line drive circuit of relevant first variation.

Fig. 7 is the circuit diagram of the formation of the reference voltage generating circuit of relevant second variation of expression.

Fig. 8 is the circuit diagram of the formation of the leading portion of the current output circuit of relevant the 3rd variation of expression.

Fig. 9 is the sequential chart that is used to illustrate the action of the 3rd variation.

Figure 10 is the circuit diagram of the formation of the reference voltage generating circuit of relevant the 4th variation of expression.

Figure 11 is the circuit diagram of the formation of the unit circuit of the data line drive circuit of relevant second embodiment of the present invention of expression.

Figure 12 is the sequential chart that is used for illustrating the action of data line drive circuit.

Figure 13 is the circuit diagram of the state of the unit circuit among the A during representing.

Figure 14 is the circuit diagram of the state of the unit circuit among the B during representing.

Figure 15 is the circuit diagram of the state of the unit circuit among the C during representing.

Figure 16 is the circuit diagram of the state of the unit circuit among the D during representing.

Figure 17 is the circuit diagram of the formation of the data line drive circuit of relevant first variation of expression.

Figure 18 is the circuit diagram of the formation of the data line drive circuit of relevant second variation of expression.

Figure 19 is the sequential chart that is used for illustrating the action of second variation.

Figure 20 is the circuit diagram of the formation of the data line drive circuit of relevant the 3rd variation of expression.

Figure 21 is the circuit diagram of the formation of the data line drive circuit of relevant the 4th variation of expression.

Figure 22 is the circuit diagram of the formation of the data line drive circuit of relevant the 3rd embodiment of expression.

Figure 23 is the sequential chart that is used for illustrating the action of data line drive circuit.

Figure 24 is the circuit diagram of the state of the reference voltage generating circuit in representing during each equivalently.

Figure 25 is the circuit diagram of the formation of the data line drive circuit of first variation of relevant the 3rd embodiment of explanation.

Figure 26 is the sequential chart that is used for illustrating the action of reference voltage generating circuit.

Figure 27 is the circuit diagram of the state of the reference voltage generating circuit in representing during each equivalently.

Figure 28 is the stereographic map of the form (personal computer) of the relevant e-machine of the present invention of expression.

Figure 29 is the stereographic map of the form (portable telephone) of the relevant e-machine of the present invention of expression.

Figure 30 is the stereographic map of the form (carrying information terminal) of the relevant e-machine of the present invention of expression.

Among the figure: 1-electro-optical device, AA-electro-optical panel, P-pixel region, the 10-scan line drive circuit, 20-data line drive circuit, U-unit circuit, the 21-reference voltage generating circuit, 211-compensating circuit, 213-translation circuit, the 22-current mirror circuit, 23-current output circuit, 25-reference voltage line, the 27-voltage supply line, 29-comparator circuit, 30-control circuit, the 40-image element circuit, the 41-OLED element, 101-sweep trace, 102-light emitting control line, the 103-data line, the 105-on-off element, Ta-compensation transistor, Tb, the TrA-electric current generates uses transistor, Td, TrB-voltage generates uses transistor, C1, the C2-capacitor, R-resistance, Ir0-reference current, the Vref1-reference voltage, the Vr1-forward voltage.

Embodiment

＜A: first embodiment 〉

＜A-1: the formation of first embodiment 〉

Fig. 1 is the block diagram of the formation of the electro-optical device of relevant first embodiment of the present invention of expression.As shown in the figure, electro-optical device 1 possesses electro-optical panel AA, scan line drive circuit 10, data line drive circuit 20 and control circuit 30.Be formed with pixel region P among the electro-optical panel AA.Among this pixel region P, be formed with the m root sweep trace 101 that extends in directions X (line direction), and with each root sweep trace 101 in pairs and the m root light emitting control line 102 (m is a natural number) that extends at directions X.In addition, among the pixel region P, be formed with the n data lines 103 (n is a natural number) of extending perpendicular to the Y direction (column direction) of directions X.In addition, corresponding to sweep trace 101 and light emitting control line 102 to data line 103 between each intersect, image element circuit 40 is set.So these image element circuits 40 are rectangular and are arranged on directions X and the Y direction in pixel region P.Each image element circuit 40 includes the OLED element 41 as the current drive-type self-emission device.

Control circuit 30 is the circuit that are used for controlling the action of electro-optical device 1, and (enable signal SENB for example described later and control signal SINI) exports to scan line drive circuit 10 and data line drive circuit 20 with various control signals such as clock signals.In addition, control circuit 30 is exported to data line drive circuit 20 with gradation data D.This gradation data D is the numerical data of 4 bits of specifying the gray scale (briliancy) of each OLED element 41.

Scan line drive circuit 10 is circuit of selecting m root sweep trace 101 in turn respectively.In more detail, scan line drive circuit 10, in each horizontal scan period, to become in turn high level sweep signal Ya1, Ya2 ..., Yam exports to each root sweep trace 101, simultaneously with led control signal Yb1, Yb2 after its logic level counter-rotating ..., Ybm exports to each root light emitting control line 102.In case sweep signal Yai (i is for satisfying the integer of 1≤i≤m) changes high level into, then selects i capable.

In addition, data line drive circuit 20, give each image element circuit 40 supply data-signal X1, the X2 be connected with scan line drive circuit 10 selected sweep traces 101 ..., Xn.Data-signal Xj (j is for satisfying the integer of 1≤i≤n) is the current signal of the briliancy (gray scale) of the image element circuit 40 of appointment j row.Data line drive circuit 20 in the present embodiment has n unit circuit U of the sum that is equivalent to data line 103.The unit circuit U of j row is the gradation data D generation data-signal Xj according to j row image element circuit 40, and exports to the circuit of data line 103.In addition, scan line drive circuit 10 and data line drive circuit 20 and control circuit 30, both can be installed on the electro-optical panel AA, can be installed in the outside (for example being installed on the circuit board among the electro-optical panel AA) of this electro-optical panel AA again by for example COG (Chip OnGlass) technology.

Next, contrast Fig. 2 describes the formation of image element circuit 40.Among the figure, though only illustrate 1 pixel 40 that belongs to the capable j row of i, other image element circuit 40 also is identical formation.Image element circuit 40 in the present embodiment is the circuit corresponding to the current drive-type (so-called current programmed mode) of the briliancy (gray scale) of the current value of data-signal Xj control OLED element 41.

As shown in Figure 2, image element circuit 40 has 4 transistors (for example thin film transistor (TFT)) Tr1 to Tr4, and capacitor C, OLED element 41.The conductivity type of transistor Tr 1 is the p channel-type, and the conductivity type of transistor Tr 2 to Tr4 is the n channel-type.Wherein, the power lead of the high-order side current potential of the source terminal of transistor Tr 1 and supply power (below be called " power supply potential ") Vdd is connected, and its drain terminal is connected with the source terminal of transistor Tr 2, the drain terminal of transistor Tr 3 and the drain terminal of transistor Tr 4.

Capacitor C one end is connected with the source terminal of transistor Tr 1, and simultaneously, the other end is connected with the drain terminal of transistor Tr 2 with the gate terminal of transistor Tr 1.Transistor Tr 3, its gate terminal is connected with sweep trace 101 with the gate terminal of transistor Tr 2, and its source terminal is connected with data line 103.In addition, the gate terminal of transistor Tr 4 is connected with light emitting control line 102, and its source terminal is connected with the anode of OLED element 41.The ground wire of the low level side current potential of the negative electrode of OLED element 41 and supply power (below be called " earthing potential ") Gnd is connected.

In i the horizontal scan period in each vertical scanning period, when sweep signal Yai became high level, transistor Tr 2 became conducting state, and transistor Tr 1 is connected by diode, and transistor Tr 3 also becomes conducting state simultaneously.So, corresponding to the electric current of data-signal Xj at route: flow in power lead → transistor Tr 1 → transistor Tr 3 → data line 103, this moment, savings was in capacitor C corresponding to the electric charge of the gate terminal current potential of transistor Tr 1.

Next, in case i horizontal scan period finishes, sweep signal Yai becomes low level, and then transistor Tr 2 and Tr3 all become cut-off state.At this moment, the voltage between the gate-source of transistor Tr 1 remains the voltage in its previous horizontal scan period.Like this, if led control signal Ybi changes high level into, then transistor Tr 4 becomes conducting state, between the source drain of transistor Tr 1, flow into electric current corresponding to its grid voltage (also promptly corresponding to the electric current of data-signal Xj) from power lead, by the supply of this electric current, OLED element 41 is luminous.

Next, the circuit diagram of the concrete formation of 1 unit circuit U being contained in the data line drive circuit 20 for expression of Fig. 3.In addition, only shown the itemize formation of a circuit U of j among this figure, but the formation of other unit circuit U too.As shown in Figure 3, each unit circuit U has Jie by reference voltage line 25 interconnected reference voltage generating circuits 21 and current output circuit 23.

Each current output circuit 23, make a living corresponding to the data-signal Xj of the current value of the gradation data D that is supplied with by control circuit 30 and export to the D/A transducer of data line 103,4 transistor T e (Te1 to Te4) with the figure place that is equivalent to gradation data D, 4 the transistor T f (Tf1 to Tf4) that are connected with the source terminal of transistor T b with each drain terminal.The gate terminal of these transistor Ts f is common to be connected on the reference voltage line 25.The source terminal of each transistor T f is connected with the ground wire that loads earthing potential Gnd.

The characteristic of transistor T f1 to Tf4 (particularly gain coefficient) is chosen to be when having loaded common voltage for each gate terminal, and the ratio of the electric current I 1 to I4 that flows among each transistor T f is " I1: I2: I3: I4=1: 2: 3: 4 ".Also promptly, transistor T f1 is to transistor T f4, plays the function of the current source of a plurality of electric currents (I1 to I4) that generation is weighted with different weights respectively.

In addition, also can adopt the decision of the characteristic of each transistor T f to allowing the ratio of electric current I 1 to I4 be the formation of 2 power (for example becoming " I1: I2: I3: I4=1: 2: 4: 8 ").In addition, be provided with, also can allow the ratio of electric current I 1 to I4 become corresponding to the size of expecting weights even only use corresponding to the number of weights individual onesize transistor and arrangement.For example, if replace the transistor T f2 of Fig. 3, to be together in parallel with two transistors of the same characteristic of transistor T f1,4 transistors that setting is connected in parallel replace transistor T f3, equally, 8 transistors that setting is connected in parallel replace transistor T f4, just can allow the ratio of electric current I 1 to I4 be " I1: I2: I3: I4=1: 2: 4: 8 ".By adopting such formation, can reduce the deviation of each transistorized threshold voltage, high precision generates the data-signal Xj of desired electric current.

In each gate terminal of transistor T e1 to Te4, be supplied to each position of the gradation data D that is exported by control circuit 30.The drain terminal of these transistor Ts e1 to Te4 is connected through the data line 103 of on-off element 105 with the j row.On-off element 105 is for being used for controlling the mechanism that whether allows to data line 103 outputting data signals Xj.Be arranged on all on-off elements 105 of the back segment of each unit circuit U, control switching corresponding to enable signal SENB by control circuit 30 common supplies.

Fig. 4 is the sequential chart of the action of explanation data line drive circuit 20.As shown in the figure, enable signal SENB, the moment T0 with the power supply of connecting electro-optical device 1 be starting point given duration during among (below be called " during the initialization ") PINI, keep low level.In addition, enable signal SENB is after the terminal point T1 that has passed through initialization period P INI, in the horizontal scan period H that selects any sweep trace 101, keep high level, simultaneously, (below be called " interim ") Hb, keeping low level from the terminal point of each horizontal scan period H during the starting point of next horizontal scan period H.On-off element 105, in keeping each horizontal scan period H of high level, enable signal SENB becomes on-state, allow the output of data-signal Xj, in addition, keep among low level initialization period P INI and each interim Hb at enable signal SENB and to become off-state, the output of forbidden data signal Xj.

In the above formation, allow the transistor T e among 4 transistor T e1 to Te4 become conducting state selectively corresponding to gradation data D.So, become among each horizontal scan period H of on-state at on-off element 105, with circulating current I among the transistor T f more than 1 that the transistor T e that becomes conducting state is connected (from I1 to I4 selected go out the electric current more than 1), the signal that these current summations form offers data line 103 as data-signal Xj.

Reference voltage generating circuit 21 shown in Fig. 3 is with the circuit that generates voltage as the benchmark of the current value of data-signal Xj (below be called " reference voltage ") Vref1.Having compensating circuit 211 generates with transistor T b and translation circuit 213 with electric current.Wherein, electric current generates use transistor T b, for circulating corresponding to the n channel transistor of the electric current of the voltage Vref0 of gate terminal (below be called " reference current ") Ir0 to source terminal from drain terminal.This electric current generates the source terminal with transistor T b, is connected with the ground wire of supplying with earthing potential Gnd.

Translation circuit 213 makes a living the reference voltage V ref1 that generates the reference current Ir0 that is generated with transistor T b corresponding to electric current, and loads the mechanism that gives reference voltage line 25, has current mirror circuit 22 and voltage generation transistor T d.Current mirror circuit 22 wherein has p channel transistor Tc1 and Tc2 that each gate terminal is connected to each other.The drain terminal of transistor T c1 is connected on its source terminal (also being that diode connects), is connected with the drain terminal that electric current generates with transistor T b simultaneously.In addition, each source terminal of transistor T c1 and Tc2 is connected with the power lead of supply power current potential Vdd.This power supply potential Vdd is set to and allows electric current generate the level that moves in the zone of saturation with transistor T d with transistor T b and transistor T c1, Tc2 and voltage generation.

If electric current generates the reference current Ir0 that is generated with transistor T b and flows among the transistor T c1, the image current Ir1 of then corresponding with it (being typically consistent) offers voltage generation transistor T d from power lead through transistor T c2.This voltage generates and uses transistor T d, is that source terminal is connected with ground wire, and drain terminal and gate terminal are connected the n channel transistor on the reference voltage line 25 jointly simultaneously.Voltage generates the voltage with the gate terminal of transistor T d, becomes the reference voltage V ref1 corresponding to image current Ir1.Also promptly, voltage generates uses transistor T d, as loading the mechanism that gives reference voltage line 25 corresponding to the reference voltage V ref1 of image current Ir1 (so corresponding to reference current Ir0).

But, if it is different with desired characteristic because of the reason on making that electric current generates with the characteristic (particularly threshold voltage) of transistor T b, then can't generate the reference current Ir0 (even reference voltage V ref1 of given magnitude of voltage) of given current value, consequently, also can produce error in the current value of data-signal Xj.Compensating circuit 211 shown in Figure 3 is to be used for the circuit of offset current generation with the characteristic deviation of transistor T b.As shown in the figure, compensating circuit 211 has compensation transistor T a and on-off element SW and capacitor C1.

Transistor T a use in compensation, is that drain terminal and gate terminal are connected the n channel transistor on the gate terminal of electric current generation usefulness transistor T b.Compensation is connected with terminal 201 with the source terminal of transistor T a.In this terminal 201 by not shown power circuit on-load voltage Vr0.In addition, capacitor C1 is to be inserted in electric current to generate with the gate terminal of transistor T b and the electric capacity between the ground wire, and performance keeps the function of compensation with the voltage of the gate terminal of transistor T a.

On-off element SW is to be used for switching compensating with the gate terminal of transistor T a and the mechanism of conducting between the voltage supply line 27 and not conducting.In this voltage supply line 27, be loaded the voltage that power circuit generated that do not show among the figure (below be called " forward voltage ") Vr1.Forward voltage Vr1 is set as and makes compensation become the level of conducting state with transistor T a.Also promptly, forward voltage Vr1 is set to than the voltage Vr0 that load to give terminal 201 and compensation with the voltage Va of the threshold voltage vt h1 addition of transistor T a (=Vr0+Vth1) high level.

The switching of on-off element SW, the control signal SINI that is supplied with by control circuit 30 controls.As shown in Figure 4, control signal SINI, be to begin through (below be called " between the first phase ") P1 during till given duration (being shorter than the duration of initialization period P INI) at starting point T0 from initialization period P INI, begin through during preset time with starting point from each interim Hb, keep high level, become low level signal in during in addition.On-off element SW keeps between first phase of high level among P1 and each interim Hb at control signal SINI and to become on-state, becomes off-state in during in addition.

＜A-2: the action of first embodiment 〉

Next, the action to reference voltage generating circuit 21 describes.At first, among the P1, the first control signal SINI becomes high level between the first phase, and when on-off element SW changed conducting state into, compensation was loaded the forward voltage Vr1 of voltage supply line 27 with the gate terminal of transistor T a.Because forward voltage Vr1 is set to the level that is higher than voltage Va, therefore, among the P1, compensation becomes conducting state with transistor T a between the first phase.In addition, among the P1, capacitor C1 is recharged by forward voltage Vr1 between the first phase.

Next, passed through P1 between the first phase, control signal SINI changes into after the low level, and on-off element SW becomes off-state, stops to the gate terminal loading forward voltage Vr1 of compensation with transistor T a.Then between this first phase among the second phase P2 of P1,, allow the electric charge of being put aside among the capacitor C1 along with the process of time is discharged with transistor T a through compensation by forward voltage Vr1.Be accompanied by this discharge, compensation slowly descends from forward voltage Vr1 with the voltage Vref0 of the gate terminal of transistor T a.Like this, voltage Vref0 be reduced to voltage Va (=Vr0+Vth1) moment, compensation changes cut-off state into transistor T a, after this, voltage Vref0 remains voltage Va.Like this, at the level equalization of voltage Vref0 after stage, the terminal point T1 of initialization period P INI arrives.Also promptly, second phase P2, the voltage Vref0 that is chosen to be than capacitor C1 drops to the longer duration of the needed duration of voltage Va from forward voltage Vr1.In addition, below will load forward voltage Vr1 to compensation and be called " more new element " with the action of transistor T a (also promptly getting out of the way pass element SW is the action of conducting state).

As implied above, in initialization period P INI, voltage Vref0 is made as voltage Va, but after this was set, the voltage Vref0 that is produced in the gate terminal of compensation with transistor T a might change because of the noise that is produced.For example, the voltage Vref0 with the gate terminal of transistor T a is lower than because of noise becomes under the voltage condition of voltage Va in compensation, and this voltage Vref0 is maintained the voltage after the decline.Also descend if be accompanied by this action reference voltage V ref1, then the current value of data-signal Xj becomes less than allowing voltage Vref0 be maintained the normal condition of voltage Va, even the result that can cause the contrast of image to reduce.In addition, be higher than under the voltage condition of voltage Va in compensation because of noise becomes with the voltage Vref0 of the gate terminal of transistor T a, because compensation changes conducting state into transistor T a, so voltage Vref0 is reduced to Va once more, so image can be subjected to The noise hardly.Also promptly, in formation shown in Figure 3, the noise of the voltage lower than voltage Va (below be called " negative polarity noise ") especially becomes problem.In order to eliminate the reduction that this negative polarity caused by noise shows grade, in the present embodiment, even in warp each interim Hb later of initialization period P INI, also get out of the way pass element SW and become conducting state, by coming regularly to carry out more new element like this corresponding to control signal SINI.

Also promptly, in case control signal SINI changes high level in interim Hb, then with the first phase between PI the same, load forward voltage Vr1 with transistor T a for compensation, by this forward voltage Vr1 capacitor C1 is charged simultaneously.In addition, in case control signal SINI changes low level into from high level, then owing to the discharge of capacitor C1, voltage Vref0 drops to Va and stable from forward voltage Vr1.In order to prevent when voltage Vref0 (also have voltage Vref1) is in the process of variation, outputting data signals Xj, and interim Hb is chosen to be the duration that total that the duration that keeps high level than control signal SINI and voltage Vref0 be reduced to the duration before the voltage Va is also grown.

If as above like that after new element more, stablize on-load voltage Vref0 to gate terminal, then electric current generates with flowing among the transistor T b corresponding to the reference current Ir0 of voltage Vref0, in addition, flow to voltage corresponding to the image current Ir1 of this reference current Ir0 and generates with among the transistor T d.So, be loaded reference voltage V ref1 in the reference voltage line 25 corresponding to voltage Vref0.Among each horizontal scan period H after the process of initialization period P INI, enable signal SENB keeps high level, therefore be the data-signal X1 to Xn that benchmark is generated in each current output circuit 23 with reference voltage V ref1, export to data line 103 through on-off element 105.

Here, electric current generates the reference current Ir0 that is flowed with among the transistor T b, represents by following formula (1).

Ir0＝(1/2)β(Vref0-Vth2) ²……(1)

In the formula, β is that electric current generates the gain coefficient with transistor T b, and Vth2 is that electric current generates the threshold voltage with transistor T b.

Because through behind the above-mentioned initialization period P INI, voltage Vref0 stabilizes to the voltage Va (Vref0=Va=Vr0+Vth1) after voltage Vr0 and the voltage Vth1 addition, so formula (1) can be represented by following formula (2).

Ir0＝(1/2)β(Vr0+Vth1-Vth2) ²?……(2)

Here, use transistor T b and compensate setting adjacent to each other because electric current generates, so its characteristic separately is roughly the same with transistor T a.Also promptly, can think that threshold voltage vt h1 and threshold voltage vt h2 are about equally.So formula (2) can be deformed into:

Ir0＝(1/2)β(Vr0) ²?……(3)

Can learn that from formula (3) reference current Ir0 does not also rely on the threshold voltage vt h2 of electric current generation with transistor T b.So,, become and compensated electric current and generate voltage (also promptly not relying on the voltage of threshold voltage vt h2) with the deviation of the threshold voltage vt h2 of transistor T b according to the reference voltage V ref1 that this reference current Ir0 is generated.In addition, reference voltage V ref1 suitably adjusts for the voltage Vr0 of terminal 201 by changing to load.Because the maximal value of the current value of data-signal Xj is set according to reference voltage V ref1, therefore, can adjust the contrast of figure shown among the pixel region P arbitrarily by changing voltage Vr0.

As mentioned above, in the present embodiment, since comprise initialization period P INI and each interim Hb repeatedly in carry out more new element, even therefore under the situation that the voltage Vref0 that compensates the gate terminal of using transistor T a descends from voltage Va because of the negative polarity noise, also can revert to voltage Va among the interim Hb after it.So, reduced the negative polarity The noise, keep good display quality.In addition, in the present embodiment, illustration among the interim Hb between adjacent front and back horizontal scan period, carry out the more formation of new element, but also can replace this formation, or with this formation, adopt in the interim between the vertical scanning period of adjacent front and back, carry out the more formation of new element.

In addition, owing to become the voltage Vref0 on the basis of reference voltage V ref1, produce by making forward voltage Vr1 be reduced to voltage Va, if therefore in certain stage in the process that this voltage Vref0 descends, the output of implementation data signal Xj then can't be set at desired current value with this data-signal Xj.In the present embodiment, passing through initialization period P INI and interim Hb, in the stage that voltage Vref0 is stabilized, therefore the output of beginning data-signal Xj have this advantage of data-signal Xj that can high precision generates corresponding to the current value of gradation data D.

＜A-3: the variation of first embodiment 〉

Can add various distortion in the above mode.Concrete mode of texturing is as follows.In addition, each following mode can appropriate combination be got up.

＜A-3-1: first variation 〉

In the above mode, illustration 1 current output circuit 23 is provided with the formation of 1 reference voltage generating circuit 21.Relative therewith, in this variation, adopt formation by a plurality of current output circuit 23 shared 1 reference voltage generating circuit 21.

Fig. 5 is the block diagram of the formation of the data line drive circuit 20 of the electro-optical device 1 of relevant this variation of expression.As shown in the figure, the data line drive circuit 20 of this variation has 1 reference voltage generating circuit 21, with n current output circuit 23 of the total radical that is equivalent to data line 103.In addition, among Fig. 5, a detailed icon corresponding to the formation of the current output circuit 23 of j column data line 103, but the formation of other current output circuits 23 is too.As shown in Figure 5, the gate terminal of the transistor T f1 to Tf4 in all current output circuits 23 that contained in the data line drive circuit 20 is connected on the reference voltage line 25 jointly.

As above shown in the explanation, in this variation, by a plurality of current output circuit 23 shared 1 reference voltage generating circuit 21, therefore compare with the formation that each current output circuit 23 is provided with Fig. 3 of reference voltage generating circuit 21, can dwindle the circuit scale of data line drive circuit 20.

In addition, generate with transistor T b and translation circuit 213, therefore played to allow reference voltage V ref1 high precision be stabilized in this effect of desired level owing to be inserted with electric current between compensating circuit 211 and the reference voltage line 25.If it is this effect is elaborated, then as described below.

Formation as a plurality of current output circuit 23 shared 1 reference voltage generating circuit 21, it is also conceivable that electric current is not set to be generated with transistor T b and translation circuit 213, but the voltage Vref0 that compensating circuit 211 is generated directly loads and gives reference voltage line 25, offers the formation (formation that also promptly allows compensation be connected with reference voltage line 25 with the gate terminal of transistor T a) of each current output circuit 23.In this formation (below be called " contrast constitute "), each transistor T f1 to Tf4 of all current output circuits 23 is connected on the gate terminal of compensation with transistor T a jointly.Here, leak in case produce electric current between the gate terminal of each transistor T f and the source terminal, compensation just descends from desired level with the voltage Vref0 of transistor T a.In the contrast formation,, therefore exist to produce electric current leakage, higher this problem of possibility that voltage Vref0 descends among the transistor T f because the gate terminal that compensates with transistor T a directly is connected with a plurality of transistor T f.

Relative therewith, in this variation, by allowing compensation be connected with transistor T b with 1 electric current generation with the gate terminal of transistor T a, after the reference voltage V ref1 that has generated with transistor T b and translation circuit 213 by the electric current generation corresponding to voltage Vref0, load the gate terminal of the transistor T f1 to Tf4 that gives each current output circuit 23.So, even produced the electric current leakage among the transistor T f of which current output circuit 23, also reference voltage V ref1 can be maintained desired level, consequently, current value that can High Accuracy Control data-signal Xj.In addition, though this effect also can realize by the formation of Fig. 3, in 1 reference voltage generating circuit 21, connect in the formation of this variation of a plurality of transistor T f, can be described as a kind of especially effectively effect.

In the formation of Fig. 5, the same with first embodiment, comprise initialization period P INI and each interim Hb repeatedly in carry out more new element.But, in this variation, also can adopt and only in initialization period P INI, carry out the more formation of new element (not carrying out the more formation of new element among each interim Hb) as shown in Figure 6.

＜A-3-2: second variation 〉

In the above mode illustration the regular execution formation of new element more.Relative therewith, in this variation, only under being lower than the situation of voltage Va, voltage Vref0 carries out more new element.

The circuit diagram of the formation of set reference voltage generating circuit 21 among each unit circuit U of Fig. 7 for this variation of expression.As shown in the figure, the reference voltage generating circuit in this variation 21 has comparator circuit (CMP) 28.This comparator circuit 28 is to compare load for the voltage Vr2 of terminal 202 with the voltage Vref0 of compensation with the gate terminal of transistor T a, corresponding to the mechanism of the switching of this comparative result gauge tap element SW.More particularly, comparator circuit 28 is lower than at voltage Vref0 under the situation of voltage Vr2, gets out of the way pass element SW and is in on-state, carries out more new element, has surpassed at voltage Vref0 under the situation of voltage Vr2, and keeping on-off element SW is off-state.Voltage Vr2 is set to any level between the voltage Vr0 to Va (Vr0＜Vr2＜Va=Vr0+Vth1).

During this constituted, under the situation that does not produce the negative polarity noise (situation that does not produce the situation of noise fully and risen because of caused by noise voltage Vref), voltage Vref0 was higher than voltage Vr2, so on-off element SW keeps off-state.So, do not carry out more new element under this situation.Relative therewith, if produced the negative polarity noise, voltage Vref0 is lower than Vr2, then gets out of the way pass element SW by comparator circuit 28 and is in conducting state.At this moment, compensation is loaded forward voltage Vr1 with the gate terminal of transistor T a, carries out more new element.

Like this, in this variation owing to only under the situation that voltage Vref0 has descended, carry out more new element, therefore with no matter whether noise is arranged, all regularly implement more the formation of first embodiment of new element and compare, can suppress consumed power.

＜A-3-3: the 3rd variation 〉

Next, the 3rd variation is described.In the related data line drive circuit 20 of this variation, the same with first embodiment, not only in initialization period P INI, after its process, also regularly carry out more new element.

Fig. 8 is the circuit diagram that the leading portion of the current output circuit 23 in the representation unit circuit U constitutes.As shown in the figure, in this variation, 1 unit circuit U has two reference voltage generating circuit 21a and 21b.Reference voltage generating circuit 21a and 21b formation separately is the same with the reference voltage generating circuit 21 shown in first embodiment.Also be, reference voltage generating circuit 21a, according to generate the reference current Ir0_a that is generated corresponding to the voltage Vref0_a that compensates with the gate terminal of transistor T a with transistor T b by electric current, output reference voltage Vref1_a, reference voltage output circuit 21b, according to the reference current Ir0_b corresponding to voltage Vref0_b, output reference voltage Vref1_b.

The on-off element SW of reference voltage generating circuit 21a, SINI_a controls switching according to control signal, the on-off element SW of reference voltage generating circuit 21b, SINI_b controls switching according to control signal.Fig. 9 is the sequential chart of the action of the data line drive circuit 20 in this variation of explanation.After the process of initialization period P INI, control signal SINI_a and SINI_b as shown in Figure 9, change high level into alternately in each given period P.So, among reference voltage generating circuit 21a and the 21b, in each period P, carry out more new element alternately.Also be, be following situation: reference voltage generating circuit 21a has carried out more after the new element in certain period P, and in ensuing period P, reference voltage generating circuit 21b carries out more new element, and then in next period P, reference voltage generating circuit 21a carries out more new element.

As shown in Figure 8, the back segment at reference voltage generating circuit 21a and 21b is provided with selection circuit 29.This selects circuit 29, it is certain among the reference voltage V ref_b that generated of the reference voltage V ref_a that generated of selection reference voltage generation circuit 21a and reference voltage generating circuit 21b, and the mechanism of reference voltage line 25 is given in loading, on-off element SWa with the back segment that is arranged on reference voltage generating circuit 21a is with the on-off element SWb of the back segment that is arranged on reference voltage generating circuit 21b.On-off element SWa wherein, between the gate terminal and reference voltage line 25 of voltage generation with transistor T d of reference voltage generating circuit 21a, the selection signal Sc_a control of being supplied with by control circuit 30 opens and closes.In addition, on-off element SWb, between the gate terminal and reference voltage line 25 of voltage generation with transistor T d of reference voltage generating circuit 21b, the selection signal Sc_b control of being supplied with by control circuit 30 opens and closes.

As shown in Figure 9, select signal Sc_a and Sc_b, in each period P, become high level alternately.In more detail, select signal Sc_a, become at control signal SINI_a between the origin-to-destination of back to back period P of period P of high level and become high level.Equally, select signal Sc_b, become at control signal SINI_b between the origin-to-destination of back to back period P of period P of high level and become high level.In other words, select signal Sc_a, in control signal SINI_b is the period P of high level, become high level, select signal Sc_b, in control signal SINI_a is the period P of high level, become high level.

During this constituted, when carrying out more new element by the side among reference voltage generating circuit 21a and the 21b, the opposing party was loaded into reference voltage V ref1 on the reference voltage line 25.For example, SINI_a becomes high level in control signal, implement by reference voltage generating circuit 21a in the period P of new element more, select signal SINI_b to change high level into, on-off element SWb becomes on-state, so the reference voltage V ref_b that reference voltage generating circuit 21b is generated loads to reference voltage line 25 as reference voltage V ref1.In addition, become in the period P of high level, become conducting state, reference voltage V ref_a is exported to reference voltage line 25 by selecting signal SINI_a to get out of the way pass element SWa at control signal SINI_b.

Like this, in this variation, do,, also can often certain reference voltage V ref1 be offered each current output circuit 23 although therefore voltage Vref0 is accompanied by more new element and changes because reference voltage generating circuit 21a and 21b cover action mutually.So, do not need forbidden data signal Xj output during (also promptly get out of the way close element 105 be in off-state during) and be used for to its on-off element of forbidding 105.

But, in the formation of this variation, with the supply source of reference voltage V ref1 from the moment that the side of reference voltage generating circuit 21a and 21b switches to the opposing party, might produce noise in the reference voltage line 25 and cause reference voltage V ref1 change.Therefore, after the formation that adopts the supply source (even also selecting the level of signal Sc_a and Sc_b to change) that in interim Hb, switches reference voltage V ref1, can be the same with first embodiment, get out of the way pass element 105 and in interim Hb, be in off-state.Owing to can produce because of the duration during the caused noise of switching of the supply source of reference voltage V ref1, new element allows voltage Vref0 vary to the time appearance of voltage Va from forward voltage Vr1 than enough short with being accompanied by more, therefore in should constituting, has the advantage that can shorten interim Hb.

In addition, among Fig. 8 illustration have the unit circuit U of two reference voltage generating circuit 21a and 21b, but also can adopt the formation that has 3 above reference voltage generating circuits 21 among 1 unit circuit U.This in each reference voltage generating circuit 21, carries out more new element in constituting in turn in each period P, in addition, select circuit 29,, select in the period P after it for the reference voltage that the reference voltage generating circuit of having carried out in period P after the new element more 21 is generated.

＜A-3-4: the 4th variation 〉

The circuit diagram of the formation of set reference voltage generating circuit 21 among the unit circuit U of Figure 10 for this variation of expression.As shown in the figure, this reference voltage generating circuit 21 replaces the on-off element SW in first embodiment, has resistance R.Also promptly, the voltage supply line 27 that has been loaded forward voltage Vr1 is electrically connected through resistance R with the gate terminal of compensation with transistor T a.Resistance R has allows the high resistance of this degree of circulation Weak current Ir in this resistance R.Electric current I r, when being in the degree near voltage Va at voltage Vref0, with compensation with the electric current that is flowed among the transistor T a about equally electric current or than its big slightly electric current.

By this formation, owing to supply with small electric current I r with transistor T a often for compensation through resistance R from voltage supply line 27, therefore the more new element as first embodiment and first to the 3rd variation not just can allow the electric current generation remain voltage Va with the voltage Vref0 of the gate terminal of transistor T b.So, the formation (for example control circuit 30) that can simplify the formation of reference voltage generating circuit 21 and be used for controlling its action.In addition, during this constitutes, be roughly necessarily, therefore suitably omitted the capacitor C1 that is used for keeping this voltage owing to keep the voltage of compensation by resistance R with the gate terminal of transistor T a.

＜A-3-5: other variation 〉

Can also add following distortion in first embodiment and first to fourth variation.

(1) in the aforesaid way, illustration between compensating circuit 211 and reference voltage line 25, be inserted with electric current and generate formation with transistor T b and translation circuit 213, omitted the formation of electric current generation but also can adopt with transistor T b and translation circuit 213, also be about to voltage Vref0 that compensating circuit 211 generated and directly load and give reference voltage line 25, offer the formation (also i.e. compensation be connected with reference voltage line 25 formation) of current output circuit 23 with the gate terminal of transistor T a.By adopting this formation, just have the advantage of the formation that can simplify each unit circuit U.But, if as first embodiment, reference voltage generating circuit 21 is to possess electric current to generate the formation of using transistor T b and translation circuit 213, then compares with the formation of this variation, has played to allow reference voltage V ref1 be stabilized to the effect of desired level accurately.Detailed content about this effect is as described below.

In the formation of this variation, all crystals pipe Tf1 to Tf4 of current output circuit 23 is connected on the gate terminal of compensation with transistor T a jointly.Here, if produced the electric current leakage between the gate terminal of each transistor T f and the source terminal, just the voltage Vref0 that then compensates with transistor T a begins to descend from desired level.In the formation of this variation,, therefore exist to produce electric current leakage, higher this problem of possibility that voltage Vref0 descends among the transistor T f owing in compensating, directly connect a plurality of transistor T f with the gate terminal of transistor T a.In addition,, need the number of degrees of the current value of increase data-signal Xj in order to realize many gray processings of image, but owing to therefore just need the number of increase transistor T f, so this problem becomes more remarkable.

In addition, in first embodiment, by connecting 1 electric current generation transistor T b in the gate terminal of using transistor T a in compensation, after the reference voltage V ref1 that has generated with transistor T b and translation circuit 213 by the electric current generation corresponding to voltage Vref0, reload gate terminal to each transistor T f1 to Tr4.So, even produced the electric current leakage among certain transistor T f of hypothesis current output circuit 23, also reference voltage V ref1 can be maintained desired level, consequently, have can High Accuracy Control data-signal Xj this advantage of current value.

(2) in Yi Shang each mode, illustration on electric current generates gate terminal with transistor T b, be connected with the formation of capacitor C1, but this capacitor C1 is not necessarily necessary.For example, if can access the effect identical with the grid capacitance that transistor T a and electric current generate with transistor T b, just capacitor C1 need be set independently outside other key elements with each mode by compensation.

(3) in Yi Shang each mode, illustration compensation have the formation of identical characteristics with the generation of transistor T a and electric current with transistor T b, but these characteristics do not need unanimity strictly.For example, as long as by visually occurring in the limit of influence in the shown image of electro-optical device 1, compensation also can be different with transistorized threshold voltage vt h2 with the electric current generation with the threshold voltage vt h1 of transistor T a.

(4) each transistorized conductivity type of suitably change formation reference voltage generating circuit 21.For example, also can adopt the n channel transistor in the reference voltage generating circuit 21 (Ta, Tb and Td) is replaced to the p channel transistor, p channel transistor (Tc1 and Tc2) be replaced to the formation of n channel transistor.But these for example need the power supply potential Vdd shown in Fig. 1 is replaced to earthing potential Gnd in constituting, and simultaneously earthing potential Gnd are replaced to power supply potential Vdd.

(5) change the formation of image element circuit 40 arbitrarily.So, in the mode of data-signal Xj also the formation corresponding to image element circuit 40 suitably change.For example, in each above mode, illustration the electro-optical device 1 of output corresponding to the data-signal Xj of the current value of gradation data D, but by in the time density corresponding to gradation data D, output becomes in the electro-optical device of pulse width modulation of data-signal Xj of first current value and second current value, also can use the present invention.In addition, with data-signal Xj in each row in turn the point of output in turn the line exported together of type of drive and the data-signal X1 to Xn that will be listed as entirely can both be suitable for the present invention in turn in any electro-optical device of type of drive.

＜B: second embodiment 〉

Next, second embodiment of the present invention is described.In addition, give with present embodiment in the element annotation identical symbol identical with first embodiment, suitably omit its explanation.

＜B-1: the formation of data line drive circuit 〉

The circuit diagram of the concrete formation of 1 unit circuit U that Figure 11 is contained in the data line drive circuit 20 for expression.In addition, among the figure, though only illustrate the formation of the unit circuit U that belongs to the j row, other unit circuit U also is identical formation.As shown in figure 11, each unit circuit U has as the reference voltage generating circuit 21 through reference voltage line 25 interconnected reference voltage generating units, with the current output circuit 23 as the electric current efferent.The formation of each current output circuit 23 is the same with first embodiment.Be arranged on all on-off elements 105 of the back segment of each unit circuit U, corresponding to controlling switching from 30 common enable signal SENB that supply with of control circuit.

Figure 12 is the sequential chart that is used for illustrating the action of data line drive circuit 20.As shown in the figure, enable signal SENB, from as the time point t0 of the timing of the power supply of connecting electro-optical device 1 to the initialization period P INI the time point t3, keep low level.In addition, enable signal SENB is after the time point t3 that has passed through as the terminal point of initialization period P INI, in the horizontal scan period H that selects arbitrary sweep trace 101, keep high level, simultaneously, from as the time point t4 of the terminal point of each horizontal scan period H to as the interim Hb the time point t7 of the starting point of next horizontal scan period H, keep low level.

The formation of＜reference voltage generating circuit 〉

Reference voltage generating circuit 21 shown in Figure 11, be the circuit that generates as the reference voltage V refl of the benchmark of the current value of data-signal Xj, generate with transistor Tr A, constitute with transistor Tr B and 4 on-off element SWA, SWB, SWC, SWD as the voltage generation of capacitor C1, the output reference voltage Vref1 of capacitance part by generating electric current as the reference current Ir0 on the basis of reference voltage V ref1.

In the reference voltage generating circuit 21, by power circuit (diagram omit) supply power current potential Vdd and setting than its lower given current potential Vref.Be under the situation of 15V at power supply potential Vdd for example, current potential Vref is set as about 13V.

Among the capacitor C1, square end is connected with power supply potential Vdd, and the opposing party's terminal is connected with the gate terminal that electric current generates with transistor Tr A, plays the effect that holding current generates the voltage of the gate terminal of using transistor Tr A.

It is the n channel-type that voltage generates with transistor Tr B, source terminal is connected with the ground wire that has been loaded earthing potential Gnd, gate terminal is connected to each other (diode is connected) with drain terminal, drain terminal is connected through the gate terminal of reference voltage line 25 with the transistor T f (Tf1 to Tf4) of current output circuit 23.

On-off element SWA, one square end is connected with power supply potential Vdd, the opposing party's terminal is connected with the source terminal that electric current generates with transistor Tr A, corresponding to control signal SA, switch to the some of connection status (conducting state) and notconnect state (nonconducting state) from control circuit 30.The on-off element SWA of present embodiment becomes connection status at control signal SA during for high level, becomes notconnect state for low level the time.

On-off element SWB, one square end is connected with current potential Vref, and the opposing party's terminal is connected with the source terminal that electric current generates with transistor Tr A, corresponding to the control signal SB from control circuit 30, switches to certain of connection status and notconnect state.The on-off element SWB of present embodiment becomes connection status at control signal SB during for high level, becomes notconnect state for low level the time.

On-off element SWC, one square end is connected with the gate terminal that electric current generates with transistor Tr A, the opposing party's terminal is connected with the drain terminal that electric current generates with transistor Tr A, corresponding to the control signal SC from control circuit 30, switches to certain of connection status and notconnect state.The on-off element SWC of present embodiment becomes connection status at control signal SC during for high level, becomes notconnect state for low level the time.

On-off element SWD, one square end is connected with the drain terminal that electric current generates with transistor Tr A, the opposing party's terminal is connected with the drain terminal that voltage generates with transistor Tr B, corresponding to the control signal SD from control circuit 30, switches to certain of connection status and notconnect state.The on-off element SWD of present embodiment becomes connection status at control signal SD during for high level, becomes notconnect state for low level the time.

It is the p channel-type that electric current generates with transistor Tr A, at the control signal SA from control circuit 30 is that high level and control signal SB are when being low level, on-off element SWA becomes connection status, and on-off element SWB becomes notconnect state, gives source terminal loading power current potential Vdd; At control signal SB is high level and control signal SA when being low level, and on-off element SWB becomes connection status, and on-off element SWA becomes notconnect state, loads current potential Vref to source terminal.In addition, as shown in figure 12, control signal SA and SB are controlled, make it opposite mutually, the logic level difference.

In addition, electric current generates and uses transistor Tr A, and when the control signal SC from control circuit 30 was high level, on-off element SWA became connection status, and gate terminal is connected to each other (diode is connected) with drain terminal.In addition, when the control signal SD from control circuit 30 was high level, on-off element SWD became connection status, and the drain terminal that electric current generates with transistor Tr A is connected with the drain terminal that voltage generates with transistor Tr B.

＜B-2: the action of second embodiment 〉

Next, the action to present embodiment describes.In addition, because the action except reference voltage generating circuit 21 is all identical with first embodiment in the present embodiment, therefore following emphasis describes the action of reference voltage generating circuit 21.

Figure 12 is the sequential chart of the action of explanation reference voltage generating circuit 21.As shown in figure 12, reference voltage generating circuit 21 move during, be divided into from time point t0 during the time point t1 A (between the first phase), from time point t1 during the time point t2 B (second phase), from time point t2 during the time point t3 C (between the third phase), from time point t3 D (between the fourth phase) during the time point t4.Figure 13 is the circuit diagram of the state of the unit circuit U among the A during representing, Figure 14 is the circuit diagram of the state of the unit circuit U among the B during representing, Figure 15 is the circuit diagram of the state of the unit circuit U among the C during representing, and Figure 16 is the circuit diagram of the state of the unit circuit U among the D during representing.Below, during the action of reference voltage generating circuit 21 is divided into A to during D, describe respectively.

＜during the action of A

At first, during among the A, as shown in figure 12, by control circuit 30, SENB is made as low level with enable signal, SA is made as low level with control signal, SB is made as high level with control signal, SC is made as high level with control signal, SD is made as high level with control signal.By this setting, as shown in figure 13, on-off element SWA becomes notconnect state, and on-off element SWB and on-off element SWC and on-off element SWD become connection status.So, the source terminal that electric current generates with transistor Tr A is loaded current potential Vref, the gate terminal that electric current generates with transistor Tr A interconnects (diode is connected) with drain terminal, and the drain terminal that electric current generates with transistor Tr A is connected with the drain terminal that voltage generates with transistor Tr B.

By the state of this connection, electric current generates the current potential with the gate terminal of transistor Tr A, becomes by electric current to generate the current potential that is determined with the ratio of the conducting resistance of transistor Tr B with transistor Tr A and voltage generation.The ratio of conducting resistance is generated with transistor Tr A and the ratio decision of voltage generation with transistor Tr B grid width separately and grid length and degree of excursion by electric current.For example, if electric current generates with grid width=5 μ m of transistor Tr A, grid length=10 μ m, degree of excursion=0.5, voltage and generates grid width=5 μ m, grid length=15 μ m, degree of excursion=1.0 with transistor Tr B, then electric current generates with transistor Tr A and voltage generation and becomes 4: 3 with the ratio of the conducting resistance of transistor Tr B.If current potential Vref=13V, then the electric current generation becomes=Vref * 3/ (3+4) ≈ 5.57V with the current potential of the gate terminal of transistor Tr A.In addition, during this period among the A, the reference voltage V ref1 that exports to reference voltage line 25 is not set as desired value as yet, but since during among the A, get out of the way pass element 105 by low level enable signal SENB and become notconnect state, therefore can be to the unsettled data-signal Xj of data line 103 outputs.

＜during the action of B

During then A during among the B, as shown in figure 12, by control circuit 30, keeping enable signal SENB is low level, and control signal SA is a low level, and control signal SB is a high level, control signal SC is a high level, and SD switches to low level from high level with control signal.By this setting, as shown in figure 14, on-off element SWD becomes notconnect state.Continuation loads current potential Vref to the source terminal that electric current generates with transistor Tr A, electric current generates gate terminal with transistor Tr A be connected with drain terminal (diode is connected), therefore, if establishing the threshold voltage that electric current generates with transistor Tr A is VthA, then the electric current generation is slowly risen with the grid potential of transistor Tr A, reaches " Vref-VthA ".

＜during the action of C

During then B during among the C, as shown in figure 12, by control circuit 30, keeping enable signal SENB is low level, and control signal SA is a low level, and control signal SB is a high level, control signal SD is a low level, and SC switches to low level from high level with control signal.By this setting, as shown in figure 15, on-off element SWC becomes notconnect state, and gate terminal and drain terminal that electric current generates with transistor Tr A become notconnect state, so keep current potential " Vref-VthA " among the capacitor C1.

＜during the action of D

During ensuing among the D, as shown in figure 12, by control circuit 30, retentive control signal SC is a low level, respectively enable signal SENB is switched to high level from low level, control signal SA switches to high level from low level, and control signal SB switches to low level from high level, and control signal SD switches to high level from low level.By this setting, as shown in figure 16, on-off element SWA becomes connection status, on-off element SWB becomes notconnect state, loading generates the current potential of the source terminal of using transistor Tr A to electric current, switch to power supply potential Vdd from current potential Vref, on-off element SWD becomes connection status, and the drain terminal that electric current generates with transistor Tr A is connected with the drain terminal that voltage generates with transistor Tr B.In addition, because the gate terminal that electric current generates with transistor Tr A is remained current potential " Vref-VthA " by capacitor C1, therefore produce reference current Ir0 to earthing potential Gnd from power supply potential Vdd.In addition, by voltage generation transistor Tr B, supply with reference voltage V ref1 to current output circuit 23 from reference voltage line 25.

The reference voltage V ref1 of current output circuit 23 offers transistor T f (Tf1 to Tf4), if the transistor T e (Te1 to Te4) corresponding to gradation data D becomes conducting state, streaming current I among the transistor T f (from I1 to I4 selected go out the electric current more than 1) then, the signal that these current summations get up offers data line 103 as data-signal Xj.

Reference current Ir0, if establishing the gain coefficient that electric current generates with transistor Tr A is β, the threshold voltage that electric current generates with transistor Tr A is VthA, it is Vgs that electric current generates with current potential between the gate-to-source of transistor Tr A, then because Vgs=Vdd-(Vref-VthA), so Ir1=(1/2) * β * (Vgs-VthA) ²=(1/2) * β * (Vdd-(Vref-VthA)-VthA) ²=(1/2) * β * (Vdd-Vref) ²Promptly, reference current Ir0 is not subjected to the influence that electric current generates the threshold voltage vt hA that uses transistor Tr A, and decides by the setting of power supply potential Vdd and current potential Vref yet.

In addition, interim Hb (during A with during B and during C) in more new element, the current potential " Vref-VthA " of capacitor C1 is carried out (the time point t4 of Figure 12 is to time point t7) before beginning to descend between the D during as horizontal scan period H.This is new element more, carries out in the interim between interim between horizontal scan period in succession or the vertical scanning period in succession.

As mentioned above, in the present embodiment, reference current Ir0 (and reference voltage V ref1) can not be subjected to electric current and generate influence with the threshold voltage vt hA of transistor Tr A, but decide according to power supply potential Vdd and current potential Vref.So, can reduce the caused threshold voltage vt hA of manufacturing process deviation and with its corresponding characteristic error, generate the reference current Ir0 (or reference voltage V ref1 of desired magnitude of voltage) of desired current value accurately.In addition, because by repeatedly carrying out more new element, come at any time the current value of reference current Ir0 is set at desired value, therefore stable benchmark voltage Vrefl can be offered current output circuit 23.

＜B-3: the variation of second embodiment 〉

Can add various distortion in the second above embodiment.If the mode of texturing that illustration is concrete is then as described below.In addition, each following mode can appropriate combination be got up.

＜B-3-1: first variation 〉

In second embodiment, illustration include the formation of 1 reference voltage generating circuit 21 and 1 current output circuit 23 among each unit circuit U that is contained in the data line drive circuit 20.Relative therewith, the same with the formation of Fig. 5 in this variation, a plurality of current output circuits 23 are connected with 1 reference voltage generating circuit 21.

Figure 17 is the circuit diagram of the formation of the data line drive circuit 20 in this variation of expression.As shown in figure 17, generate the reference voltage line 25 that the drain terminal with transistor Tr B is connected, be connected jointly on the gate terminal of transistor T f (Tf1 to Tf4) of a plurality of current output circuits 23 with the voltage of reference voltage generating circuit 21.By adopting this formation, compare with the formation that is provided with reference voltage generating circuit 21 among each unit circuit U, can dwindle circuit scale.

＜B-3-2: second variation 〉

In first embodiment, illustration include the formation of 1 reference voltage generating circuit 21 among 1 the unit circuit U that is contained in the data line drive circuit 20.Relative therewith, the same with the illustrated formation of Fig. 8 in this variation, certain in two reference voltage generating circuits 21 is connected with current output circuit 23 selectively.

Figure 18 is the circuit diagram of the formation of the data line drive circuit 20 in this variation of expression.As shown in figure 18, the unit circuit U of data line drive circuit 20 includes two reference voltage generating circuit 21A, 21B, selection circuit 29 and current output circuit 23.Reference voltage generating circuit 21A, 21B formation separately is the same with the reference voltage generating circuit 21 of second embodiment shown in Figure 11.

On-off element SWA, the SWB of reference voltage generating circuit 21A, SWC, SWD are controlled by control signal SA1, SB1, SC1, SD1 from control circuit 30 respectively.In addition, on-off element SWA, the SWB of reference voltage generating circuit 21B, SWC, SWD are controlled by control signal SA2, SB2, SC2, SD2 from control circuit 30 respectively.

Select circuit 29 to have on-off element SW1, SW2.On-off element SW1, one square end is connected with the gate terminal (reference voltage V ref1A) that the electric current of reference voltage generating circuit 21A generates with transistor Tr A, the opposing party's terminal is connected with reference voltage line 25 simultaneously, corresponding to control signal S1, switch to certain in connection status and the notconnect state from control circuit 30.On-off element SW2, one square end is connected with the gate terminal (reference voltage V ref1B) that the electric current of reference voltage generating circuit 21B generates with transistor Tr A, the opposing party's terminal is connected with reference voltage line 25 simultaneously, corresponding to control signal S2, switch to certain in connection status and the notconnect state from control circuit 30.

Next, contrast Figure 18 and Figure 19 are to describing based on the reference voltage generating circuit 21A of control circuit 30, the action of 21B.Figure 19 is the sequential chart that is used for illustrating based on the action of reference voltage generating circuit 21A, the 21B of control circuit 30 and selection circuit 29.As shown in figure 19, corresponding to control signal SA (SA1, SB1, SC1, SD1) from control circuit 30, generate the action of reference voltage V ref1A in the electric current of reference voltage generating circuit 21A generates with the gate terminal of transistor Tr A, the action illustrated with contrast Figure 12 (reference voltage generating circuit 21 generates the action of reference voltage V ref1) is identical.

At the time point t3 shown in Figure 19, D during reference voltage generating circuit 21A becomes, the grid potential Vref1A that the electric current of reference voltage generating circuit 21A generates with transistor Tr A remains Vref-VthA.At this time point, the control signal S1 of control circuit 30 switches to high level from low level, select the on-off element SW1 of circuit 29 to become connection status, electric current from reference voltage generating circuit 21A to reference voltage line 25 that supply with generates the grid potential Vref1A that uses transistor Tr A.In addition, control signal S2 keeps low level.

In addition, reference voltage generating circuit 21B, A during beginning to become from time point t3, B during time point t4 becomes, C during time point t5 becomes, D during time point t6 becomes.Among the time point t6, the grid potential Vref1B that the electric current of reference voltage generating circuit 21B generates with transistor Tr A remains Vref-VthA.At this time point, the control signal S2 of control circuit 30 switches to high level from low level, select the on-off element SW2 of circuit 29 to become connection status, electric current from reference voltage generating circuit 21B to reference voltage line 25 that supply with generates the grid potential Vref1B that uses transistor Tr A.In addition, control signal S switches to low level from high level, selects the on-off element SW1 of circuit 29 to become notconnect state.

Among the time point t7, A during reference voltage generating circuit 21A becomes once more, D during time point t10 becomes, control signal S1 switches to high level from low level, select the on-off element SW1 of circuit 29 to become connection status, electric current from reference voltage generating circuit 21A to reference voltage line 25 that supply with generates the grid potential Vref1A that uses transistor Tr A.In addition, control signal S2 switches to low level from high level, selects the on-off element SW2 of circuit 29 to become notconnect state.

Afterwards, repeat to begin action till the time point t10 from time point t3, alternately electric current from reference voltage generating circuit 21A to reference voltage line 25 that supply with generates the grid potential Vref1A with transistor Tr A, generates grid potential Vref1B with transistor Tr A with the electric current of reference voltage generating circuit 21B.

If adopt with upper type, allow two reference voltage generating circuit 21A, 21B interactive action by controlling, can often supply with stable benchmark voltage to reference voltage line 25.In addition, even can't set for a long time under the situation of interim, also can often supply with stable benchmark voltage to reference voltage line 25.

＜B-3-3: the 3rd variation 〉

In second embodiment, illustration include the formation of reference voltage generating circuit 21 and current output circuit 23 among 1 the unit circuit U that is contained in the data line drive circuit 20.Relative therewith, in this variation, employing will generate the reference current Ir0 that is generated with transistor Tr A by electric current and directly export to data line 103, drive the PWM circuit of pulse-length modulation (PWM:Pulse WidthModulation) mode of image element circuit 40.

Figure 20 is the circuit diagram of the formation of the data line drive circuit 20 in this variation of expression.As shown in figure 20, include 1 reference current generating circuit 210 among the unit circuit U of data line drive circuit 20.Reference current generating circuit 210 has electric current and generates with transistor Tr A, capacitor C1,4 on-off element SWA, SWB, SWC, SWD, and transistor Tr D.Electric current generates the formation with transistor Tr A, capacitor C1 and 3 on-off element SWA, SWB, SWC, and is identical with the reference voltage generating circuit 21 of Figure 11.

On-off element SWD, one square end is connected with the drain terminal that electric current generates with transistor Tr A, in the opposing party's terminal, supplied with than current potential Vref and the difference also low current potential Vref2 of electric current generation with the threshold voltage of transistor Tr A by power circuit (diagram is omitted).

Transistor Tr D is the n channel-type, source terminal is connected with the drain terminal that electric current generates with transistor Tr A, drain terminal is connected with square end of on-off element 105, and the gradation data D of the pulse width of definition of data signal Xj is provided for gate terminal from control circuit 30.Also promptly, exporting to the data-signal Xj of data line 103 from transistor Tr D through reference current line 220, is in the pulse width corresponding to gradation data D, and current value becomes the pulse signal of reference current Ir0.

＜B-3-4: the 4th variation 〉

In the 3rd variation, illustration with PWM with circuit as the formation of reference current generating circuit 210, but in the following variation, adopt a plurality of reference current Ir0 that respectively different electric current generations generated with transistor Tr A to export selectively, and drive the current summation type circuit of pulse-amplitude modulation (the PAM:pulse amplitude modulation) mode of image element circuit 40.

Figure 21 is the circuit diagram of the formation of 1 unit circuit U in this variation of expression.As shown in figure 21, the unit circuit U of this variation has 1 reference current generating circuit 211.This reference current generating circuit 211 has capacitor C1, two on-off element SWA and SWB, 4 electric currents generate with transistor Tr A (TrA1 to TrA4), 4 on-off element SWC (SWC1 to SWC4), 4 on-off element SWD (SWD1 to SWD4), 4 transistor Tr D (TrD1 to TrD4).

4 electric currents generate and are connected to each other with transistor Tr A source terminal separately, and gate terminal separately is connected on square end of capacitor C1 jointly simultaneously.In addition, each electric current generates the drain terminal with transistor Tr A, is connected with the source terminal of 1 the transistor Tr D that is arranged on its back segment.Be supplied to each position of gradation data D in the source terminal separately of 4 transistor Tr D, drain terminal separately is connected on the on-off element 105 jointly.Also promptly, the unit circuit U of this variation is 4 formations that are set up in parallel that electric current generates the circuit that constituted with transistor Tr A and transistor Tr D and on-off element SWC and SWD (also i.e. the identical circuit with Figure 20).

Each of 4 on-off element SWC (SWC1 to SWC4), one square end is connected with the gate terminal that electric current generates with transistor Tr A (TrA1 to TrA4), the opposing party's terminal is connected with the drain terminal that electric current generates with transistor Tr A (TrA1 to TrA4), corresponding to control signal SC, switch to certain in connection status and the notconnect state from control circuit 30.In addition, each of 4 on-off element SWD (SWD1 to SWD4), one square end is connected with the drain terminal that electric current generates with transistor Tr A (TrA1 to TrA4), the opposing party's terminal is connected with current potential Vref2, corresponding to control signal SD, switch to any in connection status and the notconnect state from control circuit 30.

If selected among 4 transistor Tr D1 at least one corresponding to gradation data D, then generate the reference current Ir0 that is generated with transistor Tr A by electric current corresponding to this transistor Tr D1, in reference current line 220, after the addition, export to data line 103 as data-signal Xj.Like this, in this variation, 4 transistor Tr D1 to TrD4 play and will export to the effect of mechanism's (signal output mechanism) of data line 103 corresponding to the data-signal Xj of reference current Ir0.By adopting this formation, owing to can not need current output circuit 23 among Figure 11, therefore can cut down needed area in the configuration of unit circuit U.

＜B-3-5: other variation 〉

In second embodiment and the variation thereof, can add the distortion of the following stated respectively.

In (1) second embodiment, illustration carry out the more formation of new element in interim between horizontal scan period in succession or the interim between the vertical scanning period in succession, but can be unit also, carry out once more new element with a plurality of horizontal scan period H or a plurality of vertical scanning period.For example, can adopt when all sweep traces 101 of pixel region P have all only been selected given number of times, carry out the more formation of new element.

In (2) second embodiments, generation is made of the p channel transistor with transistor Tr A to electric current, voltage generates and is illustrated by the situation that the n channel transistor constitutes with transistor Tr B, but also can be that the electric current generation is made of the n channel transistor with transistor Tr A, voltage generates and is made of the p channel transistor with transistor Tr B.

In (3) second embodiments, to during get out of the way among the A and close element SWD and be in connection status, electric current generated with the drain terminal of transistor Tr A and the voltage generation drain terminal with transistor Tr B couple together, setting the current potential that electric current generates with the gate terminal of transistor Tr A is illustrated, to make electric current generate voltage but also can adopt, load to electric current the generation gate terminal of transistor Tr A and the formation of drain terminal with transistor Tr A conducting.If adopt such formation, be transformed into from (during during the A+ during the B+ C) during then can allowing more new element needed (during B+ during C), during A during having shortened during the new element more.

In (4) second embodiments, illustration from the formation of the signal of control circuit 30 output control signal SA and these two systems of control signal SB, but the also side from control circuit 30 output control signal SA and control signal SB only, the opposing party's signal generates by by phase inverter logic level being reversed.

In (5) second variation, as shown in figure 18, situation about being made of two reference voltage generating circuit 21A, 21B and selection circuit 29 is illustrated, make the voltage generation of reference voltage generating circuit 21A, 21B shared but also can adopt, alternatively the formation of output reference electric current with transistor Tr B.In addition, in second variation, illustration with 2 reference voltage generating circuit 21A and 21B formation through selecting circuit 29 to be connected with 1 current output circuit 23, but also can as first variation is illustrated, adopt the formation through selecting circuit 29 to be connected with a plurality of current output circuits 23 with 2 reference voltage generating circuit 21A and 21B.

(6) in Yi Shang each mode, electric current is generated the formation that is connected with capacitor C1 in the gate terminal with transistor Tr A be illustrated, if but can holding current generate the voltage of the gate terminal of usefulness transistor Tr A, then not necessarily to constitute by capacitor.

＜C: the 3rd embodiment 〉

Next, the 3rd embodiment of the present invention is described.In addition, give with present embodiment in the element annotation identical symbol identical with first embodiment, suitably omit its explanation.

＜C-1: the formation of the 3rd embodiment 〉

Figure 22 is the circuit diagram of the formation of 1 unit circuit U in the data line drive circuit 20 of expression present embodiment.As shown in the figure, this unit circuit U possesses reference voltage generating unit 21 and current output circuit 23.The formation of current output circuit 23 is the same with first embodiment.As shown in figure 22, the reference voltage generating circuit 21 of present embodiment has p channel-type electric current and generates with transistor Tr A, n channel-type voltage generation transistor Tr B, capacitor C2 and 4 on-off element SW (SW1 to SW4).

Electric current generates and uses transistor Tr A, is that its source terminal is supplied to power supply potential Vdd with the mechanism that generates reference current Ir0.Voltage generates and uses transistor Tr B, is the reference voltage V refl that generates corresponding to reference current Ir0, the mechanism that exports to reference voltage line 25.Voltage generates gate terminal and the drain terminal with transistor Tr B, is connected electric current jointly and generates on the drain terminal and reference voltage line 25 of using transistor Tr A.In addition, voltage generates the source terminal ground connection with transistor Tr B.

Capacitor C2 is that the gap intermediary between the first electrode E1 and the second electrode E2 has dielectric electric capacity.The first electrode E1 is connected with terminal T1 through on-off element SW1, simultaneously, is connected with terminal T2 through on-off element SW2.Pass through power circuit (diagram is omitted) on-load voltage VINI among the terminal T1.Equally, be loaded voltage Vref among the terminal T2.In addition, the second electrode E2 is connected with the gate terminal that electric current generates with transistor Tr A.In addition, also can adopt to be used for holding current and to generate maintenance electric capacity, be inserted in electric current and generate with the gate terminal of transistor Tr A and the formation between the source terminal with the voltage Vg of the gate terminal of transistor Tr A.

On-off element SW3 generates between the gate terminal and earthing potential Gnd of using transistor Tr A between electric current.On-off element SW4 generates between the gate terminal and drain terminal of using transistor Tr A between electric current.So, if on-off element SW4 changes conducting state into, just then the electric current generation is connected by diode with transistor Tr A.

Each on-off element SW is to change on-state (conducting state) when the control signal S (S1 to S4) that offers it becomes high level into, changes the switch of off-state (not on-state) when becoming low level into.For example, on-off element SW1 becomes conducting state at control signal S1 during for high level, becomes off-state for low level the time.Each control signal S is supplied with by control circuit 30.

＜C-2: the action of the 3rd embodiment 〉

Figure 23 is the sequential chart that is used for illustrating the action of the reference voltage generating circuit 21 in the present embodiment.In the present embodiment, the horizontal scan period H (P4 between the fourth phase) and the enable signal SENB that enable signal SENB are kept high level keep low level interim Hb as period T, repeatedly carry out more new element.Interim Hb is divided into P1 between the first phase, second phase P2 and P3 between the third phase.P1 and second phase P2 are used for offset current to generate with during the error (deviation) of the threshold voltage vt h of transistor Tr A between the first phase, between the third phase P3 and between the fourth phase P4 (horizontal scan period H) be used for during the actual generation reference current Ir0.

Control signal S1 keeps high level in interim Hb, simultaneously, keep low level in horizontal scan period H.In addition, control signal S2 is with resulting signal after the logic level counter-rotating of control signal S1, keeps low level in interim Hb, simultaneously, keeps high level in horizontal scan period H.Control signal S3 keeps high level among the P1 between the first phase of interim Hb, keep low level in during in addition.Control signal S4 keeps high level among P1 and the second phase P2 between the first phase of interim Hb, keep low level in during in addition.

Next, contrast Figure 23 and Figure 24 describe the concrete action of reference voltage generating circuit.The circuit diagram that Figure 24 constitutes for the equivalence of the reference voltage generating circuit 21 during P1 between the expression first phase is during each of P4 between the fourth phase.

As shown in figure 23, among the P1, control signal S1 and S3 and S4 keep high level between the first phase, and control signal S2 keeps low level simultaneously.So on-off element SW1 and SW3 and SW4 change on-state into, on-off element SW2 keeps off-state simultaneously.Also promptly, as equivalent diagram in the part (a) of Figure 24, voltage INI is loaded the first electrode E1 to capacitor C2, and simultaneously, the voltage Vg of the second electrode E2 of capacitor C2 (electric current generates the gate terminal with transistor Tr A) is reduced to earthing potential Gnd.

Among the warp of the P1 second phase P2 later, control signal S3 changes low level between the first phase, simultaneously control signal S in addition keep with the first phase between the identical level of P1.So as the diagram of equivalence in the part (b) of Figure 24, on-off element SW3 changes off-state into,, stop the second electrode E2 is supplied with earthing potential Gnd by like this.Consequently, the voltage Vg of the second electrode E2, the earthing potential Gnd that sets since P1 between the first phase slowly rises, shown in the part (b) of Figure 23 and Figure 24, settle out having reached the stage that power supply potential Vdd and electric current generate with the difference (Vdd-Vth) between the threshold voltage vt h of transistor Tr A.Also promptly, among the second phase P2, the voltage Vg of the second electrode E2 is set as the magnitude of voltage corresponding to power supply potential Vdd and threshold voltage vt h.

Among the P3, control signal S4 changes low level into to the warp of second phase P2 between the third phase later, and control signal S in addition keeps the level identical with second phase P2 simultaneously.So as shown in the part (c) of Figure 24, SW4 changes off-state into by on-off element, generate the diode connection of using transistor Tr A and remove electric current.Among the P3, the voltage Vg of the second electrode E2 is maintained " Vdd-Vth " between the third phase.

Next, among the P4, control signal S1 changes low level into from high level to the warp of P3 between the fourth phase later between the third phase, and control signal S2 changes high level into from low level simultaneously.So, load the voltage of giving the first electrode E1 is varied to terminal T2 from the voltage VINI of terminal T1 voltage Vref.Between the fourth phase among the P4 because the second electrode E2 is in electric floating state, therefore because the capacitive coupling among the capacitor C2, the voltage Vg conversion of the second electrode E2 corresponding to the variation in voltage amount Δ V of the first electrode E1 (=VINI-Vref) level.More particularly, the variation in voltage amount of the second electrode E2, utilization generates with the grid capacitance of transistor Tr A and parasitic in its vicinity the coefficient k of electric capacity (be inserted with between electric current generates with the gate terminal of transistor Tr A and source terminal in the formation of maintenance electric capacity and also comprise the static capacity that keeps electric capacity) corresponding to electric current, shows as " k Δ V ".Also be, shown in the part (d) of Figure 24, between the fourth phase, among the P4, load to gate terminal by the voltage Vg after will changing (=Vdd-Vth-k Δ V), electric current generates and changes conducting state into transistor Tr A, flows through reference current Ir0 between its source terminal and the drain terminal.

If suppose between the fourth phase among the P4, electric current generates and moves under state of saturation with transistor Tr A, and then reference current Ir0 represents by following formula.

Ir0＝(β/2)·(Vgs-Vth) ²

Voltage Vgs in this formula is that electric current generates with the voltage between the gate-to-source of transistor Tr A.Now, because between the fourth phase, the voltage Vg of gate terminal is set as " Vdd-Vth-k Δ V ", so the voltage Vgs between the gate-to-source is represented as " Vdd-(Vdd-Vth-k Δ V) ".If bring this voltage Vgs into following formula and be out of shape, then derive following formula.

Ir0＝(B/2)·k·ΔV

Promptly, the reference current Ir0 in the present embodiment does not rely on electric current and generates threshold voltage vt h with transistor Tr A yet, and is set as the current value corresponding to the Δ V of the difference of voltage Vref and voltage VINI.So, generate the reference voltage V ref1 that is generated with transistor Tr B according to this reference current Ir0 by voltage, become the voltage of the error of the threshold voltage vt h that does not rely on electric current generation usefulness transistor Tr A.In addition, in the present embodiment, the coefficient k of decision reference current Ir0 depends on the electric capacity of capacitor C2.But, the easier control of error of the error ratio threshold voltage vt h of the electric capacity of the capacitor C2 among each unit circuit U.So,,, we can say also can be than existing technology more reliable and easily compensate the error of threshold voltage vt h by adopting present embodiment even consider the capacitance error of capacitor C2.

In the present embodiment, repeatedly carry out more new element discussed above (reference current Ir0 being set at the action of set-point), therefore even for example taken place in back to back interim Hb, also can return to desired value under the situation of variation because of noise etc. because of electric current generates with the voltage Vg of the gate terminal of transistor Tr A and reference voltage V refl.So, also can access the effect identical in the present embodiment with first embodiment.In addition, in the present embodiment, for carry out based on the setting of capacity coupled voltage Vg with and maintenance, and dual-purpose capacitor C1, therefore with for the setting of carrying out voltage Vg with and keep, and the formation that other capacitor is set is compared, and can dwindle the scale of circuit.

＜C-3: the variation of the 3rd embodiment 〉

In the 3rd embodiment, can add various variation.If the mode of texturing that illustration is concrete is then as described below.In addition, each following mode can appropriate combination be got up.

＜C-3-1: first variation 〉

Figure 25 is the circuit diagram of the formation of the unit circuit U in this variation of expression.As shown in the figure, the reference voltage generating circuit 21 among the unit circuit U of this variation except the key element of Figure 22, also includes on-off element SW5.This on-off element SW5 is inserted in electric current to generate between the second electrode E2 with the gate terminal of transistor Tr A and capacitor C2, the switch that the electrical connection of the two is controlled.On-off element SW5 if the control signal S5 that is supplied with by control circuit 30 is a high level, then becomes on-state, if this control signal S5 is a low level, then becomes off-state.

Next, Figure 26 is the sequential chart that is used for illustrating the action of the reference voltage generating circuit 21 in this variation.Also the same in this variation with the 3rd embodiment, in each period demand T, repeatedly carry out more new element.Period T comprises that P1 is to P5 between the fifth phase between the period P 0 and the first phase.Period P 0 is to be used for offset current to generate with during the error of the threshold voltage vt h of transistor Tr A during between the second phase P2, between the third phase P3 and between the fourth phase P4 (horizontal scan period) be used for during the actual generation reference current Ir0.Following contrast Figure 26 and Figure 27 describes the concrete action of reference voltage generating circuit 21.Figure 27 for expression each from period P 0 to P5 the fifth phase during, the circuit diagram that the equivalence of reference voltage generating circuit 21 constitutes.

As shown in figure 26, in the period P 0, control signal S1 and S3 become high level, and control signal S2, S4 and S5 become low level.So, shown in the part (a) of Figure 27, in the period P 0, generate after second electrode E2 electricity with the gate terminal of transistor Tr A and capacitor C2 disconnects at electric current, give the first electrode E1 on-load voltage VINI, simultaneously, give second electrode E2 loading earthing potential Gnd.Among the P0, electric current generates the voltage Vg with the gate terminal of transistor Tr A during this period, by the capacitive component beyond the capacitor C2 (for example electric current generates the grid capacitance with transistor Tr A), is maintained the voltage that terminal point loaded of P5 between the fifth phase.This voltage is to make electric current generate the voltage that is in conducting state with transistor Tr A.

And then between the first phase of period P 0 among the P1, as shown in figure 26, control signal S3 changes low level into, and control signal S5 changes high level into simultaneously.So, shown in the part (b) of Figure 27, stop the second electrode E2 is supplied with earthing potential Gnd, and the gate terminal that electric current generates with transistor Tr A is electrically connected with the second electrode E2 of capacitor C2.Because the second electrode E2 ground connection in the period P 0, therefore between the first phase among the P1, the electric current that is connected with the second electrode E2 generates the voltage Vg with the gate terminal of transistor Tr A, is changed to than magnitude of voltage low in the period P 0 (allowing electric current generate the magnitude of voltage that becomes conducting state with transistor Tr A).

In the second phase P2 that follows P1 between the first phase, shown in the part (c) of Figure 26 and Figure 27, control signal S4 changes high level into, and on-off element SW4 becomes on-state.Thereby, identical with the 3rd embodiment, voltage Vg, the magnitude of voltage that sets since P1 between the first phase slowly rises, and settles out having reached the stage that power supply potential Vdd and electric current generate with the difference (Vdd-Vth) between the threshold voltage vt h of transistor Tr A.In addition, among the P3, S4 changes low level into by control signal between the third phase of following second phase P2, generates the diode connection (part of Figure 27 (c)) of using transistor Tr A and remove electric current.

Among the P4, the same with the 3rd embodiment between the fourth phase, voltage that load to give the first electrode E1 changes in voltage Vref " Δ V " from voltage VINI, and by like this, the voltage Vg that electric current generates with the gate terminal of transistor Tr A changes " k Δ V ".So according to the reason identical with the 3rd embodiment, electric current generates between the source terminal and drain terminal of using transistor Tr A, shown in the part (d) of Figure 27, circulation does not rely on the reference current Ir0 of this threshold voltage vt h.

In P5 between the fifth phase behind the P4 between the fourth phase,, make the gate terminal of current control transistor TrA and second electrode E2 electricity disconnect by allowing control signal S5 keep low level.So the voltage Vg of gate terminal is maintained to the magnitude of voltage among the P4 between the fourth phase at the terminal point of period P 0.

As mentioned above, in this variation, it is all earth-free in during any that electric current generates gate terminal with transistor Tr A, so this electric current generates the state that can not become complete conducting with transistor Tr A.So, by adopting present embodiment, compare with the 3rd embodiment of the gate terminal ground connection of transistor Tr A with electric current generation among the P1 between the first phase, when being used for compensating the action of threshold voltage vt h, suppressed electric current and generated the electric current that flows with among the transistor Tr A, its result can reduce consumed power.In addition, use the gate terminal of transistor Tr A earth-free, therefore compare, have the voltage Vg that can shorten gate terminal and in second phase P2, reach this advantage of " Vdd-Vth " duration before with the 3rd embodiment because electric current generates.

＜C-3-2: second variation 〉

Among Figure 22 and Figure 25, illustration by the capacitive component beyond the capacitor C2 (for example electric current generates the grid capacitance with transistor Tr A), come holding current to generate the formation of the voltage Vg of the gate terminal of using transistor Tr A, but also can adopt the independent formation that is used for keeping this voltage Vg that is provided with.For example, the same with the capacitor C1 (Fig. 3) of first embodiment, outside capacitor C2, be inserted in electric current and generate with the gate terminal of transistor Tr A and the formation between the given wiring (for example power lead or ground wire) with being used for the capacitor of sustaining voltage Vg.

＜C-3-3: other variation 〉

In the present embodiment, also can suitably adopt and first embodiment and the identical variation of second embodiment.For example, among Figure 22 and Figure 25 illustration be provided with the formation of 1 reference voltage generating circuit 21 in each current output circuit 23, but also can adopt the formation that 1 reference voltage generating circuit 21 is connected with a plurality of current output circuits 23 (also i.e. constituting) by a plurality of current output circuit 23 common reference voltage generation circuits 21.In addition, also can with the reference voltage (or becoming its basic reference current) that is generated in a plurality of reference voltage generating circuits 21, export to the formation of current output circuit 23 selectively as Fig. 8 and shown in Figure 180.

＜D: other modes 〉

In each mode (each embodiment and variation thereof), except illustrated above, can also add various distortion.Concrete mode of texturing is as described below.

(1) changes the formation of image element circuit 40 arbitrarily.For example, in each above mode, illustration the image element circuit 40 of current programmed mode, but also can adopt magnitude of voltage, the image element circuit of the voltage-programming mode of the briliancy (gray scale) of control OLED element 41 corresponding to data-signal Xj.During this constitutes, for example, will be transformed into magnitude of voltage signal afterwards, export to each data lines 103 as data-signal Xj by the current value that the current/voltage translation circuit is exported the current output circuit 23 of each mode.

In addition, in each above mode, illustration will be used for controlling OLED element 41 on-off element (for example Tr1 to Tr4 of Fig. 2) be arranged on the electro-optical device of the active matrix mode in the image element circuit 40, but in image element circuit 40, do not have can use the present invention in the electro-optical device of passive matrix mode of these on-off elements yet.

In (2) first embodiments, illustration all carry out the more formation of new element among initialization period P INI and each interim Hb both sides, only in each interim Hb, carry out the more formation of new element but also can adopt.In addition, in each above mode, carrying out more, the moment of new element is not limited in initialization period P INI and interim Hb.Like this, among the present invention, so long as it is just enough repeatedly to carry out the formation of new element more.

(3) the illustrated mode of contrast Figure 20 also can be equally applicable to first embodiment and the 3rd embodiment.For example, in first embodiment, can adopt electric current to generate the reference current Ir0 (or image current Ir1) that is flowed with among the transistor T b, by export to the formation of data line 103 as data-signal Xj corresponding to the time density (pulse width) of gradation data D.For the 3rd embodiment too, also can adopt the electric current of Figure 22 to generate the reference current Ir0 that is flowed with among the transistor Tr A, by export to the formation of data line 103 as data-signal Xj corresponding to the time density (pulse width) of gradation data D.

(4) in Yi Shang each mode illustration use the electro-optical device 1 of OLED element 41, but in the electro-optical device that utilizes electrooptic element in addition, also can be suitable for the present invention.For example, display device at the display device of using inorganic EL element, electric field transmitted display (FED:Field EmissionDisplay), surface conduction type electron emission display device (SED:Surface-conductionElectron-emitter Display), ballistic electron emission display (B SD:Ballistic electronSurface emitting Display), use light emitting diode, or the writing in the first-class various electro-optical device of optical-write-in mode printer and electronic copier, also can be suitable for the present invention.

＜E: application examples 〉

Next, the e-machine that is suitable for associated electrical optical devices of the present invention is described.Figure 28 for expression with the associated electrical optical devices 1 of embodiment stereographic map as the formation of the portable personal computer of display device.Personal computer 2000 has electro-optical device 1 and main part 2010 as display device.In the main part 2010, be provided with power switch 2001 and keyboard 2002.Because this electro-optical device 1 uses OLED element 41, therefore can demonstrate the picture of watching easily at wide visual angle.

Among Figure 29, represented the formation of portable telephone of the associated electrical optical devices 1 of suitable embodiment.Portable telephone 3000 has a plurality of action buttons 3001 and scroll button 3002, and as the electro-optical device 1 of display device.By operation scroll button 3002, shown picture in the electro-optical device 1 that can roll.

Among Figure 30, shown the formation of the information carried terminal (PDA:Personal Digital Assitants) of the associated electrical optical devices 1 of suitable embodiment.Information carried terminal 4000 has a plurality of action buttons 4001 and power switch 4002, and as the electro-optical device 1 of display device.By operating power switch 4002, can be in electro-optical device 1 various information such as explicit address record and schedule.

In addition, be suitable for the e-machine of associated electrical optical devices of the present invention, except Figure 28 to shown in Figure 30, can also list digital camera, televisor, video camera, automobile navigation apparatus, pager, electronic notebook, Electronic Paper, counter, word processor, workstation, videophone, POS terminal, printer, scanner, duplicating machine, video player, have the machine of touch-screen etc.

Claims (27)

1. the driving circuit of an electro-optical device is a kind ofly to have corresponding to the data-signal of exporting to data line, and the driving circuit of the electro-optical device of the electrooptic element of control gray scale separately is characterized in that possessing:

The reference current that generates reference current generates mechanism; And

The signal output mechanism, it generates the data-signal that generates the current value of the reference current that mechanism generated corresponding to described reference current according to gradation data, exports to described data line,

Described reference current generates mechanism, repeatedly carries out the more new element that the current value of described reference current is made as set-point.

2. the driving circuit of electro-optical device as claimed in claim 1 is characterized in that,

Described reference current generates mechanism and comprises:

Transistor is used in compensation, and its first terminal is loaded voltage, is electrically connected between second terminal and the gate terminal;

Capacitance part, it keeps the voltage of described compensation with transistorized gate terminal; And

The voltage load maintainer, it is repeatedly carried out and will make described compensation load to the described more new element of described compensation with transistorized gate terminal with the forward voltage that transistor is in conducting state,

Generation is corresponding to the described reference current of the voltage that described capacitance part kept.

3. the driving circuit of electro-optical device as claimed in claim 2 is characterized in that,

Possess the mapping device of generation corresponding to the reference voltage of described reference current,

Described reference current generates mechanism, comprises that electric current generates to use transistor, and it loads to gate terminal by the voltage that will be kept in the described capacitance part, generates described reference current,

Described signal output mechanism according to gradation data, generates the data-signal corresponding to the reference voltage that described mapping device generated, and exports to described data line.

4. the driving circuit of electro-optical device as claimed in claim 3 is characterized in that,

Described mapping device comprises: current mirror circuit, and it generates with described electric current and generates with the corresponding image current of the reference current that transistor generated; And the mechanism of the corresponding described reference voltage of image current that generated of generation and described current mirror circuit.

5. as the driving circuit of each described electro-optical device in the claim 2～4, it is characterized in that,

Possess the comparison mechanism that described compensation is compared with the voltage and the given voltage of transistorized gate terminal,

Described voltage load maintainer, with corresponding moment of comparative result of described relatively mechanism, give described compensation with transistorized gate terminal loading forward voltage.

6. the driving circuit of electro-optical device as claimed in claim 5 is characterized in that,

Described given voltage is load to give the voltage of described compensation with transistorized the first terminal, and with described compensation with the voltage between transistorized threshold voltage and this voltage addition voltage afterwards.

7. the driving circuit of electro-optical device as claimed in claim 1 is characterized in that,

Described reference current generates mechanism and comprises:

Electric current generates and uses transistor, and it comprises gate terminal, the first terminal and second terminal; And

Capacitance part, it keeps the voltage of described electric current generation with transistorized gate terminal;

Described more new element comprises:

Compensating movement, it is by under described gate terminal and state that described the first terminal is electrically connected, load first voltage for described second terminal, generate with transistorized threshold voltage according value and the voltage of this gate terminal is set at corresponding to described first voltage and described electric current, and keep by described capacitance part; And

Generate action, it is by under the state of described gate terminal and the disconnection of described the first terminal electricity, load second voltage different for described second terminal, and between described the first terminal and described second terminal, produce and the corresponding described reference current of voltage that in described capacitance part, is kept by described compensating movement with described first voltage.

8. the driving circuit of electro-optical device as claimed in claim 7 is characterized in that,

Described compensating movement comprises:

First action, it by under described gate terminal and state that described the first terminal is electrically connected, loads described first voltage to described second terminal during the first, loads given voltage to described gate terminal simultaneously; And

Second action, it is in the second phase of following between the described first phase, still keep being electrically connected between described gate terminal and the described the first terminal, stop to load described given voltage to described gate terminal, by like this, the voltage of this gate terminal is set at corresponding to described first voltage and described electric current generates, and keep by described capacitance part with transistorized threshold voltage according value

Described generation action comprises:

The 3rd action, it disconnects described gate terminal and described the first terminal electricity in following between the third phase of the described second phase; And

The 4th action, its between the described third phase between the fourth phase later, by loading described second voltage for described second terminal, and between described the first terminal and described second terminal, produce and the corresponding described reference current of voltage that in described capacitance part, is kept by described second action.

9. as the driving circuit of claim 7 or 8 described electro-optical devices, it is characterized in that,

Described reference current generates mechanism, comprises that each gate terminal is connected a plurality of described electric current generation transistor in the described capacitance part jointly,

Described signal output mechanism, select described a plurality of electric current to generate corresponding to gradation data with the electric current generation transistor more than 1 in the transistor, with the summation of this electric current generation more than 1, export as data-signal with the electric current that is flowed between the first terminal in the transistor and second terminal.

10. the driving circuit of electro-optical device as claimed in claim 8 is characterized in that,

Described reference current generates mechanism, comprise voltage generation transistor, it is corresponding to the first terminal that has been loaded tertiary voltage and be connected the described reference current that is flowed between second terminal on the gate terminal, and the voltage of this gate terminal is set at reference voltage

Described signal output mechanism according to gradation data, generates corresponding to the data-signal of described voltage generation with the reference voltage of transistorized gate terminal, exports to described data line,

Described first action, comprise by described electric current being generated and being electrically connected with transistorized second terminal with described voltage generation with transistorized the first terminal, with the voltage of described electric current generation with transistorized gate terminal, be set at and described electric current generates with the described voltage of transistor AND gate and generates action with the corresponding described given voltage of the ratio of the conducting resistance between the transistor and described first voltage, described tertiary voltage

Described second action comprises by described electric current being generated with transistorized the first terminal and described voltage generating with the disconnection of transistorized second terminal electricity, stops the action of the loading of described given voltage.

11. the driving circuit as each described electro-optical device in the claim 8～10 is characterized in that,

The described second phase, be than the voltage of described electric current generation with transistorized gate terminal, the described given voltage that sets between the described first phase, change to described first voltage and described electric current generate with till the difference between the transistorized threshold voltage the time length during.

12. the driving circuit as each described electro-optical device in the claim 8～10 is characterized in that,

The described second phase, be than the voltage of described electric current generation with transistorized gate terminal, the described given voltage that sets between the described first phase, change to described first voltage and described electric current generate with till the difference between the transistorized threshold voltage the time long during.

13. the driving circuit of electro-optical device as claimed in claim 1 is characterized in that,

Comprise: electric current generates uses transistor, second terminal that it comprises gate terminal, the first terminal and is loaded given voltage; And

Capacitance part, it comprises first electrode and second electrode that is connected with transistorized gate terminal with described electric current generation,

Described more new element comprises:

Compensating movement, it is by having loaded under the state of first voltage for described first electrode, described electric current generation is electrically connected with the first terminal with transistorized gate terminal, loads corresponding to described given voltage and the transistorized threshold voltage according of described electric current generation for described second electrode; And

Generate action, it is by generating at described electric current under the state that disconnects with transistorized gate terminal and the first terminal electricity, make the change in voltage of described first electrode be second voltage different with described first voltage, make the voltage of described second electrode, begin to change from the voltage that described compensating movement, sets, at the described reference current that produces between described the first terminal and described second terminal corresponding to the voltage after this variation corresponding to the difference between described first voltage and described second voltage.

14. the driving circuit of electro-optical device as claimed in claim 13 is characterized in that,

Described compensating movement comprises:

First action, it by generating under the state that disconnects with transistorized gate terminal electricity at described second electrode and described electric current, loads described first voltage for described first electrode during the first, loads tertiary voltage for simultaneously described second electrode;

Second action, it stopped to load after the described tertiary voltage to described second electrode in the second phase of following between the described first phase, and described second electrode is connected with transistorized gate terminal with described electric current generation; And

The 3rd action, it is in following between the third phase of the described second phase, by being generated, described electric current couples together with transistorized gate terminal and the first terminal, the voltage of described second electrode is made as with described given voltage and described electric current generates with the corresponding voltage of transistorized threshold voltage

Described generation action comprises:

The 4th action, it generates described electric current with transistorized gate terminal and the disconnection of the first terminal electricity in then between the fourth phase between the third phase; And

The 5th the action, its between the fifth phase of following between the described fourth phase in, be described second voltage by the change in voltage that makes described first electrode, and between described the first terminal and described second terminal generation described reference current.

15. the driving circuit as each described electro-optical device in the claim 1～14 is characterized in that,

Possess and comprise that respectively described reference current generates a plurality of unit circuits of mechanism and described signal output mechanism.

16. the driving circuit as each described electro-optical device in the claim 1～14 is characterized in that,

Possess a plurality of described signal output mechanisms, it generates respectively with 1 described reference current and generates the corresponding data-signal of reference voltage that mechanism generated.

17. the driving circuit as each described electro-optical device in the claim 1～14 is characterized in that,

Possess: a plurality of described reference currents generate mechanism; And

Selection mechanism, it selects described a plurality of reference current to generate in the mechanism certain,

Described signal output mechanism according to gradation data, generates corresponding to the data-signal that generates the reference current that mechanism generated by the selected reference current of described selection mechanism, exports to described data line.

18. the driving circuit of electro-optical device as claimed in claim 17 is characterized in that,

Described a plurality of reference current generates each of mechanism, carries out more new element in the mutually different moment.

19. the driving circuit as each described electro-optical device in the claim 1～18 is characterized in that,

Described reference current generates mechanism, carries out more new element in during each is given.

20. the driving circuit as each described electro-optical device in the claim 1～19 is characterized in that,

Described reference current generates mechanism, the interim between horizontal scan period in succession, or in the interim between the vertical scanning period in succession, carry out more new element.

21. the driving circuit as each described electro-optical device in the claim 1～20 is characterized in that,

Described reference current generates mechanism, the moment before described signal output mechanism begins to move, with begin to move after the moment, carry out more new element.

22. an electro-optical device is characterized in that possessing,

A plurality of electrooptic elements corresponding to the data-signal control gray scale separately of exporting to data line; And

As each described driving circuit in the claim 1～21.

23. an e-machine is characterized in that,

Possesses the electro-optical device described in the claim 22.

24. the driving method of an electro-optical device is a kind ofly to possess: corresponding to the data-signal of exporting to data line, a plurality of electrooptic elements of control gray scale separately; The reference current that generates reference current generates mechanism; With according to gradation data, generate the data-signal that generates the current value of the reference current that mechanism generated corresponding to described reference current, and export to described data line the signal output mechanism, the driving method of electro-optical device, it is characterized in that,

Repeatedly carry out the more new element that the current value of described reference current is made as set-point.

25. the driving method of electro-optical device as claimed in claim 24 is characterized in that,

Described reference current generates mechanism and comprises:

Transistor is used in compensation, and its first terminal is loaded voltage, is electrically connected between second terminal and the gate terminal; And

Capacitance part, it keeps the voltage of described compensation with transistorized gate terminal,

Repeatedly carry out to make described compensation be in the forward voltage of conducting state with transistor, load and give the described more new element of described compensation with transistorized gate terminal, generation is corresponding to the described reference current of the voltage that described capacitance part kept.

26. the driving method of electro-optical device as claimed in claim 24 is characterized in that,

Described reference current generates mechanism and comprises:

Electric current generates and uses transistor, and it comprises gate terminal, the first terminal and second terminal; And

Capacitance part, it keeps the voltage of described electric current generation with transistorized gate terminal,

Described more new element comprises:

Compensating movement, it is by under described gate terminal and state that described the first terminal is electrically connected, load first voltage for described second terminal, generate with transistorized threshold voltage according value and the voltage of this gate terminal is set at corresponding to described first voltage and described electric current, and keep by described capacitance part; And

Generate action, it is by under the state of described gate terminal and the disconnection of described the first terminal electricity, load second voltage different for described second terminal, and between described the first terminal and described second terminal, produce and the corresponding described reference current of voltage that in described capacitance part, is kept by described compensating movement with described first voltage.

27. the driving method of electro-optical device as claimed in claim 24 is characterized in that,

Comprise: electric current generates uses transistor, second terminal that it comprises gate terminal, the first terminal and is loaded given voltage; And

Capacitance part, it has first electrode and generates second electrode that is connected with transistorized gate terminal with described electric current,

Described more new element comprises:

Compensating movement, it is by having loaded under the state of first voltage for described first electrode, described electric current generation is electrically connected with the first terminal with transistorized gate terminal, loads corresponding to described given voltage and the transistorized threshold voltage according of described electric current generation for described second electrode; And

Generate action, it is by generating at described electric current under the state that disconnects with transistorized gate terminal and the first terminal electricity, make the change in voltage of described first electrode be second voltage different with described first voltage, make the voltage of described second electrode, begin to change from the voltage that described compensating movement, sets, at the described reference current that produces between described the first terminal and described second terminal corresponding to the voltage after this variation corresponding to the difference between described first voltage and described second voltage.

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