TWI802078B - Pixel circuit and driving method - Google Patents

Abstract

A pixel circuit configured to generate a driving current to drive a light emitting element. The pixel circuit includes a first driving circuit, a second driving circuit and a regulator circuit. The first driving circuit includes a first driving transistor, a first capacitor and a first control circuit. The first driving circuit is configured to control pulse amplitude of the driving transistor. A first terminal of the first capacitor is electrically coupled to a gate terminal of the first driving transistor. The second driving circuit includes a second driving transistor, a second capacitor and a second control circuit. The second driving transistor is configured to control pulse width of the driving current. A first terminal of the second capacitor is electrically coupled to a gate terminal of the second driving transistor. The regulator circuit is electrically coupled to a second terminal of the first capacitor and a second terminal of the second capacitor. The regulator circuit is configured to stable the voltage levels of the first capacitor and the second capacitor.

Description

Pixel circuit and driving method

This case relates to a pixel circuit, in particular to a pixel circuit for driving a light-emitting element and its driving method.

In today's display technology, as the technology of the driving circuit gradually changes the gray scale of the light-emitting element by modulating the pulse width of the driving current, how to better control the pulse waveform of the driving current is an important issue in this field.

The disclosed document provides a pixel circuit for generating a driving current to drive a light emitting element to emit light, wherein the pixel circuit includes a first driving circuit, a second driving circuit and a voltage stabilizing circuit. The drive current flows from the system high voltage end and the first drive circuit to the system low voltage end. The first driving circuit includes a first driving transistor, a first capacitor and a first control circuit. The first driving transistor is electrically coupled between the system high voltage terminal and the system low voltage terminal for controlling the pulse amplitude of the driving current. One terminal of the first capacitor is electrically coupled to the gate terminal of the first driving transistor. The first control circuit is electrically coupled to the gate terminal of the first driving transistor for adjusting the potential of the gate terminal of the first driving transistor to control the pulse width of the driving current. The second driving circuit is electrically coupled to the first driving circuit. The second driving circuit includes a second driving transistor, a second capacitor and a second control circuit. The first terminal of the second capacitor is electrically coupled to the gate terminal of the second driving transistor. The second control circuit is electrically coupled to the gate terminal of the second driving transistor, and the second control circuit is used for adjusting the potential of the gate terminal of the second driving transistor to control the pulse width of the driving current. The voltage stabilizing circuit is electrically coupled to the second terminal of the first capacitor and the second terminal of the second capacitor, and the voltage stabilizing circuit is used for stabilizing the potentials of the first capacitor and the second capacitor.

A driving method for driving pixel circuits. The pixel circuit is used for generating driving current to drive the light emitting element to emit light. The pixel circuit includes a first driving circuit, a second driving circuit and a voltage stabilizing circuit. The first driving circuit is used for controlling the pulse amplitude of the driving current. The first driving circuit includes a first driving transistor and a first capacitor. The first terminal of the first capacitor is electrically coupled to the gate terminal of the first driving transistor. The second terminal of the first capacitor is electrically coupled to the voltage stabilizing circuit. Wherein the second driving circuit is used to control the pulse width of the driving current. The second driving circuit includes a second driving transistor and a second capacitor. The first terminal of the second capacitor is electrically coupled to the gate terminal of the second driving transistor. The second terminal of the second capacitor is electrically coupled to the voltage stabilizing circuit. The driving method includes the following steps. When the potential of the gate terminal of the second driving transistor is reset, the voltage of the system voltage terminal is transmitted to the second terminal of the second capacitor by the voltage stabilizing circuit; when the potential of the gate terminal of the first driving transistor is reset, the voltage of the stabilizing circuit is The piezoelectric circuit transmits the voltage of the system voltage terminal to the second terminal of the first capacitor.

To sum up, the disclosed document uses a voltage stabilizing circuit to stabilize the voltage of the first capacitor in the first driving circuit and the second capacitor in the second driving circuit, thereby enhancing the ability to control the pulse waveform of the driving current, and further Enhanced low-grayscale control.

The following is a detailed description of the embodiments in conjunction with the attached drawings, but the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structure and operation is not intended to limit the execution sequence. Any recombination of components Structures and devices with equivalent functions are all within the scope of this disclosure. In addition, the illustrations are for illustration purposes only and are not drawn in original size. To facilitate understanding, the same elements or similar elements will be described with the same symbols in the following description.

The terms (terms) used throughout the specification and claims, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the disclosed content and in the special content.

In addition, the words "comprising", "including", "having", "containing", etc. used in this article are all open terms, meaning "including but not limited to". In addition, "and/or" used herein includes any one and all combinations of one or more items in the relevant listed items.

Herein, when an element is referred to as "coupled" or "connected", it may mean "electrically coupled" or "electrically connected". "Coupled" or "connected" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as "first", "second", ..., etc. are used herein to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms.

Please refer to FIG. 1 , which is a functional block diagram of a pixel circuit 100 according to some embodiments of the present disclosure. As shown in Figure 1, the pixel circuit 100 includes a first driving circuit 110, a second driving circuit 120, a reset circuit 130, a voltage stabilizing circuit 140, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T10. Transistor T12. During the light-emitting period of the pixel circuit 100, the driving current for driving the light-emitting element L1 flows from the system high voltage terminal VDD, the tenth transistor T10, the first driving transistor TD1, the twelfth transistor T12, and the light-emitting element L1. To the system low voltage terminal VSS.

Functionally, the first driving circuit 110 is used to control the pulse width of the driving current, and the second driving circuit 120 is used to control the pulse width of the driving current. How the first driving circuit 110 and the second driving circuit 120 control the pulse amplitude and pulse width of the driving current will be described in detail in subsequent embodiments.

The first driving circuit 110 includes a first driving transistor TD1 , a first control circuit 112 and a first capacitor C1 . The first driving transistor TD1 is electrically coupled between the system high voltage terminal VDD and the system low voltage terminal VSS.

In detail, the first end of the tenth transistor T10 is electrically coupled to the system high voltage terminal VDD, the second end of the tenth transistor T10 is electrically coupled to the first end of the first drive transistor TD1, and the tenth transistor T10 is electrically coupled to the first end of the first drive transistor TD1. The gate terminal of the crystal T10 is used for receiving the second light emission control signal EM2[n].

The first end of the first driving transistor TD1 is electrically coupled to the second end of the tenth transistor T10, and the second end of the first driving transistor TD1 is electrically coupled to the first end of the twelfth transistor T12. A gate terminal of a driving transistor TD1 is electrically coupled to the first terminal of the first capacitor C1 and the first control circuit 112 . Functionally, the first control circuit 112 is used to adjust the potential of the gate terminal of the first driving transistor TD1 , so that the first driving transistor TD1 controls the pulse width of the driving current according to the potential of the gate terminal of the first driving transistor TD1 .

The first end of the twelfth transistor T12 is electrically coupled to the second end of the first drive transistor TD1, the second end of the twelfth transistor T12 is electrically coupled to the first end of the light emitting element L1, and the twelfth transistor T12 is electrically coupled to the first end of the light emitting element L1. The gate terminal of the transistor T12 is used for receiving the first light emission control signal EM1[n]. The second end of the light emitting element L1 is electrically coupled to the system low voltage end VSS.

The second driving circuit 120 includes a second driving transistor TD2, a second control circuit 122 and a second capacitor C2. The first terminal of the second driving transistor TD2 is electrically coupled to the gate terminal of the first driving transistor TD1, and the second terminal of the second driving transistor TD2 is electrically coupled to the second terminal of the eleventh transistor T11. Gate terminals of the two driving transistors TD2 are electrically coupled to the first terminal of the second capacitor C2 and the second control circuit 122 . Functionally, the second control circuit 122 is used to adjust the potential of the gate terminal of the second driving transistor TD2, so that the second driving transistor TD2 controls the pulse width of the driving current according to the potential of the gate terminal of the second driving transistor TD2.

The first end of the eleventh transistor T11 is electrically coupled to the voltage stabilizing circuit 140, the second end of the eleventh transistor T11 is electrically coupled to the second end of the second driving transistor TD2, and the eleventh transistor T11 The gate terminal of is used for receiving the first light emission control signal EM1[n].

The reset circuit 130 is electrically coupled to the gate terminal of the first driving transistor TD1 and the gate terminal of the second driving transistor TD2 . The reset circuit 130 is used for resetting the potential of the gate terminal of the first driving transistor TD1 and for resetting the potential of the gate terminal of the second driving transistor TD2 .

The voltage stabilizing circuit 140 is electrically coupled to the second end of the first capacitor C1 and the second end of the second capacitor C2. The voltage stabilizing circuit 140 is used for stabilizing the potential of the second terminal of the first capacitor C1, and for stabilizing the potential of the second terminal of the second capacitor C2.

Please refer to FIG. 2 . FIG. 2 is a circuit structure diagram of a pixel circuit 100 a according to some embodiments of the present disclosure. As shown in FIG. 2 , the first control circuit 112 includes an eighth transistor T8 and a ninth transistor T9 . The second control circuit 122 includes a fifth transistor T5 and a sixth transistor T6. The reset circuit 130 includes a fourth transistor T4 and a seventh transistor T7. The voltage stabilizing circuit 140 includes a first transistor T1 , a second transistor T2 and a third transistor T3 .

In detail, the first end of the eighth transistor T8 is electrically coupled to the second end of the first driving transistor TD1, and the second end of the eighth transistor T8 is electrically coupled to the gate terminal of the first driving transistor TD1. , the gate terminal of the eighth transistor T8 is used to receive the fourth control signal G4[n]. The first terminal of the ninth transistor T9 is electrically coupled to the first terminal of the first drive transistor TD1, the second terminal of the ninth transistor T9 is used to receive the second data signal DATA_PAM, and the gate terminal of the ninth transistor T9 For receiving the fourth control signal G4[n].

The first end of the fifth transistor T5 is electrically coupled to the first end of the second driving transistor TD2, the second end of the fifth transistor T5 is electrically coupled to the first end of the second capacitor C2, and the fifth transistor T5 The gate terminal of T5 is used for receiving the second control signal G2[n]. The first end of the sixth transistor T6 is electrically coupled to the second end of the second driving transistor TD2, the second end of the sixth transistor T6 is used to receive the first data signal DATAPWM[m], the sixth transistor T6 The gate terminal of is used to receive the second control signal G2[n].

The first terminal of the fourth transistor T4 is electrically coupled to the first terminal of the second capacitor C2 and the gate terminal of the second driving transistor TD2, the fourth transistor The second terminal of the transistor T4 is used for receiving the reset signal RES, and the gate terminal of the fourth transistor T4 is used for receiving the first control signal G1[n]. The first terminal of the seventh transistor T7 is electrically coupled to the gate terminal of the first driving transistor TD1 and the first terminal of the first capacitor C1. The second terminal of the seventh transistor T7 is used to receive the reset signal RES. The gate terminal of the seven-transistor T7 is used for receiving the third control signal G3[n].

The first terminal of the first transistor T1 is electrically coupled to the second terminal of the second capacitor C2, the second terminal of the first transistor T1 is electrically coupled to the system voltage terminal PPO, and the gate terminal of the first transistor T1 is used for Receive the first voltage regulation control signal VSET1[n]. The first terminal of the second transistor T2 is electrically coupled to the second terminal of the first capacitor C1, the second terminal of the second transistor T2 is electrically coupled to the system voltage terminal PPO, and the gate terminal of the second transistor T2 is used for Receive the second voltage regulation control signal VSET2[n].

It should be noted that, in some embodiments, the potential of the system voltage terminal PPO can be understood as a cut-off voltage, which has a logic level for turning off the first driving transistor TD1 . For example, if the first driving transistor TD1 is implemented by PMOS, the potential of the system voltage terminal PPO is at a high logic level. In some embodiments, the potential of the system voltage terminal PPO may be slightly greater than the potential of the system high voltage terminal VDD. In some other embodiments, under the corresponding circuit structure, the potential of the system voltage terminal PPO can be understood as a turn-on voltage, which has a logic level to turn on the first driving transistor TD1. Therefore, this case is not limited to this.

The first terminal of the third transistor T3 is electrically coupled to the system high voltage terminal VDD, and the second terminal of the third transistor T3 is electrically coupled to the first capacitor C1. The second terminal, the gate terminal of the third transistor T3, is used for receiving the first light emission control signal EM1[n].

FIG. 3 is a timing diagram of the control signals of the pixel circuit 100 a in FIG. 2 in the signal setting period SWP and the light emitting period EMP according to some embodiments of the present disclosure. As shown in FIG. 3 , a display period in the control sequence of the pixel circuit 100 a can be divided into two periods, which are the signal setting period SWP and the light emitting period EMP respectively. The signal setting period SWP can be divided into four periods, which are reset periods P1 and P3 and setting periods P2 and P4 respectively. It should be noted that the time lengths of the periods in FIG. 3 are only for example, and are not intended to limit the disclosed document.

Specifically, the first control signal G1[n] has a first logic level (for example, a low logic level) during the reset period P1; the first control signal G1[n] has a first logic level during the reset period P3, the set period P2 and P4 and the light-emitting period EMP have a second logic level (for example, a high logic level). The second control signal G2[n] has a first logic level during the setting period P2; the second control signal G2[n] has a second logic level during the reset periods P1 and P3, the setting period P4 and the light emitting period EMP.

The third control signal G3[n] has a first logic level during the reset period P3; the third control signal G3[n] has a second logic level during the reset period P1, the set periods P2 and P4, and the light emitting period EMP. The fourth control signal G4[n] has a first logic level during the setting period P4; the fourth control signal G4[n] has a second logic level during the reset periods P1 and P3, the setting period P2 and the light emitting period EMP.

The first voltage stabilization control signal VSET1[n] and the second voltage stabilization control signal VSET2[n] have a first logic level during the signal setting period SWP. In other words, the first voltage stabilization control signal VSET1[n] and the second voltage stabilization control signal VSET2[n] have the first logic level during the reset period P1 and P3 and the setup period P2 and P4. The first voltage stabilization control signal VSET1[n] and the second voltage stabilization control signal VSET2[n] have a second logic level during the light emitting period EMP.

The first light-emitting control signal EM1[n] and the second light-emitting control signal EM2[n] have the first logic level during the light-emitting period EMP, and the first light-emitting control signal EM1[n] and the second light-emitting control signal EM2[n] During the signal setting period, SWP has a second logic level.

The sweep signal SWEEP[n] has a second logic level during the signal setting period SWP. During the light-emitting period, the voltage of the EMP sweep signal SWEEP[n] gradually drops from a high logic level to a low logic level, and at the end of the light-emitting period, the voltage of the sweep signal SWEEP[n] is pulled back from a low logic level High logic level, thereby forming a ramp voltage.

In order to make the overall operation of the pixel circuit 100 clearer and easier to understand, please refer to FIGS. 1-4E below. FIG. 4A is a schematic diagram of the reset period P1 in the signal setting period SWP of the pixel circuit 100 according to some embodiments of the present disclosure. FIG. 4B is a schematic diagram of a setting period P2 of the pixel circuit 100 in the signal setting period SWP according to some embodiments of the present disclosure. FIG. 4C is a schematic diagram of the reset period P3 in the signal setting period SWP of the pixel circuit 100 according to some embodiments of the present disclosure. FIG. 4D shows the signal setting of the pixel circuit 100 according to some embodiments of the present disclosure. A schematic diagram of the setting period P4 in the period SWP. FIG. 4E is a schematic diagram of EMP of the pixel circuit 100 during the light emitting period according to some embodiments of the present disclosure.

During the reset period P1, since the first control signal G1[n], the first voltage regulation control signal VSET1[n] and the second voltage regulation control signal VSET2[n] have a low logic level, the first transistor T1, The second transistor T2 and the fourth transistor T4 are turned on. On the other hand, due to the second control signal G2[n], the third control signal G3[n], the fourth control signal G4[n], the first light emission control signal EM1[n] and the second light emission control signal EM2[n ] has a high logic level, so the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, The eleventh transistor T11 and the twelfth transistor T12 are turned off.

Specifically, during the reset period P1, the reset signal RES will be transmitted to the gate terminal of the second driving transistor TD2 and the first terminal of the second capacitor C2 through the fourth transistor T4 to reset the second driving transistor The potential of the gate terminal of TD2, and the voltage of the system voltage terminal PPO is transmitted to the second terminal of the second capacitor C2 through the first transistor T1, thereby stabilizing the potential of the second capacitor C2. Furthermore, the voltage of the system voltage terminal PPO is transmitted to the second terminal of the first capacitor C1 through the first transistor T1, thereby stabilizing the potential of the first capacitor C1.

During the setting period P2, since the second control signal G2[n], the first voltage stabilization control signal VSET1[n] and the second voltage stabilization control signal VSET2[n] have a low logic level, the first transistor T1, the second transistor T1 two The transistor T2, the fifth transistor T5 and the sixth transistor T6 are turned on. On the other hand, due to the first control signal G1[n], the third control signal G3[n], the fourth control signal G4[n], the first light emission control signal EM1[n] and the second light emission control signal EM2[n ] has a high logic level, so the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 And the twelfth transistor T12 will be turned off.

Specifically, during the setting period P2, the first data signal DATAPWM[m] is transmitted to the gate terminal of the second driving transistor TD2 and the second transistor T5 through the sixth transistor T6, the second driving transistor TD2 and the fifth transistor T5. The first end of the capacitor C2 until the second driving transistor TD2 is cut off. In order to perform compensation operations and data setting operations. At this time, the voltage of the system voltage terminal PPO is transmitted to the second terminal of the second capacitor C2 through the first transistor T1, thereby stabilizing the potential of the second capacitor C2.

During the reset period P3, since the third control signal G3[n], the first voltage regulation control signal VSET1[n] and the second voltage regulation control signal VSET2[n] have a low logic level, the first transistor T1, The second transistor T2 and the seventh transistor T7 are turned on. On the other hand, due to the first control signal G1[n], the second control signal G2[n], the fourth control signal G4[n], the first light emission control signal EM1[n] and the second light emission control signal EM2[n ] has a high logic level, so the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, The eleventh transistor T11 and the twelfth transistor T12 are turned off.

Specifically, during the reset period P3, the reset signal RES will be transmitted to the gate terminal of the first driving transistor TD1 and the first terminal of the first capacitor C1 through the seventh transistor T7 to reset the first driving transistor The potential of the gate terminal of TD1, and the voltage of the system voltage terminal PPO is transmitted to the second terminal of the first capacitor C1 through the second transistor T2, thereby stabilizing the potential of the first capacitor C1. Furthermore, the voltage of the system voltage terminal PPO is transmitted to the second terminal of the second capacitor C2 through the first transistor T1, thereby stabilizing the potential of the second capacitor C2.

During the setting period P4, since the fourth control signal G4[n], the first voltage stabilization control signal VSET1[n] and the second voltage stabilization control signal VSET2[n] have a low logic level, the first transistor T1, the second transistor T1 The second transistor T2, the eighth transistor T8 and the ninth transistor T9 are turned on. On the other hand, due to the first control signal G1[n], the second control signal G2[n], the third control signal G3[n], the first light emission control signal EM1[n] and the second light emission control signal EM2[n ] has a high logic level, so the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 And the twelfth transistor T12 will be turned off.

Specifically, during the setting period P4, the second data signal DATA_PAM is transmitted to the gate terminal of the first driving transistor TD1 and the terminal of the first capacitor C1 through the ninth transistor T9, the first driving transistor TD1, and the eighth transistor T8. The first end until the first driving transistor TD1 is cut off. In order to perform compensation operations and data setting operations. At this time, the system The voltage of the voltage terminal PPO is transmitted to the second terminal of the first capacitor C1 through the second transistor T2, thereby stabilizing the potential of the first capacitor C1.

During the light-emitting period EMP, since the first light-emitting control signal EM1[n] and the second light-emitting control signal EM2[n] have a low logic level, the third transistor T3, the tenth transistor T10, the eleventh transistor T11 and the The twelfth transistor T12 is turned on. On the other hand, due to the first control signal G1[n], the second control signal G2[n], the third control signal G3[n], the fourth control signal G4[n], the first voltage regulation control signal VSET1[n ] and the second voltage regulation control signal VSET2[n] have a high logic level, so the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the The seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

Specifically, during the light emitting period EMP, the driving current flows from the system high voltage terminal VDD to the system low voltage terminal VSS via the tenth transistor T10 , the first driving transistor TD1 , the twelfth transistor T12 and the light emitting element L1 . The pulse amplitude of the driving current is adjusted by the first driving transistor TD1 according to the potential of its gate terminal. The potential of the gate terminal of the first driving transistor TD1 is determined according to the voltage of the second data signal DATA_PAM received in the setting period P3. The detailed operation of setting the potential of the gate terminal of the first driving transistor TD1 has been described in the previous paragraphs, and will not be repeated here.

At this time, the voltage of the system high voltage terminal VDD is transmitted to the second terminal of the first capacitor C1 through the third transistor T3, thereby stabilizing the potential of the first capacitor C1.

Moreover, during the light emitting period EMP, the frequency sweep signal SWEEP[n] will gradually pull down the potential of the second terminal of the second capacitor C2. At this time, through capacitive coupling, the potentials of the first terminal of the second capacitor C2 and the gate terminal of the second driving transistor TD2 will also be gradually pulled down, and according to the first potential received by the second driving circuit 120 in the setting period P2 The voltage of the data signal DATAPWM[m] determines the turn-on time point of the second driving transistor TD2. When the second drive transistor TD2 is turned on, the voltage of the system voltage terminal PPO will be transmitted to the gate terminal of the first drive transistor TD1 through the eleventh transistor T11 and the second drive transistor TD2, so that the first drive transistor TD1 off, thereby controlling the pulse width of the drive current.

It should be noted that during the light-emitting period EMP, since the second voltage-stabilizing control signal VSET2[n] has a high logic level, the second transistor T2 in the voltage-stabilizing circuit 140 will be turned off, thereby achieving The system voltage terminal PPO is electrically isolated from the second terminal of the first capacitor C1. In this way, during the light-emitting period EMP, the pixel circuit 100a does not use the voltage of the system voltage terminal PPO to perform a voltage stabilizing operation on the first capacitor C1.

On the other hand, in the signal setting period SWP, since the second voltage stabilization control signal VSET2[n] has a low logic level, the second transistor T2 in the voltage stabilization circuit 140 is turned on, so as to connect the system voltage terminal PPO to the first The circuit path of the second end of a capacitor C1 is turned on. In this way, during the signal setting period SWP, the pixel circuit 100a can use the voltage of the system voltage terminal PPO to perform a voltage stabilization operation on the first capacitor C1, so as to reduce the switching of the control signal of the pixel circuit 100a or the reception of the pixel circuit 100a. The influence of the signal on the potential of the first capacitor C1 thereby stabilizes the potential of the gate terminal of the first driving transistor TD1.

Therefore, under the architecture of the pixel circuit 100a having the second transistor T2 in the voltage stabilizing circuit 140, the first driving circuit 110 can more accurately control the gate terminal of the first driving transistor TD1 and the second transistor of the first capacitor C1. The potential at one end strengthens the control over the pulse width of the driving current, thereby better controlling the luminous intensity of the light-emitting element L1, so as to increase the uniformity of the display.

Similarly, during the light-emitting period EMP, since the first voltage-stabilizing control signal VSET1[n] has a high logic level, the first transistor T1 in the voltage-stabilizing circuit 140 will be turned off, so that the system will be turned off during the light-emitting period EMP. The voltage terminal PPO is electrically isolated from the second terminal of the second capacitor C2. In this way, during the light-emitting period EMP, the pixel circuit 100a does not use the voltage of the system voltage terminal PPO to perform a voltage stabilizing operation on the second capacitor C2.

Moreover, in the signal setting period SWP, since the first voltage stabilization control signal VSET1[n] has a low logic level, the first transistor T1 in the voltage stabilization circuit 140 is turned on to connect the system voltage terminal PPO to the second capacitor The circuit path of the second end of C2 is turned on. In this way, during the signal setting period SWP, the pixel circuit 100a can use the voltage of the system voltage terminal PPO to perform a voltage stabilization operation on the second capacitor C2, so as to reduce the switching of the control signal of the pixel circuit 100a or the reception of the pixel circuit 100a. The influence of the signal on the potential of the second capacitor C2, thereby stabilizing the potential of the gate terminal of the second driving transistor TD2.

Therefore, under the architecture of the pixel circuit 100a having the first transistor T1 in the voltage stabilizing circuit 140, the second driving circuit 120 can more accurately control the gate terminal of the second driving transistor TD2 and the first transistor of the second capacitor C2. The potential at one end strengthens the control over the pulse width of the driving current, thereby better controlling the gray scale of the light-emitting element L1, so as to increase the uniformity of the display.

For a better understanding of the control signal and driving current in the pixel circuit 100a, please refer to FIGS. 5A to 5E. FIG. 5A is a waveform diagram of the driving current Id of the pixel circuit 100a according to some embodiments of the present disclosure. 5B-5D are waveform diagrams of control signals of the pixel circuit 100a according to some embodiments of the present disclosure. FIG. 5E is a waveform diagram of the light emission control signal and the frequency sweep signal SWEEP[n] of the pixel circuit 100a according to some embodiments of the present disclosure.

As shown in FIGS. 5A to 5D , the pulse width of the driving current Id is determined by the voltage of the second data signal DATA_PAM received by the first driving circuit 110 according to the fourth control signal G4[n]. The pulse width of the driving current Id is determined by the voltage of the first data signal DATAPWM[m] received by the second driving circuit 120 according to the second control signal G2[n].

Moreover, when the second driving circuit 120 performs a reset operation according to the first control signal G1[n] and a write operation according to the second control signal G2[n], the first voltage stabilization control signal VSET1[n] has a low logic. level, thereby stabilizing the potential of the second capacitor C2 in the second driving circuit 120 and the gate terminal of the second driving transistor TD2.

Similarly, when the first driving circuit 110 performs a reset operation according to the third control signal G3[n] and performs a write operation according to the fourth control signal G4[n], the second voltage regulation control signal VSET2[n] has a low voltage. logic level, thereby stabilizing the potentials of the first capacitor C1 in the first driving circuit 110 and the gate terminal of the first driving transistor TD1.

As shown in Figure 5E, the first light emission control signal EM1[n] can be provided by a shift circuit in the driver of the display, and the second light emission control signal EM2[n] is different from the first light emission control signal EM1 [n] square wave signal. In some embodiments, an external circuit may provide a square wave signal as the second light emission control signal EM2[n]. However, the present disclosure is not limited thereto, and in some embodiments, a square wave signal may also be provided by an internal circuit as the second light emission control signal EM2[n].

Since the pixel circuit 100a determines the time point when the driving current starts to be generated by whether the tenth transistor T10 electrically coupled to the current path of the driving current is turned on or not. Therefore, compared with the first light emission control signal EM1 [n], the second light emission control signal EM2 [n] implemented by using the square wave signal can turn on the tenth transistor T10 more directly and quickly. In this way, the rising edge of the driving current Id can be better controlled.

In the above-mentioned embodiments, the first driving circuit 110 is electrically coupled to the current path of the driving current, while the second driving circuit 120 is not electrically coupled to the current path of the driving current. Therefore, in the pixel circuit 100 , the second driving circuit 120 controls the first driving circuit 110 to determine the pulse width of the driving current. In some other embodiments, the circuit architecture of the pixel circuit can be implemented in other architectures, and the same effects as in this case can also be achieved by cooperating with the reset circuit 130 and the voltage stabilizing circuit 140 .

In some embodiments, both the pulse amplitude modulation circuit and the pulse width modulation circuit in the pixel circuit can be electrically coupled to the current path of the driving current. Specifically, the pulse width modulation circuit further includes a cut-off transistor (or switching transistor) electrically coupled to the current path of the driving current, and the driving transistor in the pulse width modulation circuit is electrically coupled to Connected between the system voltage terminal and the gate terminal of the cut-off transistor, the control circuit in the pulse width modulation circuit can control the driving transistor to conduct the circuit path from the system voltage terminal to the gate terminal of the cut-off transistor, so as to change the cut-off voltage The state of the crystal, so that the conduction state of the current path of the driving current is controlled by the cut-off transistor, and then the pulse width of the driving current is controlled. Under such a circuit structure, the circuit structure of the voltage stabilizing circuit 140 can also be used to stabilize the voltage of the capacitor in the pulse width modulation circuit during the signal setting period. capacitor for voltage regulation. Therefore, the waveform of the driving current can be better controlled, and thus the brightness of the light-emitting element in the gray scale can be better controlled.

FIG. 6 is a timing diagram of control signals of the pixel circuit 100 a in FIG. 2 in the signal setting period SWP and the light emitting period EMP according to some embodiments of the present disclosure. As shown in FIG. 6 , a display period in the control sequence of the pixel circuit 100 a can be divided into two periods, which are the signal setting period SWP and the light emitting period EMP respectively. The signal setting period SWP can be divided into four periods, which are reset periods P1 and P3 and setting periods P2 and P4 respectively. It should be noted that the time lengths of the periods in FIG. 6 are just examples, and are not intended to limit the disclosed document.

Compared with the timing sequence of the control signal in the embodiment of FIG. 3, the difference of the control signal in the embodiment of FIG. 6 is that the first voltage regulation control signal VSET1[n] is different from the second voltage regulation control signal VSET1[n] Signal VSET2[n]. More precisely, the first voltage stabilization control signal VSET1[n] shown in FIG. 6 has a low logic level during the reset period P1 and the set period P2 of the second driving circuit 120, so as to turn on the second capacitor C2. A circuit path from the second terminal to the system voltage terminal PPO, so as to stabilize the potential of the second capacitor C2. On the other hand, the first voltage stabilization control signal VSET1[n] has a high logic level during the reset period P3 and the set period P4 of the first driving circuit 110, so as to electrically isolate the second terminal of the second capacitor C2 from the system voltage. Terminal PPO. Similarly, the second voltage stabilization control signal VSET2[n] shown in FIG. 6 has a high logic level during the reset period P1 and the set period P2 of the second driving circuit 120, so as to electrically isolate the first capacitor C1. The second terminal and the system voltage terminal PPO. On the other hand, the second voltage stabilization control signal VSET2[n] has a low logic level during the reset period P3 and the set period P4 of the first driving circuit 110, so as to conduct the second terminal of the first capacitor C1 to the system voltage terminal PPO. circuit path, thereby stabilizing the potential of the second capacitor C2. Other detailed waveforms and action modes of the control signal in FIG. 6 are roughly the same as those of the control signal in the previous embodiment shown in FIG. 3 , and will not be repeated here.

FIG. 7 is a circuit structure diagram of the pixel circuit 100b in FIG. 1 according to some embodiments of the present disclosure. As shown in Figure 7, the pixel circuit 100b includes a first drive transistor TD1, a first capacitor C1, a first control circuit 112, a second drive transistor TD2, a second capacitor C2, a second control circuit 122, a reset The circuit 130 , the voltage stabilizing circuit 140 , the tenth transistor T10 , the eleventh transistor T11 and the twelfth transistor T12 . The first control circuit 112 includes an eighth transistor T8 and a ninth transistor T9. The second control circuit 122 includes a fifth transistor T5 and a sixth transistor T6. The reset circuit 130 includes a fourth transistor T4 and a seventh transistor T7. The voltage stabilizing circuit 140 includes a first transistor T1 , a second transistor T2 and a third transistor T3 .

Compared with the pixel circuit 100a in the embodiment of FIG. 2 , the difference of the pixel circuit 100b in the embodiment of FIG. 7 lies in the respective operation modes of the fourth transistor T4 and the seventh transistor T7 It is realized by the function similar to a diode. More precisely, both the gate terminal and the second terminal of the fourth transistor T4 shown in FIG. 7 are used to receive the first control signal G1[n], so when the first control signal G1[n] has a low logic level, the fourth transistor T4 is turned on and transmits the first control signal G1[n] with a low logic level to the first terminal of the second capacitor C2 and the gate terminal of the second driving transistor TD2 to reset Gate terminal of the second driving transistor TD2. On the other hand, when the first control signal G1 [n] has a high logic level, the fourth transistor T4 is turned off to end the reset operation.

Similarly, the gate terminal and the second terminal of the seventh transistor T7 shown in FIG. 7 are used to receive the third control signal G3[n], so when the third control signal G3[n] has a low logic bit On time, the seventh transistor T7 is turned on and transmits the third control signal G3[n] having a low logic level to the first terminal of the first capacitor C1 and the gate terminal of the first driving transistor TD1 to reset the first Gate terminal of drive transistor TD1. On the other hand, when the third control signal G3[n] has a high logic level, the seventh transistor T7 is turned off to end the reset operation. The connection relationship and operation mode of other details of the pixel circuit 100b are roughly the same as those of the pixel circuit 100a in the previous embodiment shown in FIG. 2 , and will not be repeated here.

FIG. 8 is a circuit structure diagram of the pixel circuit 100c in FIG. 1 according to some embodiments of the present disclosure. As shown in Figure 8, the pixel circuit 100c includes a first drive transistor TD1, a first capacitor C1, a first control circuit 112, a second drive transistor TD2, a second capacitor C2, a second control circuit 122, a reset The circuit 130 , the voltage stabilizing circuit 140 , the tenth transistor T10 , the eleventh transistor T11 and the twelfth transistor T12 . The first control circuit 112 includes an eighth transistor T8 and a ninth transistor T9. The second control circuit 122 includes a fifth transistor T5 and a sixth transistor T6. The reset circuit 130 includes a seventh transistor T7. The voltage stabilizing circuit 140 includes a first transistor T1 , a second transistor T2 and a third transistor T3 .

Compared with the pixel circuit 100b in the embodiment of FIG. 7, the pixel circuit 100c in the embodiment of FIG. 8 is different in that it does not have the fourth transistor T4, and replaces the seventh transistor T7. The signal received by the gate terminal. More precisely, both the gate terminal and the second terminal of the seventh transistor T7 shown in FIG. 8 are used to receive the reset control signal RES[n]. For easier understanding, please refer to FIG. 9. FIG. 9 is a timing diagram of control signals of the pixel circuit 100c in FIG. 8 in the signal setting period SWP and the light emitting period according to some embodiments of the present disclosure. As shown in FIG. 8, a display period in the control sequence of the pixel circuit 100c can be divided into two periods, which are the signal setting period SWP and the light emitting period EMP. The signal setting period SWP can be divided into four periods, which are reset periods P1 and P3 and setting periods P2 and P4 respectively. It should be noted that the time lengths of the periods in FIG. 9 are just examples, and are not intended to limit the disclosed document.

Compared with the timing sequence of the control signal in the embodiment of FIG. 3, the difference of the control signal in the embodiment of FIG. 9 is that there is no first control signal G1[n] and third control signal G3[n] ], but has a reset control signal RES[n]. The reset control signal RES[n] has a low logic level during the reset period P1 of the second driving circuit 120 to turn on the circuit path from the second terminal of the first capacitor C1 to the reset control signal RES[n], thereby stabilizing The potential of the first capacitor C1. Similarly, the reset control signal RES[n] has a low logic level during the reset period P3 of the first driving circuit 110 to turn on the circuit path from the second terminal of the first capacitor C1 to the reset control signal RES[n]. , so as to stabilize the potential of the first capacitor C1. On the other hand, the reset control signal RES[n] has a high logic level during the setting periods P2 and P4 and the light emitting period EMP, so as to electrically isolate the second end of the first capacitor C1 from the reset control signal RES[n]. Other detailed waveforms and action modes of the control signal in FIG. 9 are roughly the same as the control signal in the previous embodiment in FIG. 3 , and will not be repeated here.

Please refer to FIG. 10 . FIG. 10 is a timing diagram of control signals of the pixel circuit 100 c in FIG. 8 during the signal setting period SWP and the light emitting period according to some embodiments of the present disclosure. As shown in FIG. 10 , a display period in the control sequence of the pixel circuit 100 c can be divided into two periods, which are the signal setting period SWP and the light emitting period EMP respectively. The signal setting period SWP can be divided into four periods, which are reset periods P1 and P3 and setting periods P2 and P4 respectively. It should be noted that the time lengths of the periods in FIG. 10 are only examples, and are not intended to limit the disclosed document.

Compared with the timing sequence of the control signal in the embodiment of FIG. 9 , the difference of the control signal in the embodiment of FIG. 10 lies in the waveform of the sweep signal SWEEP[n]. More precisely, the sweep signal SWEEP[n] has been switched to a high logic level during the light-emitting period EMP, and is gradually pulled down to a low logic level during the light-emitting period, because the sweep signal SWEEP[n] is passed through The capacitive coupling effect drives (pulls up or pulls down) the gate terminal of the second driving transistor TD2 by changing the potential. Therefore, the frequency sweep signal SWEEP[n] in the foregoing embodiments can also be replaced by the frequency sweep signal SWEEP[n] shown in FIG. 10 . Other detailed waveforms and action modes of the control signal in FIG. 10 are roughly the same as those of the control signal in the previous embodiment shown in FIG. 9 , and will not be repeated here.

In some embodiments, the circuit structure of the pixel circuit may not include a compensation circuit (for example, the fifth transistor T5, the eighth transistor T8), and correspondingly adjust the setting circuit (for example, the sixth transistor T6, the ninth transistor The connection relationship between crystal T9) and the second driving transistor TD2 and the first driving transistor TD1 can also form a suitable pixel circuit, and then use the reset circuit 130 and the voltage stabilizing circuit 140 to achieve the functions of reset and voltage stabilization .

The foregoing transistors TD1 , TD2 , and T1 ˜ T12 are illustrated by using P-type MOSFET (PMOS) switches as examples, but this disclosure is not limited thereto. In another embodiment, those skilled in the art can replace the transistors TD1, TD2 and T1-T12 above with N-type metal oxide semiconductor field effect transistors (N-type MOSFET, NMOS) switches, C Type Metal Oxide Semiconductor Field Effect Transistor (C-type MOSFET, CMOS) switch or other similar switching elements, and system voltage (for example, system high voltage terminal VDD, system low voltage terminal VSS and system voltage terminal PPO), Control signals (for example, the first control signal G1[n], the second control signal G2[n], the third control signal G3[n], the fourth control signal G4[n], the first voltage regulation control signal VSET1[n] ], the second voltage regulation control signal VSET2[n], the first light emission control signal EM1[n], the second light emission control signal EM2[n]) and the logic of the first data signal DATAPWM[m] and the second data signal DATA_PAM Adjusting the level correspondingly can also achieve the same function as that of this embodiment. Moreover, the aforementioned light emitting element L1 may be implemented by a micro light emitting diode, a submillimeter light emitting diode or other light emitting elements.

To sum up, the disclosed document utilizes the voltage stabilizing circuit 140 to stabilize the voltage of the first capacitor C1 in the first driving circuit 110 and the second capacitor C2 in the second driving circuit 120 during the signal setting period SWP, thereby strengthening the protection against The ability to control the pulse waveform of the driving current, thereby enhancing the low gray scale control. And using the square wave signal as the first light emission control signal EM1[n] to control the third transistor T3 in the voltage stabilizing circuit 140 can quickly open the current path of the driving current, and the configuration of the third transistor T3 can also be used in The pixel circuit 100 has the above functions to reduce the number of transistors in the circuit structure.

Although the present disclosure has been disclosed above in terms of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field may make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection disclosed shall be subject to what is defined in the scope of the appended patent application.

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the descriptions of the attached symbols are as follows: 100, 100a, 100b, 100c: pixel circuit 110: the first drive circuit 112: the first control circuit 120: the second drive circuit 122: the second control circuit 130: reset circuit 140: Regulator circuit TD1: The first driving transistor TD2: The second driving transistor T1: first transistor T2: second transistor T3: The third transistor T4: The fourth transistor T5: fifth transistor T6: sixth transistor T7: The seventh transistor T8: eighth transistor T9: ninth transistor T10: tenth transistor T11: Eleventh transistor T12: Twelfth Transistor C1: the first capacitor C2: second capacitor L1: light emitting element VDD: system high voltage terminal VSS: System low voltage terminal PPO: system voltage terminal DATAPWM[m]: the first data signal DATA_PAM: the second data signal VSET1[n]: the first voltage regulation control signal VSET2[n]: The second voltage regulation control signal G1[n]: The first control signal G2[n]: Second control signal G3[n]: The third control signal G4[n]: The fourth control signal EM1[n]: the first light emitting control signal EM2[n]: Second light emitting control signal SWEEP[n]: frequency sweep signal RES: reset signal RES[n]: reset control signal P1, P3: Reset period P2, P4: Setting period SWP: signal setting period EMP: Emitting Period

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1 is a functional block diagram of a pixel circuit according to some embodiments of the present disclosure. FIG. 2 is a circuit structure diagram of the pixel circuit in FIG. 1 according to some embodiments of the present disclosure. FIG. 3 is a timing diagram of the control signals of the pixel circuit in FIG. 2 during the signal setting period and the light emitting period according to some embodiments of the present disclosure. FIG. 4A is a schematic diagram of a reset period of a pixel circuit in a signal setting period according to some embodiments of the present disclosure. FIG. 4B is a schematic diagram of a pixel circuit during a signal setting period according to some embodiments of the present disclosure. FIG. 4C is a schematic diagram of a reset period of a pixel circuit in a signal setting period according to some embodiments of the present disclosure. FIG. 4D is a schematic diagram of a pixel circuit during a signal setting period according to some embodiments of the present disclosure. FIG. 4E is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure during a light emitting period. FIG. 5A is a waveform diagram of a driving current of a pixel circuit according to some embodiments of the present disclosure. FIGS. 5B-5D are waveform diagrams of control signals of pixel circuits according to some embodiments of the present disclosure. FIG. 5E is a waveform diagram of a lighting control signal and a frequency sweep signal of a pixel circuit according to some embodiments of the present disclosure. FIG. 6 is a timing diagram of control signals of the pixel circuit in FIG. 2 according to some embodiments of the present disclosure during the signal setting period and the light emitting period. FIG. 7 is a circuit structure diagram of the pixel circuit in FIG. 1 according to some embodiments of the present disclosure. FIG. 8 is a circuit structure diagram of the pixel circuit in FIG. 1 according to some embodiments of the present disclosure. FIG. 9 is a timing diagram of the control signals of the pixel circuit in FIG. 8 during the signal setting period and the light emitting period according to some embodiments of the present disclosure. FIG. 10 is a timing diagram of the control signals of the pixel circuit in FIG. 8 during the signal setting period and the light emitting period according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100:Pixel circuit

110: the first drive circuit

112: the first control circuit

120: the second drive circuit

122: the second control circuit

130: reset circuit

140: Regulator circuit

TD1: The first driving transistor

TD2: The second driving transistor

T10: tenth transistor

T11: Eleventh transistor

T12: Twelfth Transistor

C1: the first capacitor

C2: second capacitor

L1: light emitting element

VDD: system high voltage terminal

VSS: System low voltage terminal

PPO: system voltage terminal

VSET1[n]: the first voltage regulation control signal

VSET2[n]: The second voltage regulation control signal

G1[n]: The first control signal

G3[n]: The third control signal

EM1[n]: the first light emitting control signal

EM2[n]: Second light emitting control signal

SWEEP[n]: frequency sweep signal

RES: reset signal

Claims (9)

A pixel circuit, used to generate a driving current to drive a light-emitting element to emit light, wherein the pixel circuit includes: a first driving circuit, wherein the driving current flows from a system high voltage terminal, the first driving circuit to a The system low-voltage terminal, wherein the first driving circuit includes: a first driving transistor electrically coupled between the system high-voltage terminal and the system low-voltage terminal for controlling a pulse width of the driving current; A first capacitor, the first terminal of which is electrically coupled to the gate terminal of the first driving transistor; and a first control circuit, electrically coupled to the gate terminal of the first driving transistor, for adjusting the first The potential of the gate terminal of the driving transistor is used to control a pulse width of the driving current; a second driving circuit is electrically coupled to the first driving circuit, wherein the second driving circuit includes: a second driving transistor; a A second capacitor whose first terminal is electrically coupled to the gate terminal of the second driving transistor; and a second control circuit electrically coupled to the gate terminal of the second driving transistor for adjusting the second driving The potential of the gate terminal of the transistor is used to control the pulse width of the driving current; and a voltage stabilizing circuit includes a first transistor and a third transistor, wherein the first transistor is electrically coupled to the second capacitor the second end and Between a system voltage terminal, the first transistor is used for conducting during a signal setting period to stabilize the potential of the second capacitor, wherein the third transistor is electrically coupled to the second terminal of the first capacitor and the system between the high voltage terminals, and the third transistor is used for conducting in a light-emitting period to stabilize the potential of the first capacitor. The pixel circuit as described in Claim 1, wherein the first terminal of the first transistor is electrically coupled to the second terminal of the second capacitor, wherein the second terminal of the first transistor is electrically coupled to the system A voltage terminal, wherein the gate terminal of the first transistor is used to receive a first voltage stabilization control signal, and wherein the voltage stabilization circuit further includes: a second transistor, the first end of which is electrically coupled to the first capacitor The second terminal is electrically coupled to the system voltage terminal, and the gate terminal is used to receive a second voltage regulation control signal. The pixel circuit as described in claim 2, wherein the first end of the third transistor is electrically coupled to the system high voltage end, and the second end of the third transistor is electrically coupled to the first capacitor of the first capacitor Two terminals, the gate terminal of the third transistor is used to receive a first light-emitting control signal, wherein: during the signal setting period, the second voltage stabilization control signal has a first logic level to turn on the second transistor , so that the voltage of the system voltage terminal is transmitted to the second terminal of the first capacitor through the second transistor, and the first light-emitting control signal has a second logic level potential to turn off the third transistor, so that The system high voltage terminal and the second capacitor of the first Terminals are electrically isolated; and during the lighting period, the second voltage regulation control signal has the second logic level to turn off the second transistor, so that the system voltage terminal is electrically connected to the second terminal of the first capacitor isolated, and the first light-emitting control signal has the first logic level to turn on the third transistor, so that the voltage of the system high voltage terminal is transmitted to the second terminal of the first capacitor through the third transistor. The pixel circuit as described in claim 2 further includes a reset circuit, wherein the reset circuit includes: a fourth transistor, the first end of which is electrically coupled to the first end of the second capacitor and the first end The gate terminal of the two driving transistors, the second terminal thereof is used to receive a reset signal, and the gate terminal thereof is used to receive a first control signal, wherein: during a first reset period among the signal setting periods, the The first control signal has a first logic level to turn on the fourth transistor, so that the reset signal is transmitted to the first terminal of the second capacitor through the fourth transistor, and the first voltage regulation control signal has The first logic level is to turn on the first transistor, so that the voltage of the system voltage terminal is transmitted to the second terminal of the second capacitor through the first transistor. The pixel circuit as described in claim 2, wherein the first control circuit includes: a fifth transistor, the first end of which is electrically coupled to the first end of the second drive transistor, and the second end of which is electrically coupled to the first end of the second capacitor, the gate end of which is used to receive a second control signal; and A sixth transistor, the first terminal of which is electrically coupled to the second terminal of the second drive transistor, the second terminal of which is used to receive a first data signal, and the gate terminal of which is used to receive the second control signal; Wherein: during a first setting period among the signal setting periods, the second control signal has a first logic level to turn on the fifth transistor and the sixth transistor, so that the voltage of the first data signal Through the sixth transistor, the second drive transistor and the fifth transistor to the first terminal of the second capacitor, and the first voltage regulation control signal has the first logic level to turn on the first transistor The crystal is used to transmit the voltage of the system voltage terminal to the second terminal of the second capacitor through the first transistor. The pixel circuit as described in Claim 2 further includes a reset circuit, wherein the reset circuit includes: a seventh transistor, the first end of which is electrically coupled to the gate end of the first driving transistor and the The first terminal of the first capacitor, its second terminal is used to receive a reset signal, and its gate terminal is used to receive a third control signal, wherein: during a second reset period of the signal setting period, the The third control signal has a first logic level to turn on the seventh transistor, so that the reset signal is transmitted to the first terminal of the first capacitor through the seventh transistor, and the second voltage regulation control signal has The first logic level is to turn on the second transistor, so that the voltage of the system voltage terminal is transmitted to the second terminal of the first capacitor through the second transistor. The pixel circuit as described in claim 2, wherein the second control The control circuit includes: an eighth transistor, the first terminal of which is electrically coupled to the second terminal of the first driving transistor, and the second terminal of which is electrically coupled to the gate terminal of the first driving transistor and the first terminal of the first driving transistor. The first terminal of the capacitor, the gate terminal of which is used to receive a fourth control signal; and a ninth transistor, the first terminal of which is electrically coupled to the first terminal of the first driving transistor, and the second terminal of which is used for receiving a second data signal, the gate terminal of which is used to receive the fourth control signal, wherein: during a second setting period of the signal setting period, the fourth control signal has a first logic level to turn on the The eighth transistor and the ninth transistor make the voltage of the second data signal pass through the ninth transistor, the first driving transistor and the eighth transistor to the first end of the first capacitor, and the The second voltage regulation control signal has the first logic level to turn on the second transistor, so that the voltage of the system voltage terminal is transmitted to the second terminal of the first capacitor through the second transistor. The pixel circuit as described in claim 1, further comprising: a tenth transistor, the first end of which is electrically coupled to the high voltage end of the system, and the second end is electrically coupled to the first drive transistor. The first terminal and its gate terminal are used to receive a second light-emitting control signal, wherein the second light-emitting control signal is a square wave signal. A driving method for driving a pixel circuit, wherein the pixel circuit is used to generate a driving current to drive a light emitting element to emit light, And the pixel circuit includes a first driving circuit, a second driving circuit and a voltage stabilizing circuit, wherein the first driving circuit is used to control the pulse width of the driving current, and the first driving circuit includes a first driving circuit A transistor and a first capacitor, wherein the first end of the first capacitor is electrically coupled to the gate terminal of the first drive transistor, and the second end of the first capacitor is electrically coupled to the voltage regulator circuit, wherein the The second drive circuit is used to control the pulse width of the drive current, and the second drive circuit includes a second drive transistor and a second capacitor, wherein the first end of the second capacitor is electrically coupled to the second drive The gate terminal of the transistor, the second terminal of the second capacitor is electrically coupled to the voltage stabilizing circuit, wherein the driving method includes: when the potential of the gate terminal of the second driving transistor is reset, the voltage stabilizing circuit Transmit the voltage of a system voltage terminal to the second terminal of the second capacitor; when the potential of the gate terminal of the first driving transistor is reset, the voltage of the system voltage terminal is transmitted to the first capacitor of the first capacitor by the voltage stabilizing circuit Two terminals; when a first data signal is applied to the first drive circuit, the voltage of the system voltage terminal is transmitted from the voltage stabilizing circuit to the second terminal of the second capacitor; and when a second data signal is applied to When the second driving circuit is used, the voltage of the system voltage terminal is transmitted to the second terminal of the first capacitor by the voltage stabilizing circuit.

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