CN113394264A - Flat electric field groove semiconductor chip terminal structure and preparation method thereof - Google Patents
Flat electric field groove semiconductor chip terminal structure and preparation method thereof Download PDFInfo
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- 230000005684 electric field Effects 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
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- 239000000463 material Substances 0.000 claims description 13
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- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
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- 238000005137 deposition process Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910000676 Si alloy Inorganic materials 0.000 claims description 6
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/112—Field plates comprising multiple field plate segments
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Abstract
本发明公开了一种平电场沟槽功率半导体芯片及其制备方法，所述芯片包括：位于N型衬底之上的P区和P+区，位于N型衬底的上表面的凹型沟槽，位于沟槽的底部及N型衬底表面的氧化层，位于氧化层之上的多晶硅场板，位于多晶硅场板及未被所述多晶硅场板覆盖的氧化层表面之上的绝缘层，位于绝缘层之上的金属场板，位于金属场板及未被金属场板覆盖的绝缘层之上的钝化层，位于N型衬底之下的金属层。本发明的芯片设置了平电场沟槽结构，优化了现有的芯片制造流程及工艺参数，并采用CMP工艺，制备了具有表面平电场沟槽结构的功率半导体芯片，使芯片的表面电场分布更加均匀，提升了芯片的耐压性能，增强了芯片的可靠性。
The invention discloses a flat electric field trench power semiconductor chip and a preparation method thereof. The chip comprises: a P region and a P+ region located on an N-type substrate, a concave groove located on the upper surface of the N-type substrate, An oxide layer on the bottom of the trench and on the surface of the N-type substrate, a polysilicon field plate on the oxide layer, an insulating layer on the polysilicon field plate and the surface of the oxide layer not covered by the polysilicon field plate, on the insulating layer The metal field plate above the layer, the passivation layer above the metal field plate and the insulating layer not covered by the metal field plate, the metal layer below the N-type substrate. The chip of the invention is provided with a flat electric field groove structure, the existing chip manufacturing process and process parameters are optimized, and a CMP process is used to prepare a power semiconductor chip with a surface flat electric field groove structure, so that the surface electric field distribution of the chip is more Evenly, the voltage resistance performance of the chip is improved, and the reliability of the chip is enhanced.
Description
Technical Field
The invention relates to the technical field of power semiconductor chips, in particular to a flat electric field groove power semiconductor chip terminal structure and a preparation method thereof.
Background
At present, a power semiconductor chip mostly adopts a conventional structure terminal design, the conventional terminal structure comprises a field limiting ring structure, a field limiting ring and field plate structure, a JTE terminal, a VLD structure, a semi-insulating polycrystalline field plate structure and a derivative terminal structure design scheme thereof, the terminal structure directly influences the performance of the chip and the reliability of the chip, and the embodied direct parameters are voltage withstanding parameters (BVces) and a surface electric field bearing the voltage withstanding structure. The voltage-resistant parameters affect the application of the chip, and the electric field distribution of the bearing voltage-resistant structure affects the reliability of the chip. At present, electric field distribution on the surface of a conventional terminal structure is uneven, a fluctuation peak value is generated on the surface, and large-range fluctuation of a part of peak value is easily generated under the condition that surface oxide layer charges are unstable, so that electric field distribution is influenced, long-term reliability of a chip is further influenced, and damage can be caused in practical application.
Therefore, a new terminal structure is needed, which can further improve the voltage resistance and the surface electric field performance, form a stable peak in the surface electric field, reduce the interference of the surface electric field caused by the surface charge, and enhance the long-term reliability of the chip.
Fig. 1 illustrates a cross-sectional view of a power semiconductor chip having a conventional field limiting ring termination structure, the structure comprising: an N-type substrate 101, a plurality of P-type field limiting rings 102, a silicon dioxide layer 103, a polysilicon gate 104 and a metal field plate 105.
Disclosure of Invention
The invention provides a flat electric field groove power semiconductor chip terminal structure, which solves the problems that the electric field distribution on the surface of the conventional terminal structure is not uniform and the surface generates fluctuation peak values.
The invention provides a flat electric field groove semiconductor chip terminal structure, comprising:
a P region and a P + region formed on an N-type substrate, wherein the P region and the P + region are adjacent to each other;
a concave trench on the surface of the N-type substrate, wherein the bottom of the concave trench is formed by a first surface, a second surface and a third surface, wherein the first surface is the upper surface of the P region, the second surface is the surface of the region where the P + region adjoins the P region, and the third surface is the surface of the region where the N-type substrate adjoins the P region;
the oxide layer is filled in the concave groove and covers the P + region on the periphery of the concave groove and the surface of the N-type substrate;
a plurality of polysilicon field plates are distributed on the oxide layer at intervals at one side close to the P + region;
an insulating layer on the plurality of polysilicon field plates and the surface of the oxide layer not covered by the plurality of polysilicon field plates;
a plurality of metal field plates disposed on the insulating layer above the opposing plurality of polysilicon field plates, wherein a portion of the plurality of metal field plates contact the polysilicon field plates through first contact holes through the insulating layer therebelow and contact the P + region through second contact holes through the insulating layer therebelow, the polysilicon field plates, and the oxide layer;
a metal field plate arranged on the insulating layer above the surface of the oxide layer which is not covered by the plurality of polysilicon field plates;
a passivation layer on the plurality of metal field plates and the surface of the insulating layer not covered by the metal field plates;
a metal layer located below the N-type substrate.
In an embodiment of the present invention, the thickness of the P + region is greater than the thickness of the P region.
In an embodiment of the present invention, the implantation dose of the P + region is greater than or equal to the implantation dose of the P region.
In an embodiment of the present invention, it is,
the doping concentration range of the N-type substrate is 4.45 multiplied by 1014cm-3～1.08×1014cm-3；
The range of the implantation dosage of the P region is 1.00 multiplied by 1011cm-2～1.00×1013cm-2；
The range of the implantation dosage of the P + region is 1.00 multiplied by 1013cm-2～1.00×1015cm-2；
The depth range of the concave groove is 0.5-2 μm, and the width range is 50-150 μm;
the thickness range of the oxide layer is 1-5 mu m;
the thickness of the insulating layer is in the range of
The thickness range of the polysilicon field plate is
The doping concentration is in the range of 1.00X 1016cm-3～1.00×1020cm-3。
In an embodiment of the present invention, it is,
the oxide layer is made of silicon dioxide;
the insulating layer is made of borophosphosilicate glass, silicate glass or a mixed material of the borophosphosilicate glass and the silicate glass;
the metal field plate material is aluminum or aluminum-silicon alloy;
the passivation layer is made of nitride, oxide or organic matter.
The invention also provides a preparation method of the flat electric field groove semiconductor chip terminal structure, which comprises the following steps:
forming a first masking layer on the surface of an N-type substrate, injecting P-type ions into the upper surface of the N-type substrate by using the first masking layer which is reserved at a corresponding position after etching as a mask so as to form a P + region on the upper surface of the N-type substrate, and performing knot pushing on the P + region to a specified depth;
injecting P-type ions into the upper surface of the N-type substrate by using the first masking layer which is reserved at the corresponding position after etching as a mask again so as to form a P region on the upper surface of the N-type substrate which is not covered by the P + region, and performing junction pushing on the P region to a specified depth;
forming a second masking layer on the surface of the N-type substrate, and preparing a concave groove on the upper surface of the N-type substrate by using the second masking layer which is etched and remains at a corresponding position as a mask, wherein the bottom of the concave groove is formed by the surface of the P region, the surface of the region, adjacent to each other, of the P region and the P + region, and the surface of the region, adjacent to each other, of the P region and the N-type substrate;
preparing oxide layers on the surfaces of the concave groove, the P + region on the periphery of the concave groove and the N-type substrate to reach the specified thickness, and preparing a plurality of polysilicon field plates distributed at intervals on one side of the oxide layer close to the P + region to reach the specified thickness;
preparing insulating layers on the multiple polysilicon field plates and the surface of the oxide layer which is not covered by the multiple polysilicon field plates to reach a specified thickness;
preparing a plurality of metal field plates on the insulating layer above the plurality of polysilicon field plates, wherein a portion of the plurality of metal field plates contact the polysilicon field plates through first contact holes made through the insulating layer therebelow and contact the P + region through second contact holes made through the insulating layer therebelow, the polysilicon field plates, and the oxide layer;
preparing a metal field plate on the insulating layer above the surface of the oxide layer which is not covered by the plurality of polysilicon field plates;
preparing a passivation layer on the metal field plate and the insulating layer not covered by the metal field plate;
preparing a metal layer under the N-type substrate.
In an embodiment of the present invention, it is,
and preparing the P area and the P + area, and performing knot pushing by adopting a thermal annealing process, wherein the temperature range of knot pushing by the thermal annealing process is set to be 1000-1200 ℃.
In an embodiment of the present invention, it is,
and preparing the concave groove, the polysilicon field plate and the metal field plate by adopting a dry etching process, preparing the oxide layer by adopting an LPCVD (low pressure chemical vapor deposition) process, and grinding the surface of the oxide layer to be flat by adopting a CMP (chemical mechanical polishing) process.
In an embodiment of the present invention, it is,
the preparation of the insulating layer adopts a plasma deposition process, a high-temperature reflux process is adopted to optimize the appearance of the insulating layer, and the temperature range of the high-temperature reflux process of the insulating layer is set to be 750-950 ℃.
One or more embodiments of the present invention may have the following advantages over the prior art:
1. the improved surface flat electric field groove structure is arranged in the power semiconductor chip terminal structure, so that the electric leakage of the power semiconductor chip terminal structure is 10 DEG-9Less than ampere, and 10 electric leakage compared with the traditional terminal structure-9The high-voltage-resistance chip has more excellent voltage-resistance parameters above ampere, the application range of the chip is expanded, the voltage-resistance mode borne by the chip structure is improved, and the electric field on the surface of the chip forms a stable peak, so that the surface electric field of the chip is more uniformly distributed, the influence of the surface charge of an oxidation layer on the surface electric field of the chip structure is reduced, the fluctuation of the surface electric field along with the charge of the oxidation layer is reduced, and the reliability of the chip is enhanced.
2. The invention also provides a preparation method of the flat electric field groove power semiconductor chip terminal structure, the invention optimizes the existing chip manufacturing flow and process parameters by improving the injection region structure, the polycrystal etching structure and the metal etching structure and adopting the CMP process, the power semiconductor chip terminal structure with the surface flat electric field groove structure is prepared, and the pressure resistance of the chip is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 illustrates a schematic cross-sectional view of a power semiconductor chip having a conventional field limiting ring termination structure;
FIG. 2 is a cross-sectional view of a flat field trench structure of an exemplary power semiconductor chip in accordance with the present invention;
FIG. 3 is a diagram illustrating an exemplary conventional field limiting ring termination structure BV simulation Y-axis logarithmic curve in accordance with the present invention;
FIG. 4 is a schematic diagram of a simulated Y-axis logarithmic curve for an exemplary flat field trench termination structure BV in accordance with the present invention;
FIG. 5 is a schematic diagram of an electric field distribution of an exemplary conventional field limiting ring termination structure according to the present invention;
FIG. 6 is a schematic diagram of an electric field distribution of an exemplary flat electric field trench termination structure of the present invention;
FIG. 7 is a schematic diagram illustrating surface electric field lines of a conventional field limiting ring termination structure according to an exemplary embodiment of the present invention;
fig. 8 is a graphical representation of surface electric field lines of an exemplary flat electric field trench termination structure in accordance with the present invention.
FIG. 9 is a flow chart illustrating a method for fabricating a flat field trench power semiconductor chip in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a cross-sectional view of a chip structure corresponding to steps S100 and S200 according to an exemplary embodiment of the present invention;
FIG. 11 is a cross-sectional view of an exemplary chip structure corresponding to steps S300 and S400;
FIG. 12 is a cross-sectional view of a chip structure corresponding to step S500 in accordance with an exemplary embodiment of the present invention;
fig. 13 is a schematic cross-sectional view illustrating a chip structure corresponding to steps S600 and S700 according to an exemplary embodiment of the invention;
fig. 14 is a schematic cross-sectional view of a chip structure corresponding to step S800 according to an example of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the present invention with reference to the accompanying drawings is provided to fully understand and implement the technical effects of the present invention by solving the technical problems through technical means. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
Fig. 2 is a schematic cross-sectional view of a flat electric field trench structure of a power semiconductor chip of the present embodiment, as shown in fig. 2, including: the field plate comprises an N-type substrate 101, a P region 2, a P + region 3, an oxide layer 4, a polysilicon field plate 5, an insulating layer 6, a metal field plate 7 and a passivation layer 8.
FIG. 3 is a diagram illustrating a log curve of a BV simulation axis of a conventional field limiting ring terminal structure according to the present embodiment;
FIG. 4 is a schematic diagram of a simulated Y-axis logarithmic curve of the flat electric field trench termination structure BV of the present embodiment;
FIG. 5 is a schematic diagram of an electric field distribution of a conventional field limiting ring termination structure according to the present embodiment;
FIG. 6 is a schematic diagram of the electric field distribution of the flat electric field trench termination structure of the present embodiment;
FIG. 7 is a schematic diagram of a surface electric field line curve of a conventional field limiting ring termination structure of the present embodiment;
fig. 8 is a schematic diagram of the surface electric field lines of the planar electric field trench termination structure of the present embodiment.
The N-type substrate layer 101 in this embodiment may include various semiconductor elements, such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, or may include a mixed semiconductor structure, such as silicon carbide, gallium nitride, indium phosphide, gallium arsenide, alloy semiconductor, or a combination thereof, which is not limited herein. In the present embodiment, the N-type substrate 101 is preferably a silicon substrate, and in the present embodiment, an N-type substrate is taken as an example for description.
The present embodiment provides a flat field trench semiconductor chip, including:
a P region 2 and a P + region 3 located over the N-type substrate 101, wherein the P region 2 and the P + region 3 are adjacent to each other;
a concave trench located on the upper surface of the N-type substrate 101, wherein the bottom of the concave trench is formed by the surface of the P region 2, the surface of the P + region 3 adjacent to the P region 2, and the surface of the N-type substrate 101 adjacent to the P region 2;
an oxide layer 4 filling the concave groove and covering the P + region 3 at the periphery of the concave groove and the surface of the N-type substrate 101;
a plurality of polysilicon field plates 5 are distributed on the oxide layer 4 at intervals at one side close to the P + region 3;
an insulating layer 6 located on the polysilicon field plates 5 and the surface of the oxide layer 4 not covered by the polysilicon field plates 5;
a plurality of metal field plates 7 disposed on the insulating layer 6 above the opposing plurality of polysilicon field plates, wherein a portion of the plurality of metal field plates 7 contacts the polysilicon field plate 5 through a first contact hole through the insulating layer 6 therebelow and contacts the P + region 3 through a second contact hole through the insulating layer 6 therebelow, the polysilicon field plate 5 and the oxide layer 4;
a metal field plate 7 disposed on the insulating layer 6 above the surface of the oxide layer 4 relatively uncovered by the plurality of polysilicon field plates 5;
a passivation layer 8 on the plurality of metal field plates 7 and the surface of the insulating layer 6 not covered by the metal field plates 7;
a metal layer located under the N-type substrate 101, which is not shown in fig. 2.
In this embodiment, a groove is disposed on the surface of the N-type substrate, and the groove is in contact with the P region, the P + region, and the N-type substrate.
In this embodiment, the thickness of the P + region is greater than the thickness of the P region.
In this embodiment, a contact hole is disposed between the polysilicon field plate above the P + region and the metal field plate above the polysilicon field plate.
Specifically, the present embodiment improves the field limiting ring structure in the conventional terminal structure to the flat electric field groove structure based on the conventional terminal structure. The power semiconductor chip of the embodiment comprises a higher concentration N-type substrate 101, wherein the doping concentration range of the N-type substrate 101 is 4.45 multiplied by 1014cm-3～1.08×1014cm-3The specific doping concentration can be optimally set according to the voltage withstanding requirement of the chip structure. The P + region 3 is arranged on the N-type substrate 101, and the implantation dosage range of the P + region 3 is 1.00 multiplied by 1013cm-2～1.00×1015cm-2Meanwhile, a P region 2 is arranged on the N-type substrate 101, and the implantation dosage range of the P region 2 is 1.00 multiplied by 1011cm-2～1.00×1013cm-2The implantation dose of the P + region 3 is greater than or equal to the implantation dose of the P region 2, the specific implantation doses of the P region 2 and the P + region 3 can be optimally set according to the withstand voltage requirement of the chip structure, the P region 2 and the P + region 3 are adjacent in the horizontal direction, and the thickness of the P + region 3 after being subjected to knot pushing is greater than that of the P region 2 after being subjected to knot pushing.
Specifically, in the present embodiment, a concave trench is formed on the surface of the N-type substrate 101, and the bottom of the concave trench contacts the P region 2, the P + region 3, and the N-type substrate 101 not covered by the P region 2 and the P + region 3. Wherein, the depth range of the concave groove is set to be 0.5-2 μm, the width range is set to be 50-150 μm, and the specific setting parameters are optimized according to the voltage-resistant requirement of the chip.
Specifically, in this embodiment, an oxide layer 4 is disposed at the bottom of the trench and on the surface of the N-type substrate 101, the oxide layer 4 is disposed on the P region 2 and the P + region 3, the oxide layer 4 is in contact with both the P region 2 and the P + region 3, the oxide layer 4 is also in contact with the surface of the N-type substrate 101 not covered by the P region 2 and the P + region 3, the thickness range of the oxide layer 4 is set to be 1 μm to 5 μm, and the specific setting parameters are optimally set according to the withstand voltage requirement of the chip. The oxide layer 4 is made of various oxides, and preferably made of silicon dioxide in the present embodiment.
Specifically, in this embodiment, polysilicon field plates 5 are disposed above the oxide layer 4,wherein the polysilicon field plate 5 is arranged on the oxide layer 4 above the P + region 3 region, and the thickness range of the polysilicon field plate 5 is set as
The doping concentration range was set to 1.00X 1016cm-3～1.00×1020cm-3And the specific setting parameters are optimally set according to the pressure resistance requirement of the chip.
Specifically, in the present embodiment, the insulating layer 6 is disposed on the polysilicon field plate 5 and the surface of the oxide layer 4 not covered by the polysilicon field plate 5, and the thickness range of the insulating layer 6 is set as
And the specific setting parameters are optimally set according to the pressure resistance requirement of the chip. The insulating layer 6 is made of various glass materials, and in this embodiment, it is preferably made of borophosphosilicate glass, silicate glass, or a mixture of borophosphosilicate glass and silicate glass.
Specifically, in the present embodiment, metal field plates 7 are disposed at intervals above the insulating layer 6, wherein the insulating layer regions above the polysilicon field plate 5 are each provided with a metal field plate 7, and the metal field plate material is preferably aluminum or aluminum-silicon alloy. Contact holes are arranged between the metal field plate 7 and the polysilicon field plate 5, wherein the first contact hole penetrates through the insulating layer to connect the metal field plate 7 and the polysilicon field plate 5, the second contact hole penetrates through the insulating layer 6 along the edge of the polysilicon field plate 5 to connect the metal field plate 7 and the polysilicon field plate 5, and metal materials, preferably aluminum or aluminum-silicon alloy, are filled in the contact holes. The first contact hole is mainly used for communicating the polysilicon field plate 5 and the metal field plate 7 to reduce the on-resistance of the chip, and the second contact hole is mainly used for connecting the metal field plate 7 and the P + region 3 to enable the potentials of the metal field plate 7 and the P + region 3 to be equal, so that the electric field is uniformly distributed. And the metal field plate 7 without the contact hole, the polysilicon field plate 5 and the insulating layer 6 between the two together form a composite field plate for balancing electric field distribution. The metal field plate 7 arranged above the surface of the oxide layer 4 which is not covered by the polysilicon field plates 5 on the insulating layer 6 plays a role of a suspension field plate, and the polysilicon field plates 5 are not arranged, so that the metal field plate has strong electric field concentration capability and larger electric field curvature radius, is used for balancing electric field distribution, and avoids the electric field from concentrating on the left side of a chip terminal structure.
A passivation layer 8 is provided on the metal field plate 7 and the insulating layer 6 not covered by said metal field plate 7, the material of the passivation layer 8 preferably being nitride, oxide or organic.
A metal layer, which is not shown in fig. 2, is also disposed under the N-type substrate 101.
Fig. 3 and 4 are BV simulation Y-axis logarithmic curves schematic diagrams of a conventional field-limiting ring termination structure and a flat-field trench termination structure, respectively.
As can be seen from the simulation result, in the flat field trench termination structure of the present embodiment and the conventional field limiting ring termination structure, under the condition of the X axis of 800V, the Collector current of the Collector in the Y axis is not in one order, and the leakage current of the flat field trench termination structure is 10V-9Ampere or less, and the leakage current of the conventional field limiting ring terminal structure is 10-9The current is higher than ampere, so that the power semiconductor chip is easy to break down, and the flat electric field groove terminal structure of the embodiment has more excellent voltage-resistant parameters.
Fig. 5 and 6 are schematic diagrams of electric field distributions of a conventional field limiting ring termination structure and a flat-electric-field trench termination structure, respectively.
From the results of the schematic diagrams, it can be seen that the flat electric field trench terminal structure is obviously different from the conventional field limiting ring terminal structure in the voltage withstanding mode, regions with high electric field intensity concentration are marked in the drawing, the surface electric field of the flat electric field trench terminal structure forms an electric field concentration point 1 with the oxide layer 4 on the left side of the trench on the upper portion of the main junction P + region 3, an electric field concentration point 2 is formed in the N-type substrate 101 on the lower portion of the P region 2 and the P + region 3, and an electric field concentration point 3 is formed on the right side of the P region and the N-type substrate contact region. And the conventional field limiting ring terminal structure forms an electric field concentration area at the right side of the P-type field limiting ring, forms an electric field concentration point at the top of the field limiting ring and an electric field concentration point at the bottom of the field limiting ring, and forms an electric field concentration area at the surface of the rightmost field limiting ring.
Fig. 7 and 8 are schematic surface electric field line curves of the conventional field limiting ring terminal structure and the flat electric field trench terminal structure, respectively.
According to the curves of the withstand voltage electric field lines of the two structures in the attached drawings, the electric field lines of the flat electric field groove terminal structure and the electric field lines of the conventional field limiting ring terminal structure have great difference, wherein a stable peak is formed by the curves of the flat electric field groove terminal structure, the surface withstand voltage mode is uniform, the electric field fluctuates at a relatively small position, even under the influence of surface charges, the electric field is maintained in a relatively stable fluctuation range, the change rate of the electric field is mild, and the power semiconductor chip is not easy to break down. The curve of the conventional field limiting ring terminal structure forms several peaks with abrupt structure change, the voltage-resisting mode is uneven, the peaks are mainly concentrated on the last junctions, the secondary fluctuation of the peaks is easily caused under the influence of surface charges, the electric field change rate is very high, and the power semiconductor chip is easier to break down.
In summary, in the present embodiment, the improved surface flat electric field trench structure is disposed in the power semiconductor chip, so that the leakage current of the power semiconductor chip of the invention is 10-9Less than ampere, and 10 electric leakage compared with the traditional terminal structure-9The high-voltage-resistance chip has more excellent voltage-resistance parameters above ampere, the application range of the chip is expanded, the voltage-resistance mode borne by the chip structure is improved, and the electric field on the surface of the chip forms a stable peak, so that the electric field on the surface of the chip is more uniformly distributed, the influence of the surface charge of an oxidation layer on the electric field on the surface of the chip structure is reduced, the fluctuation of the surface electric field along with the charge of the oxidation layer is reduced, the possibility of the leakage current to puncture the power semiconductor chip is reduced, and the reliability of the chip is enhanced.
Second embodiment
FIG. 9 is a flow chart illustrating a method for fabricating a flat field trench power semiconductor chip in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a cross-sectional view of a chip structure corresponding to steps S100 and S200 according to an exemplary embodiment of the present invention;
FIG. 11 is a cross-sectional view of an exemplary chip structure corresponding to steps S300 and S400;
FIG. 12 is a cross-sectional view of a chip structure corresponding to step S500 in accordance with an exemplary embodiment of the present invention;
fig. 13 is a schematic cross-sectional view illustrating a chip structure corresponding to steps S600 and S700 according to an exemplary embodiment of the invention;
fig. 14 is a schematic cross-sectional view of a chip structure corresponding to step S800 according to an example of the present invention.
Fig. 2 shows a schematic cross-sectional view of a planar electric field trench semiconductor chip structure of this embodiment, which includes: n-type substrate 101, P region 2, P + region 3, oxide layer 4, polysilicon field plate 5, insulating layer 6, metal field plate 7, passivation layer 8, wherein the metal layer under N-type substrate 101, not shown in fig. 2.
The N-type substrate layer 101 in this embodiment may include various semiconductor elements, such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, or may include a mixed semiconductor structure, such as silicon carbide, gallium nitride, indium phosphide, gallium arsenide, alloy semiconductor, or a combination thereof, which is not limited herein. In the present embodiment, the N-type substrate 101 is preferably a silicon substrate, and in the present embodiment, an N-type substrate is taken as an example for description.
In the embodiment, on the basis of the traditional terminal structure, the field limiting ring structure in the conventional terminal structure is improved into a flat electric field groove structure by adopting the existing semiconductor chip manufacturing process.
As shown in fig. 8, the present invention provides a method for manufacturing a flat field trench semiconductor chip, comprising the steps of:
step S100: forming a first masking layer on the upper surface of the N-type substrate 101, injecting second conductive type ions on the upper surface of the N-type substrate 101 by using the first masking layer which is reserved at the corresponding position after etching as a mask so as to form a P + region 3 on the upper surface of the N-type substrate 101, and performing junction pushing on the P + region 3 to a specified depth.
Specifically, step S100 includes the steps of:
the power semiconductor chip of the embodiment comprises a higher concentration N-type substrate 101, wherein the doping concentration range of the N-type substrate 101 is 4.45 multiplied by 1014cm-3～1.08×1014cm-3And the specific doping concentration is optimally set according to the voltage-resistant requirement of the chip structure.
A layer of silicon dioxide is manufactured on the upper surface of the N-type substrate 101 by adopting a deposition process to be used as a first masking layer;
opening an etching area by adopting terminal photoetching plate exposure, and opening a fixed window by an etching process;
implanting P-type ions, preferably boron ions, on the upper surface of the N-type substrate 101 by an ion implantation process, setting an implantation dose range to 1.00 × 1013cm-2～1.00×1015cm-2The specific implantation dosage is optimally set according to the pressure-resistant requirement of the chip structure;
and then, performing knot pushing by adopting a high-temperature thermal annealing process to form a terminal P + type region 3, wherein the temperature range of the thermal annealing knot pushing process is set to be 1000-1200 ℃, and the specific temperature is optimally set according to the pressure-resistant requirement of the chip structure.
Step S200: and implanting second conductive type ions on the upper surface of the N-type substrate 101 by using the first masking layer which is reserved at the corresponding position after etching as a mask, forming a P region 2 on the upper surface of the N-type substrate 101 which is not covered by the P + region 3, performing junction pushing on the P region 2 to a specified depth, and implementing the step 100 and the step 200 to obtain a chip structure with a cross section as shown in FIG. 10.
Specifically, step S200 includes the steps of:
opening an etching area on the first masking layer by adopting a terminal photoetching plate exposure process, and opening a fixed window by adopting the etching process;
implanting P-type ions, preferably boron ions, on the upper surface of the N-type substrate 101 by an ion implantation process, setting an implantation dose range to 1.00 × 1011cm-2～1.00×1013cm-2The specific implantation dosage is optimally set according to the pressure-resistant requirement of the chip structure;
and then, performing knot pushing by adopting a high-temperature thermal annealing process to form a terminal P-type region 2, wherein the temperature range of the thermal annealing knot pushing process is set to be 1000-1200 ℃, and the specific temperature is optimally set according to the pressure-resistant requirement of the chip structure.
The implantation dosage of the P + region 3 is more than or equal to that of the P region 2, the P + region 3, the P region 2 and the P + region 3 are adjacent in the horizontal direction, and the thickness of the P + region 3 after being pushed is more than that of the P region 2 after being pushed.
Step S300: and forming a second masking layer on the surface of the N-type substrate 101, and preparing a concave groove on the upper surface of the N-type substrate 101 by using the second masking layer which is etched and remains at a corresponding position as a mask, wherein the bottom of the concave groove is formed by the surface of the P region 2, the surface of the adjacent region of the P + region 3 and the P region 2, and the surface of the adjacent region of the N-type substrate 101 and the P region 2.
Specifically, in this embodiment, a layer of silicon dioxide is formed on the upper surface of the N-type substrate 101 by a deposition process to serve as a second masking layer, a concave trench etching window is opened by a photolithography process, a concave trench is etched by a dry etching process, and the bottom of the concave trench is in contact with the P region 2 and the P + region 3 and in contact with the N-type substrate 101 which is not covered by the P region 2 and the P + region 3. Wherein, the depth range of the concave groove is set to be 0.5-2 μm, the width range is set to be 50-150 μm, and the specific setting parameters are optimized according to the voltage-resistant requirement of the chip.
Step S400: an oxide layer 4 is formed on the recessed trench, the P + region 3 around the recessed trench, and the surface of the N-type substrate 101 to a predetermined thickness, and the cross-sectional view of the chip structure after steps 300 and 400 is shown in fig. 11.
Specifically, in this embodiment, an oxide layer 4 is disposed at the bottom of the trench and on the surface of the N-type substrate 101 by an LPCVD process, the oxide layer 4 is disposed on the P region 2 and the P + region 3, the oxide layer 4 is in contact with both the P region 2 and the P + region 3, the oxide layer 4 is also in contact with the surface of the N-type substrate 101 not covered by the P region 2 and the P + region 3, the thickness range of the oxide layer 4 is set to be 1 μm to 5 μm, and specific setting parameters are optimally set according to the withstand voltage requirement of the chip. The oxide layer 4 is made of various oxides, and preferably made of silicon dioxide in the present embodiment. Thereafter, the surface of the oxide layer 4 is polished flat by a CMP process.
Step S500: a plurality of polysilicon field plates 5 are formed on the oxide layer 4 at intervals on the side close to the P + region 3 to a specified thickness, and the cross-sectional view of the chip structure after step 500 is performed is shown in fig. 12.
Specifically, in the present embodiment, in the oxidationDepositing a polysilicon layer on the layer 4 by a deposition process, opening a window of a region to be etched by a photoetching process, and etching the polysilicon by a dry etching technique to form polysilicon field plates 5 distributed at intervals, wherein the polysilicon field plates 5 are arranged on the oxide layer 4 above the P + region 3 region, and the thickness range of the polysilicon field plates 5 is set as
The doping concentration range was set to 1.00X 1016cm-3～1.00×1020cm-3And the specific setting parameters are optimally set according to the pressure resistance requirement of the chip.
Step S600: an insulating layer 6 is prepared on the surfaces of the multiple polysilicon field plates 5 and the oxide layer 6 not covered by the multiple polysilicon field plates 5 to reach a specified thickness.
Specifically, in the present embodiment, the insulating layer 6 is deposited on the surface of the polysilicon field plate 5 and the oxide layer 4 not covered by the polysilicon field plate 5 by an ion deposition process, and the thickness range of the insulating layer 6 is set as
And the specific setting parameters are optimally set according to the pressure resistance requirement of the chip. The insulating layer 6 is made of various glass materials, preferably, borophosphosilicate glass, silicate glass or a mixed material of borophosphosilicate glass and silicate glass; after deposition, the appearance of the insulating layer 6 is optimized by adopting a high-temperature reflux process, and the temperature range of the high-temperature reflux process is set to be 750-950 ℃.
Step S700: preparing a plurality of metal field plates 7 on the insulating layer 6 above the opposing plurality of polysilicon field plates 5, wherein a portion of the metal field plates 7 of the plurality of metal field plates 7 contacts the polysilicon field plates 5 through first contact holes made through the insulating layer 6 therebelow, and second contact holes are made through the insulating layer 6 therebelow, the polysilicon field plates 5 and the oxide layer 4 to contact the P + region 3;
a metal field plate 7 is formed on the insulating layer 6 above the surface of the oxide layer 4 not covered by the polysilicon field plates 5, and the cross-sectional view of the chip structure after steps 600 and 700 is shown in fig. 13.
Specifically, in this embodiment, a contact hole is opened in the insulating layer 6 above the P + region 3, a metal material, preferably aluminum or aluminum-silicon alloy, is deposited in the contact hole and above the insulating layer 6 through a deposition process, then a window to be etched is opened through a photolithography process, and then metal is etched through a dry etching process to form metal field plates 7 distributed at intervals.
The insulating layer 6 area above the multiple polysilicon field plates 5 is provided with a metal field plate 7, contact holes are arranged between part of the metal field plates 7 of the multiple metal field plates 7 and the polysilicon field plates 5, wherein part of the metal field plates 7 of the multiple metal field plates 7 are connected with the polysilicon field plates 5 by making first contact holes through the insulating layer 6 below the metal field plates and are connected with the P + region 3 on the surface of the N-type substrate 101 by making second contact holes through the insulating layer 6, the polysilicon field plates 5 and the oxide layer 4, and metal materials, preferably aluminum or aluminum-silicon alloy, are filled in the contact holes;
step S800: a passivation layer 8 is prepared over the metal field plate 7 and the insulating layer 6 not covered by the metal field plate 7. After step 800, a cross-sectional view of the chip structure is shown in fig. 14, and the material of the passivation layer 8 is preferably nitride, oxide or organic.
Step S900: the metal layer on the bottom of the N-type substrate 101 is fabricated according to a conventional process.
The advantages of the flat electric field trench power semiconductor chip and the power semiconductor chip of the conventional field limiting ring structure have been described in detail in embodiment 1.
In summary, the invention provides a method for manufacturing a flat electric field trench power semiconductor chip, which optimizes the existing chip manufacturing process and process parameters by improving an injection region structure, a polycrystal etching structure and a metal etching structure and adopting a CMP (chemical mechanical polishing) process, prepares a power semiconductor chip with a surface flat electric field trench structure, and improves the voltage resistance of the chip.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed, and that the scope of the invention is not to be limited to the particular embodiments disclosed herein but is to be accorded the full scope of the claims.
Claims (10)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113889407A (en) * | 2021-09-27 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type IGBT device and trench type IGBT device |
| CN115472495A (en) * | 2022-07-21 | 2022-12-13 | 上海林众电子科技有限公司 | A preparation method of a power chip termination area and a preparation method of a power chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719509A (en) * | 2009-11-10 | 2010-06-02 | 深圳深爱半导体有限公司 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor |
| US20130168761A1 (en) * | 2011-12-30 | 2013-07-04 | Feei Cherng Enterprise Co., Ltd. | Semiconductor power device having improved termination structure for mask saving |
| JP2014049694A (en) * | 2012-09-03 | 2014-03-17 | Renesas Electronics Corp | Igbt |
| CN105405869A (en) * | 2015-11-25 | 2016-03-16 | 电子科技大学 | Shallow-trench junction terminal expansion structure |
| CN107342325A (en) * | 2017-06-30 | 2017-11-10 | 东南大学 | A kind of lateral double-diffused metal-oxide semiconductor device |
| WO2019170631A1 (en) * | 2018-03-06 | 2019-09-12 | Abb Schweiz Ag | High power semiconductor device with self-aligned field plate and mesa termination structure and method for manufacturing the same |
| CN212033027U (en) * | 2020-03-12 | 2020-11-27 | 珠海格力电器股份有限公司 | Flat electric field groove semiconductor chip terminal structure and semiconductor chip |
-
2020
- 2020-03-12 CN CN202010170752.8A patent/CN113394264A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719509A (en) * | 2009-11-10 | 2010-06-02 | 深圳深爱半导体有限公司 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor |
| US20130168761A1 (en) * | 2011-12-30 | 2013-07-04 | Feei Cherng Enterprise Co., Ltd. | Semiconductor power device having improved termination structure for mask saving |
| JP2014049694A (en) * | 2012-09-03 | 2014-03-17 | Renesas Electronics Corp | Igbt |
| CN105405869A (en) * | 2015-11-25 | 2016-03-16 | 电子科技大学 | Shallow-trench junction terminal expansion structure |
| CN107342325A (en) * | 2017-06-30 | 2017-11-10 | 东南大学 | A kind of lateral double-diffused metal-oxide semiconductor device |
| WO2019170631A1 (en) * | 2018-03-06 | 2019-09-12 | Abb Schweiz Ag | High power semiconductor device with self-aligned field plate and mesa termination structure and method for manufacturing the same |
| CN212033027U (en) * | 2020-03-12 | 2020-11-27 | 珠海格力电器股份有限公司 | Flat electric field groove semiconductor chip terminal structure and semiconductor chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113889407A (en) * | 2021-09-27 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type IGBT device and trench type IGBT device |
| CN115472495A (en) * | 2022-07-21 | 2022-12-13 | 上海林众电子科技有限公司 | A preparation method of a power chip termination area and a preparation method of a power chip |
| CN115472495B (en) * | 2022-07-21 | 2024-05-31 | 上海林众电子科技有限公司 | Preparation method of power chip termination region and preparation method of power chip |
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