CN113381758A - Compensation circuit and digital-to-analog conversion device - Google Patents

Compensation circuit and digital-to-analog conversion device Download PDF

Info

Publication number
CN113381758A
CN113381758A CN202110679601.XA CN202110679601A CN113381758A CN 113381758 A CN113381758 A CN 113381758A CN 202110679601 A CN202110679601 A CN 202110679601A CN 113381758 A CN113381758 A CN 113381758A
Authority
CN
China
Prior art keywords
sampling
module
input
accumulator
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110679601.XA
Other languages
Chinese (zh)
Other versions
CN113381758B (en
Inventor
孟凡贵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongguan Mindong Electronic Technology Co ltd
Original Assignee
Dongguan Mindong Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongguan Mindong Electronic Technology Co ltd filed Critical Dongguan Mindong Electronic Technology Co ltd
Priority to CN202110679601.XA priority Critical patent/CN113381758B/en
Publication of CN113381758A publication Critical patent/CN113381758A/en
Application granted granted Critical
Publication of CN113381758B publication Critical patent/CN113381758B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/78Simultaneous conversion using ladder network
    • H03M1/785Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本发明公开了一种补偿电路及数模转换装置,利用信号采样模块对输入的原始数字信号进行采样获得输入采样值,系数输入模块输入偏差系数,采样预测模块根据偏差系数生成预测采样值;比较模块比较输入采样值和预测采样值,并输出比较结果;编码模块基于逐次逼近法进行编码得到补偿值,在比较结果满足预设条件时存储补偿值,并基于所存储的补偿值对原始数字信号进行再编码,形成补偿数字信号。本发明基于逐次逼近法对输入的原始数字信号进行编码,使得数字信号在进入数模转换电路前经过编码得以消除偏差,从而避免了模拟信号的失真。本发明提供的补偿方案不需要改变数模转换电路的结构,电路结构简单,能够降低成本且易于实现。

Figure 202110679601

The invention discloses a compensation circuit and a digital-to-analog conversion device. A signal sampling module is used to sample an input original digital signal to obtain an input sampling value, a coefficient input module inputs a deviation coefficient, and a sampling prediction module generates a predicted sampling value according to the deviation coefficient; The module compares the input sampling value and the predicted sampling value, and outputs the comparison result; the coding module performs coding based on the successive approximation method to obtain the compensation value, stores the compensation value when the comparison result meets the preset condition, and based on the stored compensation value. Re-encoding is performed to form a compensated digital signal. The invention encodes the input original digital signal based on the successive approximation method, so that the digital signal is encoded before entering the digital-to-analog conversion circuit to eliminate the deviation, thereby avoiding the distortion of the analog signal. The compensation scheme provided by the present invention does not need to change the structure of the digital-to-analog conversion circuit, the circuit structure is simple, the cost can be reduced, and the realization is easy.

Figure 202110679601

Description

Compensation circuit and digital-to-analog conversion device
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a compensation circuit and a digital-to-analog conversion device.
Background
DAC (Digital to Analog converter) is a device that converts Digital signals into Analog signals, and is widely used in Digital circuits, and by using Digital signals to process data in Digital circuits, the circuits can obtain higher anti-interference capability, and the data processing method is more flexible, but at the input and output ends of signals, feedback signals and controlled object control quantities may still be Analog signals, and Analog input quantities can be converted into Digital signals by adc (Analog to Digital converter), and Digital signals are reduced into Analog signals by DAC at the signal output end.
The R2R resistor network is a traditional digital-to-analog conversion method, and has the advantages of simple principle, easy implementation, etc., but because the error between the resistors can cause nonlinear distortion, which is usually serious, the R2R resistor network has very high precision requirement on the resistors, and the resistors need to be strictly selected and adjusted, resulting in complex production and high cost. In order to solve the above problems, the conventional techniques reduce distortion by a series, parallel, bipolar, or the like, in many cases, starting from the resistor itself, but such a compensation circuit is difficult to realize because it has a complicated structure and a large circuit area.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a compensation circuit and a digital-to-analog conversion device, which solve the problem that the prior art reduces the distortion of an R2R resistance network in a series connection mode, a parallel connection mode, a bipolar mode and the like, and the compensation circuit is complex in structure and large in circuit area, so that the compensation circuit is difficult to realize.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a compensation circuit, comprising: the device comprises a signal sampling module, a coefficient input module, a sampling prediction module, a comparison module and an encoding module;
the signal sampling module is used for sampling an input original digital signal to obtain an input sampling value, the coefficient input module is used for inputting a deviation coefficient, and the sampling prediction module is used for generating a prediction sampling value according to the deviation coefficient; the comparison module is used for comparing the input sampling value with the predicted sampling value and outputting a comparison result;
and the coding module codes based on a successive approximation method to obtain a compensation value, stores the compensation value when the comparison result meets a preset condition, and recodes the original digital signal based on the stored compensation value to form a compensation digital signal.
Optionally, the compensation circuit further includes a clock module for generating a timing control signal, where the clock module includes a counter, and an output end of the counter is connected to an input end of the sampling prediction module and an input end of the encoding module;
the coefficient input module inputs a deviation coefficient once when the counter counts once; the sampling prediction module sequentially generates prediction sampling values according to the deviation coefficients input by the coefficient input module;
the counter counts a specified number of times to form a clock cycle, and the signal sampling module samples an input original digital signal once in one clock cycle of the clock module.
Optionally, an output end of the coefficient input module is connected to an input end of the sampling prediction module, an output end of the sampling prediction module and an output end of the signal sampling module are respectively connected to an input end of the comparison module, and an output end of the comparison module is connected to an input end of the encoding module and an input end of the sampling prediction module.
Optionally, the sample prediction module comprises a sample predictor, a sample selector and a sample accumulator; the sampling predictor is used for outputting a prediction sampling value according to the deviation coefficient, and the sampling accumulator is used for storing the currently generated prediction sampling value;
the output end of the coefficient input module and the output end of the sampling accumulator are connected with the input end of the sampling predictor; the output end of the sampling predictor, the output end of the comparison module and the output end of the sampling accumulator are connected with the input end of the sampling selector; the output end of the sampling selector is connected with the input end of the sampling accumulator.
Optionally, when the comparison result is that the predicted sample value is greater than the input sample value, the sample selector outputs a signal to the sample accumulator to actuate the sample accumulator; and when the comparison result is that the predicted sampling value is smaller than the input sampling value, the sampling selector outputs a signal to the sampling predictor to enable the sampling predictor to act.
Optionally, the output end of the counter is connected to a sampling accumulator, and the counter sends a clear signal to the sampling accumulator every time a clock cycle elapses, so that the sampling accumulator clears the stored predicted sampling value.
Optionally, the encoding module includes an encoding generator, an output end of the counter is connected to an input end of the encoding generator, and the encoding generator is configured to output a count value x of the counter as a binary code y according to the following formula:
y=2x
optionally, the encoding module further comprises an encoding predictor, an encoding selector and an encoding accumulator; the coding predictor is used for outputting a compensation value according to the binary coding, and the coding accumulator is used for storing the currently generated compensation value;
the output end of the code generator and the output end of the code selector are connected with the input end of the code accumulator, the output end of the code generator and the output end of the code accumulator are connected with the input end of the code predictor, and the output end of the code accumulator, the output end of the code predictor and the output end of the comparison module are connected with the input end of the code selector.
Optionally, when the comparison result is that the predicted sample value is greater than the input sample value, the encoding selector sends a signal to the encoding accumulator to actuate the encoding accumulator; and when the comparison result shows that the prediction sampling value is smaller than the input sampling value, the coding selector sends a signal to the coding predictor to enable the coding predictor to act.
The invention also provides a digital-to-analog conversion device, which comprises the compensation circuit and a digital-to-analog conversion circuit;
the digital-to-analog conversion circuit is used for receiving the compensation digital signal formed in the compensation circuit and converting the compensation digital signal into an analog signal.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a compensation circuit and a digital-to-analog conversion device, which encode an input original digital signal based on a successive approximation method according to a preset deviation coefficient, so that the digital signal is encoded before entering a digital-to-analog conversion circuit to eliminate deviation, thereby avoiding the distortion of an analog signal. The compensation scheme provided by the invention does not need to change the structure of the digital-to-analog conversion circuit, has a simple circuit structure, can reduce the cost and is easy to realize.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a prior art R2R resistor network;
FIG. 2 is a schematic diagram of a compensation circuit according to the present invention;
fig. 3 is a schematic structural diagram of a digital-to-analog conversion apparatus provided in the present invention.
In the above figures: 100. a clock input; 101. a coefficient input module; 102. a signal sampling module; 103. a code output end; 200. a counter; 201. a code generator; 202. a coding accumulator; 203. a coding predictor; 204. a code selector; 210. a sampling accumulator; 211. a sampling predictor; 212. a sampling comparator; 213. a sampling selector; A. a compensation circuit; B. a digital-to-analog conversion circuit.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To facilitate understanding of the technical solutions of the present invention, the technical background of the present invention is briefly introduced here:
digital-to-analog converter (DAC) is an indispensable technical means for Digital storage, transmission and playing of music information. A DAC is a device that converts a digital signal into an analog signal in the form of current, voltage, or charge, etc., so that the digital signal can be recognized by the outside world.
In the prior art, the DAC architecture includes three types, namely a resistor string, an R2R resistor network and a current source array. As shown in fig. 1, taking R2R resistor network as an example, the R2R resistor network is easy to generate analog signals obtained by conversion due to the difference between resistors, and the specific principle is as follows:
the n-bit R2R output voltage Vo is written in weighted form: vo-k 0V 0+ k 1V 1+ k 2V 2+ … + kn Vn;
ideally:
kx(x=0 to n);
kn=1/2;
kn-1=1/4;
kn-2=1/8;
kn-3=1/16;
Kx=1/2n-x+1=2x-n-1;
because of the error between the resistors in the R2R resistor network, kx may deviate from 2x-n-1, resulting in distortion of the final analog signal due to the deviation.
The present invention is directed to provide a circuit compensation scheme for encoding a digital signal input to a digital-to-analog converter to compensate for a deviation, thereby preventing an analog signal converted by the digital-to-analog converter from being distorted.
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Referring to fig. 2, an embodiment of the invention provides a compensation circuit, including: a signal sampling module 102, a coefficient input module 101, a sample prediction module, a comparison module, an encoding module, and a clock module. The output end of the coefficient input module 101 is connected to the input end of the sampling prediction module, the output ends of the sampling prediction module and the signal sampling module 102 are respectively connected to one input end of the comparison module, and the output end of the comparison module is connected to the input end of the coding module and the input end of the sampling prediction module.
The clock module is used for generating a time sequence control signal and comprises a clock input end 100 and a counter 200 used for counting, wherein the output end of the counter 200 is connected with the input end of the sampling prediction module and the input end of the coding module; counter 200 counts for a specified number of clock cycles each time. In this embodiment, when the count value of the counter 200 is 32, one clock cycle is completed.
Specifically, the signal sampling module 102 is configured to sample an input original digital signal to obtain an input sampling value, and within one clock cycle of the clock module, the signal sampling module 102 performs one-time sampling on the input original digital signal; that is, the counter 200 samples the input original digital signal again every 32 times.
The coefficient input module 101 is used for inputting a deviation coefficient, which has 32 bits in this embodiment. The coefficient input module 101 inputs a deviation coefficient once every time the counter 200 counts, and the sampling prediction module sequentially generates prediction sampling values according to the deviation coefficient and outputs the prediction sampling values to the comparison module.
The comparison module includes a sample comparator 212 for comparing the input sample value with the predicted sample value and outputting the comparison result to the sample prediction module and the encoding module. When the comparison result is that the predicted sampling value is larger than the input sampling value, the comparison result is false; the comparison result is true when the predicted sample value is less than the input sample value.
The encoding module is used for generating and encoding the count value of the counter 200 based on a successive approximation method to obtain a compensation value, storing the compensation value when the comparison result meets a preset condition, outputting the stored compensation value once after one clock period is finished, namely, after the counter 200 counts 32 times, and then recoding the original digital signal based on the compensation value to form a compensation digital signal.
Further, in this embodiment, the sample prediction module includes a sample predictor 211, a sample selector 213, and a sample accumulator 210; the sample predictor 211 is configured to output a predicted sample value based on the deviation factor, and the sample accumulator 210 is configured to store the currently generated predicted sample value.
The output end of the coefficient input module 101 and the output end of the sampling accumulator 210 are connected with the input end of the sampling predictor 211; the output end of the sampling predictor 211, the output end of the comparison module and the output end of the sampling accumulator 210 are connected with the input end of the sampling selector 213; the output of the sample selector 213 is connected to the input of the sample accumulator 210.
It will be appreciated that when the comparison result is false, the sample selector 213 selects the sample accumulator 210, and the sample accumulator 210 is actuated by the output signal to the sample accumulator 210, the sample accumulator 210 storing the currently generated predicted sample value. When the comparison result is true, the sample selector 213 selects the sample predictor 211, outputs a signal to the sample predictor 211 to operate the sample predictor 211, and outputs the predicted sample value to the sample accumulator 210 again according to the deviation coefficient.
In this embodiment, the output terminal of the counter 200 is connected to the sample accumulator 210, and each time a clock cycle elapses, that is, when the count value of the counter 200 reaches 32, the counter 200 sends a clear signal to the sample accumulator 210, so that the sample accumulator 210 clears the stored predicted sample value.
Further, the encoding module includes an encoding generator 201, an output terminal of the counter 200 is connected to an input terminal of the encoding generator 201, and the encoding generator 201 is configured to output a count value x of the counter 200 as a binary code y according to the following formula:
y=2x
in addition, the encoding module further includes an encoding predictor 203, an encoding selector 204, and an encoding accumulator 202; the coding predictor 203 is used for predicting according to the binary coding y and outputting a compensation value according to a prediction result; the code accumulator 202 is used to store the currently generated compensation value.
The output end of the code generator 201 and the output end of the code selector 204 are connected with the input end of the code accumulator 202, the output end of the code generator 201 and the output end of the code accumulator 202 are connected with the input end of the code predictor 203, and the output end of the code accumulator 202, the output end of the code predictor 203 and the output end of the comparison module are connected with the input end of the code selector 204.
It is to be understood that, in the present embodiment, the coding predictor 203 and the sampling predictor 211 both employ adders.
In this embodiment, when the comparison result is false, the code selector 204 selects the code accumulator 202, sends a signal to the code accumulator 202, and causes the code accumulator 202 to act to store the compensation value; when the comparison result is true, the code selector 204 sends a signal to the code predictor 203 to operate the code predictor 203, performs prediction again from the binary code y, and outputs a compensation value from the code output terminal 103 based on the prediction result.
In this embodiment, the output end of the counter 200 is connected to the code accumulator 202, and each time a clock cycle passes, that is, when the count value of the counter 200 reaches 32, the counter 200 sends a clear signal to the code accumulator 202, so that the code accumulator 202 clears the stored compensation value.
Referring to fig. 3, based on the foregoing embodiments, the present invention further provides a digital-to-analog conversion apparatus, including the compensation circuit a as described above, and further including a digital-to-analog conversion circuit B; the digital-to-analog conversion circuit B is used for receiving the compensation digital signal formed in the compensation circuit A and converting the compensation digital signal into an analog signal.
Specifically, in this embodiment, the digital-to-analog conversion circuit B may be an R2R resistor network, or may be another type of digital-to-analog conversion circuit.
The invention compensates the original digital signal input into the digital-to-analog conversion circuit B in the digital domain by the compensation circuit A and adopting an FPGA method, thereby reducing the requirement on the resistance precision, and meanwhile, the compensation circuit has simple structure, low cost and easy realization.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1.一种补偿电路,其特征在于,包括:信号采样模块、系数输入模块、采样预测模块、比较模块以及编码模块;1. a compensation circuit is characterized in that, comprising: a signal sampling module, a coefficient input module, a sampling prediction module, a comparison module and an encoding module; 所述信号采样模块用于对输入的原始数字信号进行采样获得输入采样值,所述系数输入模块用于逐次输入偏差系数,所述采样预测模块用于根据所述偏差系数逐次生成预测采样值;所述比较模块用于逐次比较所述输入采样值和预测采样值,并输出比较结果;The signal sampling module is used for sampling the input original digital signal to obtain the input sample value, the coefficient input module is used for successively inputting the deviation coefficient, and the sampling prediction module is used for successively generating the predicted sample value according to the deviation coefficient; The comparison module is used to compare the input sample value and the predicted sample value successively, and output the comparison result; 所述编码模块用于逐次编码得到补偿值,在所述比较结果满足预设条件时存储所述补偿值,并基于所存储的所述补偿值对所述原始数字信号进行编码,形成补偿数字信号;The encoding module is used for successive encoding to obtain the compensation value, and when the comparison result satisfies the preset condition, the compensation value is stored, and the original digital signal is encoded based on the stored compensation value to form a compensation digital signal ; 所述系数输入模块初次输入的偏差系数为预先设定值。The deviation coefficient input by the coefficient input module for the first time is a preset value. 2.根据权利要求1所述的补偿电路,其特征在于,还包括用于生成时序控制信号的时钟模块,所述时钟模块包括计数器,所述计数器的输出端连接所述采样预测模块的输入端和所述编码模块的输入端;2 . The compensation circuit according to claim 1 , further comprising a clock module for generating timing control signals, the clock module comprising a counter, and an output end of the counter is connected to an input end of the sampling prediction module. 3 . and the input end of the encoding module; 所述计数器每进行一次计数,所述系数输入模块输入一次偏差系数;所述采样预测模块根据所述系数输入模块输入的偏差系数依次生成预测采样值;Each time the counter counts, the coefficient input module inputs a deviation coefficient; the sampling prediction module sequentially generates predicted sampling values according to the deviation coefficient input by the coefficient input module; 所述计数器每进行指定数量的计数为一个时钟周期,在所述时钟模块的一个时钟周期内,所述信号采样模块对输入的原始数字信号进行一次采样;Each time the counter performs a specified number of counts as one clock cycle, within one clock cycle of the clock module, the signal sampling module samples the input original digital signal once; 每经过一个时钟周期,所述编码模块输出一次所述补偿值。The encoding module outputs the compensation value every time a clock cycle passes. 3.根据权利要求2所述的补偿电路,其特征在于,所述系数输入模块的输出端连接所述采样预测模块的输入端,所述采样预测模块的输出端和所述信号采样模块的输出端分别连接所述比较模块的一个输入端,所述比较模块的输出端连接所述编码模块的输入端和所述采样预测模块的输入端。3. The compensation circuit according to claim 2, wherein the output of the coefficient input module is connected to the input of the sampling prediction module, the output of the sampling prediction module and the output of the signal sampling module The terminals are respectively connected to an input terminal of the comparison module, and the output terminal of the comparison module is connected to the input terminal of the encoding module and the input terminal of the sampling prediction module. 4.根据权利要求3所述的补偿电路,其特征在于,所述采样预测模块包括采样预测器、采样选择器和采样累加器;所述采样预测器用于根据所述偏差系数输出预测采样值,所述采样累加器用于存储当前生成的所述预测采样值;4. The compensation circuit according to claim 3, wherein the sampling prediction module comprises a sampling predictor, a sampling selector and a sampling accumulator; the sampling predictor is configured to output a predicted sampling value according to the deviation coefficient, The sample accumulator is used to store the currently generated predicted sample value; 所述系数输入模块的输出端和所述采样累加器的输出端连接所述采样预测器的输入端;所述采样预测器的输出端、所述比较模块的输出端和所述采样累加器的输出端连接所述采样选择器的输入端;所述采样选择器的输出端连接所述采样累加器的输入端。The output end of the coefficient input module and the output end of the sampling accumulator are connected to the input end of the sampling predictor; the output end of the sampling predictor, the output end of the comparison module and the output end of the sampling accumulator are connected. The output end is connected to the input end of the sampling selector; the output end of the sampling selector is connected to the input end of the sampling accumulator. 5.根据权利要求4所述的补偿电路,其特征在于,当所述比较结果为预测采样值大于输入采样值时,所述采样选择器输出信号至所述采样累加器使所述采样累加器动作;当所述比较结果为预测采样值小于输入采样值时,所述采样选择器输出信号至所述采样预测器使所述采样预测器动作。5. The compensation circuit according to claim 4, wherein when the comparison result is that the predicted sampling value is greater than the input sampling value, the sampling selector outputs a signal to the sampling accumulator to make the sampling accumulator Action; when the comparison result is that the predicted sample value is smaller than the input sample value, the sample selector outputs a signal to the sample predictor to make the sample predictor act. 6.根据权利要求4所述的补偿电路,其特征在于,所述计数器的输出端连接采样累加器,每经过一个时钟周期,所述计数器向所述采样累加器发送清零信号,使所述采样累加器清空存储的预测采样值。6. The compensation circuit according to claim 4, wherein the output end of the counter is connected to a sampling accumulator, and each time a clock cycle passes, the counter sends a clearing signal to the sampling accumulator, so that the The sample accumulator clears the stored predicted sample values. 7.根据权利要求2所述的补偿电路,其特征在于,所述编码模块包括编码生成器,所述计数器的输出端连接所述编码生成器的输入端,所述编码生成器用于根据如下公式将所述计数器的计数值x输出二进制编码y:7. The compensation circuit according to claim 2, wherein the encoding module comprises a code generator, an output end of the counter is connected to an input end of the code generator, and the code generator is used for the following formula: Output the count value x of the counter to the binary code y: y=2xy= 2x . 8.根据权利要求7所述的补偿电路,其特征在于,所述编码模块还包括编码预测器、编码选择器和编码累加器;所述编码预测器用于根据所述二进制编码输出补偿值,所述编码累加器用于存储当前生成的补偿值;8. The compensation circuit according to claim 7, wherein the coding module further comprises a coding predictor, a coding selector and a coding accumulator; the coding predictor is configured to output a compensation value according to the binary code, the The encoding accumulator is used to store the currently generated compensation value; 所述编码生成器的输出端和所述编码选择器的输出端连接所述编码累加器的输入端,所述编码生成器的输出端和所述编码累加器的输出端连接所述编码预测器的输入端,所述编码累加器的输出端、所述编码预测器的输出端和所述比较模块的输出端连接所述编码选择器的输入端。The output end of the code generator and the output end of the code selector are connected to the input end of the code accumulator, and the output end of the code generator and the output end of the code accumulator are connected to the code predictor The input end of the code accumulator, the output end of the code predictor and the output end of the comparison module are connected to the input end of the code selector. 9.根据权利要求8所述的补偿电路,其特征在于,当所述比较结果为预测采样值大于输入采样值时,所述编码选择器发送信号至所述编码累加器,使所述编码累加器动作;当所述比较结果为预测采样值小于输入采样值时,所述编码选择器发送信号至所述编码预测器,使所述编码预测器动作。9 . The compensation circuit according to claim 8 , wherein when the comparison result is that the predicted sample value is greater than the input sample value, the code selector sends a signal to the code accumulator to cause the code to accumulate. 10 . When the comparison result is that the predicted sample value is smaller than the input sample value, the encoding selector sends a signal to the encoding predictor to make the encoding predictor act. 10.一种数模转换装置,其特征在于,包括如权利要求1至9任一项所述的补偿电路,还包括数模转换电路;10. A digital-to-analog conversion device, comprising the compensation circuit as claimed in any one of claims 1 to 9, and a digital-to-analog conversion circuit; 所述数模转换电路用于接收所述补偿电路中形成的补偿数字信号,并转换为模拟信号。The digital-to-analog conversion circuit is used for receiving the compensation digital signal formed in the compensation circuit and converting it into an analog signal.
CN202110679601.XA 2021-06-18 2021-06-18 A compensation circuit and a digital-to-analog conversion device Active CN113381758B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110679601.XA CN113381758B (en) 2021-06-18 2021-06-18 A compensation circuit and a digital-to-analog conversion device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110679601.XA CN113381758B (en) 2021-06-18 2021-06-18 A compensation circuit and a digital-to-analog conversion device

Publications (2)

Publication Number Publication Date
CN113381758A true CN113381758A (en) 2021-09-10
CN113381758B CN113381758B (en) 2024-11-12

Family

ID=77577800

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110679601.XA Active CN113381758B (en) 2021-06-18 2021-06-18 A compensation circuit and a digital-to-analog conversion device

Country Status (1)

Country Link
CN (1) CN113381758B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103036564A (en) * 2011-10-07 2013-04-10 Nxp股份有限公司 Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter
CN105680864A (en) * 2015-12-31 2016-06-15 杭州士兰微电子股份有限公司 Successive approximation analog-digital converter, analog-digital conversion method and sensing signal processing device
CN107994904A (en) * 2018-01-29 2018-05-04 北京特邦微电子科技有限公司 Digital analog converter
CN111049520A (en) * 2018-10-11 2020-04-21 瑞昱半导体股份有限公司 Digital-to-analog converter device and correction method
CN111095802A (en) * 2017-09-11 2020-05-01 美国亚德诺半导体公司 Adaptive analog-to-digital converter
WO2020190340A1 (en) * 2019-10-29 2020-09-24 Futurewei Technologies, Inc. Successive approximation analog to digital converter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103036564A (en) * 2011-10-07 2013-04-10 Nxp股份有限公司 Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter
CN105680864A (en) * 2015-12-31 2016-06-15 杭州士兰微电子股份有限公司 Successive approximation analog-digital converter, analog-digital conversion method and sensing signal processing device
CN111095802A (en) * 2017-09-11 2020-05-01 美国亚德诺半导体公司 Adaptive analog-to-digital converter
CN107994904A (en) * 2018-01-29 2018-05-04 北京特邦微电子科技有限公司 Digital analog converter
CN111049520A (en) * 2018-10-11 2020-04-21 瑞昱半导体股份有限公司 Digital-to-analog converter device and correction method
WO2020190340A1 (en) * 2019-10-29 2020-09-24 Futurewei Technologies, Inc. Successive approximation analog to digital converter

Also Published As

Publication number Publication date
CN113381758B (en) 2024-11-12

Similar Documents

Publication Publication Date Title
CN105591651B (en) Successive approximation register analog-to-digital converter and related method thereof
CN111654285B (en) Digital background calibration method for capacitor mismatch and gain error of pipeline SAR ADC
US8599059B1 (en) Successive approximation register analog-digital converter and method for operating the same
CN111953347B (en) A Correction Method Applicable to Two-Step Monoslope Analog-to-Digital Converter
CN111313900A (en) Two-step double-slope analog-to-digital converter and analog-to-digital conversion method thereof
JPH07193509A (en) Thermometer binary encoding method
CN107493104A (en) Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof
TWI792438B (en) Signal converter device, dynamic element matching circuit, and dynamic element matching method
JP2015171087A (en) Analog/digital conversion circuit
JP6422073B2 (en) A / D conversion circuit
KR100294787B1 (en) Sub-ranging analog-to-digital converter with open-loop differential amplifiers
JP2006121378A (en) A/d converter
CN111628772B (en) High-speed high-precision time domain analog-to-digital converter
CN113381758A (en) Compensation circuit and digital-to-analog conversion device
US11258454B2 (en) Analog-digital converter
WO2017145494A1 (en) Analog-to-digital converter, electronic device, and method for controlling analog-to-digital converter
CN116318161B (en) Multi-step monoslope analog-to-digital conversion circuit and control method for image sensor
CN110048719A (en) A kind of parallel comparison A/D C of segmentation
TWI726822B (en) Signal converting apparatus
JP2014236373A (en) A/d conversion device
CN101594148B (en) A Flash ADC with Current Interpolation Structure
KR100301041B1 (en) Analog to digital converter of flash type
Li Design of high speed folding and interpolating analog-to-digital converter
CN107517059B (en) Circuit and method for improving conversion speed of analog-to-digital converter
JP6633135B2 (en) Tent mapping operation circuit and A / D conversion circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant