CN113381758A - Compensation circuit and digital-to-analog conversion device - Google Patents
Compensation circuit and digital-to-analog conversion device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
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Abstract
The invention discloses a compensating circuit and a digital-to-analog conversion device.A signal sampling module is used for sampling an input original digital signal to obtain an input sampling value, a coefficient input module is used for inputting a deviation coefficient, and a sampling prediction module generates a prediction sampling value according to the deviation coefficient; the comparison module compares the input sampling value with the predicted sampling value and outputs a comparison result; the coding module codes based on a successive approximation method to obtain a compensation value, stores the compensation value when a comparison result meets a preset condition, and recodes the original digital signal based on the stored compensation value to form a compensated digital signal. The invention codes the input original digital signal based on the successive approximation method, so that the digital signal is coded before entering the digital-to-analog conversion circuit to eliminate the deviation, thereby avoiding the distortion of the analog signal. The compensation scheme provided by the invention does not need to change the structure of the digital-to-analog conversion circuit, has a simple circuit structure, can reduce the cost and is easy to realize.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a compensation circuit and a digital-to-analog conversion device.
Background
DAC (Digital to Analog converter) is a device that converts Digital signals into Analog signals, and is widely used in Digital circuits, and by using Digital signals to process data in Digital circuits, the circuits can obtain higher anti-interference capability, and the data processing method is more flexible, but at the input and output ends of signals, feedback signals and controlled object control quantities may still be Analog signals, and Analog input quantities can be converted into Digital signals by adc (Analog to Digital converter), and Digital signals are reduced into Analog signals by DAC at the signal output end.
The R2R resistor network is a traditional digital-to-analog conversion method, and has the advantages of simple principle, easy implementation, etc., but because the error between the resistors can cause nonlinear distortion, which is usually serious, the R2R resistor network has very high precision requirement on the resistors, and the resistors need to be strictly selected and adjusted, resulting in complex production and high cost. In order to solve the above problems, the conventional techniques reduce distortion by a series, parallel, bipolar, or the like, in many cases, starting from the resistor itself, but such a compensation circuit is difficult to realize because it has a complicated structure and a large circuit area.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a compensation circuit and a digital-to-analog conversion device, which solve the problem that the prior art reduces the distortion of an R2R resistance network in a series connection mode, a parallel connection mode, a bipolar mode and the like, and the compensation circuit is complex in structure and large in circuit area, so that the compensation circuit is difficult to realize.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a compensation circuit, comprising: the device comprises a signal sampling module, a coefficient input module, a sampling prediction module, a comparison module and an encoding module;
the signal sampling module is used for sampling an input original digital signal to obtain an input sampling value, the coefficient input module is used for inputting a deviation coefficient, and the sampling prediction module is used for generating a prediction sampling value according to the deviation coefficient; the comparison module is used for comparing the input sampling value with the predicted sampling value and outputting a comparison result;
and the coding module codes based on a successive approximation method to obtain a compensation value, stores the compensation value when the comparison result meets a preset condition, and recodes the original digital signal based on the stored compensation value to form a compensation digital signal.
Optionally, the compensation circuit further includes a clock module for generating a timing control signal, where the clock module includes a counter, and an output end of the counter is connected to an input end of the sampling prediction module and an input end of the encoding module;
the coefficient input module inputs a deviation coefficient once when the counter counts once; the sampling prediction module sequentially generates prediction sampling values according to the deviation coefficients input by the coefficient input module;
the counter counts a specified number of times to form a clock cycle, and the signal sampling module samples an input original digital signal once in one clock cycle of the clock module.
Optionally, an output end of the coefficient input module is connected to an input end of the sampling prediction module, an output end of the sampling prediction module and an output end of the signal sampling module are respectively connected to an input end of the comparison module, and an output end of the comparison module is connected to an input end of the encoding module and an input end of the sampling prediction module.
Optionally, the sample prediction module comprises a sample predictor, a sample selector and a sample accumulator; the sampling predictor is used for outputting a prediction sampling value according to the deviation coefficient, and the sampling accumulator is used for storing the currently generated prediction sampling value;
the output end of the coefficient input module and the output end of the sampling accumulator are connected with the input end of the sampling predictor; the output end of the sampling predictor, the output end of the comparison module and the output end of the sampling accumulator are connected with the input end of the sampling selector; the output end of the sampling selector is connected with the input end of the sampling accumulator.
Optionally, when the comparison result is that the predicted sample value is greater than the input sample value, the sample selector outputs a signal to the sample accumulator to actuate the sample accumulator; and when the comparison result is that the predicted sampling value is smaller than the input sampling value, the sampling selector outputs a signal to the sampling predictor to enable the sampling predictor to act.
Optionally, the output end of the counter is connected to a sampling accumulator, and the counter sends a clear signal to the sampling accumulator every time a clock cycle elapses, so that the sampling accumulator clears the stored predicted sampling value.
Optionally, the encoding module includes an encoding generator, an output end of the counter is connected to an input end of the encoding generator, and the encoding generator is configured to output a count value x of the counter as a binary code y according to the following formula:
y＝2x。
optionally, the encoding module further comprises an encoding predictor, an encoding selector and an encoding accumulator; the coding predictor is used for outputting a compensation value according to the binary coding, and the coding accumulator is used for storing the currently generated compensation value;
the output end of the code generator and the output end of the code selector are connected with the input end of the code accumulator, the output end of the code generator and the output end of the code accumulator are connected with the input end of the code predictor, and the output end of the code accumulator, the output end of the code predictor and the output end of the comparison module are connected with the input end of the code selector.
Optionally, when the comparison result is that the predicted sample value is greater than the input sample value, the encoding selector sends a signal to the encoding accumulator to actuate the encoding accumulator; and when the comparison result shows that the prediction sampling value is smaller than the input sampling value, the coding selector sends a signal to the coding predictor to enable the coding predictor to act.
The invention also provides a digital-to-analog conversion device, which comprises the compensation circuit and a digital-to-analog conversion circuit;
the digital-to-analog conversion circuit is used for receiving the compensation digital signal formed in the compensation circuit and converting the compensation digital signal into an analog signal.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a compensation circuit and a digital-to-analog conversion device, which encode an input original digital signal based on a successive approximation method according to a preset deviation coefficient, so that the digital signal is encoded before entering a digital-to-analog conversion circuit to eliminate deviation, thereby avoiding the distortion of an analog signal. The compensation scheme provided by the invention does not need to change the structure of the digital-to-analog conversion circuit, has a simple circuit structure, can reduce the cost and is easy to realize.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a prior art R2R resistor network;
FIG. 2 is a schematic diagram of a compensation circuit according to the present invention;
fig. 3 is a schematic structural diagram of a digital-to-analog conversion apparatus provided in the present invention.
In the above figures: 100. a clock input; 101. a coefficient input module; 102. a signal sampling module; 103. a code output end; 200. a counter; 201. a code generator; 202. a coding accumulator; 203. a coding predictor; 204. a code selector; 210. a sampling accumulator; 211. a sampling predictor; 212. a sampling comparator; 213. a sampling selector; A. a compensation circuit; B. a digital-to-analog conversion circuit.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
To facilitate understanding of the technical solutions of the present invention, the technical background of the present invention is briefly introduced here:
digital-to-analog converter (DAC) is an indispensable technical means for Digital storage, transmission and playing of music information. A DAC is a device that converts a digital signal into an analog signal in the form of current, voltage, or charge, etc., so that the digital signal can be recognized by the outside world.
In the prior art, the DAC architecture includes three types, namely a resistor string, an R2R resistor network and a current source array. As shown in fig. 1, taking R2R resistor network as an example, the R2R resistor network is easy to generate analog signals obtained by conversion due to the difference between resistors, and the specific principle is as follows:
the n-bit R2R output voltage Vo is written in weighted form: vo-k 0V 0+ k 1V 1+ k 2V 2+ … + kn Vn;
ideally:
kx(x＝0 to n)；
kn＝1/2；
kn-1＝1/4；
kn-2＝1/8；
kn-3＝1/16；
…
Kx＝1/2n-x+1＝2x-n-1；
because of the error between the resistors in the R2R resistor network, kx may deviate from 2x-n-1, resulting in distortion of the final analog signal due to the deviation.
The present invention is directed to provide a circuit compensation scheme for encoding a digital signal input to a digital-to-analog converter to compensate for a deviation, thereby preventing an analog signal converted by the digital-to-analog converter from being distorted.
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Referring to fig. 2, an embodiment of the invention provides a compensation circuit, including: a signal sampling module 102, a coefficient input module 101, a sample prediction module, a comparison module, an encoding module, and a clock module. The output end of the coefficient input module 101 is connected to the input end of the sampling prediction module, the output ends of the sampling prediction module and the signal sampling module 102 are respectively connected to one input end of the comparison module, and the output end of the comparison module is connected to the input end of the coding module and the input end of the sampling prediction module.
The clock module is used for generating a time sequence control signal and comprises a clock input end 100 and a counter 200 used for counting, wherein the output end of the counter 200 is connected with the input end of the sampling prediction module and the input end of the coding module; counter 200 counts for a specified number of clock cycles each time. In this embodiment, when the count value of the counter 200 is 32, one clock cycle is completed.
Specifically, the signal sampling module 102 is configured to sample an input original digital signal to obtain an input sampling value, and within one clock cycle of the clock module, the signal sampling module 102 performs one-time sampling on the input original digital signal; that is, the counter 200 samples the input original digital signal again every 32 times.
The coefficient input module 101 is used for inputting a deviation coefficient, which has 32 bits in this embodiment. The coefficient input module 101 inputs a deviation coefficient once every time the counter 200 counts, and the sampling prediction module sequentially generates prediction sampling values according to the deviation coefficient and outputs the prediction sampling values to the comparison module.
The comparison module includes a sample comparator 212 for comparing the input sample value with the predicted sample value and outputting the comparison result to the sample prediction module and the encoding module. When the comparison result is that the predicted sampling value is larger than the input sampling value, the comparison result is false; the comparison result is true when the predicted sample value is less than the input sample value.
The encoding module is used for generating and encoding the count value of the counter 200 based on a successive approximation method to obtain a compensation value, storing the compensation value when the comparison result meets a preset condition, outputting the stored compensation value once after one clock period is finished, namely, after the counter 200 counts 32 times, and then recoding the original digital signal based on the compensation value to form a compensation digital signal.
Further, in this embodiment, the sample prediction module includes a sample predictor 211, a sample selector 213, and a sample accumulator 210; the sample predictor 211 is configured to output a predicted sample value based on the deviation factor, and the sample accumulator 210 is configured to store the currently generated predicted sample value.
The output end of the coefficient input module 101 and the output end of the sampling accumulator 210 are connected with the input end of the sampling predictor 211; the output end of the sampling predictor 211, the output end of the comparison module and the output end of the sampling accumulator 210 are connected with the input end of the sampling selector 213; the output of the sample selector 213 is connected to the input of the sample accumulator 210.
It will be appreciated that when the comparison result is false, the sample selector 213 selects the sample accumulator 210, and the sample accumulator 210 is actuated by the output signal to the sample accumulator 210, the sample accumulator 210 storing the currently generated predicted sample value. When the comparison result is true, the sample selector 213 selects the sample predictor 211, outputs a signal to the sample predictor 211 to operate the sample predictor 211, and outputs the predicted sample value to the sample accumulator 210 again according to the deviation coefficient.
In this embodiment, the output terminal of the counter 200 is connected to the sample accumulator 210, and each time a clock cycle elapses, that is, when the count value of the counter 200 reaches 32, the counter 200 sends a clear signal to the sample accumulator 210, so that the sample accumulator 210 clears the stored predicted sample value.
Further, the encoding module includes an encoding generator 201, an output terminal of the counter 200 is connected to an input terminal of the encoding generator 201, and the encoding generator 201 is configured to output a count value x of the counter 200 as a binary code y according to the following formula:
y＝2x。
in addition, the encoding module further includes an encoding predictor 203, an encoding selector 204, and an encoding accumulator 202; the coding predictor 203 is used for predicting according to the binary coding y and outputting a compensation value according to a prediction result; the code accumulator 202 is used to store the currently generated compensation value.
The output end of the code generator 201 and the output end of the code selector 204 are connected with the input end of the code accumulator 202, the output end of the code generator 201 and the output end of the code accumulator 202 are connected with the input end of the code predictor 203, and the output end of the code accumulator 202, the output end of the code predictor 203 and the output end of the comparison module are connected with the input end of the code selector 204.
It is to be understood that, in the present embodiment, the coding predictor 203 and the sampling predictor 211 both employ adders.
In this embodiment, when the comparison result is false, the code selector 204 selects the code accumulator 202, sends a signal to the code accumulator 202, and causes the code accumulator 202 to act to store the compensation value; when the comparison result is true, the code selector 204 sends a signal to the code predictor 203 to operate the code predictor 203, performs prediction again from the binary code y, and outputs a compensation value from the code output terminal 103 based on the prediction result.
In this embodiment, the output end of the counter 200 is connected to the code accumulator 202, and each time a clock cycle passes, that is, when the count value of the counter 200 reaches 32, the counter 200 sends a clear signal to the code accumulator 202, so that the code accumulator 202 clears the stored compensation value.
Referring to fig. 3, based on the foregoing embodiments, the present invention further provides a digital-to-analog conversion apparatus, including the compensation circuit a as described above, and further including a digital-to-analog conversion circuit B; the digital-to-analog conversion circuit B is used for receiving the compensation digital signal formed in the compensation circuit A and converting the compensation digital signal into an analog signal.
Specifically, in this embodiment, the digital-to-analog conversion circuit B may be an R2R resistor network, or may be another type of digital-to-analog conversion circuit.
The invention compensates the original digital signal input into the digital-to-analog conversion circuit B in the digital domain by the compensation circuit A and adopting an FPGA method, thereby reducing the requirement on the resistance precision, and meanwhile, the compensation circuit has simple structure, low cost and easy realization.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A compensation circuit, comprising: the device comprises a signal sampling module, a coefficient input module, a sampling prediction module, a comparison module and an encoding module;
the signal sampling module is used for sampling an input original digital signal to obtain an input sampling value, the coefficient input module is used for inputting a deviation coefficient one by one, and the sampling prediction module is used for generating a prediction sampling value one by one according to the deviation coefficient; the comparison module is used for successively comparing the input sampling value with the predicted sampling value and outputting a comparison result;
the coding module is used for coding successively to obtain a compensation value, storing the compensation value when the comparison result meets a preset condition, and coding the original digital signal based on the stored compensation value to form a compensation digital signal;
the deviation coefficient input for the first time by the coefficient input module is a preset value.
2. The compensation circuit of claim 1, further comprising a clock module for generating a timing control signal, the clock module comprising a counter, an output of the counter being coupled to an input of the sample prediction module and an input of the encoding module;
the coefficient input module inputs a deviation coefficient once when the counter counts once; the sampling prediction module sequentially generates prediction sampling values according to the deviation coefficients input by the coefficient input module;
the counter counts every specified number to be one clock cycle, and the signal sampling module samples input original digital signals once in one clock cycle of the clock module;
the encoding module outputs the compensation value once every one clock cycle.
3. The compensation circuit of claim 2, wherein an output of the coefficient input module is connected to an input of the sampling prediction module, an output of the sampling prediction module and an output of the signal sampling module are respectively connected to an input of the comparison module, and an output of the comparison module is connected to an input of the coding module and an input of the sampling prediction module.
4. The compensation circuit of claim 3, wherein the sample prediction module comprises a sample predictor, a sample selector, and a sample accumulator; the sampling predictor is used for outputting a prediction sampling value according to the deviation coefficient, and the sampling accumulator is used for storing the currently generated prediction sampling value;
the output end of the coefficient input module and the output end of the sampling accumulator are connected with the input end of the sampling predictor; the output end of the sampling predictor, the output end of the comparison module and the output end of the sampling accumulator are connected with the input end of the sampling selector; the output end of the sampling selector is connected with the input end of the sampling accumulator.
5. The compensation circuit of claim 4 wherein the sample selector outputs a signal to the sample accumulator to actuate the sample accumulator when the comparison result is that the predicted sample value is greater than the input sample value; and when the comparison result is that the predicted sampling value is smaller than the input sampling value, the sampling selector outputs a signal to the sampling predictor to enable the sampling predictor to act.
6. The compensation circuit of claim 4, wherein the output of the counter is coupled to a sample accumulator, and wherein each clock cycle the counter sends a clear signal to the sample accumulator to clear the sample accumulator of the stored predicted sample value.
7. The compensation circuit of claim 2, wherein the encoding module comprises an encoding generator, an output of the counter is connected to an input of the encoding generator, and the encoding generator is configured to output a count value x of the counter as a binary code y according to the following formula:
y＝2x。
8. the compensation circuit of claim 7, wherein the coding module further comprises a code predictor, a code selector, and a code accumulator; the coding predictor is used for outputting a compensation value according to the binary coding, and the coding accumulator is used for storing the currently generated compensation value;
the output end of the code generator and the output end of the code selector are connected with the input end of the code accumulator, the output end of the code generator and the output end of the code accumulator are connected with the input end of the code predictor, and the output end of the code accumulator, the output end of the code predictor and the output end of the comparison module are connected with the input end of the code selector.
9. The compensation circuit of claim 8 wherein the code selector sends a signal to the code accumulator to actuate the code accumulator when the comparison result is that the predicted sample value is greater than the input sample value; and when the comparison result shows that the prediction sampling value is smaller than the input sampling value, the coding selector sends a signal to the coding predictor to enable the coding predictor to act.
10. A digital-to-analog conversion apparatus comprising the compensation circuit of any one of claims 1 to 9, and further comprising a digital-to-analog conversion circuit;
the digital-to-analog conversion circuit is used for receiving the compensation digital signal formed in the compensation circuit and converting the compensation digital signal into an analog signal.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103036564A (en) * | 2011-10-07 | 2013-04-10 | Nxp股份有限公司 | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| CN105680864A (en) * | 2015-12-31 | 2016-06-15 | 杭州士兰微电子股份有限公司 | Successive approximation analog-digital converter, analog-digital conversion method and sensing signal processing device |
| CN107994904A (en) * | 2018-01-29 | 2018-05-04 | 北京特邦微电子科技有限公司 | Digital analog converter |
| CN111049520A (en) * | 2018-10-11 | 2020-04-21 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| CN111095802A (en) * | 2017-09-11 | 2020-05-01 | 美国亚德诺半导体公司 | Adaptive analog-to-digital converter |
| WO2020190340A1 (en) * | 2019-10-29 | 2020-09-24 | Futurewei Technologies, Inc. | Successive approximation analog to digital converter |
-
2021
- 2021-06-18 CN CN202110679601.XA patent/CN113381758A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103036564A (en) * | 2011-10-07 | 2013-04-10 | Nxp股份有限公司 | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| CN105680864A (en) * | 2015-12-31 | 2016-06-15 | 杭州士兰微电子股份有限公司 | Successive approximation analog-digital converter, analog-digital conversion method and sensing signal processing device |
| CN111095802A (en) * | 2017-09-11 | 2020-05-01 | 美国亚德诺半导体公司 | Adaptive analog-to-digital converter |
| CN107994904A (en) * | 2018-01-29 | 2018-05-04 | 北京特邦微电子科技有限公司 | Digital analog converter |
| CN111049520A (en) * | 2018-10-11 | 2020-04-21 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| WO2020190340A1 (en) * | 2019-10-29 | 2020-09-24 | Futurewei Technologies, Inc. | Successive approximation analog to digital converter |
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