JP6633135B2 - Tent mapping operation circuit and A / D conversion circuit - Google Patents

Description

  The present invention relates to a tent mapping operation circuit for calculating a tent mapping and an A / D conversion circuit for converting an analog voltage into a digital value using the tent mapping operation circuit.

  Conventionally, a parallel type (flash type) A / D conversion circuit shown in FIG. 24 has been known as an A / D conversion circuit. In this example, the analog input signal is supplied to the inverting input terminals of the comparators CMP01 to CMP07 using the seven comparators CMP01 to CMP07. The non-inverting input terminals of the comparators CMP01 to CMP07 are supplied with a threshold voltage obtained by dividing the reference voltage VREF by resistors R01 to R08 connected in series. The comparators CMP01 to CMP07 compare the respective threshold voltages with the input voltages and output H or L to the encoder 110. Digitization is performed by the encoder 110.

  As an improved A / D conversion circuit, there is a “parallel A / D converter” described in Patent Document 1. Patent Document 1 discloses a comparison unit 120 in which a plurality of reference voltages and a plurality of comparators CMP <b> 1 to CMP <b> 9 that determine a magnitude relationship between the reference voltage and the input voltage, and a logical operation based on outputs of the plurality of comparators. And an encoder 130 that detects a change point according to the detection result, and generates a digital code according to the detection result. The comparators CMP1 to CMP9 input an input signal between the first reference voltage and the second reference voltage. It has a ternary determination function that outputs a determination result only when there is a signal, and furthermore, the difference between the first reference voltage and the second reference voltage is the same in all comparators CMP1 to CMP9. Is described.

  A successive approximation type A / D converter circuit shown in FIG. 25 is known as the most widely used A / D converter circuit. This successive approximation type A / D conversion circuit mainly includes a comparator CMP, a successive approximation register 120, and a D / A converter DAC. The analog input signal is held in the sample hold amplifier SH, and the analog input signal is compared with the analog input signal using the output signal of the D / A converter DAC as a threshold. For example, assume that the maximum voltage of the analog input signal is 1V. In the initial state, when the successive approximation register 120 sets the MSB to 1, 0.5 V, which is half of the maximum voltage 1 V, is output from the D / A converter DAC, and the comparator CMP sets the threshold of 0.5 V to the analog input signal. A comparison is made with the voltage. Here, if the voltage value of the analog input signal is larger, the MSB is maintained at one. Subsequently, the second bit of the successive approximation register is set to 1, and the D / A converter DAC outputs 0.75 V obtained by adding 0.25 V to the above 0.5 V, which is a half of the above 0.5 V. This value and the voltage of the analog input signal are compared by the comparator CMP. Here, if the voltage of the input signal is lower than 0.75 V, the second bit of the successive approximation register 120 is set to “0”. Hereinafter, the same processing is continued until the desired resolution is reached. The timing control unit 125 controls the sampling and holding timing of the sample-and-hold amplifier SH and the signal acquisition and signal output timing of the successive approximation register 120.

Further, a ΔΣ (delta sigma) type A / D conversion circuit shown in FIG. 26 is also known as an A / D conversion circuit.
This A / D conversion circuit has a configuration in which the output of a D-FF (D-type flip-flop) is subtracted from an analog input signal via a resistor R2 at a stage preceding the integration circuit 130. The result of the subtraction is applied to the integration circuit 130 and integrated, and the integrated value is compared by the comparator CMP to obtain an output of 1 or 0, which is applied to the D terminal of the D-FF. The above operation for the number of clocks of the D-FF is repeated for one sample, and the output of the D-FF is converted into a digital conversion value by the counter 140.

  Patent Document 2 discloses a discrete-time integrator 1 having an amplification coefficient of s (1-β) and a damping factor of β in a data conversion method based on a scaled β mapping, and a serial connection with the discrete-time integrator 1. An A / D conversion circuit using a β mapping, comprising a quantizer 2 connected thereto and a feedback circuit 3 connected from an output side of the quantizer 2 to an input side of the discrete time integrator 1 is described. Have been. This A / D conversion circuit is a data converter system based on β-mapping suitable for an A / D converter or a chaos generation circuit, which is suitable for implementation by an integrated circuit and can perform stable operation of the circuit. Have been.

  Further, a pipeline type A / D conversion circuit shown in FIG. 27 is also known. This pipeline type A / D conversion circuit has a configuration in which successive approximation types are connected in series. The A / D conversion is divided into several stages and A / D conversion is performed bit by bit. Things.

  More specifically, each stage includes an ADC for A / D converting a signal coming from an input side (or an upper side), a DAC for digitizing an output of the ADC, and a signal coming from the input side (or an upper side). It comprises a residual amplifier for amplifying an analog residual between the signal and the output signal of the DAC. A sample and hold circuit for passing a signal from an upper stage to a lower stage is provided between the stages.

JP 2010-11057 A International Publication No. 2011/125296 pamphlet

  Although the A / D conversion circuit shown in FIG. 24 is the fastest, it requires a comparator CMP which is a multiple of 2 times the number of resolutions, and has a problem that the scale becomes large. That is, this parallel type (flash type) A / D conversion circuit has a problem in that, by increasing the number of resolutions, a comparator is required exponentially and the scale is increased.

  According to the A / D conversion circuit described in Patent Document 1 described above, the number of comparators can be reduced to half, but a parallel (flash type) A / D conversion circuit having a large circuit size is also required. Have common problems.

  According to the successive approximation type A / D converter shown in FIG. 25, only one comparator is required. However, since the bits are sequentially compared, the input voltage signal sampled during the sequence is held by the sample-hold amplifier. And there is a problem that a correct conversion value cannot be obtained due to the movement of the held input voltage value. Further, in this A / D conversion circuit, D / A conversion is necessary for performing successive comparison, and the scale of the D / A conversion unit is increased by increasing the resolution, which causes a problem of process variation of elements.

  The ΔΣ (delta sigma) type A / D conversion circuit shown in FIG. 26 realizes high-precision A / D conversion, but it is necessary to increase the number of samplings in order to increase the accuracy, and high-speed conversion cannot be performed. There is a problem that it is not suitable for a proper conversion.

  The A / D conversion circuit described in Patent Document 2 aims to generate digital data by generating chaos by β-mapping based on an input analog value. It does not have a mechanism to convert it to binary data that can be used. In addition, since it is configured using an integrating circuit like the ΔΣ type A / D conversion, it is not intended to perform the batch conversion for one clock pulse.

  The pipeline type A / D conversion circuit shown in FIG. 27 needs D / A conversion and therefore needs to have a DAC. As shown in FIG. 27, each stage has a residual amplifier and a 1-bit output unit. It is necessary to provide a sample and hold amplifier, and there is a problem that the configuration becomes large.

  FIG. 28 summarizes the features of the conventional A / D conversion, and FIG. 29 shows the relationship between speed and resolution. As is apparent from FIG. 29, the Δ 分解 能 type has a good resolution, the parallel type is relatively poor, and the successive approximation type and the pipeline type are arranged in the middle. From the viewpoint of high-speed conversion, they are arranged in the order of parallel type, pipeline type, successive approximation type, and ΔΣ type.

  An object of the present invention is to provide a tent mapping operation circuit and an A / D conversion circuit.

A tent mapping operation circuit according to the present invention includes a one-time operation unit that performs one-time analog operation of a tent mapping for an input input analog signal, and converts the input analog signal to be input in accordance with the number n of bits of a gray code. A comparator that extracts a 1-bit digital value and outputs a gray code by comparing the input voltage with a predetermined threshold value, subtracts an input voltage from a predetermined voltage value, and multiplies the input voltage by a predetermined value. A plurality of analog arithmetic circuits for performing an operation of multiplying and subtracting a predetermined voltage value from an input voltage value, a switch provided between required analog arithmetic circuits in the plurality of analog arithmetic circuits, and the input analog signal A group of switches provided on a path leading to a required analog operation circuit among the plurality of analog operation circuits, and the input analog signal and a threshold value. Based on the magnitude relation, the operation to control the opening and closing of the switches of the switch for each clock edge, to achieve the operation circuit of the primary functions in the tent mapping function is determined by the magnitude relationship between the threshold value, which is the realization And a control circuit for controlling the analog operation to be performed collectively by the circuit.

A tent mapping operation circuit according to the present invention includes a one-time operation unit that performs one-time analog operation of a tent mapping for an input input analog signal, and converts the input analog signal to be input in accordance with the number n of bits of a gray code. A comparator that extracts a 2-bit digital value by comparing with a threshold value and outputs a gray code, wherein the tent mapping function is a function of a form in which a linear expression is multiplied by a constant. Comprises a first analog arithmetic circuit for performing an operation of multiplying the constant,
A second analog operation circuit that performs the operation of the linear expression, and the input analog signal input to the one-time operation unit is directly led to the first analog operation circuit, or the second analog operation circuit A switch group for guiding or switching a path to the first analog operation circuit via a circuit, and turning on / off the switch group by a clock edge based on the magnitude of the input analog signal input to the single operation unit. A control unit that realizes an operation circuit of a linear function in the tent mapping function determined by the magnitude relationship with the threshold value, and controls the analog operation to be performed collectively by the realized operation circuit. It is characterized by having.

  In the tent mapping operation circuit according to the present invention, the one-time operation unit outputs one bit or two or more predetermined bits.

  In the tent mapping arithmetic circuit according to the present invention, a required analog arithmetic circuit in the analog arithmetic circuit is configured by an operational amplifier or an NMOS transistor.

  In the tent mapping operation circuit according to the present invention, a required analog operation circuit in the analog operation circuit is constituted by an operational amplifier or a PMOS transistor.

  In the tent mapping operation circuit according to the present invention, the one-time operation unit includes an analog operation circuit for subtracting a predetermined number.

An A / D conversion circuit according to the present invention includes one tent mapping operation circuit according to claim 1, a path for feeding back an output of a single operation unit in the tent mapping operation circuit to its own input ,
A buffer for accumulating an output of each one-time operation of the one-time operation unit, wherein the tent mapping operation circuit repeats the operation by the one-time operation unit a predetermined number of times, and outputs a predetermined bit A from the buffer. / D conversion output.

  The A / D conversion circuit according to the present invention is characterized by comprising a conversion means for converting the obtained Gray code into a binary code.

  According to the present invention, an analog operation of a tent mapping can be performed, and an A / D conversion circuit can be obtained using a tent mapping operation circuit.

FIG. 1 is a configuration diagram of an A / D conversion circuit according to a first embodiment of the present invention. Return map of tent mapping. The figure which shows the time series which made r of the formula (1) of a tent mapping a horizontal axis, and made X _{r + 1} a vertical axis. The figure which shows the 4-bit Gray code by the formula (2) of a tent mapping. The figure which shows the tent map image at the time of extracting a bit string for 4 bits from a tent map. Corresponding to FIG. 5, shows a value in the range of the initial value X _0. The figure which shows an example of the circuit which performs a binary conversion of a Gray code. FIG. 2 is a diagram showing a first circuit example of an analog operation circuit used in the A / D conversion circuit according to the present invention. FIG. 4 is a diagram illustrating a second circuit example of the analog operation circuit used in the A / D conversion circuit according to the present invention. FIG. 7 is a detailed configuration diagram of a main part of a second embodiment of the A / D conversion circuit according to the present invention. FIG. 4 is a configuration diagram of an A / D conversion circuit according to a second embodiment of the present invention. 9 is a timing chart showing the operation of the second embodiment of the A / D conversion circuit according to the present invention. FIG. 9 is a configuration diagram of an A / D conversion circuit according to a third embodiment of the present invention. FIG. 14 is a diagram showing a tent map image used in the fourth embodiment of the A / D conversion circuit according to the present invention. FIG. 9 is a configuration diagram of an A / D conversion circuit according to a fourth embodiment of the present invention. FIG. 14 is a diagram showing a tent map image used in the fifth embodiment of the A / D conversion circuit according to the present invention. FIG. 13 is a diagram showing a gray code obtained by a fifth embodiment of the A / D conversion circuit according to the present invention, a converted binary code, and a final digital value obtained by inverting the converted binary code. FIG. 11 is a configuration diagram of an A / D conversion circuit according to a fifth embodiment of the present invention. FIG. 13 is a main part configuration diagram of a fifth embodiment of an A / D conversion circuit according to the present invention. FIG. 20 is a diagram showing a result of performing DC analysis on the circuit of FIG. 19; FIG. 13 is a configuration diagram of an A / D conversion circuit according to a sixth embodiment of the present invention. FIG. 15 is a configuration diagram of a main part of an A / D conversion circuit according to a sixth embodiment of the present invention. FIG. 23 is a diagram illustrating a result of performing a DC analysis on the circuit in FIG. 22. FIG. 2 is a diagram showing a configuration of a conventional parallel (flash) A / D conversion circuit. FIG. 4 is a diagram showing a configuration of a conventional successive approximation A / D conversion circuit. FIG. 3 is a diagram showing a configuration of a conventional ΔΣ (delta sigma) type A / D conversion circuit. FIG. 2 is a diagram illustrating a configuration of a conventional pipelined A / D conversion circuit. The figure which summarized the characteristic of the conventional A / D conversion. The figure which shows the relationship between the speed and resolution of the conventional A / D conversion.

  Hereinafter, an embodiment of a tent mapping operation circuit and an A / D conversion circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted.

Overview

  In the present embodiment, as an example, an A / D (analog to digital) conversion circuit that performs an operation of a tent mapping known as a one-dimensional repetitive mapping by an operational amplifier and converts an analog voltage value into a digital value is proposed.

  Tent maps are commonly known as having chaotic properties. For example, in a tent mapping with a slope of 2, a tent mapping operation is performed from a certain initial value, and a bit “1” is obtained when the mapping takes a value of 0.5 or more, and a bit “0” is obtained when the mapping is less than 0.5. I do. Under such an agreement, the range of possible initial values is equally divided, and when the initial values are obtained starting from each of the equally divided ranges, a gray code corresponding to each range is output. It is known that, for example, “Hidetoshi Okutomi,“ Properties of Initial Value Estimation Method for Pseudo Random Bit Strings Obtained from Tent Mapping ”, issued on Jan. 30, 2012, Cryptography and Information Security Symposium 2012 (SCIS2012) ), Proceedings CD-ROM [2F3-6] ”).

  In the present embodiment, the initial value of the tent mapping is set as an analog voltage value to be sampled, the operation of the tent mapping is performed by an analog operation using an operational amplifier, and a bit is extracted by a comparator to obtain a gray code. Further, binary conversion is performed on the acquired Gray code to obtain an A / D conversion value corresponding to an analog voltage value.

  In the A / D conversion circuit using the tent mapping according to the present embodiment, a batch conversion such as a parallel type (flash type) can be realized without increasing the circuit scale, and the encoding is performed simultaneously with the analog operation. Becomes unnecessary. Further, the A / D conversion circuit using the tent mapping according to the present embodiment does not need to hold the sampled voltage value unlike the successive approximation type A / D conversion circuit, and does not need the D / A conversion circuit. It has various advantages. Further, the circuit scale of the A / D conversion circuit according to the present embodiment is mainly determined by the configuration for performing the repetitive operation of the tent mapping, and if an analog operation circuit having more ideal calculation accuracy is adopted, a high resolution is obtained. Can be. That is, according to this embodiment, a small-scale and high-speed A / D conversion circuit can be obtained.

principle

First, the principle of the embodiment will be described.
[I] Tent Mapping The tent mapping is defined by the following equation (1).

FIG. 2 shows a return map of the tent mapping, and FIG. 3 shows a time series in which r in the equation (1) is set on the horizontal axis and _{Xr + 1} is set on the vertical axis. Figure 2 is a geometric image of the tent map, X _r executes the operations when 2X _r of less than 0.5, perform the operations in the case 2 (1-X _r) of 0.5 or more, the value range and becomes the interval [ [0,1] to perform mapping. FIG. 2 shows a case where the initial value is set to X ₀ = 0.123, and shows an example up to X ₄ = 0.032.

  In the present embodiment, an A / D conversion circuit is configured by using an analog arithmetic circuit that executes the arithmetic operation of Expression (1). As shown in FIG. 3, the processing of extracting the bit “0” when the digital value of the A / D conversion is less than 0.5 and the bit “1” when the digital value is 0.5 or more is continued.

[II] Generation of Gray Code Gray code is known as a numerical code for a digital circuit, which has a feature that the Hamming distance of a code adjacent before and after is always 1 in a binary number.
Gray code is converted by the following equation (2). Here, "b" is a binary bit string.

  FIG. 4 shows a 4-bit Gray code according to equation (2).

Next, generation of a gray code by tent mapping will be described.
The area of the initial value that can be taken in the tent mapping is equally divided, and any value within each area is determined as the initial value, the tent mapping operation is performed, and the bit is set when the mapping takes a value of 0.5 or more. When "1" is acquired and a bit value "0" is acquired when a value less than 0.5 is acquired, and a bit string is continuously acquired from the acquired bit values, a gray code corresponding to each range is output.

As an example here, the initial value region 16 split X _0, select the initial value X ₀ from the respective regions, the tent map image when taking out 4 bits of the bit string from the tent map in the above rules, Fig. It becomes 5. Corresponding to FIG. 5, the value in the range of the initial value X ₀ shown in FIG. As shown in FIG. 6, when taken consecutively the most significant bit of the tent map from the scope of the initial value X _0, the same code as the gray code according to equation (2) is output.

The initial value X ₀ may take any value as long as it is within the range shown in FIG. 6, and a gray code corresponding to each range can be output by repeating the tent mapping. By performing a binary conversion on the Gray code, an original binary bit string can be obtained. FIG. 7 shows a circuit for binary-converting a Gray code. FIG. 4 shows the relationship between the gray code and the bit string of the binary conversion.

Here, it is determined whether the bit string obtained by the calculation of the tent mapping matches the Gray code by tracking the equation.
Bit string of arbitrary n bits before conversion to Gray code

give. i is each bit digit.
When the bit sequence of the gray code and G _i from the equation (2), each bit digit of Gray code

Is represented by
A bit string of tent map X _r, T _r, and _i the number of mapping the (round) r, a bit digit as i.
The value of the most significant bit digit _{Tr, n} for each mapping obtained from the tent mapping is equivalent to the Gray code as follows:

Although it should be, it verifies the most significant bit digit T _R for each _mapping, and _n, whether each bit digit G _i of the Gray code are equal.

Considering the case where the initial value X ₀ is obtained from the intermediate value of each range shown in FIG. 6 (for example, in the case of “n = 4”, in the case of the first section of FIG. Is "0.03125 (0.00001) ₂ "), and if the initial value X ₀ , any initial value X ₀

Initial value X ₀ (r = 0)
The most significant bit of the initial value X ₀ is

And matches the most significant bit _Gn of the Gray code.

One mapping X ₁ (r = 1)
When mapping X _r to consider the calculation results in the case of more than 0.5, in the case of the most significant bit b _n is "1" it is necessary to operate the 1-X _r. In that case, an operation of adding 1 to the one's complement (bit inversion) is performed.
If the bit string considering inversion is α _{1, i} ,

Becomes
Finally, since the operation of 2 _Xr or 2 (1−X _r ) shifts β _{1, i} right by one bit, the bit arrangement T _{1, i} of X after the first tent mapping is

  Equation (5) holds, and it can be seen that the most significant bit of one tent mapping is equal to the second most significant bit of the Gray code.

Two mappings X ₂ (r = 2)
If T _{1, i} (the most significant bit) is 1, the bit sequence considering the inversion is α _{2, i}

And the lower bits are shifted left by one bit for each round.
From these, it is confirmed that the most significant bit string output from the tent mapping is the same as the Gray-coded converted bit string, which leads to the following relationship.

From the arbitrary value X ₀ (b _{0, i} ), the output of the most significant bit “T _{r, n} ” of the tent mapping in order matches the value converted by the Gray code.

Although the above has been confirmed by digital calculation, in the present embodiment, the analog voltage value to be digitally sampled is set as the initial value X ₀ of the tent mapping, the tent mapping is calculated by the analog arithmetic circuit, and the gray code is extracted by the comparator. A digital value is obtained by performing binary conversion using the circuit shown in FIG.

[III] Analog calculation circuit for calculating tent mapping Calculation of tent mapping is performed by analog calculation using an operational amplifier.
The mapping X _r as a voltage value, in the case of less than 0.5 [V], at analog operation of the non-inverting amplifier circuit according to an operational amplifier 30 shown in FIG. 8, performs a computation of _{X r + 1 = 2 X r} , X in the inverting amplifier circuit according to an operational amplifier 31 in FIG. 9 when _r is greater than or equal 0.5 [V], 1 - after performing the calculation of _{X r, X r + 1 =} 2 at the non-inverting amplifier circuit in FIG. 8 (1 _-Perform operation of X _r ). Here, the inverting amplifier circuit of the operational amplifier 31 in FIG. 9 has a resistance ratio of 1 to 1 (amplification factor is 1), and the reference voltage is 0.5 [V]. To calculate 1- _Xr . It should be noted that the inverting amplifier circuit is of a negative feedback type, and since current is generated in the preceding circuit, the resistance value (Ω) of the resistance element is desirably set to a high resistance.

FIG. 10 shows a circuit diagram for performing one operation of the tent mapping of Expression (1). As shown in FIG. 10, the voltage value at the beginning to X _r is, the comparator 24 outputs Low or High levels depending 0.5 [V] below or 0.5 [V] or more, when the clock signal becomes a High state In both cases, the output of the AND circuit whose input is in the high state becomes high, the analog switch SW1 or SW2 is selected, and either of them is conducted. The circuit of FIG. 10 will be described later in detail.

If the switch SW1 is selected, the calculation of X _{r + 1} = 2 X _r is performed, and outputs a voltage level X _{r + 1.} If the switch SW2 is selected, 1 - carried out by the inverting amplifier circuit calculates the X _r (FIG. 9), then the non-inverting amplifier circuit (FIG. 8) at _{X r + 1 = 2 (1} - X r) And outputs a voltage level _{Xr + 1} . The output potential level becomes a calculation result of one tent mapping, and the potential level of this calculation result is again used as an input value to continue the repetitive calculation of the tent mapping (FIG. 10).

  FIG. 1 shows a configuration diagram of an A / D conversion circuit according to the first embodiment of the present invention. The A / D conversion circuit includes a sample and hold unit 11, a calculation unit 12, and a conversion unit 13. The sample-and-hold means 11 samples and holds a signal (analog signal) to be subjected to A / D conversion. The arithmetic means 12 performs a analog operation of the tent mapping on the sampled and held signal, and has a comparator for comparing the initial value and the operation result with a threshold value corresponding to the number of bits of the gray code, and outputs a gray code. . As described above, the analog operation of the tent mapping is performed on the initial value of the analog signal, and the threshold value is compared with “0.5” which is の of the value (“1” in the above example) that the operation result can take. The gray code can be obtained by performing the comparison using the detector. The conversion means 13 converts the Gray code obtained by the calculation means into a binary code. According to the first embodiment, an analog signal can be appropriately converted into a digital signal.

  FIG. 11 shows a configuration diagram of an A / D conversion circuit according to the second embodiment. This second embodiment can be referred to as a batch type, and performs a batch A / D conversion (sampling / quantization / encoding) every time a high edge is received with a high edge of a clock signal as a trigger. It has a configuration. Since this A / D conversion circuit has a 4-bit resolution, a tent mapping operation circuit 1 (1-1 to 1-3), which is a single operation unit for performing one analog operation of the tent mapping, is cascaded in three circuits. Connected and configured. The number of the tent mapping operation circuits 1 as one operation unit is changed according to the resolution. The output of the final stage tent mapping operation circuit 1-3 is given to the comparator CMP.

  The output from the gray code terminal G of the tent mapping operation circuits 1-1 to 1-3 and the output of the comparator CMP are provided to the binary conversion circuit 3, and the binary conversion circuit 3 converts the gray code into a binary code. Is performed. The output of the binary conversion circuit 3 is held in the output buffer 4 and output therefrom.

  The tent mapping operation circuit 1 as a single operation unit is configured as shown in FIG. That is, the tent mapping operation circuit 1 includes a control unit 21, an analog operation circuit 22 as a first operation circuit, an analog operation circuit 23 as a second operation circuit, and (analog) switches SW1 and SW2 as a switch group. ing. The switches SW1 and SW2, which are a group of switches, directly lead the signal input to the one-time arithmetic unit to the first arithmetic circuit, or switch the first arithmetic circuit through the second arithmetic circuit. A group of switches for guiding to or switching the path.

  The control unit 21 controls on / off of the switch group based on the magnitude of the signal input to the one-time calculation unit. The control unit 21 includes a comparator (comparator) 24 for converting an input signal into a gray code (1 bit), and a logic circuit 25 for generating a control signal for controlling the switches SW1 and SW2 based on the output of the comparator 24. You. Here, the logic circuit 25 includes an inverter 25a, AND gates 25b and 25c, and an OR gate 25d. Since the switching timing of the switches SW1 and SW2 is performed after the output of the comparator 24 is determined to be High or Low, the switching can be synchronized by providing a delay circuit in the input clock signal.

  In the present embodiment, since the tent mapping function is a function of a form that multiplies a linear expression by a constant, the analog operation circuit 22 is configured as a first operation circuit that performs an operation of multiplying the constant by an analog operation circuit 23. It is configured as a second arithmetic circuit that performs the arithmetic of the above-mentioned linear expression.

The analog operation circuit (first operation circuit) 22 performs an operation of multiplying the input signal _Xr or 1− _Xr by a constant 2 by analog operation of the non-inverting amplifier circuit using the operational amplifier 30 shown in FIG.

The analog arithmetic circuit (second arithmetic circuit) 23 is an inverting amplifier circuit, has a resistance ratio of 1 to 1 (amplification factor is 1), and has a linear equation in which an input signal _Xr is 1− _Xr. Is calculated.

  The A / D conversion circuit according to the second embodiment configured as described above operates as follows. The analog signal to be converted is provided to the sample and hold amplifier 2 via the switch SW1. The output of the sample hold amplifier 2 is provided to the tent mapping operation circuit 1-1 via the switch SW2. When the clock signal is in the low state, the switch SW1 is in the conducting state and the switch SW2 is in the non-conducting state, and the voltage level of the output of the sample and hold is always synchronized with the input analog signal. Next, when the clock signal changes to the high state, the switch SW1 changes to the non-conductive state, and the voltage level at that time is sampled and held.

Voltage level sampled by the sample and hold amplifier 2, the switch SW2 is turned on, an initial value X ₀ of the tent map, given the tent map calculation circuit 1-1, the operation result X ₁ is outputted. Computation result X ₁ as an input value, given in the following tent map arithmetic circuit 1-2. On the other hand, the comparator 24 of the tent mapping operation circuit 1-1 outputs a signal obtained by determining whether it is 0.5 or more or less than 0.5 to the logic circuit 25, and the high state of the output clock signal of the OR gate 25d is changed to the tent mapping operation. The signal is sent to the circuit 1-2. Such a repetitive operation is performed in the tent mapping calculation circuits 1-1 to 1-3 for the bits of the resolution, and the calculation of the tent mapping is performed.

Each of the calculation results X _{r + 1} obtained by the tent mapping calculation circuits 1-1 to 1-3 is classified into 1 or 0 by a built-in comparator 24 that determines whether the value is 0.5 or more and less than 0.5, and thus, Xr _{+ 1} is gray. The output of the tent mapping operation circuit 1-3 at the last stage where the code is generated is given to the comparator CMP, and is compared with a threshold value 0.5 [V] to be a gray code. The Gray code is converted into a binary code through the binary conversion circuit 3, and a digital value can be finally obtained from the output buffer 4.

  The binary conversion circuit 3 is composed of three exclusive OR circuits as shown in FIG. The uppermost exclusive OR circuit performs an exclusive operation on the MSB and the second digit, and the second exclusive OR circuit outputs the output of the uppermost exclusive OR circuit and the third digit. And the third exclusive OR circuit performs the output of the second exclusive OR circuit and the third digit exclusive operation.

FIG. 12 is a timing chart showing transitions of signal waveforms of each unit when the A / D conversion circuit according to the second embodiment shown in FIG. 11 operates. Each time receiving the High edges of the clock signal, the voltage value of the analog signal at that time as an initial value X ₀ of the tent map, taken by the sample-hold amplifier 2, the tent map in tent mapping operation circuit 1-1 to 1-3 Is performed collectively. The result of the operation shows respective voltage level outputted from the Vout tent mapping operation circuit 1-1 to 1-3 as an analog voltage value as _{X 1, X 2, X 3} .

The analog voltage values X ₀ , X ₁ , X ₂ , and X ₃ are determined to be 0.5 V or more by the comparator 24 in the tent mapping operation circuits 1-1 to 1-3 and the comparator CMP shown in FIG. It is output as a gray code that is distinguished between 1 and 0 depending on whether it is less than 1 or not, and is finally converted into digital values shown as OUT0, OUT1, OUT2, and OUT3 in FIGS. 11 and 12 through binary conversion by the binary conversion circuit 3. Output.

FIG. 12 shows an example in which a series of A / D conversions by the first high edge of the clock signal are executed with the initial value X ₀ = 0.15 [V] of the tent mapping. As a result of the tent map by tent mapping operation circuit _{1-1~1-3, X 0 = 0.15 [V} ], X 1 = 0.30 [V], X 2 = 0.60 [V], X 3 = 0.80 of [V] Voltage level is output. In response to this voltage level, a gray code (0 1 1 1) is output by the comparator 24 in the tent mapping operation circuits 1-1 to 1-3 and the comparator CMP shown in FIG. Finally, a digital output (0 0 1 0) is output.

In the second series of A / D conversion by the high edge of the clock signal, the initial value X ₀ = 0.48 [V] of the tent mapping is taken in, and in the third series of A / D conversion by the high edge of the clock signal. , The initial value of the tent mapping X ₀ = 0.79 [V] is captured, and in the series of A / D conversion by the second high edge of the clock signal, the initial value of the tent mapping X ₀ = 0.63 [V] is captured. FIG. 12 shows that the gray code is obtained and the binary code is obtained by the above-described operation in each round.

"Delay" shown in FIG. 12 corresponds to the time when the clock to be sampled in FIG. 10 is delayed by the delay circuit. If the clock signal becomes Low, because all the switches SW1, SW2 are nonconductive, the voltage level X _{r + 1} (X ₀ shown in FIG. 11 and FIG. 12, X _1, X _2, X ₃ ) is reset.

  Although the reference voltage is set to 1 [V] here, for example, when the reference voltage is set to 10 [V], the threshold value of the comparator is 5 [V], and it is determined that the threshold is 5 [V] or more. become. As described above, the reference voltage and the threshold value of the comparator may be set arbitrarily according to the mounting environment.

The batch type A / D conversion circuit according to the second embodiment is a parallel type (flash type) or a conventional A / D conversion circuit in that the A / D conversion is completed with one clock. Equivalent to pipeline type. A conventional parallel type (flash type) requires 255 (= 2 ⁸ -1) comparators (operational amplifiers) when the resolution is 8 bits with 256 gradations. On the other hand, in the A / D conversion circuit according to the second embodiment, since the number of the tent mapping operation circuits 1 is three in accordance with the number of stages with four bits shown in FIG. It can be seen that only seven are required. One tent mapping operation circuit 1 includes three operational amplifiers. To design an 8-bit circuit, add 3 x 7 = 21 operational amplifiers and add two sample-and-hold and last comparators. It turns out that there are 23 pieces.

Further, considering a circuit with a resolution of 16 bits, the conventional parallel type (flash type) requires 65535 (= 2 ¹⁶ -1) comparators (operational amplifiers), whereas the configuration according to the present embodiment has 15 stages. It can be seen that batch conversion can be configured with about 3 × 15 + 2 = 47. In a parallel type (flash type) A / D conversion circuit (FIG. 24), the divided voltage by each resistor is input as a threshold voltage, and after the quantization by the comparator group by the division with the voltage level of the analog input, the encoding is performed. In the method using tent mapping, a 1/0 bit is extracted by a comparator depending on whether the value is 0.5 or more or less than 0.5, and encoding can be performed simultaneously with analog arithmetic. Become.

  FIG. 13 shows a configuration diagram of an A / D conversion circuit according to the third embodiment. The third embodiment can be referred to as a repetitive type, receives a High edge of a clock signal, performs one tent mapping operation, and holds a voltage level of the operation result by a sample-hold amplifier 38 by a Low edge. The second tent mapping operation is performed in response to the High edge of the next clock signal. In the same manner, a tent mapping operation is performed in response to a High edge of a clock signal, and a gray code is repeatedly and successively extracted one bit at a time.

  The A / D conversion circuit according to the third embodiment includes a sample and hold amplifier 38, a tent mapping operation circuit 1, a register 32, switches SW0, SW1, SW2, and a control unit 5. The switch SW0 is provided on a path for guiding an analog input signal to be subjected to A / D conversion to an input terminal of the sample and hold amplifier 38, and the switch SW1 is a path for guiding an output of the sample and hold amplifier 38 to an input terminal of the tent mapping operation circuit 1. The switch SW2 is provided in a path for guiding the output signal of the tent mapping operation circuit 1 to the input terminal of the sample-hold amplifier 38.

  The control unit 5 is a control unit that controls opening and closing of the switches SW0, SW1, and SW2. When the resolution of the A / D conversion circuit according to the third embodiment is set to N bits, the control unit 5 first sets the switch SW0 to the conductive state in response to the low edge of the clock signal when sampling the analog signal. The signal is taken into the sample and hold amplifier 38. Next, the control unit 5 makes the switch SW0 non-conductive and the switch SW1 conductive at the High edge of the clock signal, and transfers the sampled and held voltage level to the tent mapping operation circuit 1. From the second time on the clock signal, control is performed such that the switch SW2 is turned on (the switch SW1 is turned off) at the Low edge, and the switch SW1 is turned on (the switch SW2 is turned off) at the High edge. The voltage level of the calculation result of the tent mapping by the mapping calculation circuit 1 is sent to the sample hold amplifier 38, and the tent mapping calculation circuit 1 repeats the tent mapping calculation "N-1" times thereafter. The gray code extracted by the comparator 24 in the tent mapping operation circuit 1 and output from the gray code terminal G is stored bit by bit in the register 32, and is transferred to the binary conversion circuit 3 when N bits are stored. The data is transferred and converted, and is controlled via the output buffer 4 so as to finally obtain a digital value. Such an operation is repeatedly performed as one set, and it is possible to acquire N bits at a time.

  The A / D conversion circuit according to the third embodiment requires more time than the A / D conversion circuit (collective type) according to the second embodiment, but a single tent mapping circuit (tent mapping operation circuit) Since only 1) is required, the number of operational amplifiers becomes four, which reduces the area. In terms of the number of times, it is close to a successive approximation type.

  Since the conventional successive approximation type has a D / A conversion circuit, there is a problem in that the circuit scale increases as the resolution increases. The difference from the successive approximation type is that the A / D conversion circuit according to the third embodiment does not require the sample / hold amplifier 38 to maintain the initial voltage value until a series of digital conversions is completed. The advantage is that no circuit is required (the reference voltage of the comparator only needs to be 0.5 [V]).

  Next, an A / D conversion circuit according to a fourth embodiment will be described. The A / D conversion circuit according to this embodiment outputs a plurality of bits for one mapping. When outputting two bits for one mapping operation, the following equation (7) is used.

The geometric image of the tent mapping map of Expression (7) is a tent mapping having two peaks as shown in FIG.
Range of X _r is,

  Thus, for each operation of the equation (7), a bit string is output for two bits, and a gray code (digital value) is obtained continuously for the number of resolution bits.

For example, in the case of the structure with a resolution of 4 bits, the 16 type range of the initial value X ₀ corresponding to FIG. 6, and outputs the two bits from the initial value X ₀ first, then the initial value X ₀ Is used to obtain 2 bits from X ₁ obtained by executing the operation of equation (7), and a total of 4 bits of gray code (digital value) is obtained. This is a configuration that only needs to be performed.

  FIG. 15 shows a configuration diagram of an A / D conversion circuit according to the fourth embodiment. This A / D conversion circuit includes a control unit 41, analog operation circuits 42, 43, and 44 and switches SW1 to SW6. The control unit 41 generates a control signal for controlling on / off of the switches SW1 to SW6, and includes a comparator for comparing an initial value and an operation result coming from the input terminal 40 with a threshold value according to the number of bits of the gray code. It outputs the code.

  The switch SW1 is provided on a path between the input terminal 40 and the analog operation circuit 42, and the switch SW2 is provided between the output terminal of the analog operation circuit 43 and the input terminal of the analog operation circuit 42. Further, the switch SW3 is provided in a path between the output terminal of the analog operation circuit 42 and the output terminal 49, and the switch SW4 is provided between the output terminal of the analog operation circuit 42 and the input terminal of the analog operation circuit 44. I have. The switch SW5 is a switch for applying a reference voltage of 0.75 [V] to the analog operation circuit 43, and the switch SW6 is a switch for applying a reference voltage of 0.25 [V] to the analog operation circuit 43.

Analog operation circuit 42 is a quadrupling circuit an input signal, the analog operation circuit 43 is the input signal X _r the (Vin) 0.5 - the circuit which performs the calculation of the linear expression to X _r - X _r or 1.5 The analog operation circuit 44 is a circuit that performs subtraction by subtracting 2. The analog operation circuit 44 is a circuit in which the drain of the NMOS transistor 44b is connected to the drain of the diode-connected NMOS transistor 44a, and the connection point is used as an output terminal. A switch SW4 is connected to a connection point between the source and the gate of the NMOS transistor 44a, so that an input signal can be taken. 0.0 [V] is applied to the gate of the NMOS transistor 44b, and -2.0 [V] is applied to the source of the NMOS transistor 44b.

  The control unit 41 includes comparators CMP51 to CMP53. The comparator CMP51 compares the input signal with a threshold value of 0.25 [V], and inverts its output by the inverter 41a to create “-025A”. The comparator CMP52 compares the input signal with a threshold value 0.5 [V], and produces an output “High05”. "High05" is a control signal for the switch SW4. When "High05" is at the H level, SW4 is closed. “High05” is inverted by the inverter 41b to create “Low05”. “Low05” is a control signal for the switch SW3. When “Low05” is at the H level, SW3 is closed.

  The comparator CMP53 compares the input signal with a threshold value 0.75 [V], and produces an output “075-D”. "075-D" is a control signal for the switch SW5. When "075-D" is at the H level, SW5 is closed. "Low05" and the output of the comparator CMP51 are AND-operated by an AND gate to create "025-05B". “025-05B” is a control signal for the switch SW6. When “025-05B” is at the H level, SW6 is closed.

  The output "075-D" of the comparator CMP53 and the output signal "025-05B" of the AND gate 41c are OR-operated by the OR gate 41e, and this OR signal is AND-operated with the clock signal by the AND gate 41f. A control signal is created. When the control signal of the switch SW2 is at the H level, the switch SW2 is closed.

  The OR operation of the signal "05-075C" generated by the AND gate 41d and the output of the inverter 41a is performed by the OR gate 41g. The logical OR signal is ANDed with the clock signal by the AND gate 41h. A control signal is created. When the control signal of the switch SW1 is at the H level, the switch SW1 is closed.

  The control unit 41 includes OR gates 41i and 41j each having one input terminal connected thereto. The signal "075-D" and the signal "05-075C" are supplied to the OR gate 41i to obtain the signal G1 of the first bit of the gray code, and the signal "025-05B" and the signal "05-075C" are supplied to the OR gate 41j. To obtain the second bit signal G2 of the gray code.

In the A / D conversion circuit according to the fourth embodiment configured as described above, when the input signal X _r (V _in ) input to the input terminal 40 satisfies X _r <0.25, the switch SW 1 , SW3 are mapping operation of closing has been X _r + 1 = 4X _r is executed. The input signal X _r inputted to the input terminal 40 (V _in) is, when 0.25 ≦ X _r <0.5, the switch SW2, SW3, SW6 is closed X _r + 1 = 2- mapping operation in 4X _r is executed.

Furthermore, the input signal X _r inputted to the input terminal 40 (V _in) is, when 0.5 ≦ X _r <0.75, switches SW1, SW4 is closed X _r + 1 = 4X _r -2 Is performed. The input signal X _r inputted to the input terminal 40 (V _in) is, 0.75 ≦ when X _r, mapping switches SW2, SW4, SW5 is closed in X _r + 1 = 4-4X _r An operation is performed.

  In the third embodiment, one bit is output for each repetition of the mapping. However, according to the A / D conversion circuit according to the fourth embodiment using Expression (7), two bits are output for each repetition. Since the output can be performed, if the number of bits of the resolution is 4, the required number of clocks may be 2. It can be seen that in the third embodiment, the number of clocks required for A / D conversion is four, but only a few clocks are required.

  The A / D conversion circuit according to the fourth embodiment does not use the D / A conversion used by the A / D conversion circuit according to the conventional example, but employs a conventional pipelined A / D conversion circuit. It does not use a residual amplifier or a sample-and-hold amplifier for each 1-bit output. Further, the A / D conversion circuit according to the fourth embodiment prepares a mapping function that can output several bits in one mapping in the A / D conversion by the tent mapping, so that the flash type and the pipeline type are combined. It is possible to adopt a configuration such as a sub-range type in which the conversion speed, circuit area, and resolution accuracy are traded off.

  In addition, using the A / D conversion circuit according to the fourth embodiment, for example, an apparatus that performs A / D conversion with a resolution of 8 bits is realized by a configuration like the second embodiment shown in FIG. can do. That is, each of the tent mapping operation circuits 1-1 to 1-3 shown in FIG. 11 is replaced by the A / D conversion circuit according to the present embodiment shown in FIG. 15, and the comparator CMP shown in FIG. It will be replaced by the unit 41. Then, since the A / D conversion circuit according to the present embodiment includes five comparators (op-amps) of one A / D conversion circuit, the tent mapping operation circuits 1-1 to 1-3 have a total of 5 circuits. × 3 = 15. Further, since the control section 41 includes three comparators (operational amplifiers), the number becomes 15 + 3 = 18, and the total is 19 including one sample hold. On the other hand, in the case of creating an 8-bit circuit with the same resolution in a parallel type (flash type), 255 comparators are required. Therefore, the present embodiment realizes a circuit with the same resolution with a far smaller number of components. It is possible.

Next, a single-time operation unit applied to the A / D conversion circuit according to the fifth embodiment will be described. The tent mapping operation circuit 1 which is a one-time calculation unit for performing the mapping of the equation (1) once is shown in FIG. The inverting amplifier circuit shown in FIG. 10 is a negative feedback type, and executes “1−X _r ”. However, when the response time (latency) becomes slow and the cascade connection of a plurality of stages is performed, There is a concern that the current generated in the circuit will affect the calculation accuracy. Therefore, by configuring the inverting amplifier circuit using, for example, an NMOS transistor, it can be expected that effects such as improvement in response time (latency), improvement in calculation accuracy, and reduction in circuit area can be obtained. Therefore, in the A / D conversion circuit of the present embodiment, the following equation (8) can be used as the tent mapping equation.

FIG. 16 shows a geometric image of the tent mapping map of the above equation (8). This tent mapping map becomes a V-shaped tent mapping and repeats the range [1,2]. Range of X _r is,
When _Xr <1.5 Bit string "1"
When 1.5 ≤ _Xr Bit string "0"
To get.

When implementing the equation (8), the mapping from the range of the initial value X ₀ shown in FIG. 17, to generate a Gray code, by performing binary conversion to obtain a final digital value. However, when acquiring a bit string by the above rule by Equation (8), as shown in FIG. 17, a value obtained by binary translation from being generated in descending order (ascending order opposite the initial value X _0). For this reason, by inverting the value that was finally subjected to the binary conversion, it is possible to finally obtain an appropriate digital value (ascending order).

  FIG. 18 shows a tent mapping operation circuit 50 configured by replacing the inverting amplifier circuit shown in FIG. 10 with an NMOS transistor. The tent mapping operation circuit 50 shown in FIG. 18 is a one-time operation unit that realizes the expression (8). That is, the tent mapping arithmetic circuit 50 includes a control unit 51, an analog arithmetic circuit 52 as a first arithmetic circuit, an analog arithmetic circuit 53 as a second arithmetic circuit, an analog arithmetic circuit 54 as a third arithmetic circuit, and a switch. (Analog) switches SW1 and SW2 as a group are provided.

  The switches SW1 and SW2, which are a group of switches, directly lead the signal input to the one-time arithmetic unit to the first arithmetic circuit, or switch the first arithmetic circuit through the second arithmetic circuit. A group of switches for guiding to or switching the path.

  The control unit 51 controls ON / OFF of the switch group based on the magnitude of the signal input to the one-time calculation unit. The control unit 51 includes a comparator (comparator) 56 for converting an input signal into a gray code (1 bit) and an inverter 51a, and a logic circuit 55 for generating a control signal for controlling the switches SW1 and SW2 based on the output of the comparator 56. It consists of. Here, the logic circuit 55 includes AND gates 55b and 55c and an OR gate 55d. The output of the logic circuit 55 is a clock signal to be sent to the next stage when using the cascade connection shown in FIG.

  In the present embodiment, since the tent mapping function is a function of multiplying a linear expression by a first constant and then subtracting a second constant, the analog operation circuit 52 performs an operation of multiplying the first constant. The first arithmetic circuit, the analog arithmetic circuit 53 is configured as a second arithmetic circuit for performing the operation of the above-described linear expression, and the analog arithmetic circuit 54 is configured as a third arithmetic circuit for performing the operation of subtracting the second constant. It is configured as an arithmetic circuit.

The analog operation circuit (first operation circuit) 52 performs an operation of multiplying the input signal _Xr or 3- _Xr by a constant 2 by analog operation of the non-inverting amplifier circuit by the operational amplifier 30 shown in FIG.

When X _r <1.5, the analog arithmetic circuit (second arithmetic circuit) 53 folds the “1.5” shown in FIG. 16 so that the operation of “3-X _r ” is performed by the NMOS transistors 53a and 53b. This is performed by the configured subtraction circuit. Here, as shown in FIG. 19, the analog arithmetic circuit (second arithmetic circuit) 53 is configured by connecting another NMOS transistor 53b to the drain of a diode-connected NMOS transistor 53a. A voltage value Vgs is applied to a connection point between the gate and the source of the diode-connected NMOS transistor 53a. In the other NMOS transistor 53b, the gate is connected to Vin, and the source is connected to Vs. The connection point between the two NMOS transistors 53a and 53b is an output terminal, and the voltage level of the output Vout has a relationship of "Vout = Vgs-Vin + Vs (where Vin≤Vgs / 2)".

  FIG. 20 shows the result of DC analysis of the circuit using the NMOS transistors 53a and 53b shown in FIG. FIG. 20 shows the voltage level of Vout when Vin is changed from 0.0 [V] to 3.0 [V]. In the range of “Vin ≦ Vgs / 2 (= 1.5 [V])”, Vout is the value obtained by subtracting the voltage level of Vin from Vgs = 3.0 [V] at the boundary of 1.5 [V]. 20 appears linearly. The voltage conditions for DC analysis are Vgs = 3.0 [V] and Vs = 0.0 [V].

  The analog operation circuit (third operation circuit) 54 has the same configuration as the analog operation circuit (second operation circuit) 53. In the analog operation circuit (third operation circuit) 54, the output signal of the analog operation circuit (first operation circuit) 52 is input to the connection point between the gate and the source of the diode-connected NMOS transistor. With this configuration, the analog operation circuit (third operation circuit) 54 functions as a circuit that subtracts 2 from the input.

Corresponds to a voltage level input Vin in FIG. 18 "X _r" is, the switch SW2 is closed by the control unit 51 when X _r <1.5, when 1.5 ≦ X _r, the switch SW1 is closed. With the above structure, 1.5 ≦ the control unit 51 when the X _r switch SW1 is closed (SW2 is opened) is an analog operation circuit 52 and the analog operation circuit 54 is _{connected, X r + 1 = "2X} r A circuit for performing the operation of -2 "is formed, and X _{r + 1} is obtained. On the other hand, when _Xr <1.5, the control unit 51 closes the switch SW2 (SW1 is opened), connects the analog arithmetic circuit 53, the analog arithmetic circuit 52, and the analog arithmetic circuit 54, and obtains _{Xr + 1} = "2". A circuit for performing the operation of (3−X _r ) ₋₂ (= ₄₋₂ X _r ) ”is configured, and X _{r + 1} is obtained.

  The single operation unit applied to the A / D conversion circuit according to the fifth embodiment shown in FIG. 18 is configured by the inverting amplifier circuit of FIG. 10 as compared with the single operation unit shown in FIG. By replacing the analog operation circuit 23 with the analog operation circuit 53 composed of NMOS transistors, effects such as improvement in response time (latency), improvement in operation accuracy, and reduction in circuit area are expected.

  Next, a single operation unit applied to the A / D conversion circuit according to the sixth embodiment will be described. FIG. 21 is a circuit diagram of a tent mapping operation circuit 20 that is a tent mapping operation circuit that is a one-time operation unit applied to the A / D conversion circuit according to the sixth embodiment. The tent mapping operation circuit 20, which is a one-time operation unit, is different from the one-time operation unit shown in FIG. 10 in that the analog operation circuit 23 constituted by the inverting amplifier circuit in FIG. 10 is configured by PMOS transistors 63a and 63b. It has been replaced. The tent mapping operation circuit 20, which is the one-time operation unit, performs the mapping operation of Expression (1).

The analog operation circuit 23 in FIG. 10, the analog operation circuit 63 is replaced by the construction by the PMOS transistors 63a, 63b is - a subtraction circuit to perform the "1 X _r", 2 pieces of PMOS transistors as shown in FIG. 22 It consists of. The source and the gate of the PMOS transistor 63b shown on the lower side of the figure are connected to Vs = 0.0 [V]. The drain of this PMOS transistor 63b is connected to the drain of another PMOS transistor 63a. Power from the source of the further PMOS transistor 63a is supplied with Vdd = 1.0 [V], the input voltage level Vin on which an arithmetic operation to the gate of the PMOS transistor 63a is supplied as X _r. The output voltage Vout from the drain of the PMOS transistor 63b whose source and gate are connected to Vs = 0.0 [V] has a relationship of “Vout = Vdd−Vin (where Vdd / 2 ≦ Vin)”.

  FIG. 23 shows a result of performing a DC analysis on a circuit including the PMOS transistors 63a and 63b in FIG. FIG. 23 shows a change in the output voltage level Vout when the input potential level Vin is changed from 0.0 [V] to 1.0 [V]. In the range of "Vdd / 2 (= 0.5 [V]) ≤ Vin", the value obtained by subtracting the voltage level of Vin from Vdd = 1.0 [V] at the boundary of 0.5 [V], It appears linearly in FIG.

  According to the sixth embodiment, like the one-time operation unit shown in FIG. 18 applied to the A / D conversion circuit according to the fifth embodiment, the one-time operation unit shown in FIG. Therefore, by replacing the analog arithmetic circuit 23 constituted by the inverting amplifier circuit of FIG. 10 with a configuration including the PMOS transistors 63a and 63b, effects such as improvement of response time (latency), improvement of arithmetic accuracy, and reduction of circuit area can be obtained. be able to.

  A field of application of the present invention will be described. The present invention can be used for A / D conversion for converting an analog voltage value to a digital value. In particular, it is suitable for use in video applications requiring high-speed conversion such as a parallel type (flash type). It is also suitable for scientific and technical analysis of natural waves containing unknown high frequency components and for signal sampling by sensors.

Reference Signs List 2 sample hold amplifier 3 binary conversion circuit 4 output buffer 5 control unit 11 sample hold unit 12 calculation unit 13 conversion unit 20 tent mapping calculation circuit 21 control unit 22, 23 analog calculation circuit 24 comparator 25 logic circuit 30, 31 operational amplifier 32 register 38 Sample hold amplifiers 41, 51 Control units 42, 43, 44 Analog arithmetic circuits 50 Tent mapping arithmetic circuits 52, 53, 54 Analog arithmetic circuits 55 Logic circuits 56 Comparators 63 Analog arithmetic circuits 110 Encoder 120 Successive comparison register 125 Timing control unit 130 Integration Circuit 140 counter

Claims (8)

A single operation unit for performing one analog operation of the tent mapping for the input analog signal to be input once;
A comparator that compares the input analog signal with a threshold value corresponding to the number n of bits of a gray code, extracts a 1-bit digital value, and outputs a gray code;
With
The one-time operation unit includes:
A plurality of analog arithmetic circuits for performing an operation of subtracting the input voltage from the predetermined voltage value, multiplying the input voltage by a predetermined number, and subtracting the predetermined voltage value from the input voltage value;
A switch provided between a required analog operation circuit in the plurality of analog operation circuits and a switch provided on a path for leading the input analog signal to the required analog operation circuit in the plurality of analog operation circuits Groups and
Based on the magnitude relationship between the input analog signal and the threshold value, controlling the opening and closing of the switches in the switch group for each edge of the clock , calculating a linear function arithmetic circuit in the tent mapping function determined by the magnitude relationship with the threshold value And a control circuit that controls the analog circuit to be performed collectively by the realized operation circuit. A single operation unit for performing one analog operation of the tent mapping for the input analog signal to be input once;
A comparator for comparing the input analog signal with a threshold value corresponding to the number n of bits of a gray code, extracting a 2-bit digital value, and outputting a gray code;
With
A tent mapping function is a function in which a linear expression is multiplied by a constant,
The one-time operation unit includes:
A first analog operation circuit for performing an operation of multiplying the constant,
A second analog operation circuit that performs the operation of the linear expression;
Whether the input analog signal input to the one-time arithmetic unit is directly guided to the first analog arithmetic circuit, or is guided to the first analog arithmetic circuit via the second analog arithmetic circuit; A group of switches for switching paths,
On / off of the switch group is controlled by the edge of the clock based on the magnitude of the input analog signal input to the one-time operation unit, and a linear function of a tent mapping function determined by a magnitude relationship with the threshold is determined. A control unit that realizes an arithmetic circuit and controls the analog circuit to be performed collectively by the realized arithmetic circuit.   The tent mapping operation circuit according to claim 1, wherein the one-time operation unit outputs one bit or two or more predetermined bits.   4. The tent mapping operation circuit according to claim 1, wherein a required analog operation circuit in the analog operation circuit is configured by an operational amplifier or an NMOS transistor.   4. The tent mapping operation circuit according to claim 1, wherein a required analog operation circuit in the analog operation circuit is configured by an operational amplifier or a PMOS transistor. The one-time operation unit includes:
The tent mapping operation circuit according to any one of claims 1 to 5, further comprising an analog operation circuit for subtracting a predetermined number. A tent mapping operation circuit according to claim 1 ;
A path for feeding back the output of the single operation unit in the tent mapping operation circuit to its own input ;
A buffer for accumulating an output for each single operation of the single operation unit;
With
The A / D conversion circuit of the tent mapping operation circuit, wherein the A / D conversion output of a predetermined bit is obtained from the buffer by repeatedly performing the operation by the one time operation unit a predetermined number of times.   The A / D conversion circuit according to claim 7, further comprising a conversion unit that converts the obtained Gray code into a binary code.

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