CN111313900A - Two-step double-slope analog-to-digital converter and analog-to-digital conversion method thereof - Google Patents

Two-step double-slope analog-to-digital converter and analog-to-digital conversion method thereof Download PDF

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Publication number
CN111313900A
CN111313900A CN202010160748.3A CN202010160748A CN111313900A CN 111313900 A CN111313900 A CN 111313900A CN 202010160748 A CN202010160748 A CN 202010160748A CN 111313900 A CN111313900 A CN 111313900A
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slope
fine
coarse
generating circuit
analog
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吴旭
王志鹏
何龙
冯军
李连鸣
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Southeast University
Network Communication and Security Zijinshan Laboratory
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Southeast University
Network Communication and Security Zijinshan Laboratory
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

Abstract

The invention discloses a two-step double-slope analog-to-digital converter and an analog-to-digital conversion method thereof. For the ADC, determining a coarse range of an input signal by comparing the input signal with a voltage value of a coarse ramp, and simultaneously determining a few high-order bit data of analog-to-digital conversion; determining an integration start level of the fine ramp generator according to a result of the coarse ramp counter; the remaining low order bit data of the analog to digital conversion is determined by comparing the input signal with the fine ramp integrated signal. The invention can ensure the conversion precision of the ADC under the condition that the ADC only uses one coarse ramp generating circuit and one fine ramp generating circuit, and can greatly improve the problem of overlong conversion time of the traditional single-slope ADC.

Description

Two-step double-slope analog-to-digital converter and analog-to-digital conversion method thereof
Technical Field
The present invention relates to analog-to-digital converters, and more particularly, to a two-step dual-slope analog-to-digital converter and an analog-to-digital conversion method thereof.
Background
The CMOS array read-out circuit has the significant advantages of high integration level, small size, low power consumption, low price, etc., and is gaining more and more attention. In a readout circuit, a core processing unit analog-to-digital converter (ADC) has been a difficult design and research hotspot. The conventional ADC mainly uses a single-slope ADC, which generates a ramp signal by a ramp generator, compares the ramp signal with the analog signal of the pixel to complete comparison from all 0 to all 1, and the flip point (the output level changes from high level to low level or from low level to high level) output by the comparator is converted into a digital code by the analog signal of the pixel. However, such a conventional single-slope ADC cannot achieve a win-win of high accuracy and high speed because in this configuration, high accuracy means increasing the ramp time of the ramp signal or increasing the frequency of the clock signal, which reduces the processing speed of the system and increases the circuit difficulty.
The system architecture of the conventional single-slope ADC mainly includes a comparator, a counter, a latch, and a ramp generator. For conversion accuracy of K-bit accuracy, a single slope ADC requires 2KOne conversion cycle can complete an analog-to-digital conversion.
However, the ADC using two slopes, which is presented later, includes a coarse ramp generating circuit and a plurality of fine ramp generating circuits, which greatly increases the power consumption of the ADC circuit.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the problems in the prior art, the invention provides a two-step double-slope analog-to-digital converter and an analog-to-digital conversion method thereof, which can accelerate the conversion speed while ensuring the conversion precision and not increasing the power consumption.
The technical scheme is as follows: in order to realize the purpose, the invention adopts the following technical scheme:
a two-step double-slope analog-to-digital converter comprises a coarse slope generating circuit, a fine slope generating circuit, a comparator, a coarse slope counter, a fine slope counter and a time sequence control circuit, wherein the positive input end of the comparator is connected with an analog input signal, the time sequence control circuit controls and selects the output end of the coarse slope generating circuit or the fine slope generating circuit to be in input connection with the negative end of the comparator, meanwhile, the time sequence control circuit controls and selects the output end of the comparator to be connected with the coarse slope counter or the fine slope counter, and the output end of the comparator is also connected with one input end of the time sequence control circuit; the time sequence control circuit controls the on-off between the coarse slope generating circuit and the fine slope generating circuit, and in addition, the time sequence control circuit controls a switch in the coarse slope generating circuit to enable the coarse slope generating circuit to generate a step-shaped voltage value; and the high-order bit data output by the coarse ramp counter and the low-order bit data output by the fine ramp counter are connected in series to be output as a digital output signal.
Optionally, the timing control circuit selects the output terminal of the coarse ramp generating circuit or the fine ramp generating circuit to be connected to the input of the negative terminal of the comparator by controlling the single-pole double-throw switch S1, and simultaneously, the timing control circuit selects the output terminal of the comparator to be connected to the coarse ramp counter or the fine ramp counter by controlling the single-pole double-throw switch S2.
Optionally, the coarse ramp generating circuit comprises 2MA resistor
Figure BDA0002405697260000021
2MA switch B<1>～B<2M>And an output buffer composed of an operational amplifier, wherein 2MA resistor
Figure BDA0002405697260000022
Connected in series in sequence, resistor R1Is grounded, and a resistor R1Second terminating resistor R2First terminal of (3), resistor R2Second terminating resistor R3The first end of (1), and so on, the resistor
Figure BDA0002405697260000023
First terminating resistor
Figure BDA0002405697260000024
Second terminal of, resistor
Figure BDA0002405697260000025
Second terminal of (2) is connected to a reference voltage Vref(ii) a Switch B<1>～B<2M>One end of each is connected with a resistor
Figure BDA0002405697260000026
Second terminal of (B), switch B<1>～B<2M>The other end of the operational amplifier is connected with the positive input end of the operational amplifier, and the negative input end of the operational amplifier is connected with the output end of the operational amplifier.
Optionally, the coarse ramp generating circuit is capable of obtaining the reference voltage VrefIs partially scaled, the specific output is scaled by switch B<1>～B<2M>Whether to close or not, and generating a switch B by a time sequence control circuit<1>～B<2M>Control level of
Figure BDA0002405697260000027
Controlling the level of switch B<1>～B<2M>In which there is only a switch B<2M>Closed in the first clock cycle, only switch B<2M-1>Closed in the second clock cycle, and so on, with only switch B<1>Closed in the last clock cycle; thereby causing the coarse ramp generating circuit to output a stepped voltage value.
Optionally, the coarse ramp generating circuit includes a digital-to-analog converter configured to ramp down its output voltage step by step with a clock period T of a fine ramp counter in the two-step dual-slope analog-to-digital converter or n times nT of the clock period of the fine ramp counter, where n is any real number greater than 1.
Optionally, the coarse ramp generating circuit is a resistor voltage dividing structure, a capacitor array structure or a binary current source structure.
Optionally, the fine ramp generating circuit includes a current source, a single-pole double-throw switch S3, and an integrating capacitor C, wherein upper and lower plates of the integrating capacitor C are both connected to the fine ramp integration start level V in the initial stateFINE_STARTIn a single-pole double-throw switchWhen S3 is switched to the current source, the upper plate of the integrating capacitor C will generate a voltage V from the integration start levelFINE_STARTA starting ramp voltage value of 2NThe voltage value climbing in one clock period is equal to one step of the step-shaped voltage generated by the coarse slope generating circuit; the connection state switching of the single-pole double-throw switch S3 is controlled by a timing control circuit.
The invention also provides an analog-to-digital conversion method based on the two-step double-slope analog-to-digital converter, which comprises the following steps:
(1) the single-pole double-throw switch S1 gates a coarse slope generating circuit, the single-pole double-throw switch S2 gates a coarse slope counter, and two input voltage values of the comparator are an analog input signal Vin and a step-shaped voltage value generated by the coarse slope generating circuit respectively; when the output level of the comparator jumps, recording the voltage value generated by the current coarse slope generating circuit, thereby obtaining the coarse range of the analog input signal Vin and determining M-bit high-order bit data of analog-to-digital conversion;
(2) single-pole double-throw switch S3 gated fine-slope integration start level VFINE_STARTConnecting the voltage value generated by the coarse slope generating circuit recorded in the step (1) to the upper and lower electrode plates of the integrating capacitor C to make the level value of the upper electrode plate of the integrating capacitor C be the integration initial level V of the fine slopeFINE_START；
(3) The single-pole double-throw switch S1 gates a fine slope generating circuit, the single-pole double-throw switch S2 gates a fine slope counter, and when the single-pole double-throw switch S3 is switched to a current source, the upper plate of the integrating capacitor C generates an integration starting level V from the fine slopeFINE_STARTThe starting ramp-like voltage value; the two voltage values compared by the comparator are respectively an analog input signal Vin and a slope-shaped voltage value generated by the fine slope generating circuit; when the output level of the comparator jumps, the clock counter converts the difference value of the analog input signal and the voltage value generated by the coarse slope generating circuit recorded in the step (1) into finally output N-bit low-order bit data;
(4) and performing parallel-to-serial processing on the M-bit high-order bit data and the N-bit low-order bit data in the analog-to-digital conversion process to complete the digitization process of the analog input signal, and obtaining the final analog-to-digital conversion results D < M + N-1> to D <0 >.
The invention also provides a CMOS array type reading circuit based on the two-step double-slope analog-to-digital converter, which is characterized by comprising a plurality of pixels arranged in a matrix form with rows and columns and at least one reading circuit used for reading the electric signals generated by the pixels, wherein the reading circuit comprises at least one two-step double-slope analog-to-digital converter, and the two-step double-slope analog-to-digital converter is used for receiving the electric signals from the pixels and converting the electric signals into digital signals to be output.
Optionally, at least one column of pixels in the plurality of pixels arranged in the matrix form shares at least one two-step dual-slope analog-to-digital converter.
Has the advantages that: the ADC according to the invention enables faster convergence of the analog input signal onto the output of the coarse ramp generator than a conventional single slope ADC. For the conversion precision of M + N bit precision, where M is the high bit number of the coarse slope and N is the low bit number of the fine slope, in the coarse comparison stage, 2 is neededMOne switching cycle, in the fine comparison phase, requires 2NAnd (4) a switching period. Because of the fine comparison phase, the fine ramp does not start from zero, its integration start level VFINE_STARTDetermined by the output of the coarse comparison stage. Therefore, the invention can ensure the precision of analog-to-digital conversion and increase the conversion speed without increasing the power consumption. The invention can ensure the conversion precision of the ADC under the condition that the ADC only uses one coarse slope generating circuit and one fine slope generating circuit, and greatly solves the problem of overlong conversion time of the traditional single-slope ADC under the condition of not increasing power consumption.
Drawings
FIG. 1 is a schematic diagram of a two-step dual slope ADC according to the present invention;
FIG. 2 is a schematic diagram of a coarse ramp generating circuit;
FIG. 3 shows a switch B in the coarse ramp generation circuit<1>-B<2M>The control level of (d);
FIG. 4 is a diagram illustrating a readout timing of a two-step dual-slope ADC;
FIG. 5 is a schematic diagram of a read timing sequence for a coarse compare process;
FIG. 6 is a read timing diagram of a fine compare process.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the two-step dual slope analog-to-digital converter includes a coarse slope generating circuit, a fine slope generating circuit, a comparator, a coarse slope counter, a fine slope counter and a timing control circuit, wherein a positive input terminal of the comparator is connected to an analog input signal, a negative input terminal is connected to an output of the coarse slope generating circuit or the fine slope generating circuit, an output of the comparator is connected to the coarse slope counter or the fine slope counter, and an output of the comparator is also connected to an input terminal of the timing control circuit; the time sequence control circuit selects the output end of the coarse slope generating circuit or the fine slope generating circuit to be connected with the input of the negative end of the comparator by controlling the single-pole double-throw switch S1, meanwhile, the time sequence control circuit selects the output of the comparator to be connected with the coarse slope counter or the fine slope counter by controlling the single-pole double-throw switch S2, the time sequence control circuit controls the on-off between the coarse slope generating circuit and the fine slope generating circuit, and in addition, the time sequence control circuit controls the switch in the coarse slope generating circuit to generate a step-shaped voltage value; the output of the coarse ramp counter is used as high-order bit data, the output of the fine ramp counter is used as low-order bit data, and the high-order bit data and the low-order bit data are connected in series to be output as a digital output signal.
Take the conversion precision of K bit precision (K ═ M + N) as an example, where there are M-bit high-order bit data and N-bit low-order bit data.
The coarse ramp generating circuit may be composed of a resistor voltage dividing structure, a capacitor array structure, a binary current source structure, etc., as shown in fig. 2, for example, the coarse ramp generating circuit is composed of a string of equal resistors, and the coarse ramp generating circuit includes 2MA resistor
Figure BDA0002405697260000041
2MA switch B<1>～B<2M>And an output buffer composed of an operational amplifier, wherein 2MA resistor
Figure BDA0002405697260000042
Connected in series in sequence, resistor R1Is grounded, and a resistor R1Second terminating resistor R2First terminal of (3), resistor R2Second terminating resistor R3The first end of (1), and so on, the resistor
Figure BDA0002405697260000043
First terminating resistor
Figure BDA0002405697260000044
Second terminal of, resistor
Figure BDA0002405697260000045
Second terminal of (2) is connected to a reference voltage Vref(ii) a Switch B<1>～B<2M>One end of each is connected with a resistor
Figure BDA0002405697260000046
Second terminal of (B), switch B<1>～B<2M>The other end of the operational amplifier is connected with the positive input end of the operational amplifier, and the negative input end of the operational amplifier is connected with the output end of the operational amplifier. Resistance (RC)
Figure BDA0002405697260000047
The resistance values are equal.
The coarse ramp generating circuit can obtain a reference voltage VrefOf any proportion, the proportion of a particular output being supplied by a switch B to an output buffer<1>～B<2M>And whether to close, wherein the output buffer is composed of a unity gain operational amplifier. Generating switch B by sequential control circuit<1>～B<2M>Control level of
Figure BDA0002405697260000051
As shown in fig. 3, where the high levelIndicating that the switch is closed and low indicating that the switch is open. Controlling the level of switch B<1>～B<2M>In which there is only a switch B<2M>Closed in the first clock cycle, only switch B<2M-1>Closed in the second clock cycle, and so on, with only switch B<1>Closed in the last clock cycle; i.e. reference voltage V during the first clock cyclerefIs directly connected with the positive input end of the operational amplifier; resistance in the second clock cycle
Figure BDA0002405697260000052
Is connected to the positive input of the operational amplifier, and at this time, the resistor
Figure BDA0002405697260000053
The serial voltage division is used as the positive input end voltage of the operational amplifier; resistance R in the third clock cycle2 M -1Is connected to the positive input of the operational amplifier, at which time the resistor R is connected to the positive input of the operational amplifier1～R2 M -2The serial voltage division is used as the positive input end voltage of the operational amplifier; by analogy, in the last clock cycle, the resistor R1Is connected to the positive input of the operational amplifier, and at this time, the resistor R1The series voltage division is used as the positive input terminal voltage of the operational amplifier. Thereby, the coarse ramp generating circuit outputs a step-shaped voltage value, namely, a step-shaped coarse ramp signal. As shown in the dashed box of fig. 4. And the coarse ramp generating circuit also provides a fine ramp integration starting level for the fine ramp generating circuit after the coarse comparison stage is finished.
The coarse ramp generating circuit may further include a digital-to-analog converter (DAC) configured to gradually ramp down an output voltage of the DAC in a step shape. Its clock period may be the clock period (T) of the fine ramp counter in the ADC, or n times the clock period (nT) of the fine ramp counter, where n may be any real number greater than 1. Wherein the DAC is matched to the ADC of the present invention.
The fine slope generating circuit consists of a current source and a single-pole double-throw switchS3 and an integrating capacitor C, as shown in the dashed box of fig. 1. The upper and lower plates of the integrating capacitor C are both connected to a fine-slope integration starting level in an initial state. When the spdt switch S3 switches to the current source, the upper plate of the integrating capacitor C generates a ramp-like voltage value from the integration start level. The ramp voltage value is 2NThe voltage value that climbs in one clock cycle is equal to one step of the stepped voltage generated by the coarse ramp generating circuit. The connection state switching of the single-pole double-throw switch S3 is controlled by a timing control circuit.
The comparator has positive and negative input ports and an output port, wherein the analog input signal is connected to the positive input of the comparator, and the single-pole double-throw switch S1 gates the coarse ramp generating circuit or the fine ramp generating circuit to be connected to the negative input of the comparator. When the input level of the positive terminal is higher than that of the negative terminal, the output port of the comparator outputs a high level; when the positive terminal input level is less than the negative terminal input, the comparator output port outputs a low level.
The coarse ramp counter, the fine ramp counter and the time sequence control circuit are all composed of digital circuits. Wherein the coarse slope counter is used for recording high-order bit data (MSB) of analog-to-digital conversion, the fine slope counter is used for recording low-order bit data (LSB) of analog-to-digital conversion, the output end of the comparator is connected to the input end of the time sequence control circuit, so that various control signals are output according to the output result of the comparator, and the time sequence control circuit generates control signals
Figure BDA0002405697260000061
Respectively controlling switches B in the coarse ramp generating circuit<1>～B<2M>Meanwhile, the timing control circuit also generates control signals SW1, SW2 and SW3 to respectively control the gating condition of the single-pole double-throw switch S1, the gating condition of the single-pole double-throw switch S2, the gating condition of the single-pole double-throw switch S3 in the fine ramp generating circuit and the like.
The timing control circuit is for receiving the output of the comparator and providing a switching means between the selected ramp signal and the comparator, the switching means S1 being configured to selectively connect either the coarse ramp generating circuit signal or the fine ramp generating circuit signal to the comparator input. The time sequence control circuit is used for receiving the output of the coarse ramp counter and providing a starting time signal for starting integration for the fine ramp generating circuit.
A method of analog-to-digital converting an analog input signal, the method comprising receiving the analog signal, generating a coarse ramp signal covering the input range, deriving an approximate range of the analog input signal by a comparator, regenerating a fine ramp signal covering the approximate range, and converting the analog input signal to a digital output signal by comparing the input signal to a selected ramp signal. The method specifically comprises the following steps:
as shown in fig. 5, in the first phase of the analog-to-digital conversion, the single-pole double-throw switch S1 gates the coarse ramp generating circuit, the single-pole double-throw switch S2 gates the coarse ramp counter, and the two input voltage values of the comparator are the analog input signal Vin and the step-like voltage value generated by the coarse ramp generating circuit, respectively. When the output level of the comparator jumps (namely the output voltage changes from low level to high level or from high level to low level), the states of the control signals of the switches of the current coarse ramp generating circuit and the voltage value of the output of the coarse ramp generating circuit are recorded. Therefore, the rough range of the analog input signal Vin can be obtained, and M high-order bit data D < M + N-1> to D < N > of analog-to-digital conversion are determined.
In the second phase of the analog-to-digital conversion, switch B after the high-order bit data (MSB) has been determined in the first phase<1>～B<2M>Each switch B of the coarse ramp generating circuit when the output level of the comparator changes from low level to high level or from high level to low level<1>～B<2M>The state of the control signal. Single-pole double-throw switch S3 gated fine-slope integration start level VFINE_STARTConnecting the voltage value of the coarse slope generating circuit recorded in the step one to the upper and lower polar plates of the integrating capacitor C to make the level value of the upper polar plate of the integrating capacitor C be the integration initial level V of the fine slopeFINE_STARTEven if the voltage value output from the coarse ramp generating circuit is used as the integration start level V of the fine rampFINE_STARTConnected to the lower plate of the integrating capacitor C.
As shown in FIG. 6, in the third stage of the analog-to-digital conversion, the single-pole double-throw switch S1 gates the fine ramp generating circuit, the single-pole double-throw switch S2 gates the fine ramp counter, and the upper and lower plates of the integrating capacitor C are both connected to the integration start level V of the fine ramp in the initial stateFINE_START. When the spdt switch S3 switches to the current source, the upper plate of the integrating capacitor C generates a ramp-like voltage value from the integration start level. The two voltage values compared by the comparator are respectively the analog input signal Vin and the ramp-like voltage value generated by the fine ramp generating circuit. When the output level of the comparator jumps (namely the output voltage changes from low level to high level or from high level to low level), the fine ramp counter (with the clock period T) converts the difference value of the input signal and the voltage value of the coarse ramp generating circuit recorded in the step one into the finally output N-bit low-bit data D<N-1>～D<0>。
And finally, performing parallel-to-serial processing on the M-bit high-order bit data (MSB) and the N-bit low-order bit data (LSB) in the analog-to-digital conversion process to complete the digitization process of the input analog signal and obtain the final analog-to-digital conversion results D < M + N-1> to D <0 >.
In summary, for the two-step dual-slope ADC, the first step finds a coarse range of the analog input signal by comparing the analog input signal with the voltage value output by the coarse ramp generating circuit, and determines the high-order bit data of the analog-to-digital conversion; secondly, determining an integral starting level of a fine slope generating circuit according to the result of the coarse slope counter; the third step determines the low order bit data of the analog-to-digital conversion by comparing the analog input signal with the fine ramp integration signal integrated from the integration start level generated in the second step. The ADC according to the invention enables faster convergence of the analog input signal onto the output of the coarse ramp generating circuit than a conventional single slope ADC. For K-bit conversion accuracy, where M is the high-order bit number of the coarse ramp and N is the low-order bit number of the fine ramp, 2 is required in the coarse comparison stageMOne switching cycle, in the fine comparison phase, requires 2NAnd (4) a switching period. Because of the fact thatIn the fine comparison stage, the fine ramp does not start from zero, and the integration start level is determined by the output result of the coarse comparison stage. Therefore, the invention can ensure the precision of analog-to-digital conversion and increase the conversion speed without increasing the power consumption.
Taking the conversion accuracy of K-bit accuracy as an example, it requires 2 compared to a conventional single slope ADCKOne conversion cycle can complete an analog-to-digital conversion. If the conversion precision M + N of the invention is equal to K (0)<M<K and 0<N<K) The period of one A/D conversion is 2M+2NWhich is much smaller than 2KTherefore, the conversion precision is ensured, and the conversion speed is greatly improved.
Compared with the existing ADC adopting two slopes, the invention only uses a coarse slope generating circuit and a fine slope generating circuit, thereby greatly reducing the area of the ADC and the power consumption.
A CMOS array readout circuit includes a plurality of pixels arranged in a matrix having rows and columns and at least one readout circuit for reading out electrical signals generated by the pixels. The readout circuit comprises at least one two-step double-slope analog-to-digital converter (ADC) as described above, which is configured to receive the electrical signal from the pixel, convert it to a digital signal, and output it.
A CMOS array readout circuit comprising at least one readout circuit for reading out electrical signals generated by pixels, each readout circuit comprising at least one ADC as described above.
And the CMOS array type reading circuit, at least one column of pixels in the array share at least one ADC.

Claims (10)

1. A two-step double-slope analog-to-digital converter is characterized by comprising a coarse slope generating circuit, a fine slope generating circuit, a comparator, a coarse slope counter, a fine slope counter and a time sequence control circuit, wherein the positive input end of the comparator is connected with an analog input signal, the time sequence control circuit controls and selects the output end of the coarse slope generating circuit or the fine slope generating circuit to be connected with the input end of the negative end of the comparator, meanwhile, the time sequence control circuit controls and selects the output end of the comparator to be connected with the coarse slope counter or the fine slope counter, and the output end of the comparator is also connected with one input end of the time sequence control circuit; the time sequence control circuit controls the on-off between the coarse slope generating circuit and the fine slope generating circuit, and in addition, the time sequence control circuit controls a switch in the coarse slope generating circuit to enable the coarse slope generating circuit to generate a step-shaped voltage value; and the high-order bit data output by the coarse ramp counter and the low-order bit data output by the fine ramp counter are connected in series to be output as a digital output signal.
2. The two-step double-slope ADC of claim 1, wherein the timing control circuit selects the output of the coarse slope generating circuit or the fine slope generating circuit to be connected to the negative terminal input of the comparator by controlling the single-pole double-throw switch S1, and the timing control circuit selects the output of the comparator to be connected to the coarse slope counter or the fine slope counter by controlling the single-pole double-throw switch S2.
3. A two-step, dual slope analog-to-digital converter as claimed in claim 1, wherein the coarse slope generating circuit comprises 2MA resistor
Figure FDA0002405697250000011
2MA switch B<1>～B<2M>And an output buffer composed of an operational amplifier, wherein 2MA resistor
Figure FDA0002405697250000012
Connected in series in sequence, resistor R1Is grounded, and a resistor R1Second terminating resistor R2First terminal of (3), resistor R2Second terminating resistor R3The first end of (1), and so on, the resistor
Figure FDA0002405697250000013
First terminating resistor
Figure FDA0002405697250000014
Second terminal of, resistor
Figure FDA0002405697250000016
Second terminal of (2) is connected to a reference voltage Vref(ii) a Switch B<1>～B<2M>One end of each is connected with a resistor
Figure FDA0002405697250000015
Second terminal of (B), switch B<1>～B<2M>The other end of the operational amplifier is connected with the positive input end of the operational amplifier, and the negative input end of the operational amplifier is connected with the output end of the operational amplifier.
4. A two-step dual slope adc as recited in claim 3, wherein the coarse slope generating circuit is capable of obtaining the reference voltage VrefIs partially scaled, the specific output is scaled by switch B<1>～B<2M>Whether to close or not, and generating a switch B by a time sequence control circuit<1>～B<2M>Control level phi of1～Φ2MControlling the level of the switch B<1>～B<2M>In which there is only a switch B<2M>Closed in the first clock cycle, only switch B<2M-1>Closed in the second clock cycle, and so on, with only switch B<1>Closed in the last clock cycle; thereby causing the coarse ramp generating circuit to output a stepped voltage value.
5. A two-step dual slope adc according to claim 1, wherein the coarse ramp generating circuit comprises a digital-to-analog converter configured to step down the output voltage thereof in a step-like manner with a clock period T of a fine ramp counter in the two-step dual slope adc or n times nT of the clock period of the fine ramp counter, n being any real number greater than 1.
6. The two-step dual slope analog-to-digital converter according to claim 1, wherein the coarse slope generating circuit is a resistor voltage dividing structure, a capacitor array structure or a binary current source structure.
7. The two-step dual-slope analog-to-digital converter according to claim 1, wherein the fine slope generating circuit comprises a current source, a single-pole-double-throw switch S3, and an integrating capacitor C, and upper and lower plates of the integrating capacitor C are both connected to a fine slope integration start level V in an initial stateFINE_STARTWhen the single-pole double-throw switch S3 is switched to the current source, the upper plate of the integrating capacitor C generates a voltage level V from the integration start levelFINE_STARTA starting ramp voltage value of 2NThe voltage value climbing in one clock period is equal to one step of the step-shaped voltage generated by the coarse slope generating circuit; the connection state switching of the single-pole double-throw switch S3 is controlled by a timing control circuit.
8. An analog-to-digital conversion method based on the two-step dual-slope analog-to-digital converter of any one of claims 1 to 7, comprising the steps of:
(1) the single-pole double-throw switch S1 gates a coarse slope generating circuit, the single-pole double-throw switch S2 gates a coarse slope counter, and two input voltage values of the comparator are an analog input signal Vin and a step-shaped voltage value generated by the coarse slope generating circuit respectively; when the output level of the comparator jumps, recording the voltage value generated by the current coarse slope generating circuit, thereby obtaining the coarse range of the analog input signal Vin and determining M-bit high-order bit data of analog-to-digital conversion;
(2) single-pole double-throw switch S3 gated fine-slope integration start level VFINE_STARTConnecting the voltage value generated by the coarse slope generating circuit recorded in the step (1) to the upper and lower electrode plates of the integrating capacitor C to make the level value of the upper electrode plate of the integrating capacitor C be the integration initial level V of the fine slopeFINE_START；
(3) The single-pole double-throw switch S1 gates a fine slope generating circuit, the single-pole double-throw switch S2 gates a fine slope counter, and the single-pole double-throw switch S3 is switched to currentWhen the source is in use, the upper plate of the integrating capacitor C generates an integration starting level V from a fine slopeFINE_STARTThe starting ramp-like voltage value; the two voltage values compared by the comparator are respectively an analog input signal Vin and a slope-shaped voltage value generated by the fine slope generating circuit; when the output level of the comparator jumps, the clock counter converts the difference value of the analog input signal and the voltage value generated by the coarse slope generating circuit recorded in the step (1) into finally output N-bit low-order bit data;
(4) and performing parallel-to-serial processing on the M-bit high-order bit data and the N-bit low-order bit data in the analog-to-digital conversion process to complete the digitization process of the analog input signal, and obtaining the final analog-to-digital conversion results D < M + N-1> to D <0 >.
9. A CMOS array readout circuit based on a two-step dual-slope analog-to-digital converter according to any of claims 1 to 7, comprising a plurality of pixels arranged in a matrix having rows and columns and at least one readout circuit for reading out electrical signals generated by said pixels, the readout circuit comprising at least one two-step dual-slope analog-to-digital converter for receiving electrical signals from the pixels and converting them to digital signal outputs.
10. The CMOS array readout circuit of claim 9, wherein at least one column of pixels in the plurality of pixels arranged in a matrix share at least one two-step, dual slope analog-to-digital converter.
CN202010160748.3A 2020-03-10 2020-03-10 Two-step double-slope analog-to-digital converter and analog-to-digital conversion method thereof Pending CN111313900A (en)

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