CN113380697A - 基于溴插层多层石墨烯或石墨薄膜的碳基器件和电路结构的制备方法 - Google Patents
基于溴插层多层石墨烯或石墨薄膜的碳基器件和电路结构的制备方法 Download PDFInfo
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Abstract
本发明专利公开了一种基于溴插层多层石墨烯或石墨薄膜的碳基器件和电路结构的制备方法,在低功耗器件、超密集和超薄集成电路等领域具有应用前景。本发明通过对多层石墨烯或者石墨薄膜进行溴插层处理,提高了材料的电导性能。其中,导电通道为溴插层处理后再经过减薄的单层或双层石墨烯,溴被封装在单层或双层石墨烯与衬底之间或是双层石墨烯片层间,提高了沟道的导电性能。本发明通过图形化单片石墨烯或者石墨薄膜的方式,同时制备器件和电极以及局部互联线,极大地降低了器件和电路中的接触电阻,并且这种电路结构中的局部互联线不需要其他材料,从而简化了生产中的工艺制造过程。而且本发明中的制备工艺也可以与目前主流的半导体加工工艺相兼容。
Description
技术领域
本发明提出了一种基于溴插层多层石墨烯或石墨薄膜的碳基器件和电路结构的制备方法,在低功耗器件,超密集和超薄集成电路等领域具有应用前景。
背景技术
石墨烯由于具有极高的载流子迁移率、优异的机械性能和良好的热导率等受到了广泛的研究,是一种十分具有潜力的电子材料。近年来,石墨烯被应用在许多种电子器件和电路的制备中,比如石墨烯场效应晶体管、石墨烯原子开关等器件以及利用石墨烯场效应晶体管实现的石墨烯环形振荡器、石墨烯多级反相器等电路。但是在传统的石墨烯场效应晶体管中,源端和漏端通常采用金属做电极,因此不可避免的存在石墨烯/金属的接触,这样的接触电阻通常有几百到几千Ωμm。石墨烯的本征性能受到接触电阻的极大限制,尤其是载流子的迁移率。因此,选择合适的电极材料对高性能石墨烯基器件的制备及其在电路中的应用尤为重要。
目前已有的降低石墨烯基器件中接触电阻的方法包括:选择与石墨烯相比功函数差异较大的金属,通过对金属下方的石墨烯重掺杂来增加态密度从而降低接触电阻率;采用热退火处理来降低接触电阻;Franklin等人探索了一种在石墨烯层上下均具有接触金属的双接触几何结构,使得接触电阻降低了40%;也有研究小组通过在接触区域的石墨烯内形成切口从而增强载流子注入来降低接触电阻。而目前提出的“全石墨烯”器件通过无缝连接可以使接触电阻大幅降低,并且有可能成为具有前所未有的性能和能效以及更高可靠性的超致密和薄型集成电路。
发明内容
本发明的目的在于提出一种基于溴插层多层石墨烯或石墨薄膜的碳基器件和电路结构的制备方法,其中,导电通道为溴插层处理后再经过减薄的单层或双层石墨烯,溴被封装在单层或双层石墨烯与衬底之间或是双层石墨烯片层间,源漏电极为溴插层后的石墨或多层石墨烯,并与沟道部分石墨烯直接相连。
本发明可以通过如下技术方案实现:
1)多层石墨烯或石墨薄膜的溴插层处理:将采用化学气相沉积(CVD)法合成的多层石墨烯薄膜(层数大于2)或者机械剥离的多层石墨烯或者石墨薄膜通过干法或者湿法转移的方法转移到绝缘体或半导体等不同的衬底表面。将分析纯液溴与转移后的样品一同置于密闭容器中,使多层石墨烯或石墨薄膜暴露于溴蒸汽氛围中,并且长时间静置进行溴插层,如图1所示,静置时间通常在1-24小时。
2)石墨烯器件沟道的制备:在溴插层处理后的样品表面涂上光刻胶,通过光刻,显影形成沟道区域。然后利用蒸发或者溅射方式镀上金属,再将样品放入丙酮溶液中剥离掉沟道区域以外的金属,最后将样品置于稀盐酸溶液中,使金属溶解同时除去沟道区域多层石墨烯或者石墨薄膜中每一层碳原子。重复该过程直到沟道区域是一层或两层石墨烯,形成器件的沟道部分。也可以采用光刻胶做掩膜,进行温和的氧等离子体刻蚀以产生大量空位缺陷,再进行氢等离子体刻蚀去除最上层含大量缺陷的石墨烯。重复该过程以减薄沟道区域的多层石墨烯薄膜或者石墨,形成一层或两层石墨烯的沟道区。最后用丙酮溶液除去光刻胶掩膜;
3)源与漏电极的制备:在样品表面涂上光刻胶,利用光刻、显影图像化出电极区域,然后用等离子体刻蚀,除去不需要的石墨烯或是石墨薄膜部分,形成多层石墨烯或者石墨的源与漏电极,从而完成碳基器件。
4)碳基电路的互连实现:电路中的局部互联线采用溴插层处理后的多层石墨烯薄膜或石墨薄膜,该步骤可以与步骤(3)同时进行,采用光刻、显影的方式定义出互联部分,然后利用等离子体刻蚀,除去不需要的多层石墨烯或石墨薄膜,形成多层石墨烯的互连结构,从而完成碳基器件的互连。
本发明的技术特点:
本发明通过在多层石墨烯或者石墨薄膜中进行溴插层处理,使得薄膜的面内电电导率增加,并且可以通过改变溴插层处理的时间,调节石墨烯或者石墨的掺杂程度。器件导电通道部分为溴插层处理后减薄的单层或双层石墨烯,溴被封装在石墨烯与衬底之间或双层石墨烯片层之间,提高了沟道的导电性能。且利用这种插层处理后的材料做电极、沟道和内部互联线可以使器件或者电路的整体电阻降低。
本发明通过图形化多层石墨烯或者石墨薄膜的方式,利用局部减薄技术同时制造导电通道、有源区、互联线等,使得各部分无缝连接,大大降低了接触电阻,并且不需要不同的材料来实现局部互联从而简化了制造工艺。
附图说明
图1为多层石墨烯薄膜经过溴插层处理后的示意图;
图2为本发明制备的基于溴插层多层石墨烯薄膜碳基场效应晶体管的示意图,(a)为俯视图,(b)为正视图;
图3为本发明制备的基于溴插层石墨的碳基两级反相器链的石墨层示意图;
其中,1—石墨烯薄膜;2—溴分子;3—经过溴插层处理后的多层石墨烯薄膜或者石墨薄膜,4—减薄后的单层或双层石墨烯构成的沟道,5—介质层,6——重掺杂硅,7——互联线;图片中所有结构的尺寸比例不代表真实比例。
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是,公布实施例的目的在于帮助进一步理解本发明,但是本领域的技术人员可以理解:在不脱离本发明及所附权利要求的精神和范围内,各种替换和修改都是可能的。因此,本发明不应局限于实施例所公开的内容,本发明要求保护的范围以权利要求书界定的范围为准。
实例1:基于溴插层多层石墨烯薄膜碳基场效应晶体管的制备,如图2所示。
1)石墨烯薄膜的溴插层处理:将利用化学气相沉积法合成的均匀七层石墨烯薄膜转移至二氧化硅(栅介质)/低阻硅(背栅电极)表面。将转移后的样品和盛放分析纯液溴的容器一同静置于密闭的容器中,插层5小时。
2)石墨烯沟道的制备:用乙醇冲洗插层处理后的样品表面,除去表面和晶界多余的溴以及吸附较弱的溴。然后在样品表面旋涂一层PMMA光刻胶(4000rpm,一分钟),光刻、显影后暴露出长3微米、宽1微米的线条,作为沟道部分。利用氧等离子体温和刻蚀最上层石墨烯,以引入空位缺陷,其中射频功率为150W,气体压强为0.11Torr,刻蚀时间为3s。然后用氢等离子体刻蚀除去最上层,其中射频功率为30W,气体压强为0.35Torr,刻蚀时间为60min。经过上述两步刻蚀,将沟道部分最上层石墨烯除去。重复6次上述两步刻蚀将沟道区域减薄至单层石墨烯,最后用丙酮溶液冲洗除去表面的光刻胶掩膜。
3)石墨烯源和漏电极的制备:在样品表面旋涂一层PMMA光刻胶(4000rpm,一分钟),按照预先设计好的版图进行光刻定义出源和漏以及沟道区域,然后显影使源和漏电极以及沟道区域以外的石墨烯暴露出来。利用光刻胶做掩膜,采用氧等离子体刻蚀除去不需要的石墨烯,其中射频功率为30W,气体压强为25mTorr,刻蚀时间为5min。
4)使用直流探针台(MPI,TS150)、半导体参数分析仪(Keysight B1500)对器件的电学性能进行测量。
实例2:基于溴插层石墨烯纳米薄膜的碳基单电子晶体管的制备,如图2所示。
1)石墨烯纳米薄膜的溴插层处理:用透明胶带通过机械剥离的方式从高取向的热解石墨转移一块50nm厚的石墨烯薄膜至二氧化硅(栅介质)/低阻硅(背栅电极)表面。将转移后的样品和盛放分析纯液溴的容器一同静置于密闭的容器中,插层处理时间为15小时。
2)石墨烯导电通道的制备:用乙醇冲洗插层处理后的样品表面,除去表面和晶界多余的溴以及吸附较弱的溴。然后在样品表面旋涂一层PMMA光刻胶(4000rpm,一分钟),光刻、显影后暴露出长1微米、宽1微米的窗口,作为沟道部分。利用氧等离子体温和刻蚀最上层石墨烯,以引入空位缺陷,其中射频功率为150W,气体压强为0.11Torr,刻蚀时间为3s。然后用氢等离子体刻蚀除去最上层,其中射频功率为30W,气体压强为0.35Torr,刻蚀时间为60min。经过上述两步刻蚀,将沟道部分最上层石墨烯除去。重复上述两步刻蚀直到将沟道区域减薄至单层石墨烯,最后用丙酮溶液冲洗除去表面的光刻胶掩膜。
3)石墨烯源和漏电极的制备:在样品表面旋涂两层PMMA光刻胶(每层旋涂时转速为4000rpm,一分钟),按照预先设计好的版图进行光刻定义出源和漏以及沟道区域,然后显影使源和漏电极以及沟道区域以外的石墨烯暴露出来。利用光刻胶做掩膜,采用氧等离子体刻蚀除去不需要的石墨烯。
4)使用直流探针台(MPI,TS150)、半导体参数分析仪(Keysight B1500)对器件进行电学方面的制备。首先在器件的源漏端之间施加随时间线性增加的偏压,速率为0.57V/s,同时检测通过沟道的电流。当电流出现下降时,立刻以225V/s的速率将偏压降至0。重复这一步骤,直到器件在100mV的源漏偏压下电阻超过100MΩ。。
实例3:基于溴插层石墨薄膜的碳基两级反相器电路结构的制备,如图3所示。
1)石墨薄膜的溴插层处理:用透明胶带通过机械剥离的方式从高取向的热解石墨转移一块500nm厚的石墨薄膜至二氧化硅/低阻硅表面。将转移后的样品和盛放分析纯液溴的容器一同静置于密闭的容器中,插层处理时间为15小时。
2)石墨的图形化:用乙醇冲洗插层处理后的样品表面,除去表面和晶界多余的溴以及吸附较弱的溴。在样品表面涂上光刻胶,利用光刻图形化出石墨烯导电通道、有源区和互联线,然后利用光刻胶做掩膜,氧等离子体刻蚀除去不需要的石墨。
3)石墨烯导电通道的制备:在样品表面旋涂一层PMMA光刻胶(4000rpm,一分钟),光刻、显影后暴露出沟道部分。利用氧等离子体温和刻蚀最上层石墨烯,以引入空位缺陷,其中射频功率为150W,气体压强为0.11Torr,刻蚀时间为3s。然后用氢等离子体刻蚀除去最上层,其中射频功率为30W,气体压强为0.35Torr,刻蚀时间为60min。经过上述两步刻蚀,将沟道部分最上层石墨烯除去。重复上述两步刻蚀直到将沟道区域减薄至单层石墨烯,最后用丙酮溶液冲洗除去表面的光刻胶掩膜。
3)PMOS沟道的制备:由于溴本身会对石墨造成P型掺杂,因此要对PMOS的沟道进行N型轻掺杂。N型掺杂的方式采用电子束辐照的方式,使用场发射扫描电子显微镜,首先在10kV的加速电压下进行成像,快速定位到沟道区域,然后在高真空(小于10-6Torr)下,加速电压为20kV,发射电流保持在10μA,对应的束流约为10pA,对1×3μm2的区域进行辐照。实验中束流保持恒定,通过调整曝光时间来控制电子辐照剂量,沟道区域曝光时间为10s。
4)栅极的制备:在样品表面涂上光刻胶,通过光刻显影图形化栅极图案,然后淀积。再进行一次光刻图形化,转移一层重掺杂石墨薄膜作为栅极。其中介质层可以为氧化石墨烯、氧化铪、二氧化硅等材料。
5)有源区的制备:NMOS有源区同样采用电子束辐照的方式,加速电压,束流等参数与步骤3)形同,曝光时间增加至50s,形成NMOS有源区;PMOS的有源区仍然采用溴掺杂,在样品表面旋涂一层PMMA光刻胶(转速为4000rpm,一分钟),按照预先设计好的版图进行光刻定义出PMOS的有源区,然后显影使有源区的石墨暴露出来,再静置于溴蒸汽氛围中24h进行掺杂,形成PMOS的有源区。
虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (9)
1.一种碳基器件的制备方法,其特征在于,包括:
1)将采用化学气相沉积法合成的多层石墨烯薄膜,或者机械剥离的多层石墨烯或者石墨薄膜通过干法或者湿法转移的方法转移到衬底表面;将分析纯液溴与转移后的多层石墨烯或者石墨薄膜一同置于密闭容器中,使多层石墨烯或石墨薄膜暴露于溴蒸汽氛围中,进行长时间静置形成溴插层;
2)在溴插层处理后的多层石墨烯或者石墨薄膜表面涂上光刻胶,通过光刻,显影形成沟道区域,然后利用溅射的方式淀积一层金属层,再放入丙酮溶液中剥离掉沟道区域以外的金属,最后置于稀盐酸溶液中,除去沟道区域的多层石墨烯薄膜中每一层的碳原子,重复该过程直到沟道区域薄至一层或两层石墨烯薄膜;或在沟道区域的多层石墨烯或者石墨薄膜表面涂上光刻胶,采用光刻胶做掩膜,进行温和的氧等离子体刻蚀以产生大量空位缺陷,再进行氢等离子体刻蚀去除含大量缺陷的石墨烯层,重复该过程直到沟道区域薄至一层或两层石墨烯薄膜,用丙酮溶液除去光刻胶掩膜;
3)接着在上述溴插层处理后的多层石墨烯或者石墨薄膜表面再涂上光刻胶,利用光刻、显影图像化出电极区域,然后用等离子体刻蚀形成多层石墨烯的源与漏电极,完成碳基器件的制备。
2.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤1)所述多层石墨烯薄膜是大于等于5层。
3.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤1)所述石墨薄膜的厚度在100nm-2μm。
4.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤1)所述衬底是云母、蓝宝石、氮化硅、硅或氧化硅/硅。
5.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤1)所述的静置的时间在1-24小时之间。
6.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤2)所述金属采用锌或者铝。
7.如权利要求1所述的碳基器件的制备方法,其特征在于,步骤3)所述源与漏电极的石墨烯的层数为大于等于5层。
8.一种基于如权利要求1所述的碳基器件制备电路结构的方法,其特征在于,所述碳基器件的电极相互连接构成电路,互连部分的制备为,通过在溴插层处理后的多层石墨烯或者石墨薄膜表面涂上光刻胶,采用光刻、显影的方式定义出互联部分,然后利用等离子体刻蚀得到多层石墨烯或石墨的互连结构。
9.如权利要求7所述的制备电路结构的方法,其特征在于,所述互连结构的石墨烯的层数为大于等于5层,石墨薄膜的厚度为100nm-2μm。
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