CN113363345A - High-speed photon integrated chip based on surface plasmon enhancement and preparation method thereof - Google Patents

High-speed photon integrated chip based on surface plasmon enhancement and preparation method thereof Download PDF

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CN113363345A
CN113363345A CN202110603985.7A CN202110603985A CN113363345A CN 113363345 A CN113363345 A CN 113363345A CN 202110603985 A CN202110603985 A CN 202110603985A CN 113363345 A CN113363345 A CN 113363345A
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CN113363345B (en
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张国刚
王永进
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Nanjing University of Posts and Telecommunications
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    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
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Abstract

The invention relates to a high-speed photon integrated chip based on surface plasmon enhancement and a preparation method thereof. The surface plasmon enhanced LED device, the optical waveguide and the surface plasmon enhanced photoelectric detector are integrated on the same chip, light emitted by the LED device is laterally coupled into the optical waveguide and transmitted through the optical waveguide, and is detected by the photoelectric detector at the other end of the waveguide, the modulation bandwidth of the LED device and the responsivity of the photoelectric detector can be improved through the surface plasmon coupling effect, the overlapping degree of the light emitting spectrum of the LED and the response spectrum of the detector is increased, and finally the high-speed photon integrated chip is realized.

Description

High-speed photon integrated chip based on surface plasmon enhancement and preparation method thereof
Technical Field
The invention relates to the field of semiconductor photoelectronic devices and integration, in particular to a high-speed photon integrated chip based on surface plasmon enhancement and a preparation method thereof.
Background
The visible light communication technology is a novel wireless light transmission technology for performing data communication by using visible light, and has the advantages of high bandwidth, strong anti-interference performance, good confidentiality, no electromagnetic radiation and the like compared with the traditional wireless communication technology. With the rapid development and popularization of light emitting diodes, the increasing demand of high-speed wireless access, and the pulling of 6G layout in the future, the visible light communication technology has been rapidly developed in recent years. Gallium nitride (GaN) based material has excellent optical and electrical properties, can realize a homogeneous photon integrated chip of a light source, a waveguide and a detector, realizes electro-optical conversion by modulating the GaN-based light source, loads signals on modulated light, is coupled into the GaN-based optical waveguide, and is transmitted to the GaN-based photoelectric detector through the waveguide, so that the modulated light emitted by the light source is sensed by the detector, realizes the output of electric signals through the photoelectric conversion, and completes the information transmission in the chip.
The modulation bandwidth of the LED in the photonic integrated chip is mainly determined by an RC time constant and the service life of a current carrier, and the junction capacitance can be effectively reduced and the RC time constant can be reduced by reducing the size of the LED, so that the modulation bandwidth of the LED is improved, however, the method can also reduce the light output power of the LED; on the other hand, although InGaN multi-quantum well visible light detectors in photonic integrated chips have made some progress, great challenges still face to realize commercial applications, such as poor quality of epitaxial layer materials, high background carrier concentration, insufficient light absorption of multi-quantum wells, and the like, and InGaN detectors still have problems of low responsivity, slow response speed, and the like.
The surface plasmon is an element excitation mode formed by co-resonance oscillation of metal surface electrons under the excitation of an external electromagnetic field, has the characteristics of surface locality, near field enhancement and the like, can effectively improve the spontaneous radiation rate of a quantum well by utilizing the resonance coupling enhancement effect of the surface plasmon, correspondingly reduces the radiation recombination life of a carrier, namely can improve the luminous efficiency and the modulation bandwidth of an LED by utilizing the coupling effect of the surface plasmon; on the other hand, when the incident light resonates with free electrons in the metal nanostructure, the generated surface plasmons can cause strong light scattering and local electric field enhancement, and these effects can greatly increase the probability of generating electron-hole pairs in the epitaxial layer, thereby effectively enhancing the detection performance of the photodetector.
ZL201911133039X discloses a surface plasmon enhanced InGaN/GaN multiple quantum well photoelectrode, the invention adopts a self-assembly Ni mask top-down etching method to regulate and control the distance between plasma metal and multiple quantum wells, so that near field coupling can be generated, and under the combined action of an electromagnetic field generated by a surface plasmon effect and a built-in electric field formed by high doping concentration of a p-n region, the generation and transportation efficiency of electron hole pairs on the surface of an active region of the multiple quantum wells is effectively improved.
ZL2009100307856 discloses an integrated optical fiber-optic gyroscope chip based on a surface plasmon waveguide, which utilizes the transmission characteristic of the surface plasmon waveguide to realize single polarization of long-range transmission of optical signals, directly modulates a surface plasmon waveguide core layer, has a specific structure to eliminate the influence of light leakage on the precision of the fiber-optic gyroscope, but the bandwidth of the integrated optical fiber-optic gyroscope chip cannot be adjusted and the responsivity of the integrated optical fiber-optic gyroscope chip is slow.
Disclosure of Invention
In order to solve the problems, the invention provides a high-speed photonic integrated chip based on surface plasmon enhancement, wherein light emitted by an LED is transmitted through a waveguide, and is detected by a photoelectric detector at the other end of the waveguide, so that a single-chip high-speed photonic integrated chip is realized, and a preparation method of the high-speed photonic integrated chip is provided.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the invention relates to a high-speed photon integrated chip based on surface plasmon enhancement, which takes a silicon substrate LED epitaxial wafer as a carrier and comprises a silicon substrate layer, a buffer layer arranged on the silicon substrate layer, a non-doped GaN layer arranged on the buffer layer, an n-type GaN layer arranged on the non-doped GaN layer, an InGaN/GaN multi-quantum well layer arranged on the n-type GaN layer and a p-type GaN layer arranged on the InGaN/GaN multi-quantum well layer; the LED device and the photoelectric detector are arranged on the silicon substrate LED epitaxial wafer and are connected through a waveguide, the LED device and the photoelectric detector are both composed of a p-n junction, a p-type electrode and an n-type electrode, namely, the p-type GaN layer is etched downwards to the n-type GaN layer to form the LED device and the photoelectric detector, the LED device and the photoelectric detector respectively comprise a p-type electrode, an n-type electrode and a p-type region formed after the p-type GaN layer is etched, a Ni/Au current expansion layer connected with the p-type electrode is arranged on the p-type region, the p-type electrode is arranged on a silicon dioxide layer, and the n-type electrode and the silicon dioxide layer are respectively arranged on an n-type table board; the LED device and the photoelectric detector both further comprise an etched InGaN/GaN multi-quantum well layer and an etched n-type GaN layer; the photodetector size is smaller than the LED device size.
The invention is further improved in that: the number of the n-type mesas is two, the n-type mesas are arranged on the n-type GaN layer, and n-type electrodes are symmetrically arranged on two sides of each p-type electrode.
The invention is further improved in that: the p-n junction comprises an n-type GaN layer, an InGaN/GaN multi-quantum well layer and a p-type GaN layer which are sequentially connected from bottom to top, the LED device and the photoelectric detector are provided with an ordered nano-pore array in the p-type GaN (6), the depth of the nano-pore array extends from the surface of the p-type GaN layer to the inside of the p-type GaN layer and has a certain distance with the InGaN/GaN multi-quantum well layer, the period of the nano-pore array in the photoelectric detector is larger than that in the LED device, and the duty ratio of the nano-pore array is 0.5; the bottom of the nanopore array is provided with a two-dimensional metal nanopore array, the period of the nanopore array is 500nm and the depth of the nanopore array is 130 nm and 280nm, and the thickness of the two-dimensional metal nanopore array is 15-30 nm.
The invention is further improved in that: an n-type table top is etched on the n-type GaN layer, a silicon dioxide isolation layer is arranged on the n-type table top, current expansion layers are respectively arranged on the surface of the p-type GaN layer of the LED device and the surface of the p-type GaN layer of the photoelectric detector, the p-type electrode is arranged on the silicon dioxide isolation layer and connected with the current expansion layers, and the n-type electrode is arranged on the n-type table top.
The invention relates to a preparation method of a high-speed photon integrated chip based on surface plasmon enhancement, which comprises the following steps:
1) thinning the silicon substrate layer behind the silicon-based InGaN/GaN multi-quantum well LED epitaxial wafer;
2) uniformly coating a layer of PMGI electron beam glue (11) which is easy to remove glue and peel on an LED epitaxial wafer, then uniformly coating a second layer of electron beam glue ZEP520A (12) on the PMGI electron beam glue (11), defining the positions of two-dimensional nanopore patterns by using an electron beam exposure technology, and transferring the nanopore patterns to a p-type GaN layer by using an Inductively Coupled Plasma (ICP) etching technology to ensure that the bottoms of the nanopores have a certain distance with an InGaN/GaN multi-quantum well layer;
3) evaporating metal by using an electron beam evaporation technology, and forming a two-dimensional metal nano array at the bottom of the nano hole of the p-type GaN layer by using a stripping process to obtain a metal/semiconductor nano composite structure;
4) defining an LED device, a photoelectric detector and a waveguide region by utilizing a photoetching alignment technology based on the metal/semiconductor nano composite structure prepared in the step 3), and etching an LED epitaxial wafer by adopting Inductive Coupling Plasma (ICP) to penetrate downwards to an n-type GaN layer to expose an n-type GaN table top;
5) defining p-type areas of the LED device and the photoelectric detector, evaporating a Ni/Au current expansion layer on the exposed p-type areas by using an electron beam evaporation technology, and quickly annealing to complete ohmic contact;
6) growing a silicon dioxide layer on the surface of an InGaN/GaN multi-quantum well LED epitaxial wafer, defining the silicon dioxide layer region by photoetching as a p-type electrode isolation region of an LED device and a photoelectric detector, and finishing silicon dioxide (SiO) by adopting a Reactive Ion Etching (RIE) etching process2) An isolation layer pattern;
7) defining p-type electrode and n-type electrode regions of LED device and photodetector, and evaporating Cr/Au layer as p-type electrode and n-type electrode by electron beam evaporation technology, wherein the p-type electrode is evaporated on silicon dioxide (SiO)2) On the isolation layer, the isolation layer is partially overlapped with the Ni/Au current expansion layer, and the n-type electrode is evaporated on the table top of the n-type GaN layer to obtain an LED device and a photoelectric detector;
8) and defining a back etching window which is aligned with and covers the LED device, the photoelectric detector and the waveguide, and suspending the chip to obtain the high-speed photon integrated chip based on surface plasmon enhancement.
The invention is further improved in that: in the InGaN/GaN multi-quantum well layer, the In component is more than or equal to 0.15 and less than or equal to 0.30, the light emitting wavelength of an active layer of the InGaN/GaN multi-quantum well layer is 430nm to 540nm, the number of cycles of a quantum well is 5-10, and the thickness of a p-type GaN layer (6) is 150-300 nm.
The invention is further improved in that: the size of the LED device is 30-150 μm, the size of the photoelectric detector is 20-130 μm, the width of the optical waveguide is 30-150 μm, and the length of the optical waveguide is 200-1000 μm.
The invention is further improved in that: in the step 8), the device is suspended by adopting a deep silicon etching technology and a nitride etching technology, and the thickness of the suspended device is 2-4 microns.
The invention is further improved in that: and a cavity is arranged below the waveguide, the LED device and the photoelectric detector to suspend the LED device, the photoelectric detector and the waveguide, and the cavity penetrates through the silicon substrate layer, the buffer layer and the non-doped GaN layer to the bottom surface of the n-type GaN layer.
The invention is further improved in that: the p-type electrode and the n-type electrode are both made of metal materials of chromium/gold.
The invention is further improved in that: the p-type electrode and the n-type electrode are made of chromium/gold (Cr/Au), the p-type electrode window area comprises a suspended p-type electrode area window, a p-type electrode conducting area window and a p-type electrode lead area window which are sequentially connected, the n-type electrode window area comprises an n-type electrode conducting area window and an n-type electrode lead area window which are mutually connected, and the stripping process and the air atmosphere rapid annealing technology with the temperature controlled at 550 ℃ are adopted.
The invention has the beneficial effects that: according to the high-speed photon integrated chip based on surface plasmon enhancement, an LED device with surface plasmon enhancement, an optical waveguide and a photoelectric detector with surface plasmon enhancement are integrated on the same chip, light emitted by the LED device is laterally coupled into the optical waveguide, is transmitted through the optical waveguide and is detected by the photoelectric detector at the other end of the waveguide, and a single-chip photon integrated device is realized; the resonance wavelengths of surface plasmons in the LED and the detector are respectively regulated and controlled, and the carrier recombination rate in the multiple quantum wells can be effectively accelerated through the resonance coupling enhancement effect of the surface plasmons, so that the modulation bandwidth of the LED is improved; on the other hand, the surface plasmon resonance wavelength is matched with the absorption wavelength of the photoelectric detector, the responsivity of the detector is effectively improved, the size of the detector is properly reduced, the RC time constant of the detector can be reduced, the corresponding speed of the detector is further improved, the overlapping degree of the emission spectrum of the LED and the response spectrum of the detector can be increased under the action of the surface plasmon, and finally the high-speed photon integrated chip is realized.
Drawings
FIG. 1 is a front view of a high speed photonic integrated chip in accordance with the present invention.
FIG. 2 is a top cross-sectional view of a high speed photonic integrated chip in accordance with the present invention.
FIG. 3 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (1) of the embodiment.
FIG. 4 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (2) of the embodiment.
FIG. 5 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (3) of the embodiment.
FIG. 6 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (4) of the embodiment.
FIG. 7 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (5) of the embodiment.
FIG. 8 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (6) of the embodiment.
FIG. 9 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (7) of the embodiment.
FIG. 10 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (8) of the embodiment.
FIG. 11 is a schematic structural diagram of the high-speed photonic integrated chip obtained in step (9) of the embodiment.
FIG. 12 is a diagram illustrating the structure of the high-speed photonic integrated chip obtained in step (10) of the embodiment.
Wherein: 1-a silicon substrate layer; 2-a buffer layer; 3-undoped GaN layer; a 4-n type GaN layer; 5-InGaN/GaN multi-quantum well layer; a 6-p type GaN layer; 7-a metal; 8-Ni/Au current spreading layer; 9-a silicon dioxide layer; 10-Cr/Au layer; 11-PMGI; 12-ZEP 520A.
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary.
As shown in the figure 1-2, the invention relates to a high-speed photonic integrated chip based on surface plasmon enhancement, which takes an InGaN/GaN multi-quantum well LED epitaxial wafer as a carrier, and comprises a silicon substrate layer 1, a buffer layer 2 arranged on the silicon substrate layer 1, a non-doped GaN layer 3 arranged on the buffer layer 2, an n-type GaN layer 4 arranged on the non-doped GaN layer 3, an InGaN/GaN multi-quantum well layer 5 arranged on the n-type GaN layer 4, and a p-type GaN layer 6 arranged on the InGaN/GaN multi-quantum well layer 5; the LED/GaN multi-quantum well LED epitaxial wafer comprises an LED device and a photoelectric detector which are arranged on an InGaN/GaN multi-quantum well LED epitaxial wafer, wherein the LED device and the photoelectric detector are connected through a waveguide, the LED device and the photoelectric detector respectively comprise a p-n junction, a p-type electrode and an n-type electrode, and the size of the photoelectric detector is smaller than that of the LED device.
The LED device and the photoelectric detector are characterized in that a p-n junction of the LED device and the photoelectric detector comprises an n-type GaN layer 4, an InGaN/GaN multi-quantum well layer 5 and a p-type GaN layer 6 which are sequentially connected from bottom to top, the LED device and the photoelectric detector are provided with an ordered nanopore array in a p-type region, the depth of the nanopore array is from the surface of the p-type GaN layer 6 to the inside of the p-type GaN layer, the nanopore array is spaced from the InGaN/GaN multi-quantum well layer 5, and a two-dimensional metal nanoarray is arranged at the bottom of the nanopore array.
An n-type mesa is etched on the n-type GaN layer 4, a silicon dioxide isolation layer 9 is arranged on the n-type mesa, a Ni/Au current expansion layer 8 is respectively arranged on the surface of the p-type GaN layer 6 of the LED device and the surface of the p-type GaN layer 6 of the photoelectric detector, the p-type electrode is arranged on the silicon dioxide isolation layer 9 and connected with the Ni/Au current expansion layer 8, and the n-type electrode is arranged on the n-type mesa.
And a cavity which is opposite to the LED device, the photoelectric detector and the waveguide and penetrates through the silicon substrate layer 1, the buffer layer 2, the non-doped GaN layer 3 to the bottom surface of the n-type GaN layer 4 is arranged below the n-type GaN layer 4, so that the LED device, the photoelectric detector and the waveguide are suspended.
The waveguide is formed by etching from the p-type GaN layer 6 down to the n-type GaN layer 4.
The p-type electrode and the n-type electrode are both made of metal materials of chromium/gold (Cr/Au).
The InGaN/GaN multi-quantum well layer 5 is more than or equal to 0.15, the In component is less than or equal to 0.30, the light emitting wavelength of the multi-quantum well active layer is 430nm to 540nm, the number of cycles of the multi-quantum well is 5-10, and the thickness of the p-type GaN layer 6 is 150nm to 300 nm.
The period of the nanopore array is 300-500nm, and the depth is 130-280 nm.
The LED device has a size of 30 μm × 30 μm-150 μm × 150 μm, and the photodetector has a size of 20 μm × 20 μm-130 μm × 130 μm.
The width of the waveguide is 30-150 μm, and the length is 200-1000 μm.
A preparation method of a high-speed photon integrated chip based on surface plasmon enhancement comprises the following steps:
1) sequentially growing a buffer layer 2, a non-doped GaN layer 3, an n-type GaN layer 4, an InGaN/GaN multi-quantum well layer 5 and a p-type GaN layer 6 on a silicon substrate layer 1 to prepare an InGaN/GaN multi-quantum well LED epitaxial wafer; the In component In the InGaN/GaN multi-quantum well LED epitaxial wafer is 0.2, the light emitting wavelength is 450nm, the periodicity of an InGaN/GaN multi-quantum well layer 5 is 5, the thickness of the InGaN well layer is 3nm, and the thickness of a GaN barrier layer is 12 nm; the thickness of the p-type GaN layer 6 is 200 nm;
2) thinning the back of a silicon substrate layer 1 on an InGaN/GaN multi-quantum well LED epitaxial wafer, homogenizing a layer of PMGI electron beam glue 11 which is easy to remove glue and strip and has the glue thickness of 30nm, homogenizing a second layer of ZEP520A electron beam glue 12, and homogenizing the glue thickness of 400 nm;
3) the positions of two-dimensional nanopore patterns are defined by using an electron beam exposure technology, the period of the nanopore in the LED area is 400nm, the duty ratio is 0.5, and the size is 60 micrometers multiplied by 60 micrometers; the period of the nano-pores in the photodetector region is 410nm, the duty ratio is 0.5, and the size is 50 micrometers multiplied by 50 micrometers;
4) transferring the nanopore graph to p-type GaN by using double-layer electron beam glue as a mask and adopting an ICP (inductively coupled plasma) etching technology, and controlling the etching depth to enable the distance from the bottom of the nanopore to the multi-quantum well layer to be about 20 nm;
5) evaporating a layer of aluminum (Al) metal layer 7 on the surface of an LED epitaxial wafer by adopting an electron beam evaporation system (PVD), wherein the thickness of the aluminum (Al) metal layer is 20 nanometers, then removing the residual electron beam photoresist and the Al metal layer on the surface of the sample wafer by adopting a stripping process, namely utilizing ZEP stripping liquid to remove the residual electron beam photoresist and the Al metal layer on the surface of the sample wafer, and forming a two-dimensional Al nano array 7 at the bottom of a p-type GaN hole, wherein the period of the Al nano array in an LED region is 400nm, the duty ratio is 0.5, the period of the Al nano array in a photoelectric detector region is 410nm, and the duty ratio is 0.5;
6) defining an LED device, a photoelectric detector and a waveguide region by adopting a photoetching alignment technology, wherein the sizes of the LED device and the photoelectric detector are respectively 60 micrometers multiplied by 60 micrometers and 50 micrometers multiplied by 50 micrometers, etching the LED epitaxial wafer by adopting ICP (inductively coupled plasma) to penetrate downwards to the n-type GaN layer 4, exposing the n-type GaN mesa, and etching the depth of 500 nm;
7) defining p-type regions of an LED device and a photoelectric detector on an LED epitaxial wafer by adopting a photoetching alignment technology, evaporating a Ni/Au current expansion layer 8 on the exposed p-type region by utilizing PVD (physical vapor deposition), wherein the thickness of the Ni/Au current expansion layer is 5nm, removing photoresist, and then rapidly annealing at 550 ℃ in an air atmosphere to complete ohmic contact;
8) growing a silicon dioxide layer on the surface of the InGaN/GaN multi-quantum well LED epitaxial wafer by adopting PECVD (plasma enhanced chemical vapor deposition), then photoetching and defining a silicon dioxide isolation layer area, and finishing the pattern of the silicon dioxide layer 9 by adopting RIE (reactive ion etching) process;
9) photoetching and defining p-type electrode and n-type electrode regions, utilizing PVD to evaporate a Cr/Au layer 10 to be used as the p-type electrode and the n-type electrode, wherein the thickness of the Cr/Au layer 10 is 50/150nm, the p-type electrode is evaporated on a silicon dioxide isolation layer 9 and partially overlapped with a Ni/Au current expansion layer (8), and the n-type electrode is evaporated on a table top of an n-type GaN layer 4, so that an LED device and a photoelectric detector are obtained;
10) coating glue on the top layer of the silicon substrate LED epitaxial wafer for protection to prevent surface devices from being damaged in the etching process, spin-coating a photoresist layer on the lower surface of a silicon substrate layer 1 of the silicon substrate LED epitaxial wafer, and defining a back etching window which is aligned with and covers the LED devices, the photoelectric detector and the waveguide region by using a back alignment technology; taking the buffer layer as an etching barrier layer, and etching the silicon substrate layer 1 to the lower surface of the buffer layer through a back etching window by utilizing a deep silicon etching technology to form a cavity; performing nitride thinning treatment on the buffer layer 2, the non-doped GaN layer 3 and the n-type GaN layer 4 from bottom to top by adopting an ICP (inductively coupled plasma) etching technology, wherein the thickness of the residual GaN is about 3 mu m; and removing residual photoresist, namely the surface plasmon enhanced high-speed photonic integrated chip.
The above description is only an embodiment of the present invention, and is not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (8)

1. The utility model provides a high-speed photon integrated chip based on surface plasmon enhancement, high-speed photon integrated chip includes silicon substrate layer (1), buffer layer (2), non-doping GaN layer (3), n type GaN layer (4), InGaN/GaN multiple quantum well layer (5) and p type GaN layer (6) by supreme down in proper order, its characterized in that: the high-speed photon integrated chip takes a silicon substrate LED epitaxial wafer as a carrier, an LED device and a photoelectric detector are arranged on the silicon substrate LED epitaxial wafer, the LED device is connected with the photoelectric detector through a waveguide, and the LED device and the photoelectric detector respectively comprise a p-n junction, a p-type electrode and an n-type electrode.
2. The surface plasmon enhancement based high speed photonic integrated chip of claim 1, wherein: the P-n junction is a P-type region formed by etching the P-type GaN layer (6) downwards through an InGaN/GaN multi-quantum well layer (5) to an n-type GaN layer (4), an ordered nanopore array is arranged in the P-type GaN layer (6) of the LED device, the duty ratio of the nanopore array of the LED device is 0.5, the depth of the nanopore array of the LED device extends from the surface of the P-type GaN layer (6) to the inside of the P-type GaN layer and is spaced from the InGaN/GaN multi-quantum well layer (5), the ordered nanopore array is arranged in the P-type GaN layer (6) of the photoelectric detector, the duty ratio of the nanopore array of the photoelectric detector is 0.5, the depth of the nanopore array of the photoelectric detector extends from the surface of the P-type GaN layer (6) to the inside of the P-type GaN layer and is spaced from the InGaN/GaN multi-quantum well layer (5), and the period of the nanopore array in the photoelectric detector is larger than that of the nanopore array in the LED device, and two-dimensional metal nano arrays (7) are respectively arranged at the bottoms of the nano hole arrays of the LED device and the photoelectric detector.
3. The surface plasmon enhancement based high speed photonic integrated chip of claim 2, wherein: the period of the nanopore array is 300-500nm, the depth is 130-280nm, and the thickness of the two-dimensional metal nanopore array (7) is 15-30 nm.
4. The surface plasmon enhancement based high speed photonic integrated chip of claim 1, wherein: an n-type table top is etched on the n-type GaN layer (4), a silicon dioxide isolation layer (9) is arranged on the n-type table top, a current expansion layer (8) is respectively arranged on the surface of a p-type GaN layer (6) of the LED device and the surface of a p-type GaN layer (6) of the photoelectric detector, a p-type electrode is arranged on the silicon dioxide isolation layer (9) and connected with the current expansion layer (8), and the n-type electrode is arranged on the n-type table top.
5. The method for preparing the high-speed photonic integrated chip based on surface plasmon enhancement according to any of claims 1-4, wherein: the preparation method comprises the following steps:
1) thinning the silicon substrate layer (1) behind the silicon substrate LED epitaxial wafer;
2) uniformly coating a layer of PMGI electron beam glue (11) on an LED epitaxial wafer, then uniformly coating a second layer of electron beam glue ZEP520A (12) on the PMGI electron beam glue (11), defining the positions of two nanopore patterns by using an electron beam exposure technology, and transferring the nanopore patterns to a p-type GaN layer (6) by adopting an inductive coupling plasma etching technology to ensure that the bottoms of the nanopores have a distance with an InGaN/GaN multi-quantum well layer (5);
3) evaporating metal by using an electron beam evaporation technology, and forming a two-dimensional metal nano array (7) at the bottom of the nanopore of the p-type GaN layer (6) by using a stripping process to obtain a metal/semiconductor nano composite structure;
4) defining an LED device, a photoelectric detector and a waveguide region by utilizing a photoetching alignment technology based on the metal/semiconductor nano composite structure prepared in the step 3), etching an LED epitaxial wafer by adopting inductively coupled plasma to penetrate downwards to an n-type GaN layer (4) to expose an n-type GaN table board;
5) defining p-type regions of the LED device and the photoelectric detector, evaporating a current expansion layer (8) on the exposed p-type regions by using an electron beam evaporation technology, and quickly annealing to complete ohmic contact;
6) growing a silicon dioxide layer on the surface of an InGaN/GaN multi-quantum well LED epitaxial wafer, defining the silicon dioxide layer region by photoetching as a p-type electrode isolation region of an LED device and a photoelectric detector, and finishing the graph of the silicon dioxide isolation layer (9) by adopting a reactive ion etching process;
7) defining areas of a p-type electrode and an n-type electrode of the LED device and the photoelectric detector, and evaporating a Cr/Au layer by using an electron beam evaporation technology to serve as the p-type electrode and the n-type electrode, wherein the p-type electrode is evaporated on a silicon dioxide isolation layer (9) and partially overlapped with a current expansion layer (8), and the n-type electrode is evaporated on a table top of an n-type GaN layer to obtain the LED device and the photoelectric detector;
8) and defining a back etching window which is aligned with and covers the LED device, the photoelectric detector and the waveguide, and suspending the chip to obtain the high-speed photon integrated chip based on surface plasmon enhancement.
6. The method for preparing the high-speed photonic integrated chip based on surface plasmon enhancement according to claim 5, wherein the method comprises the following steps: in the InGaN/GaN multi-quantum well layer (5), the In component is more than or equal to 0.15 and less than or equal to 0.30, the light emitting wavelength of the active layer of the InGaN/GaN multi-quantum well layer (5) is 430nm to 540nm, the number of periods of quantum wells is 5-10, and the thickness of the p-type GaN layer (6) is 150-300 nm.
7. The method for preparing the high-speed photonic integrated chip based on surface plasmon enhancement according to claim 5, wherein the method comprises the following steps: the size of the LED device is 30-150 μm, the size of the photoelectric detector is 20-130 μm, the width of the optical waveguide is 30-150 μm, and the length of the optical waveguide is 200-1000 μm.
8. The method for preparing the high-speed photonic integrated chip based on surface plasmon enhancement according to claim 5, wherein the method comprises the following steps: in the step (8), the thickness of the suspended device is 2-4 μm.
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CN114236334A (en) * 2021-11-05 2022-03-25 严群 System for detecting electroluminescence performance of LED by enhancing current injection through optical excitation
CN114678429A (en) * 2022-05-30 2022-06-28 陕西半导体先导技术中心有限公司 MISIM type 4H-SiC ultraviolet detector with composite structure and preparation method thereof

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CN112563302A (en) * 2021-03-01 2021-03-26 南京邮电大学 Micro-nano composite structure photonic integrated chip and preparation method thereof

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CN109524516A (en) * 2018-09-29 2019-03-26 南京邮电大学 Transferable logic chip based on mechanical stripping and preparation method thereof
CN112563302A (en) * 2021-03-01 2021-03-26 南京邮电大学 Micro-nano composite structure photonic integrated chip and preparation method thereof

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CN114236334A (en) * 2021-11-05 2022-03-25 严群 System for detecting electroluminescence performance of LED by enhancing current injection through optical excitation
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