CN113327924A - Semiconductor device, display substrate and display device - Google Patents

Semiconductor device, display substrate and display device Download PDF

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Publication number
CN113327924A
CN113327924A CN202110573677.4A CN202110573677A CN113327924A CN 113327924 A CN113327924 A CN 113327924A CN 202110573677 A CN202110573677 A CN 202110573677A CN 113327924 A CN113327924 A CN 113327924A
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electrode
substrate
semiconductor device
gate
orthographic projection
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CN113327924B (en
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郭威
韩天洋
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Abstract

The utility model provides a semiconductor device, display substrate and display device, belongs to and shows technical field. The semiconductor device of the present disclosure includes: the thin film transistor and the switching element are positioned on the substrate; the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer; the switching element includes: a third electrode on the substrate; the switching element further includes: the fourth electrode and the fifth electrode are respectively positioned on two sides of the third electrode, and the cantilever beam structure is suspended on the third electrode; wherein the fourth electrode is electrically connected with the second electrode; and the orthographic projection of the cantilever beam structure on the substrate is at least partially overlapped with the orthographic projection of the third electrode, the fourth electrode and the fifth electrode on the substrate.

Description

Semiconductor device, display substrate and display device
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a semiconductor device, a display substrate and a display device.
Background
The performance of the tft, which is an important electrical device in a display device, directly affects the display effect and the service life of the display device.
In the off state of the thin film transistor in the current display device, the leakage current is large, which easily causes the device to generate heat and wastes large power consumption. In the display process of the display device, because of the existence of leakage current, the display picture is easy to have poor afterimage, and the display effect is influenced.
Disclosure of Invention
The present disclosure is directed to at least one of the problems of the prior art, and provides a semiconductor device, a display substrate and a display device.
In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including: the thin film transistor and the switching element are positioned on the substrate;
the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer;
the switching element includes: a third electrode on the substrate; the switching element further includes: the fourth electrode and the fifth electrode are respectively positioned on two sides of the third electrode, and the cantilever beam structure is suspended on the third electrode; wherein the fourth electrode is electrically connected to the second electrode;
the orthographic projection of the cantilever beam structure on the substrate is at least partially overlapped with the orthographic projection of the third electrode, the orthographic projection of the fourth electrode and the orthographic projection of the fifth electrode on the substrate.
Optionally, the gate insulating layer extends to a region where the switching element is located, wherein the gate insulating layer is hollowed at the third electrode, the gate insulating layer is located between the fourth electrode and the substrate, and the gate insulating layer is located between the fifth electrode and the substrate.
Optionally, the cantilever beam structure comprises: a support portion and a suspension portion;
the supporting part is fixed on the substrate, and one end of the supporting part is connected with one end of the suspension beam part;
one end of the suspension beam part is connected with one end of the supporting part, and the other end of the suspension beam part is suspended.
Optionally, the cantilever beam structure comprises: a support portion and a suspension portion;
the supporting part is fixed on the fifth electrode, and one end of the supporting part is connected with one end of the suspension beam part;
one end of the suspension beam part is connected with one end of the supporting part, and the other end of the suspension beam part is suspended.
Optionally, the fourth electrode and the second electrode are of an integrally formed structure.
Optionally, the cantilever beam structure is a gold/aluminum/gold laminate structure.
Optionally, the material of the active layer comprises: a carbon nanotube material.
In a second aspect, embodiments of the present disclosure provide a display substrate including the semiconductor device provided as above.
Optionally, the display substrate further comprises: the passivation layer is positioned on one side, away from the substrate, of the first electrode and the second electrode, and the first through hole penetrates through the passivation layer;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the fourth electrode on the substrate;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the fifth electrode on the substrate;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the suspended beam structure on the substrate.
Optionally, the display substrate further comprises: the first conductor layer, the second conductor layer and the third conductor layer are positioned on the substrate and are sequentially arranged in an insulating mode along the direction deviating from the substrate;
the first conductor layer includes: the grid electrode and the third electrode;
the second conductor layer includes: the first electrode, the second electrode, the fourth electrode, and the fifth electrode;
the third conductor layer includes: the suspension beam structure.
Optionally, the display substrate further comprises: a plurality of gate lines and a plurality of data lines arranged in a crossing manner.
Optionally, a plurality of the semiconductor devices are arranged in an array;
at least part of the grid electrodes of the semiconductor devices in the same row are electrically connected with the same grid line and are of an integrally formed structure;
at least part of the fifth electrodes of the semiconductor devices in the same row are electrically connected with the same data line and are of an integrally formed structure, or when the supporting part is fixed on the fifth electrodes, at least part of the fifth electrodes of the semiconductor devices in the same row are electrically connected with the same data line, and the data line and the supporting part are of an integrally formed structure.
Optionally, the display substrate further comprises: a first voltage signal line extending in the same direction as the gate line; the first voltage signal line is positioned between the adjacent grid lines;
the first conductor layer further includes: the first voltage signal line.
Optionally, at least a portion of the third electrodes of the semiconductor devices in the same row are electrically connected to the same first voltage signal line and are of an integrally formed structure.
Optionally, the display substrate further comprises: a second voltage signal line extending in the same direction as the gate line;
the third conductor layer further includes: the second voltage signal line.
Optionally, at least a portion of the suspended beam structure of the semiconductor device in the same row is electrically connected to the same second voltage signal line and is an integrally formed structure.
In a third aspect, embodiments of the present disclosure provide a display device including the display substrate provided as described above.
Drawings
FIG. 1 is a schematic diagram of an exemplary thin film transistor;
FIG. 2 is a schematic diagram of a partial structure of an exemplary display substrate;
fig. 3A is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;
fig. 3B is a schematic structural diagram of another semiconductor device provided in the embodiments of the present disclosure;
fig. 4A is a schematic cross-sectional structure of the semiconductor device shown in fig. 3A in a direction a-a';
FIG. 4B is a schematic cross-sectional view of the semiconductor device shown in FIG. 3B in the direction B-B';
FIG. 5 is a schematic view of a cantilever beam structure;
fig. 6 is a schematic structural diagram of another semiconductor device provided in the embodiments of the present disclosure;
fig. 7 is a schematic cross-sectional structure of the semiconductor device shown in fig. 6 in a direction C-C;
fig. 8A is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;
fig. 8B is a schematic structural diagram of another display substrate provided in the embodiments of the present disclosure;
FIG. 9A is a schematic cross-sectional view of the display substrate shown in FIG. 8A along the direction D-D';
FIG. 9B is a schematic cross-sectional view of the display substrate shown in FIG. 8B along the direction E-E';
fig. 10 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure;
fig. 11 is a schematic cross-sectional view of the display substrate shown in fig. 10 along the direction F-F'.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Fig. 1 is a schematic structural diagram of an exemplary thin film transistor, which is formed on a substrate 101 as shown in fig. 1, and includes: a gate electrode 102, a gate insulating layer 103, an active layer 104, a first electrode 105, and a second electrode 106; the first electrode 105 and the second electrode 106 are connected to the active layer 103, respectively; wherein one of the first electrode 105 and the second electrode 106 is a source electrode, and the other is a drain electrode. The thin film transistor may be applied to a Liquid Crystal Display (LCD) substrate, and may also be applied to an Organic Light-Emitting Diode (OLED) Display substrate. It should be noted that the thin film transistor used may also be a field effect transistor or other similar device, and since the source and the drain of the thin film transistor are symmetrical, there is no difference between the source and the drain. To distinguish the source and drain of the thin film transistor, in the embodiment of the present disclosure, the first electrode 105 may be a drain, and the second electrode 106 may be a source. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the thin film transistor, and in the following embodiment, the N-type transistor is used for explanation, when the N-type transistor is adopted, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, and when the grid electrode inputs a high level, the source electrode and the drain electrode are conducted; and the P type is opposite, and when the grid electrode inputs a low level, the source electrode and the drain electrode are conducted. In the embodiments of the present disclosure, an N-type transistor will be described as an example.
Fig. 2 is a schematic partial structure diagram of an exemplary display substrate, as shown in fig. 2, the display panel includes a plurality of common electrode lines (not shown), a plurality of Gate lines Gate and a plurality of Data lines Data, the plurality of Gate lines Gate and the plurality of Data lines Data intersect to define a plurality of pixel units, each pixel unit includes a thin film transistor T and a pixel electrode 107, each pixel electrode 107 corresponds to a common electrode, or the pixel electrodes 107 in all the pixel units correspond to an integral common electrode. The Gate electrode of the thin film transistor T is connected to the Gate line Gate, the source electrode is connected to the Data line Data, and the drain electrode is connected to the pixel electrode 107. It is understood that the pixel unit may further include a storage capacitor, other transistors, and other devices, which may be connected according to a connection method in the related art, and are not described herein again. For a liquid crystal display panel, in some embodiments, the pixel electrode 107 and the common electrode may be disposed opposite to each other, a liquid crystal layer is disposed between the pixel electrode 107 and the common electrode, and the common electrode may be connected to the common electrode line through a via hole; in other embodiments, such as Advanced Super Dimension Switch (ADS) technology, the pixel electrode 107 may be located on the same side of the liquid crystal layer as the common electrode, and an electric field (e.g., a horizontal electric field) is formed between the pixel electrode 107 and the common electrode to control liquid crystal deflection, so as to achieve display effect.
When the pixel unit displays, a scan signal can be loaded on the Gate line Gate and input to the Gate 102 of the thin film transistor T, so that the thin film transistor T is turned on. A Data voltage is applied to the Data line Data, and thus the Data voltage is input to the pixel electrode 107. A common voltage is applied to the common electrode line, and thus the common voltage is input to the common electrode. Liquid crystal molecules in the liquid crystal layer can be deflected under the drive of an electric field formed by data voltage and common voltage, the deflected liquid crystal molecules can transmit light rays with certain brightness, and the transmittance of the liquid crystal molecules can be changed by adjusting the electric field intensity between the pixel electrode 107 and the common electrode, so that different gray scale display can be realized. When the pixel unit does not display, no signal is loaded on the grid line Gate, so that the thin film transistor is closed. However, due to the semiconductor characteristics of the material of the active layer 104, the thin film transistor still has a certain leakage current when in the off state, for example, when the active layer 104 is made of carbon nanotubes, the leakage current therein may be large, so that the thin film transistor cannot be in the fully off state, which easily causes heat generation of the device and wastes large energy consumption. In the display process of the display substrate, due to the existence of leakage current, the display screen is easy to have poor image sticking, and the display effect is influenced.
The carbon nano tube is considered as an ideal active layer material for constructing the sub-nano transistor, and the tube diameter of the atomic scale ensures that the device has excellent grid electrostatic control capability and is easier to overcome the short channel effect; theoretical research shows that the carbon nanotube device has 5-10 times of advantages in speed and power consumption compared with a silicon-based device, the carbon nanotube is easy to obtain and low in price, and when the active layer is manufactured by using the carbon nanotube, modes such as coating and the like can be used, so that the process is simple, and the development requirement of an integrated circuit in the post-Mole era can be met. In the long run, the carbon nanotube material device is expected to replace a silicon-based material device.
In a particular embodiment, the material of the active layer 104 includes single-walled carbon nanotubes (SWCNTs). Specifically, single-walled carbon nanotubes are classified into semiconductor-type single-walled carbon nanotubes (s-SWCNTs) and metal-type single-walled carbon nanotubes (m-SWCNTs). The most desirable material for the active layer 104 is s-SWCNTs, which can greatly reduce the leakage current of the thin film transistor. However, due to current manufacturing techniques, there may be about 1/3 m-SWCNTs when manufacturing s-SWCNTs, which requires further purification of semiconductor-type single-walled carbon nanotubes using various purification techniques. However, according to the current purification process, even if the molar ratio of s-SWCNTs in SWCNTs is increased to 99.99%, the leakage current value of the prepared thin film transistor is still large, and it is difficult to meet the increasingly severe requirements brought by the continuous development of the driving technology.
In order to solve at least one of the above technical problems, the present disclosure provides a semiconductor device, a display substrate and a display device, and the semiconductor device, the display substrate and the display device provided in the embodiments of the present disclosure will be described in further detail with reference to the following detailed description and the accompanying drawings.
In a first aspect, an embodiment of the present disclosure provides a semiconductor device, fig. 3A is a schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure, and fig. 4A is a schematic structural cross-sectional diagram of the semiconductor device shown in fig. 3A on a-a' path, as shown in fig. 3A and fig. 4A, the semiconductor device includes: a substrate 101, and a thin film transistor and a switching element which are located on the substrate 101; the thin film transistor includes: a gate electrode 102, a gate insulating layer 103, an active layer 104, a first electrode 105 as a drain electrode, and a second electrode 106 as a source electrode; the first electrode 105 and the second electrode 106 are connected to the active layer 104, respectively. Note that the thin film transistor may have a top gate structure or a bottom gate structure, and fig. 3A and 4A illustrate the bottom gate structure as an example. Specifically, when the thin film transistor is a bottom gate structure, the gate electrode 102, the gate insulating layer 103, the active layer 104, the first electrode 105 as a drain electrode, and the second electrode 106 as a source electrode are sequentially disposed on the substrate 101, and the first electrode 105 and the second electrode 106 are respectively connected to the active layer 104, wherein the first electrode 105 and the second electrode 106 may be disposed at the same layer. The switching element includes: a third electrode 201 on the substrate 101; the switching element further includes: a fourth electrode 202 and a fifth electrode 203 respectively positioned at two sides of the third electrode 201, and a cantilever structure 204 suspended on the third electrode 201; wherein the fourth electrode 202 is electrically connected to the second electrode 106; the orthographic projection of the cantilever beam structure 204 on the substrate 101 is at least partially overlapped with the orthographic projection of the third electrode 201, the fourth electrode 202 and the fifth electrode 203 on the substrate 101. For ease of illustration, the gate insulation layer 103 is not shown in fig. 3A.
For example, the substrate 101 may be made of a rigid material such as glass, which may improve the load-bearing capacity of the substrate 101 for other film layers thereon. Certainly, the substrate 101 may also be made of a flexible material such as Polyimide (PI), which can improve the bending resistance and the tensile resistance of the semiconductor device, and avoid the substrate 101 from being broken due to the stress generated during the bending, stretching, and twisting processes, resulting in poor open circuit. In practical applications, the material of the substrate 101 can be selected according to practical requirements, so as to ensure that the semiconductor device has good performance.
For example, the material of the gate 102 may include a metal material or an alloy material, such as a metal material including molybdenum, aluminum, or titanium, or an alloy including one or more of molybdenum, aluminum, and titanium; the gate electrode 102 may be formed by evaporation or the like. The gate insulating layer 103 may be formed of a single-layer structure of silicon nitride or silicon oxide, or may be formed of a multi-layer structure of silicon nitride and silicon oxide, so as to cover the gate 102 and prevent the gate 102 from being shorted with other layers thereon. For ease of illustration, the gate insulation layer 103 is not shown in fig. 3A. The material of the active layer 104 may be metal oxide, low temperature polysilicon, or carbon nanotube material. In one particular embodiment of the present disclosure, the material of the active layer 104 includes SWCNTs. Preferably, the molar ratio of s-SWCNTs is greater than m-SWCNTs in the active layer 104 material. Further preferably, the molar ratio of s-SWCNTs to m-SWCNTs is greater than or equal to 4: 1. optionally, the molar ratio of s-SWCNTs to m-SWCNTs is greater than or equal to 99: 1. in some embodiments, the molar ratio of s-SWCNTs to m-SWCNTs is less than or equal to 999.5: 1; in some embodiments, the molar ratio of s-SWCNTs to m-SWCNTs is less than or equal to 999: 1. the semiconductor device design disclosed by the invention can be used without ultrahigh purification of the s-SWCNTs, and the production cost is saved under the condition of ensuring the device performance.
For example, the first electrode 105 and the second electrode 106, i.e., the source electrode and the drain electrode, may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by a metal material including molybdenum, aluminum, or titanium, or an alloy including one or more of molybdenum, aluminum, and titanium, for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Al/Ti/Al), and the like.
For example, fig. 3B is a schematic structural diagram of another semiconductor device provided in the embodiment of the present disclosure, and fig. 4B is a schematic structural cross-sectional diagram of the semiconductor device shown in fig. 3B along a path B-B', and referring to fig. 3B and fig. 4B, the gate insulating layer 103 extends to a region where the switching element is located, and is hollowed out at the position of the third electrode 201; in one embodiment, the gate insulating layer 103 is located between the fourth electrode 202 and the substrate, and the gate insulating layer 103 is located between the fifth electrode 203 and the substrate 101. The gate insulating layer 103 is hollowed out at the position of the third electrode 201, and it can be understood that there is at least a partially non-overlapping region between the orthographic projection of the gate insulating layer 103 on the substrate 101 and the orthographic projection of the third electrode 201 on the substrate 101, so as to expose the third electrode 201, thereby ensuring the normal operation of the switching element. Preferably, an orthogonal projection of the gate insulating layer 103 on the substrate 101 does not overlap an orthogonal projection of the third electrode 201 on the substrate 101. The fourth electrode 202 and the fifth electrode 203 are respectively disposed on two sides of the third electrode 201, due to the existence of the gate insulating layer 103, the third electrode 201 and the fourth electrode 202 are located in different film layers, the fourth electrode 202 and the fifth electrode 203 are located in the same film layer, and the height of the third electrode 201 is lower than the height of the fourth electrode 202 and the fifth electrode 203. The cantilever beam structure 204 is a conductive structure, and an orthographic projection of the cantilever beam structure on the substrate 101 at least partially overlaps with an orthographic projection of the third electrode 201, the fourth electrode 202 and the fifth electrode 203 on the substrate 101. For ease of illustration, the gate insulation layer 103 is not shown in fig. 3B.
When the entire semiconductor device is in an on state, a voltage signal is input to the gate electrode 102 in the thin film transistor, and carriers may be formed in the active layer 104, at which time, the first electrode 104 and the second electrode 105, i.e., the source and drain electrodes of the thin film transistor, are turned on through the active layer 104. The third electrode 201 and the suspended beam structure 204 in the switching element can respectively input opposite voltage signals, so that the third electrode 201 and the suspended beam structure 204 attract each other, and since the height of the third electrode 201 is lower than the height of the fourth electrode 202 and the fifth electrode 203, the suspended beam structure 204 is in contact with the fourth electrode 202 and the fifth electrode 203, and a certain gap is always kept between the suspended beam structure 204 and the third electrode 201, so that the fourth electrode 202 and the fifth electrode 203 can be conducted through the suspended beam structure 204. And, the fourth electrode 202 is connected to the second electrode 105, i.e., the drain of the thin film transistor, so that the voltage signal inputted from the fifth electrode 203 of the switching element can be transmitted in the thin film transistor and the switching element, so that the entire semiconductor device is in an on state. Alternatively, a voltage signal is input to the third electrode 201 in the switching element, and the suspended beam structure 204 may also not input a signal, but input a voltage signal through the third electrode 201 to generate induced charges, so that the third electrode 201 and the suspended beam structure 204 attract each other, and the fourth electrode 202 and the fifth electrode 203 are conducted through the suspended beam structure 204.
When the entire semiconductor device is in an off state, the first electrode 104 and the second electrode 105 in the thin film transistor, i.e., the source and the drain of the thin film transistor, are disconnected. The third electrode 201 and the suspended beam structure 204 in the switching element do not input a voltage signal, the suspended beam structure 204 returns to the original state, and at this time, the fourth electrode 202 and the fifth electrode 203 are disconnected, so that the whole semiconductor device is disconnected. Alternatively, the same voltage signal (for example, a positive voltage signal, a negative voltage signal, or a 0V voltage signal) may be input to the third electrode 201 and the suspended beam structure 204 in the switching element, and at this time, the suspended beam structure 204 and the fourth electrode 202 are not in conduction, so that the entire semiconductor device is disconnected.
As can be seen from the above, the semiconductor device provided by the embodiment of the present disclosure is composed of the thin film transistor and the switching element, and when the semiconductor device is in an off state, no leakage current is generated, so that the problems of device heating, waste of large energy consumption and the like caused by the leakage current can be avoided. When the liquid crystal display panel is applied to the driving of the LCD display substrate, the problems of poor residual images and the like of a display picture can be avoided, and the display effect is improved. Furthermore, the semiconductor device provided by the embodiment of the present disclosure has a simple structure, and it is not necessary to optimize the material of the active layer 104 to increase the process cost in order to avoid generating leakage current (for example, when SWCNTs are used as the material of the active layer, it is not necessary to highly purify s-SWCNTs, which saves the cost), and it is possible to reduce the process difficulty, thereby saving the preparation and development costs.
In some embodiments, as shown in fig. 3A, 3B, 4A, 4B, and 5, the cantilever beam structure 204 may include: a support portion 2041 and a suspended beam portion 2042; the supporting portion 2041 is fixed to the base 101, and one end thereof is connected to one end of the cantilever portion 2042; one end of the suspended beam portion 2042 is connected to the other end of the supporting portion 2041, and the other end is suspended. The supporting portion 2041 is fixed on the substrate 101, which may be understood as the supporting portion 2041 directly contacting the substrate 101, or the supporting portion 2041 is fixed on the substrate 101 through other layers or structures, for example, the supporting portion 2041 is fixed on the gate insulating layer 103, that is, the supporting portion 2041 is fixed on the substrate 101 through the gate insulating layer 103. In one embodiment, when the supporting portion 2041 is fixed on the gate insulating layer 103, opposite voltage signals can be respectively input to the third electrode 201 and the suspended beam portion 2041 through independent signal lines, so as to facilitate the control of the turn-on and turn-off of the semiconductor device.
In some embodiments, as shown in fig. 5, 6, and 7, the cantilever beam structure 204 includes: a support portion 2041 and a suspended beam portion 2042; the supporting portion 2041 is fixed on the fifth electrode 203, and one end of the supporting portion is connected to one end of the cantilever portion 2042; one end of the suspended beam portion 2042 is connected to the other end of the supporting portion 2041, and the other end is suspended.
The difference from the semiconductor device described above is that the supporting portion 2041 of the suspended beam structure 204 in the semiconductor device provided in the embodiment of the present disclosure is connected to the fifth electrode 203 and is fixed on the fifth electrode 203, so that a voltage signal input to the fifth electrode 203 can directly act on the suspended beam portion 2042, and the suspended beam portion 2042 and the third electrode 201 are attracted to each other by controlling a voltage signal on the third electrode 201, and therefore, when the semiconductor device is applied to a display substrate, it is not necessary to separately provide a signal line for providing a voltage signal to the suspended beam portion 2042, so that the number of wirings can be reduced, the wiring difficulty can be reduced, and the manufacturing efficiency can be improved.
In one embodiment, an orthographic projection of the cantilever portion 2042 on the substrate 101 at least partially overlaps an orthographic projection of each of the third electrode 201, the fourth electrode 202 and the fifth electrode 203 on the substrate 101.
In some embodiments, for example, as shown in fig. 4B and 7, the fourth electrode 202 is a unitary structure with the second electrode 106.
The fourth electrode 202 and the second electrode 106 are electrically connected together, and in the preparation process, the fourth electrode 202 and the second electrode 106 can be made of the same material and are manufactured through one-step process, and the fourth electrode 202 and the second electrode 106 can be of an integrally formed structure, so that connecting wires do not need to be arranged between the fourth electrode 202 and the second electrode 106, the preparation steps are reduced, the preparation cost is saved, a certain gap can be prevented from being formed between a thin film transistor and a switching element, the space occupied by a semiconductor device can be reduced, and the aperture opening ratio of a pixel unit can be improved when the thin film transistor and the switching element are applied to a display substrate.
In some embodiments, for example, as shown in fig. 3A, 4A and 3B, 4B, the semiconductor device further includes a gate lead 109. For example, the gate lead 109 may be made of the same material as the gate 102 through a single process, and the gate lead 109 and the gate 102 may be formed as a single-piece structure. The gate lead 109 is used for transmitting a signal to the gate 102 to control on and off of a thin film transistor in the semiconductor device.
In some embodiments, the cantilever beam structure 204 is a gold/aluminum/gold laminate structure.
The cantilever structure 204 may be formed by a gold/aluminum/gold stacked structure, wherein the thickness of the gold film may be 5nm, the thickness of the aluminum film may be 1um, and the cantilever switching time is about 100 ns. The outer gold can prevent the oxidation of the aluminum of the inner layer, so that the influence of the oxidation of the cantilever beam structure 204 on the conductive effect can be avoided, and the service life of the cantilever beam structure 204 can be prolonged.
A process for manufacturing a semiconductor device according to an alternative embodiment of the present application will be described in detail below:
s1, the gate electrode 102 and the third electrode 201 are formed on the substrate 101 by a patterning process, and the gate electrode 102 and the third electrode 201 can be formed by a single process (a film layer including the gate electrode 102 and the third electrode 201 can be referred to as a first conductive layer). The material of the substrate 101 may be glass, the material of the first conductor layer includes, but is not limited to, molybdenum and/or aluminum, and the material of the first metal layer in the embodiment of the present application may be Mo, and the thickness thereof may be 200 nm.
S2, forming the gate electrode 102 and the third electrode 201 by photolithography and etching, and depositing the gate insulating layer 103 on the whole surface, wherein the gate insulating layer 103 may be made of SiO, for example2. It should be noted that the thickness of the gate insulating layer 103 of the tft needs to be strictly balanced, and too large thickness of the gate insulating layer 103 may cause the controllability of the gate 102 to be reduced and the leakage current to be increased; too small a thickness of the gate insulating layer 103 increases the risk of source-drain and gate 102 breakdown; the thickness of the gate insulating layer 103 in the embodiment of the present disclosure is required to satisfy the on-state current requirement. For example, SiO is used2As a material of the gate insulating layer 103, its thickness may be 150 nm.
S3, the active layer 104 is prepared. The method comprises the steps of diluting an s-SWCNTs solution with concentration of 50ug/ml by toluene or xylene for 15 times and carrying out water-area ultrasonic dispersion, wherein the semiconductor carbon tube of the s-SWCNTs solution used in the embodiment of the present disclosure has purity lower than 80%, tube diameter equal to or equal to 1.55nm and length equal to or equal to 1.5um, then putting a glass sample into the s-SWCNTs dilution, taking out after 10 hours, drying the glass sample by nitrogen, putting the glass sample into an oven for heat treatment at 150 ℃ for 30 minutes, and then etching the carbon tube film by using an Inductively Coupled Plasma etching device (ICP) to form an active layer 104.
S4, the first electrode 105 and the second electrode 106 are formed by a patterning process, and the first electrode 105 and the second electrode 106 may be formed by a single process (the film layer including the first electrode 105 and the second electrode 106 may be referred to as a second conductor layer). The first electrode 105 and the second electrode 106 are made of a titanium metal layer and a palladium metal layer which are sequentially made, and the selectable thickness range of the titanium metal layer is [5nm,10nm ]; an optional thickness range for the palladium metal layer is [15nm,35nm ].
S5, a switching element is produced. The sacrificial layer is formed by coating photoresist, and the cantilever structure 204 is prepared by using a half-transmission mask plate and a photolithography process. Specifically, after the photolithography process completes the development, the sacrificial layer corresponding to the support portion 2041 is completely etched, and the sacrificial layer having a certain thickness is still disposed at the position corresponding to the suspended beam portion 2042. Next, a cantilever structure 204 is fabricated by deposition or sputtering, and the material is Au/Al/Au stacked layer or Ti/Al/Ti stacked layer or Mo/Al/Mo stacked layer. An Au/Al/Au stack means an Au, Al, Au tri-stack structure, with the material written in the front being closer to the substrate 101 than the material written in the back. An analogous interpretation can be given for Ti/Al/Ti stacks and Mo/Al/Mo stacks. Wherein the thickness of the Au layer can be 5nm, the thickness of the Ti layer can be 10nm, the thickness of the Mo layer can be 50nm, and the thickness of the Al layer can be 1 um. The Au, Ti or Mo metal layer is used to prevent oxidation of Al. And finally, removing the residual sacrificial layer to finish the manufacture of the whole semiconductor device.
It is understood that the cantilever beam structure 204 may also be implemented by an electron beam exposure process. In the electron beam exposure process, resist residue may be controlled by controlling the electron beam exposure dose at different positions to prepare the support portions 2041 and the suspended beam portions 2042.
In a second aspect, embodiments of the present disclosure provide a display substrate including a semiconductor device as provided in any of the above embodiments. Fig. 8A is a schematic structural diagram of a display substrate according to an embodiment of the disclosure, and fig. 9A is a schematic structural diagram of a cross-section of the display substrate shown in fig. 8A in a direction C-C', as shown in fig. 9A, the display substrate further includes a passivation layer 301 on a side of the first electrode 105 and the second electrode 106 away from the substrate 101, and a first via 3011 penetrating through the passivation layer 301; an orthographic projection of the first via 3011 on the substrate 101 at least partially overlaps with an orthographic projection of the fourth electrode 202 on the substrate 101; an orthographic projection of the first via hole 3011 on the substrate 101 at least partially overlaps with an orthographic projection of the fifth electrode 203 on the substrate 101; an orthogonal projection of the first via 3011 on the substrate 101 at least partially overlaps an orthogonal projection of the suspended beam structure 204 on the substrate 101. For convenience of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 8A.
For example, the passivation layer 301 is an insulating material. Specifically, the material of the passivation layer 301 is Y2O3With Al2O3Lamination of Y2O3Compared with Al2O3Closer to the substrate 101, where Y2O3May have a thickness of 5nm, Al2O3The thickness may be 50 nm.
For example, an orthographic projection of the passivation layer 301 on the substrate 101 at least partially overlaps with an orthographic projection of the fourth electrode 202 on the substrate 101.
For example, an orthographic projection of the passivation layer 301 on the substrate 101 at least partially overlaps with an orthographic projection of the fifth electrode 203 on the substrate 101.
The passivation layer 301 can prevent the corrosion of each electrode caused by the intrusion of gases such as water vapor and the like, and influence the conductivity. The first via 3011 may expose the fourth electrode 204 and the fifth electrode 203, so that the fourth electrode 202 and/or the fifth electrode 203 are connected to another structure (e.g., the cantilever structure 204) and perform signal transmission. It is understood that the semiconductor device provided in the embodiments of the present disclosure may further include other film layers such as a buffer layer, an interlayer gate insulating layer, and a planarization layer, and the arrangement manner of the other film layers may be the same as that of the film layer in the related art, and is not described herein again.
For example, the display substrate further includes: a first conductor layer, a second conductor layer and a third conductor layer which are positioned on the substrate 101 and are sequentially arranged in an insulating manner along a direction departing from the substrate 101; the first conductor layer includes: a gate electrode 102 and a third electrode 201; the second conductor layer includes: a first electrode 105, a second electrode 106, a fourth electrode 202, and a fifth electrode 203; the third conductor layer includes a cantilever beam structure 204. The structures in the first conductor layer can be respectively made of the same material by adopting a one-step process; the structures in the second conductor layer can be respectively made of the same material by adopting a one-step process; the structures in the third conductor layer can be respectively made of the same material by adopting a one-step process; the preparation steps can be reduced by one-time process preparation, and the preparation cost is saved.
In some embodiments, the display substrate further comprises: a plurality of Gate lines Gate and a plurality of Data lines Data arranged in a crossing manner.
In some embodiments, a plurality of Gate lines Gate are located on the first conductor layer; the Data lines are located on the second conductor layer.
In one embodiment, a plurality of semiconductor devices are arranged in an array; at least part of the gates 102 of the semiconductor devices in the same row are electrically connected with the same Gate line Gate and are of an integrally formed structure; specifically, the Gate wiring 109 may be the Gate line Gate or the Gate wiring 109 may be a part of the Gate line Gate.
In one embodiment, at least a portion of the fifth electrodes 203 of the semiconductor devices in the same column is electrically connected to the same Data line Data and is of an integrally formed structure.
Specifically, the Gate electrode 102 and the Gate line Gate of the semiconductor device may be made of the same material by one process, and the fifth electrode 203 and the Data line Data may be made of the same material by one process, so that the number of manufacturing steps may be reduced, and the manufacturing cost may be reduced. In addition, at least part of the gates 102 of the semiconductor devices in the same row are electrically connected with the same Gate line Gate and are of an integrally formed structure, so that the space occupied by the gates 102 and the Gate line Gate can be reduced; at least part of the fifth electrodes 203 of the semiconductor devices in the same column are electrically connected with the same Data line Data and are in an integrally formed structure, so that the space occupied by the fifth electrodes 203 and the Data line Data can be reduced, the aperture opening ratio of the pixel unit is improved, and the display effect is improved. In some embodiments, the display substrate further comprises: a first voltage signal line 401 extending in the same direction as the Gate line Gate. In one embodiment, the first voltage signal line 401 is located at the first conductor layer. In one embodiment, the first voltage signal line 401 is positioned between adjacent Gate lines Gate. In one embodiment, at least a portion of the third electrodes 201 of the semiconductor devices in the same row are electrically connected to the same first voltage signal line 401 and form an integrated structure. The first voltage signal line 401 may provide a voltage signal to the third electrode 201, so that the third electrode 201 and the suspended beam structure 204 are attracted to each other to control the on and off of the semiconductor device. Thus, the preparation steps can be reduced, and the preparation cost can be saved. At least part of the third electrodes 201 of the semiconductor devices in the same row are electrically connected with the same first voltage signal line 401 and are in an integrally formed structure, so that the space occupied by the third electrodes 201 and the first voltage signal line 401 can be reduced, the aperture opening ratio of the pixel unit is improved, and the display effect is improved. In some embodiments, as shown in fig. 8A and 9A and fig. 8B and 9B, the supporting portion 2041 of the suspended beam structure 204 may be fixed on the fifth electrode 203 to provide a voltage signal to the suspended beam structure 204 through the fifth electrode 203.
In a specific embodiment, as shown in fig. 8B, 9B, a plurality of the semiconductor devices are arranged in an array; at least part of the fifth electrodes 203 of the semiconductor devices in the same row are electrically connected to the same Data line Data, the supporting portion 2041 of the cantilever structure 204 is fixed on the fifth electrodes 203, and the Data line Data and the supporting portion 2041 are of an integrally formed structure. Specifically, the Data line Data may be located in the third conductor layer, and may be prepared in the same process as the cantilever structure 204, so that the space occupied by the Data line Data is reduced, the preparation steps are reduced, and the preparation cost is saved. For convenience of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 8B.
In some embodiments, fig. 10 is a schematic structural diagram of another display substrate provided in the embodiments of the present disclosure, fig. 11 is a schematic structural diagram of a cross section of the display substrate shown in fig. 10 in a direction D-D', and the display substrate shown in fig. 10 is different from the display substrates shown in fig. 8A and 8B in that the display substrate further includes: a second voltage signal line 402 extending in the same direction as the Gate line Gate; optionally, on the extending surface of the substrate 101, the second voltage signal line 402 is located between the first voltage signal line 401 and the corresponding Gate line Gate of the adjacent row. Preferably, the second voltage signal line 402 is located at the third conductor layer. Specifically, at least a portion of the cantilever structures 204 of the semiconductor devices in the same row is electrically connected to the same second voltage signal line 402 and is an integrally formed structure. It should be explained that the extended surface of the substrate 101 may be understood as a surface perpendicular to the thickness direction of the substrate 101.
The first voltage signal line 401 may provide a voltage signal to the third electrode 201, and the second voltage signal line 402 may provide a voltage signal to the suspended beam structure 204, so that the third electrode 201 and the suspended beam structure 204 attract each other to control the turn-on of the semiconductor device. Accordingly, the support portions 2041 of the suspended beam structure 204 may be fixed on the passivation layer 301. At least part of the cantilever structure 204 of the semiconductor device in the same row is electrically connected with the same second voltage signal line 402 and is of an integrally formed structure, so that the space occupied by the cantilever structure 204 and the second voltage signal line 402 can be reduced, the aperture opening ratio of the pixel unit is improved, and the display effect is improved. Preferably, at least a portion of the third electrodes 201 of the semiconductor devices in the same row are electrically connected to the same first voltage signal line 401 and are of an integrally molded structure. For convenience of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 10 for convenience of illustration.
In some embodiments, the supporting portion 2041 of the cantilever structure 204 may be reused as a part of the second voltage signal line 402, in which case, the cantilever portion 2042 may be directly connected to the second voltage signal line 402, so as to further save the space occupied by the cantilever structure 204 and improve the aperture ratio.
In some embodiments, as shown in fig. 8-11, the display substrate further includes a second via 3012 penetrating through the passivation layer 301, an orthographic projection of the second via 3012 on the substrate 101 at least partially overlaps with an orthographic projection of the first electrode 105 on the substrate 101; the second via hole 3012 may expose the first electrode 105 to facilitate electrical connection of the first electrode 105 with other structures and signal transmission. In one embodiment, the display substrate further comprises a pixel electrode 107. The pixel electrode 107 may be electrically connected to the first electrode 105 through the second via 3012. Optionally, the pixel electrode 107 is located on the third conductor layer. Preferably, the pixel electrode 107 and the suspended beam structure 204 are made of the same material through a single process, so as to reduce the process cost.
In a third aspect, the present disclosure provides a display device, which includes the display substrate provided in any of the above embodiments, and the display device may be, for example, an electronic device with a display function, such as a mobile phone, a tablet computer, an electronic watch, a sports bracelet, and a notebook computer. The implementation principle and the technical effect of the display device can refer to the above discussion of the implementation principle and the technical effect of the display substrate and the semiconductor device, and are not described herein again.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims (17)

1. A semiconductor device, comprising: the thin film transistor and the switching element are positioned on the substrate;
the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer;
the switching element includes: a third electrode on the substrate; the switching element further includes: the fourth electrode and the fifth electrode are respectively positioned on two sides of the third electrode, and the cantilever beam structure is suspended on the third electrode; wherein the fourth electrode is electrically connected to the second electrode;
the orthographic projection of the cantilever beam structure on the substrate is at least partially overlapped with the orthographic projection of the third electrode, the orthographic projection of the fourth electrode and the orthographic projection of the fifth electrode on the substrate.
2. The semiconductor device according to claim 1, wherein the gate insulating layer extends to a region where the switching element is located, wherein the gate insulating layer is hollowed out at the third electrode, the gate insulating layer is located between the fourth electrode and the substrate, and the gate insulating layer is located between the fifth electrode and the substrate.
3. The semiconductor device according to claim 1 or 2, wherein the cantilever beam structure comprises: a support portion and a suspension portion;
the supporting part is fixed on the substrate, and one end of the supporting part is connected with one end of the suspension beam part;
one end of the suspension beam part is connected with one end of the supporting part, and the other end of the suspension beam part is suspended.
4. The semiconductor device according to claim 1 or 2, wherein the cantilever beam structure comprises: a support portion and a suspension portion;
the supporting part is fixed on the fifth electrode, and one end of the supporting part is connected with one end of the suspension beam part;
one end of the suspension beam part is connected with one end of the supporting part, and the other end of the suspension beam part is suspended.
5. The semiconductor device according to claim 1, wherein the fourth electrode and the second electrode are of an integrally molded structure.
6. The semiconductor device of claim 1, wherein the cantilever beam structure is a gold/aluminum/gold stack.
7. The semiconductor device according to claim 1, wherein the material of the active layer comprises: a carbon nanotube material.
8. A display substrate comprising the semiconductor device according to any one of claims 1 to 7.
9. The display substrate of claim 8, further comprising: the passivation layer is positioned on one side, away from the substrate, of the first electrode and the second electrode, and the first through hole penetrates through the passivation layer;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the fourth electrode on the substrate;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the fifth electrode on the substrate;
an orthographic projection of the first via hole on the substrate is at least partially overlapped with an orthographic projection of the suspended beam structure on the substrate.
10. The display substrate of claim 8, further comprising: the first conductor layer, the second conductor layer and the third conductor layer are positioned on the substrate and are sequentially arranged in an insulating mode along the direction deviating from the substrate;
the first conductor layer includes: the grid electrode and the third electrode;
the second conductor layer includes: the first electrode, the second electrode, the fourth electrode, and the fifth electrode;
the third conductor layer includes: the suspension beam structure.
11. The display substrate of claim 10, further comprising: a plurality of gate lines and a plurality of data lines arranged in a crossing manner.
12. The display substrate according to claim 11, wherein a plurality of the semiconductor devices are arranged in an array;
at least part of the grid electrodes of the semiconductor devices in the same row are electrically connected with the same grid line and are of an integrally formed structure;
at least part of the fifth electrodes of the semiconductor devices in the same row are electrically connected with the same data line and are of an integrally formed structure, or when the supporting part is fixed on the fifth electrodes, at least part of the fifth electrodes of the semiconductor devices in the same row are electrically connected with the same data line, and the data line and the supporting part are of an integrally formed structure.
13. The display substrate of claim 11, further comprising: a first voltage signal line extending in the same direction as the gate line; the first voltage signal line is positioned between the adjacent grid lines;
the first conductor layer further includes: the first voltage signal line.
14. The display substrate of claim 13, wherein at least a portion of the third electrodes of the semiconductor devices in the same row are electrically connected to the same first voltage signal line and are integrally formed.
15. The display substrate of claim 13, further comprising: a second voltage signal line extending in the same direction as the gate line;
the third conductor layer further includes: the second voltage signal line.
16. The display substrate of claim 15, wherein at least a portion of the cantilever structures of the semiconductor devices in a same row are electrically connected to a same one of the second voltage signal lines and are integrally formed.
17. A display device comprising the display substrate according to any one of claims 8 to 16.
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