CN113322440B

CN113322440B - Semiconductor processing equipment and process chamber thereof

Info

Publication number: CN113322440B
Application number: CN202110577771.7A
Authority: CN
Inventors: 郭浩; 王宽冒
Original assignee: Beijing Naura Microelectronics Equipment Co Ltd
Current assignee: Beijing Naura Microelectronics Equipment Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2022-08-16
Anticipated expiration: 2041-05-26
Also published as: CN113322440A

Abstract

The embodiment of the application provides semiconductor processing equipment and a process chamber thereof. The process chamber includes: the deposition device comprises a chamber body, and a base, a deposition ring and a shielding ring which are arranged in the chamber body; the base is used for bearing the wafer, a cooling structure is arranged in the base and used for cooling the base and the wafer; the deposition ring is arranged around the base and comprises an annular blocking part, and when the base bears a wafer, the blocking part surrounds the wafer; the shielding ring is separably arranged on the deposition ring, when the shielding ring is positioned on the deposition ring, the shielding ring surrounds the blocking part of the deposition ring, and the top surface of the shielding ring is not higher than the top surface of the blocking part so as to block the heat of the shielding ring from being transferred to the wafer. The embodiment of the application realizes that the blocking part can prevent the heat of the blocking ring from being transferred to the wafer, so that the surface of the wafer can form a film with uniform stress, the yield of the wafer is greatly improved, and the film can be suitable for metal or alloy films with larger stress, and the applicability and the application range are greatly improved.

Description

Semiconductor processing equipment and process chamber thereof

Technical Field

The application relates to the technical field of semiconductor processing, in particular to semiconductor processing equipment and a process chamber thereof.

Background

At present, with the rapid shrinking of the process Size and the diversification of the functions of Integrated Circuits (ICs), the IC frequency is increased and the number of pins is increased dramatically, the requirements for electrical conductivity and thermal conductivity are also becoming strict, and the traditional lead technology cannot meet the requirements, so that new packaging technologies, such as Flip Chip Package (Flip Chip Package) and Chip Size Package (CSP), are beginning to emerge.

In the prior art, the magnetron sputtering technique is generally adopted to deposit a TiW (titanium tungsten) film and an Au (gold) film for flip chip packaging. In a chamber body of a magnetron sputtering apparatus in a semiconductor process apparatus, a liner, a deposition ring, and a shield ring are generally provided for protecting the chamber body, and when a thin film is deposited, sputtering particles are sputtered on a base liner and are not deposited on the chamber body. However, due to the fact that the structural design in the prior art is unreasonable, the temperature of the shielding ring in the process can be increased, the shielding ring with higher temperature can affect the stress of the titanium tungsten film on the wafer, and the film with more stable stress is not easy to form, so that the quality of the wafer is unqualified, and even the wafer is scrapped.

Disclosure of Invention

The application provides semiconductor process equipment and a process chamber thereof aiming at the defects of the existing mode, and is used for solving the technical problem that a film with stable stress cannot be formed on a wafer due to unreasonable structural design, so that the quality of the wafer is unqualified in the prior art.

In a first aspect, embodiments of the present application provide a process chamber of a semiconductor processing apparatus, comprising: the deposition device comprises a chamber body, and a base, a deposition ring and a shielding ring which are arranged in the chamber body; the base is used for bearing a wafer, a cooling structure is arranged in the base, and the cooling structure is used for cooling the base and the wafer; the deposition ring is arranged around the base and comprises an annular blocking part, and when the wafer is carried by the base, the blocking part surrounds the wafer; the shielding ring is detachably arranged on the deposition ring, and when the shielding ring is positioned on the deposition ring, the shielding ring surrounds the shielding part of the deposition ring, and the top surface of the shielding ring is not higher than that of the shielding part, so that the heat of the shielding ring is transmitted to the wafer.

In an embodiment of the present invention, when the wafer is loaded on the susceptor, a first predetermined distance is formed between an inner circumferential surface of the spacer and an edge of the wafer; and a second preset interval is formed between the outer peripheral surface of the blocking part and the inner peripheral surface of the blocking ring to form a gap, and the first preset interval and the second preset interval are both smaller than or equal to 2 millimeters.

In an embodiment of the present application, first chamfers are disposed between the top surface and the inner and outer circumferential surfaces of the barrier portion, and the first chamfers are less than or equal to 1 mm; second chamfers are arranged between the inner circumferential surface and the top surface of the shielding ring, and between the outer circumferential surface and the top surface of the shielding ring, and the second chamfers are smaller than or equal to 1 millimeter.

In an embodiment of the present application, the process chamber further includes a liner, the liner is disposed around the inner side of the chamber body, and a supporting portion is disposed at a lower end of the liner, the supporting portion being used for supporting the shielding ring when the shielding ring is separated from the deposition ring.

In an embodiment of the present invention, a second predetermined distance is provided between the inner circumferential surface of the liner and the outer circumferential surface of the shielding ring, and the second predetermined distance is less than or equal to 6 mm.

In an embodiment of the present application, a top surface of the shielding ring is flush with a top surface of the blocking portion.

In an embodiment of this application, the deposition ring is still including overlap joint portion, it sets up to separate the fender portion on the overlap joint portion, with the overlap joint portion is connected, the overlap joint portion is located separate position under the fender portion periphery side, it is located to hide the ring when the deposition ring is last, it overlaps in to hide the ring on the overlap joint portion, and the overlap joint portion with it is provided with anti-sticking structure to hide between the ring.

In an embodiment of the present application, the anti-adhesion structure includes a first groove, and the first groove is opened at the top of the overlapping portion and is disposed around the blocking portion.

In an embodiment of the present application, the anti-sticking structure further includes a second groove and a third groove, the second groove is opened on the top surface of the overlapping portion, surrounds the first groove, and is communicated with the first groove, the third groove is opened on the bottom surface of the shielding ring, the position of the shielding ring corresponds to the second groove, and is communicated with the gap between the outer circumferential surface of the shielding portion and the inner circumferential surface of the shielding ring.

In a second aspect, embodiments of the present application provide a semiconductor processing apparatus comprising a process chamber as provided in the first aspect.

The technical scheme provided by the embodiment of the application has the following beneficial technical effects:

the embodiment of the application arranges the deposition ring on the base, and the blocking part of the deposition ring surrounds the wafer loaded on the base, and the shielding ring surrounds the blocking part, because the deposition ring is cooled by the cooling structure in the base, and the blocking part is arranged between the wafer and the shielding ring, the blocking part can prevent the heat transfer of the shielding ring from being transferred to the wafer, so that the surface of the wafer can form a film with uniform stress, and the yield of the wafer is greatly improved. In addition, the stress of the wafer surface film is uniform, so that the wafer surface film can be applied to metal or alloy films with large stress, and the applicability and the application range are greatly improved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1A is a schematic partial cross-sectional view of a process chamber omitting a chamber body according to an embodiment of the present disclosure;

FIG. 1B is a schematic view, partially in cross section, of a deposition ring and a shadow ring according to an embodiment of the present invention;

FIG. 2A is a schematic partial cross-sectional view of a process chamber omitting a chamber body according to an embodiment of the present disclosure;

FIG. 2B is an enlarged view of portion A of the deposition ring shown in FIG. 2A in cooperation with a susceptor;

FIG. 2C is an enlarged view of portion B of the shadow ring shown in FIG. 2A engaged with a liner;

FIG. 3A is an enlarged view of portion C of the deposition ring and shadow ring shown in FIG. 2A;

FIG. 3B is an enlarged view of the portion C of the deposition ring shown in FIG. 2A in cooperation with a shadow ring.

Detailed Description

The present application is described in detail below and examples of embodiments of the present application are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements with the same or similar functionality throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

An embodiment of the present application provides a process chamber of a semiconductor process apparatus, and a schematic structural diagram of the process chamber is shown in fig. 1A and 1B, and includes: a chamber body (not shown in the figure) and a base 1, a deposition ring 2 and a shielding ring 3 which are arranged in the chamber body; the susceptor 1 is used for carrying the wafer 100, and the susceptor 1 has a cooling structure (not shown) therein, the cooling structure being used for cooling the susceptor 1 and the wafer 100; the deposition ring 2 is arranged around the susceptor 1, the deposition ring 2 comprises an annular barrier portion 21, and when the susceptor 1 carries the wafer 100, the barrier portion 21 surrounds the wafer 100; the shielding ring 3 is separably disposed on the deposition ring 2, and when the shielding ring 3 is located on the deposition ring 2, the shielding ring 3 surrounds the blocking portion 21 of the deposition ring 2, and the top surface of the shielding ring 3 is not higher than the top surface of the blocking portion 21, so as to block the heat of the shielding ring 3 from being transferred to the wafer 100.

As shown in fig. 1A and 1B, the process chamber may be a process chamber of a magnetron sputtering apparatus, and the specifically performed process is a process of depositing a titanium tungsten film or a gold film, but the embodiment of the present invention is not limited thereto. The susceptor 1 is disposed at a bottom center of the chamber body and used for carrying the wafer 100, and a cooling structure may be disposed in the susceptor 1 to cool the susceptor 1 and the wafer in the process. The deposition ring 2 may be disposed around the top of the susceptor 1, and a cooling structure within the susceptor 1 may also be used to cool the deposition ring 2 during processing. The deposition ring 2 may include a spacer 21, and when the wafer 100 is carried on the susceptor 1, the spacer 21 may be disposed around the wafer 100 carried on the susceptor 1 for focusing deposited particles onto the wafer 100. The shielding ring 3 may be detachably disposed on the deposition ring 2, and when the shielding ring 3 is disposed on the deposition ring 2, the shielding ring may be disposed around the outer circumference of the shielding portion 21 to prevent the deposition particles from entering the bottom of the chamber body. The top surface of the shield ring 3 is the same height as the top surface of the barrier 21, or the top surface of the shield ring 3 is lower than the top surface of the barrier 21. Since the shielding ring 3 is located at the periphery of the shielding portion 21, and since the shielding portion 21 of the deposition ring 2 can be cooled by the cooling structure, the shielding portion 21 can shield the heat of the shielding ring 3 from being transferred to the wafer 100, so that a thin film with uniform stress is formed on the surface of the wafer 100.

It should be noted that the embodiments of the present application do not limit the specific type of the process chamber and the specific process performed, for example, the process chamber may be other physical vapor deposition apparatuses or chemical vapor deposition apparatuses, and the specific process performed may be deposition of other metal or alloy films with larger stress. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of the present application, as shown in fig. 1A to 2B, when the wafer 100 is loaded on the susceptor 1, a first predetermined distance L1 is formed between the inner circumferential surface of the barrier portion 21 and the edge of the wafer; a second preset distance L2 is provided between the outer circumferential surface of the blocking portion 21 and the inner circumferential surface of the shielding ring 3, so that a gap is formed between the blocking portion 21 and the shielding ring 3, and both the first preset distance L1 and the second preset distance are less than or equal to 2 mm.

As shown in fig. 1A to 2B, the top surface of the blocking portion 21 may be provided with a circular groove, and since the blocking portion 21 may be of a circular ring structure as a whole, the circular groove is an open structure in which the top surface of the blocking portion 21 communicates with the inner circumferential surface. The bottom of the barrier portion 21 may be disposed around the top periphery of the susceptor 1, so that the circular groove on the top of the barrier portion 21 is disposed around the wafer 100, and thus the inner circumferential surface of the circular groove of the barrier portion 21 has a first predetermined distance L1 from the edge of the wafer 100. The shielding ring 3 is sleeved on the outer periphery of the shielding portion 21 and spaced from the shielding portion 21, so that a second predetermined distance L2 is formed between the outer peripheral surface of the shielding portion 21 and the inner peripheral surface of the shielding ring 3, i.e., a gap is formed between the outer peripheral surface of the shielding portion 21 and the inner peripheral surface of the shielding ring 3. Further, the first predetermined interval L1 and the second predetermined interval L2 are both less than or equal to 2 mm. By adopting the above design, a deep hole structure is formed between the deposition ring 2 and the wafers 100 and the shielding ring 3 on both sides, for example, when a titanium tungsten film is deposited, most of the film 200 is deposited on the top surfaces of the deposition ring 2, the wafers 100 and the shielding ring 3, and is difficult to deposit on the sidewall of the deep hole formed by the shielding ring 3 and the deposition ring 2, as shown in fig. 1B. The deposition of the film on the side surface of the deposition ring 2 or the shielding ring 3 is limited, so that the film can grow in a columnar shape in a single direction, the film can be effectively inhibited from exploding, the service lives of the deposition ring 2 and the shielding ring 3 in the embodiment of the application are greatly prolonged to be more than 200kWh according to an experimental result, and the maintenance cost of the process chamber is greatly reduced.

Optionally, the bottom of the circular groove is further provided with an annular groove 211, the width of the annular groove 211 is smaller than the width of the circular groove, and the annular groove 211 is disposed near the inner circumferential surface of the circular groove 212 and is used for accommodating a small amount of deposition particles in the process, so as to avoid the influence on the susceptor 1 bearing the wafer 100 caused by the deposition of too many metal particles in the circular groove.

In one embodiment, in order to effectively limit the film from entering the sidewall of the deep hole structure formed between the deposition ring 2 and the shielding ring 3, the deep hole opening formed by the deposition ring 2 and the shielding ring 3 is designed to be within 2mm, i.e. the second predetermined distance L2 is less than or equal to 2 mm. Further, in order to prevent the adhesion of the deposition ring 2 to the film deposited on the upper surface of the shadow ring 3, a typical deep hole opening range is set between 0.5mm and 2mm, thereby facilitating the separation of the deposition ring 2 from the shadow ring 3.

It should be noted that the embodiments of the present application do not limit the specific values of the first predetermined interval L1 and the second predetermined interval L2, for example, both of them can be adjusted according to the type of the film and the type of the process. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of the present application, as shown in fig. 1A to fig. 2B, the first chamfer a1 is formed between the inner circumferential surface and the outer circumferential surface of the blocking portion 21 and the top surface, and the first chamfer a1 is less than or equal to 1 mm. Specifically, in a radial cross-sectional view of the barrier portion 21, two corners of the top of the barrier portion 21 are chamfered, that is, a first chamfer a1 is provided between the inner peripheral surface and the top surface of the barrier portion 21, and a first chamfer a1 is also provided between the outer peripheral surface and the top surface of the barrier portion 21. The first chamfer a1 may be, for example, a rounded corner or a chamfered corner, but the embodiment of the present application is not limited thereto, and the setting may be adjusted by a person skilled in the art according to the actual situation. In some embodiments, the specific specification of the first chamfer A1 may be R ≦ 1 mm or C ≦ 1 mm, but the present embodiment is not limited thereto, as long as the specific specification of the first chamfer A1 is less than or equal to 1 mm, and after the deposition ring 2 is subjected to surface treatment such as sand blasting or aluminum spraying, the first chamfer A1 is almost invisible, thereby further reducing the specific specification of the first chamfer A1, but the present embodiment is not limited to the specific process of the surface treatment. By adopting the design, the film deposition at the edge of the blocking part 21 and the film explosion phenomenon caused by stress can be avoided, so that the particle pollution to the chamber body and the wafer 100 is avoided, and the process yield of the wafer 100 is greatly improved. In addition, once the film explosion phenomenon occurs in the prior art, the deposition ring 2 needs to be replaced and maintained, and the adoption of the design can also greatly reduce the maintenance frequency so as to prolong the service life, thereby improving the economic benefit.

In an embodiment of the present application, as shown in fig. 1A to 2C, a second chamfer a2 is provided between the inner circumferential surface and the outer circumferential surface of the shielding ring 3 and the top surface, and the second chamfer a2 is less than or equal to 1 mm. Specifically, in a radial cross-sectional view of the shielding ring 3, two corners of the top of the shielding ring 3 are chamfered, that is, a second chamfer a2 is provided between the inner peripheral surface and the top surface of the shielding ring 3, and a second chamfer a2 is also provided between the outer peripheral surface and the top surface of the shielding ring 3. The second chamfer angle a2 may be, for example, a rounded corner or a chamfered angle, but the embodiment of the present application is not limited thereto, and the setting may be adjusted by a person skilled in the art according to the actual situation. In some embodiments, the specification of the second chamfer A2 may be R ≦ 1 mm or C ≦ 1 mm, but the present embodiment is not limited thereto, as long as the specification of the second chamfer A2 is less than or equal to 1 mm, and after the shadow ring 3 is subjected to surface treatment such as sand blasting or aluminum spraying, the second chamfer A2 is hardly visible, thereby further reducing the specification of the second chamfer A2, but the present embodiment does not limit the specific process of the surface treatment. By adopting the design, the film can be prevented from being deposited at the top edge of the shielding ring 3 and the film explosion phenomenon caused by stress, so that the particle pollution to the cavity body and the wafer 100 is avoided, and the process yield of the wafer 100 is greatly improved. In addition, once the membrane explosion phenomenon occurs in the prior art, the shielding ring 3 must be replaced and maintained, and the design can also greatly reduce the maintenance frequency and prolong the service life, so that the economic benefit is improved.

In an embodiment of the present application, as shown in fig. 1A and fig. 2A, the process chamber further includes a liner 4, the liner 4 is disposed around the inner side of the chamber body, and a supporting portion 41 is disposed at a lower end of the liner 4, the supporting portion 41 is used for supporting the shadow ring 3 when the shadow ring 3 is separated from the deposition ring 2.

As shown in fig. 1A and fig. 2A, the liner 4 is a circular sleeve, and the top periphery of the liner 4 may be connected to the chamber body and surround the inner side of the chamber body. The lower end portion of the liner 4 may be integrally formed with a support portion 41, and the support portion 41 may extend from the lower end of the liner 4 to the inside and then extend upward for supporting the shadow ring 3 when the shadow ring 3 is separated from the deposition ring 2. Specifically, the deposition ring 2 can be lifted along with the pedestal 1, when the process is executed, the pedestal 1 drives the deposition ring 2 to lift, and at the moment, the shielding ring 3 is lapped on the deposition ring 2 to execute the process; when the process is completed, the susceptor 1 drives the deposition ring 2 to descend, and the shielding ring 3 descends along with the deposition ring 2 for a while and is supported by the support part 41 of the liner 4. By adopting the design, the lining 4 can form a relatively independent reaction cavity with the shielding ring 3 and the deposition ring 2, so that the thin film is deposited on the lining 4, the shielding ring 3 and the deposition ring 2, and the pollution to a chamber body is avoided.

The embodiment of the present application does not limit the specific structure of the support portion 41, and for example, the support portion 41 may be configured to support the shield ring 3. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of the present invention, as shown in fig. 1A to fig. 2C, a third predetermined distance L3 is provided between the inner circumferential surface of the liner 4 and the outer circumferential surface of the shadow ring 3, and the third predetermined distance L3 is less than or equal to 6 mm. Specifically, the liner 4 is located at the outer circumference of the shadow ring 3, and the supporting portion 41 of the liner 4 is supported by the bottom of the shadow ring 3, so that the inner circumference of the liner 4 and the outer circumference of the shadow ring 3 may have a third preset distance L3 therebetween, and the third preset distance L3 may be set to be less than or equal to 6 mm. Due to the adoption of the design, the corners at the top of the shielding rings 3 are designed to be chamfered, and the design of the third preset interval L3 is matched, so that the film explosion phenomenon caused by overlarge gaps and overlarge chamfers between the shielding rings 3 of the lining 4 can be avoided, the particle pollution to the cavity body and the wafer 100 is avoided, and the process efficiency of the wafer 100 is improved. In addition, the maintenance frequency of the shielding ring 3 can be reduced by adopting the design, so that the service life of the shielding ring 3 is greatly prolonged. In an embodiment of the present application, the third predetermined distance L3 may be set to be 4.25 mm, so as to further reduce the film explosion phenomenon, and prolong the service life of the shielding ring 3 while improving the yield of the wafer process. However, the embodiment of the present application does not limit the specific value of the third predetermined interval L3, and the setting can be adjusted by one skilled in the art according to the type of the film and the type of the process.

In an embodiment of the present application, as shown in fig. 1A and 1B, the top surface of the blocking ring 3 is flush with the top surface of the blocking portion 21. Specifically, the shield ring 3 specifically adopts a circular ring structure, and the sectional shape of the shield ring 3 may be, for example, a rectangle, the barrier portion 21 may adopt a circular ring structure, and the sectional shape of the barrier portion 21 is, for example, a rectangle. The shielding ring 3 is specifically nested in the periphery of the shielding part 21, and the top surface of the shielding ring 3 and the top surface of the shielding part 21 are located on the same horizontal plane, i.e. the top surface of the shielding ring 3 and the top surface of the shielding part 21 are arranged in parallel and level. By adopting the above design, since the shielding ring 3 is completely shielded by the shielding part 21, the heat of the shielding ring 3 is completely shielded by the shielding part 21 of the deposition ring 2, thereby reducing the thermal influence of the shielding ring 3 on the wafer 100, improving the stress stability of the surface film of the wafer 100, and greatly improving the yield of the wafer 100. In addition, combine above-mentioned embodiment, the top surface of the baffle portion 21 of the deposition ring 2 and the top surface of the shielding ring 3 are arranged in parallel and level, and can effectively prevent the film from depositing on the outer peripheral surface of the deposition ring 2 and the inner peripheral surface of the shielding ring 3, thereby being beneficial to prolonging the service life of the two, and further greatly reducing the maintenance frequency.

The embodiments of the present application do not limit the specific shapes and structures of the shielding ring 3 and the shielding portion 21, and for example, the shielding ring 3 and the shielding portion 21 may also be square or have other shapes. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of this application, as shown in fig. 1A to fig. 3B, the deposition ring 2 further includes a bridging portion 22, the blocking portion 21 is disposed on the bridging portion 22, and is connected to the bridging portion 22, the bridging portion 22 is located at a position below the outer peripheral side of the blocking portion 21, when the shielding ring 3 is located on the deposition ring 2, the shielding ring 3 is overlapped on the bridging portion 22, and the bridging portion 22 and the shielding ring 3 are provided with the anti-adhesion structure 5 therebetween. Specifically, the overlapping portion 22 may be specifically located at a position lower than the outer periphery side of the barrier portion 21, and the overlapping portion 22 may be a ring-shaped structure integrally formed with the barrier portion 21, but the embodiment of the present application is not limited thereto. When the shadow ring 3 is positioned on the deposition ring 2, the shadow ring 3 may be lapped on the top surface of the lap 22 for carrying the shadow ring 3. An anti-sticking structure 5 is arranged between the lapping part 22 and the shielding ring 3 and used for avoiding adhesion caused by particles deposited to the contact position of the lapping part and the shielding ring when the process is carried out. By adopting the design, not only the adhesion between the deposition ring 2 and the shielding ring 3 can be avoided, but also the particle pollution caused by the separation of the deposition ring and the shielding ring can be avoided, thereby further improving the process yield of the wafer 100.

It should be noted that the embodiment of the present application is not limited to the specific structure of the overlapping portion 22, and for example, a split structure may be adopted between the overlapping portion 22 and the barrier portion 21. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of the present application, as shown in fig. 1A to 3B, the anti-adhesion structure 5 includes a first groove 51, and the first groove 51 is opened at the top of the overlapping portion 22 and disposed around the blocking portion 21. The first groove 51 may be specifically opened at the top of the overlapping portion 22, and the specific shape of the first groove 51 is a circular ring structure, and is disposed around the periphery of the blocking portion 21, so that the first groove 51 is located at the deep hole structure between the blocking ring 3 and the deposition ring 2, for example, the width of the first groove 51 may be disposed corresponding to the first preset interval L1, but this is not limited in the embodiment of the present application. When actually carrying out the film deposition technology, can directly fall into first recess 51 when a small amount of particles sputter to the deep hole structure between deposition ring 2 and the shielding ring 3 to avoid the particles to sputter contact position between them and take place the adhesion, thereby produce granule pollution when avoiding deposition ring 2 and shielding ring 3 to separate, and can also improve the stability of this application embodiment.

In an embodiment of the present application, as shown in fig. 1A to 3B, the anti-adhesion structure 5 further includes a second groove 52 and a third groove 53, the second groove 52 is disposed on the top surface of the overlapping portion 22, surrounds the first groove 51, and is communicated with the first groove 51, the third groove 53 is disposed on the bottom surface of the shielding ring 3, and is corresponding to the second groove 52 and is communicated with the gap between the outer circumferential surface of the shielding portion 21 and the inner circumferential surface of the shielding ring 3. Specifically, the inner side of the top surface of the overlapping part 22 is provided with a circular second groove 52, and the second groove 52 can be arranged around the periphery of the first groove 51 and is communicated with the first groove 51; the bottom surface of the shielding ring 3 is provided with a circular third groove 53, the position of the third groove 53 may be corresponding to the second groove 52, and the third groove 53 may be communicated with a gap formed between the outer circumferential surface of the shielding portion 21 and the inner circumferential surface of the shielding ring, that is, the third groove 53 may be opened between the inner circumferential surface provided with the shielding ring 3 and the bottom surface. By adopting the design, the contact position of the deposition ring 2 and the shielding ring 3 can be further prevented from being sputtered by metal particles, so that particle pollution generated during separation between the deposition ring and the shielding ring is avoided.

It should be noted that the embodiments of the present application are not limited to the specific embodiments of the second groove 52 and the third groove 53, and only the second groove 52 or the third groove 53 may be provided, for example. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.

In an embodiment of the present application, as shown in fig. 1A and 3A, the top surface of the shielding ring 3 is lower than the top surface of the blocking portion 21. Specifically, the shielding ring 3 is specifically nested in the periphery of the blocking portion 21, the top surface of the shielding ring 3 and the top surface of the blocking portion 21 are located on different horizontal planes, and the top surface of the shielding ring 3 is lower than the top surface of the blocking portion 21, that is, the top surface of the shielding ring 3 is lower than the top surface of the blocking portion 21. By adopting the design, the shielding ring 3 is completely blocked by the blocking part 21, so that the shielding ring 3 is further away from the wafer 100, and the heat of the shielding ring 3 is completely blocked by the blocking part 21 of the deposition ring 2, so that the heat influence of the shielding ring 3 on the wafer 100 is further reduced, the stress stability of the surface film of the wafer 100 is improved, and the yield of the wafer 100 is greatly improved.

Based on the same inventive concept, embodiments of the present application provide a semiconductor processing apparatus including a process chamber as provided in the above embodiments.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

the embodiment of the application arranges the deposition ring on the base, and the blocking part of the deposition ring surrounds the wafer loaded on the base, and the shielding ring surrounds the blocking part, because the deposition ring is cooled by the cooling structure in the base, and the blocking part is arranged between the wafer and the shielding ring, the blocking part can prevent the heat transfer of the shielding ring from being transferred to the wafer, so that the surface of the wafer can form a film with uniform stress, and the yield of the wafer is greatly improved. In addition, the wafer surface film applied by the embodiment of the application has uniform stress, so that the embodiment of the application can be applied to metal or alloy films with larger stress, and the applicability and the application range are greatly improved.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A process chamber of a semiconductor processing apparatus, comprising: the deposition device comprises a chamber body, and a base, a deposition ring and a shielding ring which are arranged in the chamber body;

the base is used for bearing a wafer, a cooling structure is arranged in the base, and the cooling structure is used for cooling the base and the wafer;

the deposition ring is arranged on the top of the base in a surrounding mode, the deposition ring comprises an annular blocking part, and when the wafer is carried by the base, the blocking part surrounds the wafer;

the shielding ring is detachably arranged on the deposition ring, when the shielding ring is positioned on the deposition ring, the shielding ring surrounds the blocking part of the deposition ring, and the top surface of the shielding ring is not higher than the top surface of the blocking part so as to block the heat of the shielding ring from being transferred to the wafer;

when the wafer is carried by the base, a first preset distance is formed between the inner circumferential surface of the baffle part and the edge of the wafer; and a second preset interval is formed between the outer peripheral surface of the blocking part and the inner peripheral surface of the blocking ring to form a gap, and the first preset interval and the second preset interval are both smaller than or equal to 2 millimeters.

2. The process chamber of claim 1, wherein the baffle has first chamfers between the top surface and the inner and outer circumferential surfaces, the first chamfers being less than or equal to 1 mm;

second chamfers are arranged between the inner circumferential surface and the top surface of the shielding ring, and between the outer circumferential surface and the top surface of the shielding ring, and the second chamfers are smaller than or equal to 1 millimeter.

3. The process chamber of claim 1, further comprising a liner disposed around an inside of the chamber body, and a lower end of the liner is provided with a support for supporting the shadow ring when the shadow ring is separated from the deposition ring.

4. The process chamber of claim 3, wherein a third predetermined spacing is provided between an inner circumferential surface of the liner and an outer circumferential surface of the shield ring, the third predetermined spacing being less than or equal to 6 millimeters.

5. The process chamber of claim 1, wherein a top surface of the shadow ring is flush with a top surface of the barrier.

6. The process chamber of claim 1, wherein the deposition ring further comprises a lap portion, the barrier portion is disposed on the lap portion and connected to the lap portion, the lap portion is located below an outer circumferential side of the barrier portion, the shield ring overlaps the lap portion when the shield ring is located on the deposition ring, and an anti-sticking structure is disposed between the lap portion and the shield ring.

7. The process chamber of claim 6, wherein the anti-sticking structure comprises a first groove that opens at a top of the lap joint and is disposed around the barrier.

8. The process chamber of claim 7, wherein the anti-sticking structure further comprises a second groove and a third groove, the second groove opening on the top surface of the lap joint portion, being disposed around the first groove and communicating with the first groove, the third groove opening on the bottom surface of the shield ring, being positioned to correspond to the second groove and communicating with a gap between the outer circumferential surface of the barrier portion and the inner circumferential surface of the shield ring.

9. A semiconductor processing apparatus comprising the process chamber of any of claims 1 to 8.