CN115125519B - Process chamber of semiconductor device, semiconductor device and semiconductor process method - Google Patents

Process chamber of semiconductor device, semiconductor device and semiconductor process method Download PDF

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Publication number
CN115125519B
CN115125519B CN202210778421.1A CN202210778421A CN115125519B CN 115125519 B CN115125519 B CN 115125519B CN 202210778421 A CN202210778421 A CN 202210778421A CN 115125519 B CN115125519 B CN 115125519B
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China
Prior art keywords
cavity
carrier
bottom wall
protrusions
process chamber
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CN202210778421.1A
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Chinese (zh)
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CN115125519A (en
Inventor
赵雷超
高天
沈宇鑫
赵联波
郑波
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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Priority to CN202210778421.1A priority Critical patent/CN115125519B/en
Publication of CN115125519A publication Critical patent/CN115125519A/en
Priority to TW112122536A priority patent/TWI858773B/en
Priority to PCT/CN2023/100704 priority patent/WO2024001826A1/en
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Publication of CN115125519B publication Critical patent/CN115125519B/en
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The invention provides a process chamber of semiconductor equipment, the semiconductor equipment and a semiconductor process method, wherein the process chamber comprises a first cavity and a bearing piece, the bottom wall of the first cavity is provided with an opening, the bearing piece can be lifted and lowered relative to the bottom wall of the first cavity to form a process environment of the semiconductor process in cooperation with the first cavity, the bearing piece comprises a bearing part and a sealing part, the upper surface of the bearing part is used for bearing a wafer, a space is reserved between the outer peripheral surface of the bearing part and the inner peripheral surface of the bottom wall of the first cavity, the sealing part is annularly arranged around the bearing part, the upper surface of the sealing part is lower than the upper surface of the bearing part, and the upper surface of the sealing part is in contact sealing with the lower surface of the bottom wall of the first cavity. The process chamber of the semiconductor device, the semiconductor device and the semiconductor process method provided by the invention can reduce the degree and possibility of particle pollution of the wafer and improve the performance of semiconductor components.

Description

Process chamber of semiconductor device, semiconductor device and semiconductor process method
Technical Field
The invention relates to the technical field of semiconductor equipment, in particular to a process chamber of semiconductor equipment, the semiconductor equipment and a semiconductor process method.
Background
As feature sizes of semiconductor components shrink, the thickness of thin films in semiconductor components also decreases. The atomic layer deposition process is a thin film deposition process in which a single atomic layer is deposited layer by layer to a target film thickness, which is capable of depositing a thin film having a relatively thin thickness. However, the reactants used in atomic layer deposition processes (e.g., solid hafnium) are extremely temperature sensitive, and if the reactants are cold, it may be the case that the reactants are not easily purged or even condensed.
The existing process chamber of the atomic layer deposition equipment comprises an outer cavity, an inner cavity and a base, wherein the inner cavity is arranged in the outer cavity, the base is arranged in the outer cavity in a lifting manner, a wafer can be borne on the upper surface of the base, the inner cavity is used as a reaction cavity to provide a high-temperature environment for the atomic layer deposition process, the condensation of reactants of the atomic layer deposition process is prevented, the outer cavity is used as a protection cavity, and the outer wall of the outer cavity is provided with a cooling structure to prevent scalding, so that the problem that the reactants of the atomic layer deposition process are cold can be solved.
However, in the atomic layer deposition process, the upper surface of the susceptor may be in contact with the bottom wall of the inner cavity, a continuous thin film may be deposited adjacent to the inner circumferential surface of the bottom wall of the inner cavity, and after the atomic layer deposition process is completed, the upper surface of the susceptor may be separated from the bottom wall of the inner cavity, at this time, the continuous thin film deposited adjacent to the inner circumferential surface of the upper surface of the susceptor and the bottom wall of the inner cavity may be broken, and, when the upper surface of the susceptor is in contact with the lower surface of the bottom wall of the inner cavity before the atomic layer deposition process is started, the thin film deposited on the upper surface of the susceptor may be extruded, and thus particles may be easily generated to enter the inner cavity to pollute the wafer before and after the atomic layer deposition process, affecting the performance of the semiconductor device.
Disclosure of Invention
The invention aims at solving at least one of the technical problems in the prior art, and provides a process chamber of semiconductor equipment, the semiconductor equipment and a semiconductor process method, which can reduce the degree and possibility of particle pollution of a wafer, thereby improving the performance of semiconductor components.
The invention provides a process chamber of a semiconductor device, which comprises a first cavity and a bearing piece, wherein an opening is arranged on the bottom wall of the first cavity, the bearing piece can be arranged in a lifting manner relative to the bottom wall of the first cavity so as to match with the process environment of the semiconductor process formed by the first cavity, the bearing piece comprises a bearing part and a sealing part, the upper surface of the bearing part is used for bearing a wafer, a space is reserved between the outer peripheral surface of the bearing part and the inner peripheral surface of the bottom wall of the first cavity, the sealing part is annularly arranged around the bearing part, the upper surface of the sealing part is lower than the upper surface of the bearing part, and the upper surface of the sealing part is in contact sealing with the lower surface of the bottom wall of the first cavity.
Optionally, a sealing structure is disposed between the upper surface of the sealing portion and the lower surface of the bottom wall of the first cavity, the sealing structure includes a plurality of first protrusions and a plurality of second protrusions, the plurality of first protrusions are disposed on the upper surface of the sealing portion, the plurality of second protrusions are disposed on the lower surface of the bottom wall of the first cavity, each first protrusion is disposed in a ring shape along the circumferential direction of the sealing portion, each second protrusion is disposed in a ring shape along the circumferential direction of the lower surface of the bottom wall of the first cavity, and the plurality of first protrusions and the plurality of second protrusions are alternately disposed at intervals in a surrounding manner;
the upper surface of the sealing part is in contact with the lower surface of the bottom wall of the first cavity through one of the first convex part or the second convex part located at the outermost side.
Alternatively, the heights of the plurality of first protrusions and the plurality of second protrusions are gradually increased in a direction away from the outer peripheral surface of the bearing portion.
Optionally, a distance between two adjacent first protrusions and the second protrusions is greater than or equal to a distance between an outer peripheral surface of the bearing portion and an inner peripheral surface of a bottom wall of the first cavity.
Alternatively, the distance between the adjacent two first protrusions and the second protrusions is gradually reduced in a direction away from the outer peripheral surface of the bearing portion.
Alternatively, the first convex portion and the second convex portion, except for the first convex portion or the second convex portion provided at the outermost side, are each inclined in a direction away from the outer peripheral surface of the bearing portion.
Optionally, the thickness of the sealing part is 2/3 of the thickness of the bearing part.
Optionally, the process chamber further comprises a second cavity, and the first cavity and the carrier are disposed in the second cavity.
The invention also provides a semiconductor device comprising the process chamber provided by the invention.
The invention also provides a semiconductor process method, which adopts the process chamber provided by the invention and comprises the following steps:
lowering the carrier so that a gap for purging is provided between the upper surface of the sealing portion and the lower surface of the bottom wall of the first cavity;
and conveying purge gas into the first cavity, enabling the air pressure in the first cavity to be larger than the air pressure outside the first cavity, purging the upper surface of the bearing piece, and enabling the purge gas to flow through the gap.
The invention has the following beneficial effects:
according to the process chamber of the semiconductor device, the bearing piece comprises the bearing part and the sealing part which is annularly arranged around the bearing part, the wafer can be borne by means of the upper surface of the bearing part, the upper surface of the sealing part is in contact sealing with the lower surface of the bottom wall of the first cavity, the space is arranged between the outer peripheral surface of the bearing part and the inner peripheral surface of the bottom wall of the first cavity, the upper surface of the sealing part is lower than the upper surface of the bearing part, the adjacent part of the bearing piece and the first cavity is located below the wafer, and the space is arranged between the bearing piece and the wafer in the horizontal direction, so that in the semiconductor process, the space is arranged between the film deposited at the adjacent part of the bearing piece and the first cavity, and the film can be far away from the wafer on the bearing part, the quantity and the possibility of particles generated by the film can be reduced, the degree and the possibility of particle pollution of the wafer can be reduced, and the performance of semiconductor devices can be improved.
The semiconductor device provided by the invention can reduce the degree and possibility of particle pollution of a wafer by virtue of the process chamber of the semiconductor device, thereby improving the performance of semiconductor components.
According to the semiconductor process method provided by the invention, the carrier is lowered, a gap for purging is formed between the upper surface of the sealing part and the lower surface of the bottom wall of the first cavity, the purging gas is conveyed into the first cavity, the gas pressure in the first cavity is larger than the gas pressure outside the first cavity, the upper surface of the carrier is purged, the purging gas flows through the gap for purging, the particles which are deposited on the adjacent part of the carrier and the first cavity and are adhered to the upper surface of the carrier can be purged outside the first cavity, the number of the particles adhered to the upper surface of the carrier is reduced, so that the degree and the possibility of particle pollution to a wafer can be reduced, the performance of semiconductor components can be improved, and the gas flow in the first cavity can have stronger impact force and the purging effect by enabling the gas pressure in the first cavity to be larger than the gas pressure outside the first cavity.
Drawings
Fig. 1 is a schematic view of a process chamber of a semiconductor device and a structure of the semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic structural view of a sealing portion of a process chamber and a bottom wall of a first chamber of a semiconductor device according to an embodiment of the present invention, where no first protrusion and no second protrusion are provided;
fig. 3 is a schematic structural view of a first protrusion of a sealing portion of a process chamber of a semiconductor device according to an embodiment of the present invention in contact with a bottom wall of a first cavity;
fig. 4 is a schematic top view of a carrier of a process chamber of a semiconductor device according to an embodiment of the present invention provided with a first protrusion;
fig. 5 is a schematic bottom view of a bottom wall of a first chamber of a process chamber of a semiconductor device according to an embodiment of the present invention, where a second protrusion is disposed;
fig. 6 is a schematic front view of a carrier of a process chamber of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic structural view of a sealing portion of a process chamber of a semiconductor device according to an embodiment of the present invention, wherein a first protrusion of the sealing portion is not in contact with a bottom wall of the first chamber;
fig. 8 is a schematic view of a structure in which a sealing portion of a process chamber of a semiconductor device according to an embodiment of the present invention is inclined with a first protrusion and a second protrusion disposed on a bottom wall of a first cavity;
FIG. 9 is a flow chart of a semiconductor processing method according to an embodiment of the present invention;
reference numerals illustrate:
1-a first cavity; 11-a bottom wall; 12-lower surface; 13-an inner peripheral surface; 2-a carrier; 21-a carrier; 211-upper surface; 212-an outer peripheral surface; 22-sealing part; 221-upper surface; 3-a first protrusion; 4-a second protrusion; 5-a second cavity; 6-flow passage; 7-wafer; 8-film; 101-a limiting piece; 102-an air intake component; 103-a first air inlet pipe; 104-a second air inlet pipe; 105-a third air inlet pipe; 106-a first air inlet branch pipe; 107-a first outlet manifold; 108-a second air inlet branch pipe; 109-a second outlet manifold; 110-a first exhaust pipe; 111-a second exhaust pipe; 112-a first gas source; 113-a second gas source; 114-an air extraction component; 115-a first on-off valve; 116-first inlet valve; 117-a first gas outlet valve; 118-a second on-off valve; 119-a second intake valve; 120-a second gas outlet valve; 121-third three-way shut-off valve; 122-a first extraction valve; 123-a second extraction valve; 124-a first heating element; 125-a second heating element.
Detailed Description
In order to enable those skilled in the art to better understand the technical scheme of the present invention, the process chamber of the semiconductor device, the semiconductor device and the semiconductor process method provided by the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1-8, an embodiment of the present invention provides a process chamber of a semiconductor device, including a first cavity 1 and a carrier 2, where a bottom wall of the first cavity 1 is provided with an opening, the carrier 2 can be lifted and lowered relative to the bottom wall of the first cavity 1 to form a process environment of a semiconductor process in cooperation with the first cavity 1, the carrier 2 includes a carrier 21 and a sealing portion 22, an upper surface 211 of the carrier 21 is used for carrying a wafer 7, a space is provided between an outer peripheral surface 212 of the carrier 21 and an inner peripheral surface 13 of a bottom wall 11 of the first cavity 1, the sealing portion 22 is annularly disposed around the carrier 21, an upper surface 221 of the sealing portion 22 is lower than an upper surface 211 of the carrier 21, and the upper surface 221 of the sealing portion 22 is in contact sealing with a lower surface 12 of the bottom wall 11 of the first cavity 1.
In the process chamber of the semiconductor device provided by the embodiment of the invention, the carrier 2 includes the carrier 21 and the sealing portion 22 annularly arranged around the carrier 21, so that the wafer 7 can be carried by means of the upper surface 211 of the carrier 21, and the upper surface 221 of the sealing portion 22 is in contact with and sealed with the lower surface 12 of the bottom wall 11 of the first cavity 1, and by making the space between the outer peripheral surface of the carrier 21 and the inner peripheral surface of the bottom wall of the first cavity 1 and making the upper surface 221 of the sealing portion 22 lower than the upper surface 211 of the carrier 21, the adjacent position of the carrier 2 and the first cavity 1 is located below the wafer 7 in the vertical direction and has the space between the wafer 7 in the horizontal direction, so that the film 8 deposited at the adjacent position of the carrier 2 and the first cavity 1 can be far away from the wafer 7, thereby reducing the number of particles generated by the film 8 and the particles generated at the position and the wafer 7, and further reducing the probability of the semiconductor device and further being polluted by the particles.
As shown in fig. 2, in the semiconductor process, the film 8 generated by the reaction is deposited not only on the wafer 7 carried on the upper surface 211 of the carrying portion 21 but also on the upper surface 221 of the sealing portion 22 and the inner peripheral surface 13 of the bottom wall 11 of the first chamber 1, and the film 8 deposited on the upper surface 221 of the sealing portion 22 and the film 8 deposited on the inner peripheral surface 13 of the bottom wall 11 of the first chamber 1 are continuous, so that when the semiconductor process is finished, the carrying member 2 carries the wafer 7 down, the upper surface 221 of the sealing portion 22 is separated from the lower surface 12 of the bottom wall 11 of the first chamber 1, the continuous film 8 deposited on the upper surface 221 of the sealing portion 22 and the inner peripheral surface 13 of the bottom wall 11 of the first chamber 1 breaks to generate particles, which pollute the wafer 7 carried on the upper surface 211 of the carrying portion 21, and when the semiconductor process is started, the upper surface 221 of the sealing portion 22 is in contact with the lower surface 12 of the bottom wall 11 of the first chamber 1, the continuous film 8 deposited on the upper surface 221 of the sealing portion 22 can be crushed to pollute the surface 21 of the wafer 7 carried on the upper surface 21.
Since the upper surface 221 of the sealing portion 22 is lower than the upper surface 211 of the carrying portion 21 and there is a space between the outer circumferential surface 212 of the carrying portion 21 and the inner circumferential surface 13 of the bottom wall 11 of the first cavity 1, when the continuous film 8 deposited on the upper surface 221 of the sealing portion 22 and the inner circumferential surface 13 of the bottom wall 11 of the first cavity 1 breaks to generate particles, or when the film 8 deposited on the upper surface 221 of the sealing portion 22 is pressed by the lower surface 12 of the bottom wall 11 of the first cavity 1 to generate particles, the particles generated by the film 8 are lower than the upper surface 211 of the carrying portion 21 and have a space with the outer circumferential surface 212 of the carrying portion 21, so that the particles generated by the film 8 can be far away from the wafer 7 carried on the upper surface 211 of the carrying portion 21, thereby reducing the number and possibility that the particles generated by the film 8 are spread onto the wafer 7 carried on the upper surface 211 of the carrying portion 21, and consequently reducing the degree and possibility that the wafer 7 is polluted by the particles, and improving the performance of the semiconductor device.
In a preferred embodiment of the present invention, the thickness of the sealing portion 22 may be 2/3 of the thickness of the bearing portion 21. This makes it possible to provide the seal portion 22 with strength such that it does not deform when sealed in contact with the bottom wall 11 of the first chamber 1.
In practical use, the lower surface 12 of the bottom wall 11 of the first cavity 1 can be in mating contact seal with the upper surface 221 of the sealing portion 22 by increasing the thickness of the bottom wall 11 of the first cavity 1 by 1/3 of the thickness of the bearing portion 21.
In a preferred embodiment of the present invention, the interval between the outer circumferential surface 212 of the bearing portion 21 and the inner circumferential surface 13 of the bottom wall 11 of the first cavity 1 may be in the range of 0.5mm to 3mm. This prevents the carrier part 21 from colliding with the bottom wall 11 of the first chamber 1 when the carrier 2 rises to contact and seal with the bottom wall 11 of the first chamber 1.
Alternatively, the interval between the outer peripheral surface 212 of the bearing portion 21 and the inner peripheral surface 13 of the bottom wall 11 of the first cavity 1 may be 1mm.
As shown in fig. 3 to 8, in a preferred embodiment of the present invention, a sealing structure may be provided between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1, the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 being sealed by contact of the sealing structure, the sealing structure being for providing a gap between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1; the sealing structure comprises a plurality of first convex parts 3 and a plurality of second convex parts 4, wherein the plurality of first convex parts 3 are arranged on the upper surface 221 of the sealing part 22, the plurality of second convex parts 4 can be arranged on the lower surface 12 of the bottom wall 11 of the first cavity 1, each first convex part 3 is annularly arranged along the circumferential direction of the sealing part 22, each second convex part 4 is annularly arranged along the circumferential direction of the lower surface 12 of the bottom wall 11 of the first cavity 1, and the plurality of first convex parts 3 and the plurality of second convex parts 4 are alternately arranged at intervals in a surrounding way; the upper surface 221 of the sealing portion 22 is in contact with the lower surface 12 of the bottom wall 11 of the first chamber 1 via one of the first convex portion 3 or the second convex portion 4 located at the outermost side.
That is, in a preferred embodiment of the present invention, the upper surface 221 of the sealing portion 22 is not in direct contact seal with the lower surface of the bottom wall 11 of the first cavity 1, but in contact seal by the sealing structure, that is, by the first protrusion 3 or the second protrusion 4 provided around the outermost side.
And, in a direction away from the outer peripheral surface 212 of the bearing portion 21, the height of one first protrusion 3 or second protrusion 4 farthest from the outer peripheral surface 212 of the bearing portion 21 is larger than the heights of the remaining first protrusion 3 and second protrusion 4, so that when the upper surface 221 of the sealing portion 22 gradually approaches the lower surface 12 of the bottom wall 11 of the first cavity 1, the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 can be sealed by being in contact with the one first protrusion 3 or second protrusion 4 located at the outermost side, and the one first protrusion 3 or second protrusion 4 at the outermost side can provide a gap between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1.
As shown in fig. 3 to 8, the contact seal between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 by the one first convex portion 3 located at the outermost side is described as an example, when the carrier 2 is lifted, the top surface of the one first convex portion 3 located at the outermost side of the plurality of first convex portions 3 may contact seal with the lower surface 12 of the bottom wall 11 of the first cavity 1, that is, the upper surface 221 of the sealing portion 22 is contact-sealed with the lower surface 12 of the bottom wall 11 of the first cavity 1 by surrounding the one first convex portion 3 located at the outermost side, and a gap may be provided between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1.
However, the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 may be contact-sealed by the one second protrusion 4 located at the outermost side, in which case, when the carrier 2 rises, the bottom surface of the one second protrusion 4 located at the outermost side of the plurality of second protrusions 4 may be contact-sealed with the upper surface 221 of the sealing portion 22, that is, the lower surface 12 of the bottom wall 11 of the first cavity 1 is contact-sealed with the upper surface 221 of the sealing portion 22 by surrounding the one second protrusion 4 located at the outermost side, and a gap may be provided between the lower surface 12 of the bottom wall 11 of the first cavity 1 and the upper surface 221 of the sealing portion 22.
While the top surface of the first protrusion 3, which is close to the outer circumferential surface 212 of the bearing portion 21 with respect to the outermost one of the first protrusions 3 or the second protrusions 4, has a gap with the lower surface 12 of the bottom wall 11 of the first chamber 1, the bottom surface of the second protrusion 4, which is close to the outer circumferential surface 212 of the bearing portion 21 with respect to the outermost one of the first protrusions 3 or the second protrusions 4, has a gap with the upper surface 221 of the sealing portion 22, so that the flow passage 6 is formed between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first chamber 1.
In this way, the substances generated by the reaction in the semiconductor process can be brought to the position of the first convex part 3 or the second convex part 4 positioned at the outermost side through the flow channel 6 under the action of the air flow in the first cavity 1, so that on one hand, the situation that the films 8 deposited on the upper surface 221 of the sealing part 22 and the films 8 deposited on the inner peripheral surface 13 of the annular bottom wall 11 of the first cavity 1 by the substances generated by the reaction in the semiconductor process are reduced, and the substances generated by the reaction in the semiconductor process can be deposited on the position of the first convex part 3 positioned at the outermost side and far away from the bearing part 21, and the films 8 deposited on the upper surface 221 of the sealing part 22 and the films 8 deposited on the inner peripheral surface 13 of the bottom wall 11 of the first cavity 1 are not continuous can be avoided, and further, the situation that the continuous films 8 deposited on the upper surface 221 of the sealing part 22 and the inner peripheral surface 13 of the annular bottom wall 11 of the first cavity 1 are broken can be avoided, the situation that the films 8 deposited on the upper surface 221 of the sealing part 22 are extruded by the first cavity 11 can be avoided, the situation that the wafers and the particles of the films 8 are further reduced, and the performance of the semiconductor devices can be further reduced.
On the other hand, the first convex portion 3 and the second convex portion 4 located at the outermost one of the first convex portion 3 and the second convex portion 4 near the carrier portion 21 can also block the particles generated by the thin film 8 deposited at the outermost one of the first convex portion 3 and the second convex portion 4 from diffusing in a direction near the carrier portion 21, so that the number and possibility of the particles diffusing onto the wafer 7 carried on the carrier portion 21 can be further reduced, the degree and possibility of the wafer 7 being contaminated by the particles can be further reduced, and the performance of the semiconductor device can be further improved.
As shown in fig. 3 to 8, in a preferred embodiment of the present invention, the heights of the plurality of first protrusions 3 and the plurality of second protrusions 4 are gradually increased in a direction away from the outer circumferential surface 212 of the bearing portion 21.
That is, the height of the plurality of first protrusions 3 gradually increases in a direction away from the outer peripheral surface 212 of the bearing portion 21, and the height of the plurality of second protrusions 4 gradually increases, the height of one first protrusion 3 closest to the outer peripheral surface 212 of the bearing portion 21 among the plurality of first protrusions 3 disposed around is lowest, the height of one first protrusion 3 farthest from the outer peripheral surface 212 of the bearing portion 21 is highest, the height of one second protrusion 4 closest to the outer peripheral surface 212 of the bearing portion 21 among the plurality of second protrusions 4 disposed around is lowest, the height of one second protrusion 4 farthest from the outer peripheral surface 212 of the bearing portion 21 is highest, and the height of one first protrusion 3 located outermost is higher than the height of the second protrusion 4 with respect to the outer peripheral surface 212 thereof closest to the bearing portion 21.
In a preferred embodiment of the present invention, the interval between the adjacent two first protrusions 3 and second protrusions 4 may be greater than or equal to the interval between the outer peripheral surface 212 of the bearing portion 21 and the inner peripheral surface 13 of the bottom wall 11 of the first cavity 1.
This prevents the adjacent two first protrusions 3 and second protrusions 4 from colliding when the carrier 2 is lifted up to contact and seal with the bottom wall 11 of the first cavity 1.
In a preferred embodiment of the present invention, the distance between the adjacent two first protrusions 3 and second protrusions 4 may gradually decrease in a direction away from the outer peripheral surface 212 of the bearing portion 21.
That is, the distance between the adjacent two first convex portions 3 and second convex portions 4 may gradually increase in the direction approaching the outer peripheral surface 212 of the bearing portion 21. On the one hand, substances generated by reaction in the semiconductor process can more easily pass through the flow channel 6 formed by the first convex part 3 and the second convex part 4, and on the other hand, the first convex part 3 and the second convex part 4 can more effectively prevent particles generated by the thin film 8 deposited at the first convex part 3 at the outermost side from diffusing towards the direction close to the bearing part 21, so that the degree and possibility of the pollution of the wafer 7 by the particles can be further reduced, and the performance of the semiconductor component can be further improved.
Alternatively, the outer diameter of one of the first protrusions 3 circumferentially disposed at the outermost side may be equal to the outer diameter of the sealing portion 22.
In this way, the first protruding portion 3 surrounding the outermost one is furthest away from the bearing portion 21, so that the thin film 8 deposited at the first protruding portion 3 located at the outermost one can be furthest away from the bearing portion 21, the degree and possibility of particle pollution of the wafer 7 can be further reduced, and the performance of the semiconductor component can be further improved.
As shown in fig. 8, in a preferred embodiment of the present invention, the remaining first convex portion 3 and second convex portion 4 are inclined in a direction away from the outer peripheral surface 212 of the bearing portion 21 except for one of the first convex portion 3 or second convex portion 4 disposed around the outermost side.
That is, the remaining first convex portion 3 and second convex portion 4 are inclined toward the direction in which the air flow flows from inside the first chamber 1 to outside the first chamber 1, except for one first convex portion 3 or second convex portion 4 provided around the outermost side. On the one hand, substances generated by reaction in the semiconductor process can more easily pass through the flow channel 6 formed by the first convex part 3 and the second convex part 4 under the action of air flow, and on the other hand, the first convex part 3 and the second convex part 4 can more effectively prevent particles generated by the thin film 8 deposited at the first convex part 3 positioned at the outermost side from diffusing towards the direction close to the bearing part 21, so that the degree and possibility of pollution of the wafer 7 by the particles can be further reduced, and the performance of the semiconductor component can be further improved.
As shown in fig. 1, in a preferred embodiment of the present invention, the process chamber may further comprise a second cavity 5, and the first cavity 1 and the carrier 2 are disposed in the second cavity 5.
In the atomic layer deposition device, the first cavity 1 can be used as a reaction cavity to provide a high-temperature environment for the atomic layer deposition process to prevent the reactant of the atomic layer deposition process from condensing, the second cavity 5 can be used as a protection cavity, and the outer wall of the protection cavity can be provided with a cooling structure to prevent scalding, so that the problem that the reactant of the atomic layer deposition process is cold can be solved.
As shown in fig. 1-4 and fig. 6-8, optionally, a limiting member 101 may be disposed at an edge of the upper surface 211 of the carrier 21, where the limiting member 101 is annular along a circumferential direction of the carrier 21, so as to limit a position of the wafer 7 carried on the upper surface 211 of the carrier 21.
As shown in fig. 1, the process chamber may optionally further include an air inlet part 102, a first air inlet pipe 103, a second air inlet pipe 104, a third air inlet pipe 105, a first air inlet branch pipe 106, a first air outlet branch pipe 107, a second air inlet branch pipe 108, a second air outlet branch pipe 109, a first air exhaust pipe 110, a second air exhaust pipe 111, a first air source 112, a second air source 113, an air exhaust part 114, a first heating element 124, and a second heating element 125.
Wherein, the air inlet unit 102 is disposed on the top wall of the first cavity 1, one end of the first air inlet pipe 103 may be communicated with the air inlet unit 102, the other end may be communicated with a purge air source (not shown in the figure), one end of the second air inlet pipe 104 may be communicated with the air inlet unit 102, the other end may be communicated with the purge air source, one end of the first air inlet branch pipe 106 may be communicated with the first air inlet pipe 103, the other end may be communicated with an air inlet end of the first air inlet pipe 112, one end of the first air outlet branch pipe 107 may be communicated with the first air inlet pipe 103, the other end may be communicated with an air outlet end of the first air inlet pipe 112, and a communication position of the first air outlet branch pipe 107 and the first air inlet pipe 103 is close to the air inlet unit 102 relative to a communication position of the first air inlet branch pipe 106 and the first air inlet pipe 103, a first on-off valve 115 may be disposed on the first air inlet pipe 103, and the first on-off valve 115 is disposed between a communication position of the first air inlet branch pipe 106 and the first air inlet pipe 103, a first air inlet pipe 106 may be disposed on the first air inlet branch pipe 106, a first air outlet branch pipe 107 may be disposed on the air inlet pipe 106 may be communicated with an air inlet end of the first air inlet pipe 112, the first air outlet branch pipe 107 may be disposed on the first air outlet valve 107 may be disposed, and may be disposed on the first air inlet pipe 107 may be disposed with a first air inlet valve and may be disposed with a first air source (for supplying a solid state gas, for example, the first gas may supply gas may be or may be purged (or may be a gas or may be purged).
The first on-off valve 115 is used for controlling the on-off of the first air inlet pipe 103, the first air inlet valve 116 is used for controlling the on-off of the first air inlet branch pipe 106, the first air outlet valve 117 is used for controlling the on-off of the first air outlet pipe, when the first air inlet pipe 103 is in a connected state, the first air inlet branch pipe 106 is in a disconnected state, the first air outlet pipe is in a disconnected state, the first air inlet pipe 103 can convey purge gas provided by a purge gas source to the air inlet part 102, and the purge gas can enter the first cavity 1 through the air inlet part 102 to purge the first cavity 1. When the first air inlet pipe 103 is in a disconnected state, the first air inlet branch pipe 106 is in a connected state, the first air outlet pipe is in a connected state, and purge gas provided by the purge gas source can sequentially pass through the first air inlet pipe 103 and the first air inlet branch pipe 106 and enter the first gas source 112, so that a first reactant provided by the first gas source 112 can be carried to sequentially pass through the first air outlet pipe and the first air inlet pipe 103 and enter the air inlet part 102, and then enter the first cavity 1 through the air inlet part 102, and a semiconductor process reaction is performed in the first cavity 1.
One end of the second air inlet pipe 104 may be communicated with the air inlet component 102, the other end may be communicated with a purge air source, one end of the second air inlet branch pipe 108 may be communicated with the second air inlet pipe 104, the other end may be communicated with an air inlet end of the second air source 113, one end of the second air outlet branch pipe 109 may be communicated with the second air inlet pipe 104, the other end may be communicated with an air outlet end of the second air source 113, a communication position of the second air outlet branch pipe 109 and the second air inlet pipe 104 is close to the air inlet component 102 relative to a communication position of the second air inlet branch pipe 108 and the second air inlet pipe 104, a second on-off valve 118 may be arranged on the second air inlet pipe 104, and the second on-off valve 118 is located between a communication position of the second air inlet branch pipe 108 and the second air inlet pipe 104, a second air inlet valve 119 may be arranged on the second air inlet branch pipe 108, a second air outlet valve 120 may be arranged on the second air outlet branch pipe 109, the second air source 113 may provide a second reactant (for example, water capable of generating oxygen atoms), and the second air source may provide a purge gas (nitrogen or inert gas).
The second on-off valve 118 is used for controlling the on-off of the second air inlet pipe 104, the second air inlet valve 119 is used for controlling the on-off of the second air inlet branch pipe 108, the second air outlet valve 120 is used for controlling the on-off of the second air outlet pipe, when the second air inlet pipe 104 is in a connected state, the second air inlet branch pipe 108 is in a disconnected state, the second air outlet pipe is in a disconnected state, the second air inlet pipe 104 can convey purge gas provided by a purge gas source to the air inlet part 102, the purge gas can enter the first cavity 1 through the air inlet part 102, and the first cavity 1 is purged. When the second air inlet pipe 104 is in the disconnected state, the second air inlet branch pipe 108 is in the connected state, and the second air outlet pipe is in the connected state, the purge gas provided by the purge gas source can sequentially pass through the second air inlet pipe 104 and the second air inlet branch pipe 108 and enter the second gas source 113, so that the second reactant provided by the second gas source 113 can be carried to sequentially pass through the second air outlet pipe and the second air inlet pipe 104 and enter the air inlet part 102, and then enter the first cavity 1 through the air inlet part 102, and the semiconductor process reaction is performed in the first cavity 1.
One end of the third air inlet pipe 105 can be communicated with the first cavity 1, the other end of the third air inlet pipe 105 can be communicated with a purge air source, a third three-way cut-off valve 121 can be arranged on the third air inlet pipe 105, the purge air source can provide purge air (nitrogen or inert gas), the third on-off valve 121 is used for controlling on-off of the third air inlet pipe 105, and when the third air inlet pipe 105 is in a communicated state, the purge air provided by the purge air source can be conveyed into the second cavity 5, so that the air pressure in the second cavity 5 is kept stable.
One end of the first air extraction pipe 110 is communicated with the first cavity 1, the other end of the first air extraction pipe 110 is communicated with the air extraction component 114, a first air extraction valve 122 can be arranged on the first air extraction pipe 110, the first air extraction valve 122 is used for controlling the on-off of the first air extraction pipe 110, and when the first air extraction pipe 110 is in a communicated state, the air extraction component 114 can extract gas in the first cavity 1 through the first air extraction pipe 110. One end of the second air extraction pipe 111 is communicated with the second cavity 5, the other end of the second air extraction pipe 111 is communicated with the air extraction component 114, a second air extraction valve 123 can be arranged on the second air extraction pipe 111, the second air extraction valve 123 is used for controlling the on-off of the second air extraction pipe 111, and when the second air extraction pipe 111 is in a communicated state, the air extraction component 114 can extract the air in the second cavity 5 through the second air extraction pipe 111.
The first heating member 124 may be disposed in the second cavity 5 above the air inlet part 102, and the second heating member 125 may be disposed in the second cavity 5 below the carrier 2, where the first heating member 124 and the second heating member 125 are used to heat the air inlet of the first cavity 1 from above and below, respectively.
As shown in fig. 1, the embodiment of the invention further provides a semiconductor device, which includes the process chamber provided by the embodiment of the invention.
The semiconductor device provided by the embodiment of the invention can reduce the degree and possibility of the wafer 7 being polluted by particles by the aid of the process chamber of the semiconductor device, so that the performance of semiconductor components can be improved.
As shown in fig. 9, the embodiment of the present invention further provides a semiconductor processing method, which adopts the process chamber provided by the embodiment of the present invention, and includes the following steps:
s1, descending the carrier 2, so that a clearance for purging is formed between the upper surface 221 of the sealing part 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1;
s2, conveying the purge gas into the first cavity 1, enabling the air pressure in the first cavity 1 to be larger than the air pressure outside the first cavity 1, purging the upper surface 221 of the carrier 2, and enabling the purge gas to flow through the gap.
According to the semiconductor processing method provided by the embodiment of the invention, the carrier 2 is lowered to enable the gap for purging to be formed between the upper surface 221 of the sealing part 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1, the purging gas is conveyed into the first cavity 1, the air pressure in the first cavity 1 is larger than the air pressure outside the first cavity 1, the upper surface of the carrier 2 is purged, the purging gas flows through the gap for purging, the film 8 deposited at the adjacent position between the carrier 2 and the first cavity 1 can be purged to the outside of the first cavity 1 from particles which are generated and attached to the upper surface of the carrier 2, the number of particles attached to the upper surface of the carrier 2 is reduced, so that the degree and possibility that the wafer 7 is polluted by the particles can be reduced, the performance of semiconductor components can be improved, and the air flow in the first cavity 1 can have stronger impact force and the purging effect can be improved by enabling the air pressure in the first cavity 1 to be larger than the air pressure outside the first cavity 1.
When the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 are not provided with the first convex portion 3 and the second convex portion 4, the carrier 2 may be lowered with a gap for purging between the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1. When the upper surface 221 of the sealing portion 22 and the lower surface 12 of the bottom wall 11 of the first cavity 1 are provided with the first convex portion 3 and the second convex portion 4, the carrier 2 can be lowered with a gap for purging between the top surface of the outermost one of the first convex portions 3 and the lower surface 12 of the bottom wall 11 of the first cavity 1, or with a gap for purging between the bottom surface of the outermost one of the second convex portions 4 and the upper surface 221 of the sealing portion 22.
In practical applications, the opening of the first air extraction valve 122 may be reduced, so that the suction force of the air extraction component 114 on the first cavity 1 may be reduced, and the air pressure in the first cavity 1 may be increased, so that the air pressure in the first cavity 1 may be greater than the air pressure outside the first cavity 1 under the condition that the air pressure outside the first cavity 1 and the air pressure inside the second cavity 5 are unchanged.
In a preferred embodiment of the invention, the carrier 2 is lowered such that the gap between the upper surface 221 of the purge seal 22 and the lower surface 12 of the bottom wall 11 of the first chamber 1 may be 1mm-5mm.
Alternatively, the carrier 2 is lowered so that the gap between the upper surface 221 of the purge seal 22 and the lower surface 12 of the bottom wall 11 of the first chamber 1 may be 2mm.
In a preferred embodiment of the present invention, the carrier 2 is lowered so that the top surface of the outermost one of the first protrusions 3 and the lower surface 12 of the bottom wall 11 of the first chamber 1 have a clearance for purging therebetween, or so that the bottom surface of the outermost one of the second protrusions 4 and the upper surface 221 of the sealing portion 22 have a clearance for purging therebetween, may be 1mm to 5mm.
Alternatively, the carrier 2 may be lowered so that a clearance for purging is provided between the top surface of the outermost one of the first protrusions 3 and the lower surface 12 of the bottom wall 11 of the first chamber 1, or so that a clearance for purging is provided between the bottom surface of the outermost one of the second protrusions 4 and the upper surface 221 of the sealing portion 22, may be 2mm.
In a preferred embodiment of the present invention, the pressure in the first chamber 1 may be made greater than the pressure outside the 1 st chamber 1 by 0.5Torr-10Torr when the upper surface of the carrier 2 is purged.
Alternatively, the pressure in the first chamber 1 may be made greater than the pressure of 5Torr outside the 1 st chamber 1 while purging the upper surface of the carrier 2.
In summary, the process chamber of the semiconductor device, the semiconductor device and the semiconductor processing method provided by the embodiment of the invention can reduce the degree and possibility of particle pollution of the wafer 7 and improve the performance of semiconductor components.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims (10)

1. The utility model provides a process chamber of semiconductor equipment, its characterized in that includes first cavity and carrier, the diapire of first cavity is provided with the opening, the carrier can be relative the diapire of first cavity is gone up and down to set up, in order to cooperate the process environment of first cavity formation semiconductor process, the carrier includes carrier and sealing part, the upper surface of carrier is used for carrying the wafer, and the outer peripheral face of carrier and the inner peripheral face of the diapire of first cavity have the interval, sealing part encircles carrier is the ring-shaped setting, just the upper surface of sealing part is less than the upper surface of carrier, the upper surface of sealing part with the lower surface contact seal of the diapire of first cavity.
2. The process chamber of claim 1, wherein a sealing structure is disposed between an upper surface of the sealing portion and a lower surface of the bottom wall of the first chamber, the sealing structure comprising a plurality of first protrusions and a plurality of second protrusions, the plurality of first protrusions being disposed on the upper surface of the sealing portion, the plurality of second protrusions being disposed on the lower surface of the bottom wall of the first chamber, each of the first protrusions being disposed annularly along a circumferential direction of the sealing portion, each of the second protrusions being disposed annularly along a circumferential direction of the lower surface of the bottom wall of the first chamber, the plurality of first protrusions and the plurality of second protrusions being alternately disposed circumferentially at intervals;
the upper surface of the sealing part is in contact with the lower surface of the bottom wall of the first cavity through one of the first convex part or the second convex part located at the outermost side.
3. The process chamber of claim 2, wherein the heights of the plurality of first protrusions and the plurality of second protrusions each gradually increase in a direction away from the outer peripheral surface of the carrier.
4. The process chamber of claim 2, wherein a spacing between two adjacent first and second protrusions is greater than or equal to a spacing between an outer peripheral surface of the carrier and an inner peripheral surface of a bottom wall of the first cavity.
5. The process chamber of a semiconductor device according to claim 2, wherein a distance between two adjacent first convex portions and the second convex portion gradually decreases in a direction away from an outer peripheral surface of the carrier portion.
6. The process chamber of a semiconductor device according to claim 2, wherein each of the remaining first convex portion and the second convex portion is inclined in a direction away from an outer peripheral surface of the carrier portion except for the first convex portion or the second convex portion provided at an outermost side.
7. The process chamber of claim 1, wherein the seal has a thickness of 2/3 of a thickness of the carrier.
8. The process chamber of a semiconductor apparatus of claim 1, further comprising a second cavity, the first cavity and the carrier being disposed within the second cavity.
9. A semiconductor device comprising a process chamber according to any of claims 1-8.
10. A semiconductor processing method, characterized in that a process chamber according to any of claims 1-8 is used, comprising the steps of:
lowering the carrier so that a gap for purging is provided between the upper surface of the sealing portion and the lower surface of the bottom wall of the first cavity;
and conveying purge gas into the first cavity, enabling the air pressure in the first cavity to be larger than the air pressure outside the first cavity, purging the upper surface of the bearing piece, and enabling the purge gas to flow through the gap.
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