CN113270503A - Semiconductor unit cell structure - Google Patents
Semiconductor unit cell structure Download PDFInfo
- Publication number
- CN113270503A CN113270503A CN202110491421.9A CN202110491421A CN113270503A CN 113270503 A CN113270503 A CN 113270503A CN 202110491421 A CN202110491421 A CN 202110491421A CN 113270503 A CN113270503 A CN 113270503A
- Authority
- CN
- China
- Prior art keywords
- layer
- region
- substrate
- cell structure
- type base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000001465 metallisation Methods 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 38
- 229910052709 silver Inorganic materials 0.000 claims description 23
- 239000004332 silver Substances 0.000 claims description 23
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 19
- 229910052719 titanium Inorganic materials 0.000 claims description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 210000003850 cellular structure Anatomy 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000011084 recovery Methods 0.000 abstract description 5
- 238000005265 energy consumption Methods 0.000 abstract description 4
- 210000004027 cell Anatomy 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Abstract
The invention provides a diode cellular structure, which comprises an N + substrate, wherein a back metal layer is arranged on the back surface of the N + substrate, and an N-epitaxial region, a gate oxide layer, polycrystalline silicon and a metallization layer are sequentially arranged on the front surface of the N + substrate; the front middle part of the N-epitaxial region is embedded with a P-type base region, the back of the metallization layer is provided with a protruding part, the protruding part is embedded into the P-type base region, an N + region is arranged around the protruding part, and the front of the N + region and the front of the P-type base region are both covered by a gate oxide layer. Compared with a PN junction structure, the diode chip adopting the diode cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; in addition, the invention has the advantages of small conduction voltage drop, low energy consumption, small heat production and strong durability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor cellular structure.
Background
With the development of semiconductor technology, new structure diodes such as JBS, MPS, TMPS, etc. have been developed in recent years, and the performance of the diodes has been improved. However, the above structures are basically extended based on the structure of the conventional PN junction or schottky junction, and the problems of large forward voltage drop, large reverse recovery time, poor high-temperature characteristics and poor reliability of the schottky junction structure, and the like of the PN junction structure cannot be completely avoided.
Chinese patent publication No. CN102709317A discloses a low-turn-on voltage diode, which includes an N + substrate, a metallized cathode on the back of the N + substrate, and an N-epitaxial layer on the front, wherein the surface of the N-epitaxial layer is a metallized anode, two sides of the top of the N-epitaxial layer are respectively provided with a P-type heavily doped region, the inner sides of the P-type heavily doped regions are respectively provided with an N-type heavily doped region, a deep P body region is also respectively arranged below the P-type heavily doped regions, and two deep P body regions and the N-epitaxial layer therebetween form a junction field effect transistor region. The diode is not suitable for the axial high-reliability packaging commonly adopted by the existing diode, and the heat dissipation capability is relatively poor.
Disclosure of Invention
In order to solve the technical problems, the invention provides a diode cellular structure, a diode chip based on the cellular structure and a manufacturing method thereof.
The invention is realized by the following technical scheme.
The diode cellular structure comprises an N + substrate, wherein a back metal layer is arranged on the back surface of the N + substrate, and an N-epitaxial region, a gate oxide layer, polycrystalline silicon and a metallization layer are sequentially arranged on the front surface of the N + substrate; the front middle part of the N-epitaxial region is embedded with a P-type base region, the back of the metallization layer is provided with a protruding part, the protruding part is embedded into the P-type base region, an N + region is arranged around the protruding part, and the front of the N + region and the front of the P-type base region are both covered by a gate oxide layer.
And a flat P + region is arranged between the end face of the bulge part and the P-type base region.
The back metal layer sequentially comprises a titanium layer, a nickel layer and a silver layer from the back of the N + substrate to the outside.
The thickness of the titanium layer, the nickel layer and the silver layer of the back metal layer is 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 1400 nm-1500 nm of silver in sequence.
The metallization layer sequentially comprises a titanium layer, a nickel layer and a silver layer from the direction close to the N-epitaxial region to the direction far away from the N-epitaxial region.
The thicknesses of the titanium layer, the nickel layer and the silver layer of the metallization layer are 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 400 nm-600 nm of silver in sequence.
The N + substrate is a <100> crystal orientation N-type polishing sheet material.
The polysilicon is doped polysilicon.
The thickness of the polycrystalline silicon is 0.2-0.6 mu m.
The gate oxide layer is made of a high-K dielectric material.
The invention has the beneficial effects that:
the invention provides a new scheme for improving the contradiction relation between the conduction loss and the switching frequency in the diode from a brand new angle. Compared with a PN junction structure, the diode chip adopting the diode cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; in addition, the invention has the advantages of small conduction voltage drop, low energy consumption, small heat production and strong durability.
Drawings
FIG. 1 is a schematic diagram of the structure of a cell of the present invention.
FIG. 2 is a schematic diagram of a chip based on a cell structure according to the present invention.
In the figure: a 1-N + substrate; 2-back metal layer; a 3-N-epitaxial region; 4-a gate oxide layer; 5-polycrystalline silicon; 6-a metallization layer; 7-P type base region; an 8-P + region; a 9-N + region; 10-titanium layer; 11-a nickel layer; 12-silver layer.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
Fig. 1 is a schematic structural diagram of a diode cell structure according to the present invention:
the invention provides a diode cellular structure, which comprises an N + substrate 1, wherein the back surface of the N + substrate 1 is provided with a back metal layer 2, and the front surface of the N + substrate 1 is sequentially provided with an N-epitaxial region 3, a gate oxide layer 4, polycrystalline silicon 5 and a metallization layer 6; the middle of the front face of the N-epitaxial region 3 is embedded with a P-type base region 7, the back face of the metallization layer 6 is provided with a protruding portion, the protruding portion is embedded into the P-type base region 7, an N + region 9 is arranged around the protruding portion, and the front faces of the N + region 9 and the P-type base region 7 are both covered by the gate oxide layer 4.
The principle is as follows: the back metal layer 2 below the N + substrate 1 is used as a cathode of a diode electrode, the metallization layer 6 at the top of the polycrystalline silicon 5 is used as an anode of the diode, the N-epitaxial region 3 is provided with an N + region 9, a P + region 8 and a P-type base region 7 (also called as a P-base region), and the whole cell can be regarded as a planar gate power MOS cell structure similar to a gate short circuit and a drain short circuit. The minority carrier barrier is generated by an N + region 9, a P-type base region 78 and a barrier MOS channel formed by N-epitaxy, and the barrier MOS channel is formed by the difference between the diffusion of the P-type base region 7 and the diffusion of the N + region 9. For the barrier MOS, the N + region 9 may be regarded as the drain of the barrier MOS, and the diode cathode may be regarded as the source of the barrier MOS. When positive voltage is applied to the anode, positive voltage is applied to the drain gate of the barrier MOS, the channel of the P-type base region 7 below the gate oxide is inverted, the channel is opened, and current can pass through the channel. The threshold voltage of the barrier MOS is designed to be very small, which is much smaller than the general PN junction barrier voltage and smaller than the barrier formed by the contact of the metal and the semiconductor of the Schottky diode, so that very small conduction voltage drop can be obtained.
The invention provides a new scheme for improving the contradiction relation between the conduction loss and the switching frequency in the diode from a brand new angle. Compared with a PN junction structure, the diode chip adopting the diode cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; in addition, the invention has the advantages of small conduction voltage drop, low energy consumption, small heat production and strong durability.
A flat P + region 8 is arranged between the end face of the convex part and the P-type base region 7. The P + region 8 is formed on the P-type base region 7 in a diffusion mode, so that ohmic contact is improved, the use performance is improved, and the heat generation quantity is reduced.
The back metal layer 2 sequentially comprises a titanium layer 10, a nickel layer 11 and a silver layer 12 from the back of the N + substrate 1 to the outside. And the multilayer metal structure realizes better ohmic contact and optimizes the on-resistance of the product. The outermost layer of the metallization layer 6 can also adopt silver, and double-sided silver is adopted, so that the chip can directly adopt a double-sided sintering packaging process.
The thickness of the titanium layer 10, the nickel layer 11 and the silver layer 12 of the back metal layer 2 is 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 1400 nm-1500 nm of silver in sequence.
The metallization layer 6 sequentially comprises a titanium layer 10, a nickel layer 11 and a silver layer 12 from the direction close to the N-epitaxial region 3 to the direction far away from the N-epitaxial region 3. The multilayer metal structure realizes better ohmic contact and optimizes the on-resistance of the product; the outermost layer of the back metal layer 2 can also adopt silver, and double-sided silver is adopted, so that the chip can directly adopt a double-sided sintering packaging process.
The thicknesses of the titanium layer 10, the nickel layer 11 and the silver layer 12 of the metallization layer 6 are 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 400 nm-600 nm of silver in sequence.
The N + substrate 1 is a <100> crystal orientation N-type polishing sheet material. The 100-crystal-orientation silicon material has low interface state density and is more suitable for the cellular structure of the invention.
The polysilicon 5 is doped polysilicon.
The thickness of the polycrystalline silicon 5 is 0.2-0.6 mu m.
The gate oxide layer 4 is made of a high-K dielectric material. The high-K dielectric material comprises silicon dioxide, silicon nitride, hafnium dioxide, aluminum oxide and the like, and has good insulativity and reliable resistance.
Fig. 2 is a schematic structural diagram of a diode chip based on a cell structure according to the present invention:
the invention also provides a diode chip based on the cellular structure, which comprises a plurality of cellular units connected in parallel.
Compared with a PN junction structure, the diode chip based on the cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; moreover, the invention has small conduction voltage drop, low energy consumption, small heat production and strong durability; and a multi-cell parallel structure is adopted, so that the heat dissipation capability is greatly improved.
Specifically, the back metal layers 2 of different cells are integrally connected with each other to form a cathode surface, the metallization layers 6 of different cells are integrally connected with each other to form an anode surface, the N + substrates 1 of different cells are integrally connected with each other, the N-epitaxial regions 3 of different cells are integrally connected with each other, the gate oxide layers 4 of different cells are integrally connected with each other, and the polysilicon layers 5 of different cells are integrally connected with each other.
According to the scheme, units consisting of the polycrystalline silicon 5, the N + region 9, the P-type base region 7 and the P + region 8 work independently, the upper surface and the lower surface of the rest part are integrated (the upper surface refers to the metallization layer 6 and the gate oxide layer 4, and the lower surface refers to the back metal layer 2, the N-epitaxial region 3 and the N + substrate 1), the heat diffusion area is increased, heat formed by current conduction can be diffused to any direction and is finally diffused from the metal layers on the two sides, and the reliability of a product is improved; in addition, when one cell is broken and damaged, other cells can work normally without influencing the functionality of the diode chip; when the diode is manufactured, the two sides of the chip can be sintered on the lead posts, namely, a small radiator is added on the two sides of the chip, and the double-side heat dissipation of the chip is realized.
The invention also provides a manufacturing method of the diode chip based on the cellular structure, which comprises the following steps:
step one, manufacturing an N + substrate 1, and growing an N-epitaxial region 3 on the front surface of the substrate;
step two, after a terminal area is manufactured on the N-epitaxial region 3, the active region is covered by thick field oxygen, and the active region is opened through etching;
thirdly, thermally oxidizing the front surface of the N-epitaxial region 3, and growing gate oxide to form a gate oxide layer 4;
depositing and photoetching the polycrystalline silicon 5 on the gate oxide layer 4, etching a hole through photoetching, and etching the polycrystalline silicon 5 into the N-epitaxial region 3;
step five, injecting a P-type base region 7, pushing a well, then injecting an N + region 9, pushing the well, and carrying out photoetching and pushing the well on a P + region 8;
and step six, preparing a metallization layer 6 on the front side of the polycrystalline silicon 5, thinning the substrate on the back side of the N + substrate 1, and preparing a back metal layer 2 after thinning.
Claims (10)
1. A semiconductor cell structure, characterized by: the silicon-based epitaxial structure comprises an N + substrate (1), wherein a back metal layer (2) is arranged on the back surface of the N + substrate (1), and an N-epitaxial region (3), a gate oxide layer (4), polycrystalline silicon (5) and a metallization layer (6) are sequentially arranged on the front surface of the N + substrate (1); the front middle part of the N-epitaxial region (3) is embedded with a P-type base region (7), the back of the metallization layer (6) is provided with a protruding part, the protruding part is embedded into the P-type base region (7), an N + region (9) is arranged around the protruding part, and the front of the N + region (9) and the front of the P-type base region (7) are both covered by a gate oxide layer (4).
2. The semiconductor cell structure of claim 1, wherein: and a flat P + region (8) is arranged between the end face of the bulge part and the P-type base region (7).
3. The semiconductor cell structure of claim 1, wherein: the back metal layer (2) sequentially comprises a titanium layer (10), a nickel layer (11) and a silver layer (12) from the back of the N + substrate (1) to the outside.
4. The semiconductor cell structure of claim 3, wherein: the thickness of the titanium layer (10), the nickel layer (11) and the silver layer (12) of the back metal layer (2) is 80-100 nm of titanium, 80-100 nm of nickel and 1400-1500 nm of silver in sequence.
5. The semiconductor cell structure of claim 1, wherein: the metallization layer (6) sequentially comprises a titanium layer (10), a nickel layer (11) and a silver layer (12) from the direction close to the N-epitaxial region (3) to the direction far away from the N-epitaxial region (3).
6. The semiconductor cell structure of claim 5, wherein: the titanium layer (10), the nickel layer (11) and the silver layer (12) of the metallization layer (6) are 80-100 nm of titanium, 80-100 nm of nickel and 400-600 nm of silver in sequence.
7. The semiconductor cell structure of claim 1, wherein: the N + substrate (1) is a <100> crystal orientation N-type polishing sheet material.
8. The semiconductor cell structure of claim 1, wherein: the polysilicon (5) is doped polysilicon.
9. The semiconductor cell structure of claim 1 or 8, wherein: the thickness of the polycrystalline silicon (5) is 0.2-0.6 mu m.
10. The semiconductor cell structure of claim 1, wherein: the gate oxide layer (4) is made of a high-K dielectric material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110491421.9A CN113270503A (en) | 2021-05-06 | 2021-05-06 | Semiconductor unit cell structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110491421.9A CN113270503A (en) | 2021-05-06 | 2021-05-06 | Semiconductor unit cell structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113270503A true CN113270503A (en) | 2021-08-17 |
Family
ID=77229926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110491421.9A Pending CN113270503A (en) | 2021-05-06 | 2021-05-06 | Semiconductor unit cell structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113270503A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN104576361A (en) * | 2013-10-23 | 2015-04-29 | 无锡华润上华半导体有限公司 | Preparation method of power diode |
-
2021
- 2021-05-06 CN CN202110491421.9A patent/CN113270503A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN104576361A (en) * | 2013-10-23 | 2015-04-29 | 无锡华润上华半导体有限公司 | Preparation method of power diode |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101976687B (en) | Fast recovery metal oxide semiconductor diode with low power consumption | |
| CN114937693B (en) | Trench gate SiC MOSFET device with double-channel diode and preparation method thereof | |
| CN114927562B (en) | Silicon carbide JFET device structure and preparation method thereof | |
| CN114220844A (en) | Silicon carbide MOSFET device integrated with SBD and preparation method thereof | |
| CN102064201B (en) | Shallow-slot metal oxide semiconductor diode | |
| CN112786680B (en) | Cell structure of silicon carbide MOSFET device and power semiconductor device | |
| WO2021088231A1 (en) | Cellular structure of silicon carbide mosfet device, and silicon carbide mosfet device | |
| CN115832057A (en) | Silicon carbide MOSFET device and preparation method thereof | |
| CN117476774B (en) | Structure, manufacturing method and electronic equipment of vertical silicon carbide transistor | |
| CN213459736U (en) | SiC IGBT device | |
| CN111081758B (en) | SiC MPS structure capable of reducing on-resistance and preparation method thereof | |
| CN113054015A (en) | Silicon carbide MOSFET chip | |
| CN116454137A (en) | SBD (integrated SBD) groove-type split source SiC VDMOS (vertical double-diffused metal oxide semiconductor) structure and manufacturing method thereof | |
| CN214477478U (en) | Diode chip | |
| CN113270503A (en) | Semiconductor unit cell structure | |
| CN116130480A (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN115602734A (en) | Novel silicon carbide power diode with high forward current density | |
| CN112259599B (en) | Silicon wafer bonding type IGBT device and manufacturing method thereof | |
| CN217522006U (en) | Diode cell | |
| CN113270502A (en) | Diode chip and manufacturing method thereof | |
| CN210607276U (en) | Groove type power device based on Schottky structure | |
| CN109065638B (en) | Power diode device | |
| CN107863386B (en) | Trench MOS device integrated with TMBS structure and manufacturing method thereof | |
| CN107863341B (en) | Composite groove MOS device and manufacturing method thereof | |
| CN214152912U (en) | Semiconductor power device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210817 |