CN113270502A - Diode chip and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 238000001465 metallisation Methods 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 32
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 20
- 229910052709 silver Inorganic materials 0.000 claims description 20
- 239000004332 silver Substances 0.000 claims description 20
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 239000010936 titanium Substances 0.000 claims description 16
- 229910052719 titanium Inorganic materials 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 238000011084 recovery Methods 0.000 abstract description 4
- 238000005265 energy consumption Methods 0.000 abstract description 3
- 210000004027 cell Anatomy 0.000 description 36
- 230000004888 barrier function Effects 0.000 description 10
- 239000011521 glass Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
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- 210000003850 cellular structure Anatomy 0.000 description 3
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- 238000002161 passivation Methods 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
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- 210000000746 body region Anatomy 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention provides a diode chip and a manufacturing method thereof, wherein the chip comprises a plurality of cells which are mutually connected in parallel, each cell comprises an N + substrate, the back surface of the N + substrate is provided with a back metal layer, the front surface of the N + substrate is provided with an N-epitaxial region, and the front surface of the N-epitaxial region is sequentially provided with a gate oxide layer, polycrystalline silicon and a metallization layer; the middle of the front face of the N-epitaxial region is embedded with a P-type base region, the back face of the metallization layer is provided with a protruding portion, the protruding portion is embedded into the P-type base region, an N + region is arranged around the protruding portion, a P + region is arranged between the end face of the protruding portion and the P-type base region, and the front faces of the P-type base region and the N + region are both covered by a gate oxide layer. Compared with a PN junction structure, the invention has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; the conduction voltage drop is small, the energy consumption is low, the heat production is small, and the durability is strong; and a multi-cell parallel structure is adopted, so that the heat dissipation capability is greatly improved.
Description
Technical Field
The invention relates to the technical field of diodes, in particular to a diode chip and a manufacturing method thereof.
Background
With the development of semiconductor technology, new structure diodes such as JBS, MPS, TMPS, etc. have been developed in recent years, and the performance of the diodes has been improved. However, the above structures are basically extended based on the structure of the conventional PN junction or schottky junction, and the problems of large forward voltage drop, large reverse recovery time, poor high-temperature characteristics and poor reliability of the schottky junction structure, and the like of the PN junction structure cannot be completely avoided.
Chinese patent publication No. CN102709317A discloses a low-turn-on voltage diode, which includes an N + substrate, a metallized cathode on the back of the N + substrate, and an N-epitaxial layer on the front, wherein the surface of the N-epitaxial layer is a metallized anode, two sides of the top of the N-epitaxial layer are respectively provided with a P-type heavily doped region, the inner sides of the P-type heavily doped regions are respectively provided with an N-type heavily doped region, a deep P body region is also respectively arranged below the P-type heavily doped regions, and two deep P body regions and the N-epitaxial layer therebetween form a junction field effect transistor region. The diode is not suitable for the axial high-reliability packaging commonly adopted by the existing diode, and the heat dissipation capability is relatively poor.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a diode chip and a method for manufacturing the same.
The invention is realized by the following technical scheme.
The invention provides a diode chip which comprises a plurality of cells connected in parallel, wherein each cell comprises an N + substrate, the back surface of the N + substrate is provided with a back metal layer, the front surface of the N + substrate is provided with an N-epitaxial region, and the front surface of the N-epitaxial region is sequentially provided with a gate oxide layer, polycrystalline silicon and a metallization layer; the front middle part of the N-epitaxial region is embedded with a P-type base region, the back of the metallization layer is provided with a boss, the boss is embedded into the P-type base region, an N + region is arranged around the boss, a P + region is arranged between the end face of the boss and the P-type base region, and the front sides of the P-type base region and the N + region are both covered by a gate oxide layer.
The parallel connection specifically comprises that back metal layers of different cells are mutually and integrally connected to form a cathode region, metalized layers of different cells are mutually and integrally connected to form an anode region, N + substrates of different cells are mutually and integrally connected, N-epitaxial regions of different cells are mutually and integrally connected, grid oxide layers of different cells are mutually and integrally connected, and polycrystalline silicon of different cells are mutually and integrally connected.
The cells are any one of regular polygons, non-square rectangles, delta-shaped cells and strip-shaped cells.
And the anode region is also provided with a metal bump.
The metal salient points are formed by mutually and integrally connecting the metallization layers of different unit cells.
The metallization layer sequentially comprises a titanium layer, a nickel layer and a silver layer from the direction close to the N-epitaxial region to the direction far away from the N-epitaxial region.
The thicknesses of the titanium layer and the nickel layer in the metallization layer are 80 nm-100 nm of titanium and 80 nm-100 nm of nickel in sequence.
The thickness of the silver layer in the metallization layer is 35 um-40 um.
The silver layer forms a protruding portion of the metal bump.
Ohmic contact is improved by the multilayer arrangement and its thickness relationship, and current loss is minimized by the silver layer in connection with the external electrodes.
The number of the parallel connection of the unit cells is five thousand to twenty thousand.
The back metal layer sequentially comprises a titanium layer, a nickel layer and a silver layer from the back of the N + substrate to the outside.
The thickness of the titanium layer, the nickel layer and the silver layer of the back metal layer is 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 1400 nm-1500 nm of silver in sequence.
The N + substrate is a <100> crystal orientation N-type polishing sheet material.
The polysilicon is doped polysilicon. Making the polysilicon conductive.
The thickness of the polycrystalline silicon is 0.2-0.6 mu m.
The gate oxide layer is made of a high-K dielectric material.
The invention also provides a manufacturing method of the diode chip, which comprises the following steps:
step one, manufacturing an N + substrate, and growing an N-epitaxial region on the front surface of the substrate;
secondly, after a terminal area is manufactured on the N-epitaxial area, the active area is covered by thick field oxygen, and the active area is opened through etching;
thirdly, thermally oxidizing the front surface of the N-epitaxial region, and growing gate oxide to form a gate oxide layer;
step four, carrying out polycrystalline silicon precipitation and photoetching on the gate oxide layer, and etching a hole from the polycrystalline silicon to the N-epitaxial region through photoetching;
injecting a P-type base region and a drive-in well, then injecting an N + region and a drive-in well, and carrying out photoetching and drive-in well on the P + region;
and step six, preparing a metallization layer on the front side of the polycrystalline silicon, thinning the substrate on the back side of the N + substrate, and preparing a back metal layer after thinning.
In the first step, an N + substrate is manufactured by selecting a <100> crystal orientation N-type polishing sheet material.
And in the sixth step, the metallization layer is embedded into the hole etched in the fourth step and is in contact with the P-type base region.
The invention has the beneficial effects that:
the invention provides a new scheme for improving the contradiction relation between the conduction loss and the switching frequency in the diode from a brand new angle. Compared with a PN junction structure, the diode chip adopting the diode cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; moreover, the invention has small conduction voltage drop, low energy consumption, small heat production and strong durability; and a multi-cell parallel structure is adopted, so that the heat dissipation capability is greatly improved.
Drawings
FIG. 1 is a schematic diagram of the structure of a cell of the present invention.
Fig. 2 is a schematic structural diagram of a chip of the present invention.
Fig. 3 is an external structural diagram of the chip of the present invention.
Fig. 4 is a schematic diagram of a diode fabricated in accordance with the present invention.
In the figure: a 1-N + substrate; 2-back metal layer; a 3-N-epitaxial region; 4-a gate oxide layer; 5-polycrystalline silicon; 6-a metallization layer; 7-P type base region; an 8-P + region; a 9-N + region; 10-titanium layer; 11-a nickel layer; 12-a silver layer; 13-metal bumps; 14-an electrode column; 15-glass envelope; 16-electrode leads; 17-terminal region.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
Fig. 1-2 show the structure of the cell structure and the diode chip of the present invention:
the invention provides a diode chip which comprises a plurality of cells connected in parallel, wherein each cell comprises an N + substrate 1, the back surface of the N + substrate 1 is provided with a back metal layer 2, the front surface of the N + substrate 1 is provided with an N-epitaxial region 3, and the front surface of the N-epitaxial region 3 is sequentially provided with a gate oxide layer 4, polycrystalline silicon 5 and a metallization layer 6; the front middle part of the N-epitaxial region 3 is embedded with a P-type base region 7, the back of the metallization layer 6 is provided with a protruding part, the protruding part is embedded into the P-type base region 7, an N + region 9 is arranged around the protruding part, a P + region 8 is arranged between the end face of the protruding part and the P-type base region 7, and the front sides of the P-type base region 7 and the N + region 9 are both covered by a gate oxide layer 4.
The principle is as follows: the back metal layer 2 below the N + substrate 1 is used as a cathode of a diode electrode, the metallization layer 6 at the top of the polycrystalline silicon 5 is used as an anode of the diode, the N-epitaxial region 3 is provided with an N + region 9, a P + region 8 and a P-type base region 7 (also called as a P-base region), and the whole cell can be regarded as a planar gate power MOS cell structure similar to a gate short circuit and a drain short circuit. The minority carrier barrier is generated by an N + region 9, a P-type base region 78 and a barrier MOS channel formed by N-epitaxy, and the barrier MOS channel is formed by the difference between the diffusion of the P-type base region 7 and the diffusion of the N + region 9. For the barrier MOS, the N + region 9 may be regarded as the drain of the barrier MOS, and the diode cathode may be regarded as the source of the barrier MOS. When positive voltage is applied to the anode, positive voltage is applied to the drain gate of the barrier MOS, the channel of the P-type base region 7 below the gate oxide is inverted, the channel is opened, and current can pass through the channel. The threshold voltage of the barrier MOS is designed to be very small, which is much smaller than the general PN junction barrier voltage and smaller than the barrier formed by the contact of the metal and the semiconductor of the Schottky diode, so that very small conduction voltage drop can be obtained. In addition, the P + region 8 is formed on the P-type base region 7 in a diffusion mode, ohmic contact is improved, the use performance is improved, and the heat generation quantity is reduced.
The invention provides a new scheme for improving the contradiction relation between the conduction loss and the switching frequency in the diode from a brand new angle. Compared with a PN junction structure, the diode chip adopting the diode cellular structure has the advantages of lower conduction voltage, shorter reverse recovery time and the like; compared with a Schottky diode, the Schottky diode has the advantages of good high-temperature characteristic, small electric leakage, positive temperature coefficient and the like; moreover, the invention has small conduction voltage drop, low energy consumption, small heat production and strong durability; and a multi-cell parallel structure is adopted, so that the heat dissipation capability is greatly improved.
Specifically, the back metal layers 2 of different cells are integrally connected with each other to form a cathode region, the metallization layers 6 of different cells are integrally connected with each other to form an anode region, the N + substrates 1 of different cells are integrally connected with each other, the N-epitaxial regions 3 of different cells are integrally connected with each other, the gate oxide layers 4 of different cells are integrally connected with each other, and the polysilicon layers 5 of different cells are integrally connected with each other.
By the scheme, the N + region 9, the P-type base region 7 and the P + region 8 form a unit which works independently, the upper surface and the lower surface of the rest part are integrated (the upper surface refers to the metallization layer 6, the gate oxide layer 4 and the polycrystalline silicon 5, and the lower surface refers to the back metal layer 2, the N-epitaxial region 3 and the N + substrate 1), the heat diffusion area is increased, heat formed by current conduction can be diffused to any direction and is finally diffused from the metal layers on the two sides, and the reliability of the product is improved; in addition, when one cell is broken and damaged, other cells can work normally without influencing the functionality of the diode chip; when the diode is manufactured, the two sides of the chip can be sintered on the lead posts, namely, a small radiator is added on the two sides of the chip, and the double-side heat dissipation of the chip is realized.
The cells are any one of regular polygons, non-square rectangles, delta-shaped cells and strip-shaped cells. The cell is convenient to densely spread, the cells on the chip are uniformly distributed, and the heat generation and the heat dissipation are uniform.
As shown in fig. 3: the anode region is also provided with a metal bump 13. The combined area of the metallization layers 6 of all the cells is an active area of the chip, a terminal area 17 is arranged around the active area, the metal salient points 13 are higher than the terminal area 17 and the passivation area of the chip, when electrodes are welded, solder is arranged at the end parts of the metal salient points 13, the solder does not flow into the table top of the chip after being melted, and redundant solder can be absorbed by the space around the metal salient points 13, so that the problems of passivation material damage, short circuit and the like caused by contact between the solder and the passivation material in the double-sided sintering process can be effectively solved, and the reliability of products is improved.
The metal bumps 13 are formed by integrally connecting the metallization layers 6 of different cells. The voltage of the anode is directly transmitted to the inner working area of the unit cell through the metal salient point 13 without blocking, and the ohmic contact is improved.
The metallization layer 6 sequentially comprises a titanium layer 10, a nickel layer 11 and a silver layer 12 from the direction close to the N-epitaxial region 3 to the direction far away from the N-epitaxial region 3. The multilayer metal structure realizes better ohmic contact and optimizes the on-resistance of the product; the back metal layer 2 can also adopt the same structure and adopt double-sided silver, so that the chip can directly adopt a double-sided sintering packaging process.
The thicknesses of the titanium layer 10 and the nickel layer 11 in the metallization layer 6 are 80 nm-100 nm of titanium and 80 nm-100 nm of nickel in sequence.
The thickness of the silver layer 12 in the metallization layer 6 is 35 um-40 um.
The silver layer 12 constitutes a projection of the metal bump 13.
By the multilayer arrangement and its thickness relationship, the ohmic contact is improved and the current loss is minimized by the silver layer 12 in connection with the external electrodes.
The number of the parallel connection of the unit cells is five thousand to twenty thousand.
The back metal layer 2 sequentially comprises a titanium layer 10, a nickel layer 11 and a silver layer 12 from the back of the N + substrate 1 to the outside. The multilayer metal structure realizes better ohmic contact and optimizes the on-resistance of the product; the outermost layer of the metallization layer 6 can also adopt silver, and double-sided silver is adopted, so that the chip can directly adopt a double-sided sintering packaging process.
The thickness of the titanium layer 10, the nickel layer 11 and the silver layer 12 of the back metal layer 2 is 80 nm-100 nm of titanium, 80 nm-100 nm of nickel and 1400 nm-1500 nm of silver in sequence.
The N + substrate 1 is a <100> crystal orientation N-type polishing sheet material. The 100-crystal-orientation silicon material has low interface state density and is more suitable for the cellular structure of the invention.
The polysilicon 5 is doped polysilicon 5. Making the polysilicon 5 conductive.
The thickness of the polycrystalline silicon 5 is 0.2-0.6 mu m.
The gate oxide layer 4 is made of a high-K dielectric material. The high-K dielectric material comprises silicon dioxide, silicon nitride, hafnium dioxide, aluminum oxide and the like, and has good insulativity and reliable resistance.
The invention also provides a manufacturing method of the diode chip, which comprises the following steps:
step one, manufacturing an N + substrate 1, and growing an N-epitaxial region 3 on the front surface of the substrate;
step two, after a terminal region 17 is firstly manufactured on the N-epitaxial region 3, the active region is covered by thick field oxygen at the moment, and the active region is opened through etching;
thirdly, thermally oxidizing the front surface of the N-epitaxial region 3, and growing gate oxide to form a gate oxide layer 4;
depositing and photoetching the polycrystalline silicon 5 on the gate oxide layer 4, etching a hole through photoetching, and etching the polycrystalline silicon 5 into the N-epitaxial region 3;
step five, injecting a P-type base region 7, pushing a well, then injecting an N + region 9, pushing the well, and carrying out photoetching and pushing the well on a P + region 8;
and step six, preparing a metallization layer 6 on the front side of the polycrystalline silicon 5, thinning the substrate on the back side of the N + substrate 1, and preparing a back metal layer 2 after thinning.
In the first step, an N + substrate 1 is manufactured by selecting a <100> crystal orientation N-type polishing sheet material.
In the sixth step, the metallization layer 6 is embedded into the hole etched in the fourth step and is in contact with the P-type base region 7.
In the fifth step, photoetching and well pushing are carried out on the P + region 8, so that ohmic contact can be improved.
Fig. 4 is a schematic structural diagram of the packaged diode of the present invention:
the invention also provides a packaged diode manufactured by adopting the diode chip, which comprises a chip and a glass shell 15, wherein the two ends of the chip are welded with electrode columns 14, the electrode columns 14 and the chip are both encapsulated in the glass shell 15, one end of each electrode column 14, which is far away from the chip, is welded with an electrode lead 16, and the electrode lead 16 extends out of the glass shell 15.
The glass envelope 15 is passivated glass.
Claims (10)
1. A diode chip, characterized by: the cell structure comprises a plurality of cells which are connected in parallel, wherein each cell comprises an N + substrate (1), a back metal layer (2) is arranged on the back surface of each N + substrate (1), an N-epitaxial region (3) is arranged on the front surface of each N + substrate (1), and a gate oxide layer (4), polycrystalline silicon (5) and a metallization layer (6) are sequentially arranged on the front surface of each N-epitaxial region (3); the front middle part of the N-epitaxial region (3) is embedded with a P-type base region (7), the back of the metallization layer (6) is provided with a protruding part, the protruding part is embedded into the P-type base region (7), an N + region (9) is arranged around the protruding part, a P + region (8) is arranged between the end face of the protruding part and the P-type base region (7), and the front sides of the P-type base region (7) and the N + region (9) are covered by a gate oxide layer (4).
2. The diode chip of claim 1, wherein: the parallel connection specifically comprises that back metal layers (2) of different cells are mutually and integrally connected to form a cathode region, metallized layers (6) of different cells are mutually and integrally connected to form an anode region, N + substrates (1) of different cells are mutually and integrally connected, N-epitaxial regions (3) of different cells are mutually and integrally connected, grid oxide layers (4) of different cells are mutually and integrally connected, and polycrystalline silicon (5) of different cells are mutually and integrally connected.
3. The diode chip of claim 2, wherein: the cells are any one of regular polygons, non-square rectangles, delta-shaped cells and strip-shaped cells.
4. The diode chip of claim 2, wherein: and a metal bump (13) is also arranged on the anode region.
5. The diode chip of claim 4, wherein: the metal bumps (13) are formed by integrally connecting the metallization layers (6) of different cells.
6. The diode chip of claim 1 or 5, wherein: the metallization layer (6) sequentially comprises a titanium layer (10), a nickel layer (11) and a silver layer (12) from the direction close to the N-epitaxial region (3) to the direction far away from the N-epitaxial region (3).
7. The diode chip of claim 6, wherein: the thickness of the titanium layer (10) and the nickel layer (11) in the metallization layer (6) is 80 nm-100 nm of titanium and 80 nm-100 nm of nickel in sequence.
8. The diode chip of claim 7, wherein: the thickness of the silver layer (12) in the metallization layer (6) is 35-40 um, and a protruding part of the metal bump (13) is formed.
9. The method for manufacturing a diode chip as claimed in any one of claims 1 to 8, wherein: comprises the following steps of (a) carrying out,
step one, manufacturing an N + substrate (1), and growing an N-epitaxial region (3) on the front surface of the substrate;
step two, after a terminal region (17) is manufactured on the N-epitaxial region (3), the active region is covered by thick field oxygen at the moment, and the active region is opened through etching;
thirdly, thermally oxidizing the front surface of the N-epitaxial region (3), growing gate oxide and forming a gate oxide layer (4);
depositing and photoetching polysilicon (5) on the gate oxide layer (4), etching a hole through photoetching, and etching the polysilicon (5) into the N-epitaxial region (3);
step five, injecting a P-type base region (7), pushing a well, then injecting an N + region (9), pushing the well, and carrying out photoetching and pushing the well on a P + region (8);
and sixthly, preparing a metallization layer (6) on the front surface of the polycrystalline silicon (5), thinning the substrate on the back surface of the N + substrate (1), and preparing a back metal layer (2) after thinning.
10. The method for manufacturing a diode chip as claimed in claim 9, wherein: in the first step, an N + substrate (1) is manufactured by selecting a <100> crystal orientation N-type polishing sheet material.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN101859703A (en) * | 2010-05-14 | 2010-10-13 | 深圳市芯威科技有限公司 | Low turn-on voltage diode and preparation method thereof |
| CN104576361A (en) * | 2013-10-23 | 2015-04-29 | 无锡华润上华半导体有限公司 | Preparation method of power diode |
| CN108155225A (en) * | 2017-12-27 | 2018-06-12 | 电子科技大学 | Constant current device and its manufacturing method |
| CN110416189A (en) * | 2018-04-27 | 2019-11-05 | 瑞昱半导体股份有限公司 | The integrated circuit inductor device and its manufacturing method of high quality factor |
| CN110854186A (en) * | 2019-12-09 | 2020-02-28 | 安徽瑞迪微电子有限公司 | IGBT device structure and preparation method thereof |
-
2021
- 2021-05-06 CN CN202110491416.8A patent/CN113270502A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN101859703A (en) * | 2010-05-14 | 2010-10-13 | 深圳市芯威科技有限公司 | Low turn-on voltage diode and preparation method thereof |
| CN104576361A (en) * | 2013-10-23 | 2015-04-29 | 无锡华润上华半导体有限公司 | Preparation method of power diode |
| CN108155225A (en) * | 2017-12-27 | 2018-06-12 | 电子科技大学 | Constant current device and its manufacturing method |
| CN110416189A (en) * | 2018-04-27 | 2019-11-05 | 瑞昱半导体股份有限公司 | The integrated circuit inductor device and its manufacturing method of high quality factor |
| CN110854186A (en) * | 2019-12-09 | 2020-02-28 | 安徽瑞迪微电子有限公司 | IGBT device structure and preparation method thereof |
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