CN113257892A - 一种可抑制寄生器件的半导体器件 - Google Patents

一种可抑制寄生器件的半导体器件 Download PDF

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CN113257892A
CN113257892A CN202110472540.XA CN202110472540A CN113257892A CN 113257892 A CN113257892 A CN 113257892A CN 202110472540 A CN202110472540 A CN 202110472540A CN 113257892 A CN113257892 A CN 113257892A
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艾瑞克·布劳恩
张志其
柳志亨
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明提出了一种半导体器件，所述半导体器件包括第一P型区域、包围第一P型区域的N型区域、包围N型区域的第二P型区域。所述第一P型区域耦接至第一电压，所述N型区域耦接至第二电压，并且所述N型区域具有肖特基接触区，所述肖特基接触区通过金属接触耦接至第二电压。利用本发明所揭示的半导体器件，可以有效抑制所述半导体器件在部分工作条件下的产生的不必要的空穴注入，防止空穴注入引起的复合电流激活所述半导体器件的寄生PNP晶体管。

Description

一种可抑制寄生器件的半导体器件
技术领域
本发明涉及半导体器件，更具体地说，本发明涉及抑制半导体器件中的寄生器件的方法。
背景技术
金属氧化物半导体器件通常制作在集成电路芯片中，用于控制感性的负载。金属氧化物半导体器件的半导体结构常常会产生一些寄生效应。在适当的偏置条件下，这些寄生效应将被触发，可能会影响半导体器件的性能，或使半导体器件彻底失效。
图1a示出了现有的应用于开关电路的典型的高边N型DMOS(双重扩散金属氧化物半导体)器件M1。图1b示出了图1a中的N型DMOS器件M1的剖面结构图。如图1b所示，P型体区107和第一P型掩埋层105-1被N型区域102和103所包围，而N型区域102和103又进一步被P型区域106、105-2、104和101所包围。并且，漏区109和N型区域103分别通过电极接触区110和111连接至开关电路的输入电压Vin，源区114和体接触区113连接至开关电路的开关电压Vsw，以及P阱接触区112连接至参考地电压GND。在开关电路的应用中，当N型DMOS器件M1的体二极管D0的正向导通时，开关电压Vsw大于输入电压Vin。在这种情况下，相对于外围的N型区域102和103，内圈的P型体区107和P型掩埋层105-1正向偏置，空穴从体接触区113(Vsw)迁移至N型区域102和103(Vin)，并最终为P型区域106、105-2、104和101(GND)所收集。这样一来，图1a和图1b所示的寄生的PNP管Q1(发射极＝内圈的P型区域107和105-1，基极＝外围的N型区域102和103，集电极＝最外围的P型区域106、105-2、104和101)就被激活了。寄生PNP管Q1被激活将带来半导体器件正常开关和可靠性方面的问题：1)PNP管Q1将造成相当大的功率损耗Pdissipate＝Icollection×Vce，其中Icollection表征流过PNP管Q1的电流，Vce表征寄生PNP管Q1的集电极至发射极之间的压差，并且功率损耗将引起芯片局部非匀性的温度梯度，由此可能引发器件和电路的失效；2)集电极的电流将导致集电极的电位全部或局部地被抬高V＝Icollector×Rcollector，Rcollector表示集电极各部位的电阻，集电极各部位被抬高的电压幅值取决于该部分的电阻，这个电压将通过容性位移电流和/或寄生的NPN管引起集电极周边的N型区域(被集电极包围或包围住集电极的)构成的器件的闩锁效应。
因此，需要抑制寄生PNP管Q1，防止其导通。
发明内容
本发明的目的是为了抑制半导体器件中的不必要的空穴注入，防止其激活寄生的PNP管，进而导致的半导体器件的失效等非正常工作状态。
根据本发明一实施例的半导体器件，包括：P型体区，耦接至第一电压；位于P型体区下方的第一P型掩埋层；包围P型体区和第一P型掩埋层的N型区域；包围N型区域的P型区域；以及P型保护环，嵌入至N型区域，将N型区域分为第一部分和第二部分，其中所述第一部分位于P型体区和P型保护环之间，所述第二部分位于P型保护环和P型区域之间；其中，所述N型区域的第二部分具有肖特基接触区，所述肖特基接触区通过金属接触耦接至第二电压。
根据本发明一实施例的半导体器件，包括：第一P型区域，耦接至第一电压；包围第一P型区域的N型区域，耦接至第二电压；以及包围N型区域的第二P型区域；其中所述N型区域具有肖特基接触区，所述肖特基接触区通过金属接触耦接至第二电压。
根据本发明一实施例的半导体器件，包括：第一P型区域，耦接至第一电压；包围第一P型区域的N型区域，耦接至第二电压；包围N型区域的第二P型区域；以及P型保护环，嵌入至N型区域，将N型区域分成第一部分和第二部分，其中所述第一部分位于第一P型体区和P型保护环之间，所述第二部分位于P型保护环和第二P型区域之间；其中所述N型区域的第二部分具有第一肖特基接触区，通过金属接触耦接至第二电压。
附图说明
为了更好的理解本发明，将根据以下附图对本发明进行详细描述：
图1a示出了现有的应用于开关电路的典型的高边N型DMOS(双重扩散金属氧化物半导体)器件M1；
图1b示出了图1a中的N型DMOS器件M1的结构的横切面；
图2示出了根据本发明一实施例的半导体器件200的剖面结构图；
图3示出了根据本发明一实施例的半导体器件300的剖面结构图；
图4示出了根据本发明一实施例的半导体器件400的剖面结构图；
图5示出了根据本发明一实施例的半导体器件500的剖面结构图；
图6示出了根据本发明一实施例的半导体器件600的剖面结构图；
图7示出了根据本发明一实施例的半导体器件700的剖面结构图；
图8示出了根据本发明一实施例的半导体器件800的剖面结构图；
图9示出了根据本发明一实施例的半导体器件900的剖面结构图。
具体实施方式
下面参照附图充分描述本发明的示范实施例。在下面对本发明的详细描述中，为了更好的理解本发明，描述了大量的细节。然而，本领域技术人员将理解，没有这些具体细节，本发明同样可以实施。本发明可以以许多不同形式体现，不应理解为局限于这里阐述的示范实施方式。此外，图中显示的区域实质上是示意性的，它们的形状不意图限制本发明的范围。还应理解，附图不是按比例画的，为了清晰，层和区域的尺寸可被放大。
图2示出了根据本发明一实施例的半导体器件200的剖面结构图。所述半导体器件200可用于开关电路作为功率开关。如图2所示，半导体器件200包括：P型衬底101、N型隔离层102、N型隔离区域103、P型外延层104、P型掩埋层105-1和105-2、P型体区107、P阱106，N+注入区(源区)114以及漏区109。源区114和体接触区113的电位通过金属接触MT2被连至开关电压Vsw(也称作第一电压)。漏区109通过N+接触区110和金属接触MT4被连至输入电压Vin(也称作第二电压)。N型隔离层102和N型隔离区103通过金属接触MT1连至输入电压Vin。P型衬底101，P型外延层104、第二P型掩埋层105-2和P阱106被连至参考地电压GND(也称作第三电压)。
从图2可以看出，P型体区107和第一P型掩埋层105-1形成了耦接至开关电压Vsw的第一P型区域，N型隔离层102和N型隔离区103形成了耦接至输入电压Vin的N型区域，P型衬底101、P型外延层104、第二P型掩埋层105-2和P阱106形成了耦接至参考地电压GND的第二P型区域。所述第一P型区域、N型区域和第二P型区域构成了如图2所示的寄生PNP管。当开关电压Vsw在某些条件下高于输入电压Vin时，寄生PNP管Q1被激活。在图2的实施例中，为了抑制PNP管Q1的导通，肖特基接触区201代替了图1b中的欧姆接触区111，在N型隔离区103中形成了肖特基二极管D1，该肖特基二极管D1以金属接触MT1为阳极，以金属接触MT1下方的N型区域为阴极。应当理解，肖特基接触区201可以是与金属区相接触的任何具有适当离子浓度的半导体区域。图2中虚线框内的区域201仅作示意性说明，并不表示肖特基接触区的实际区域面积。当开关电压Vsw超过输入电压Vin时，肖特基二极管D1迫使空穴注入在基极引起的复合电流对基极区域充电，使电压升高，从而对发射极-基极结去偏置，抑制进一步的空穴注入，并且避免空穴电流被周边的P型区域收集。
在部分实施例中，P型外延层104并不是必需的，可以被P型衬底101所取代。
图3示出了根据本发明一实施例的半导体器件300的剖面结构图。如图3所示，N型隔离区103进一步包括P型接触区311，位于N型隔离区103的表层，其中，P型接触区311的部分区域位于金属接触MT1的下方。P型接触区311可以减小反向漏电流，防止肖特基结被击穿。
在图3实施例中，P型接触区311的部分区域位于金属接触MT1的下方。在其他实施例中，P型接触区311的全部区域位于金属接触MT1的下方。从P型接触区311的上方俯视来看，P型接触区311可以是任何形状，例如，网格状的，圆形的。本领域技术人员可根据需要决定P型接触区311的离子浓度。
在稳定工作(直流偏置)时，图2和图3中的实施例可以抑制寄生PNP管Q1的基极和集电极的电流。但是，在瞬态条件下，与寄生PNP管Q1的基极结电容充放电相关的附加基极位移电流可能会在瞬时导通寄生PNP管Q1，直至有足够的基极复合电流流过以对结电容充电，使所述半导体器件再次回到稳定工作偏置点。
图4示出了根据本发明一实施例的半导体器件400的剖面结构图。与半导体器件200相比，半导体器件400进一步包括P型保护环，将图2所示的N型隔离区103分隔成第一部分403和第二部分404。如图4所示，N型隔离区103的第一部分403位于第一P型区域和P型保护环之间，而不在第一P型区域和P型离子注入保护环之间的其余部分就构成了第二部分404。在图4中，P型保护环包括P阱406和第三P型掩埋层405。所述N型隔离区103的第一部分403包括位于金属接触MT6之下的接触区408，第二部分404包括位于金属接触MT1之下的肖特基接触201，而金属接触MT1则接至输入电压Vin。
在部分实施例中，P型保护环可能仅包括P阱406，也就是说，第三P型掩埋层405被P阱所替代。在图4实施例中，P型保护环的电位通过接触区407、408及金属接触MT5、MT6被接至N型隔离区的第一部分403。
在图4中，加入P型保护环是为了减小前面提及的与基极结电容充放电相关的基极位移电流。P型保护环就像一个假集电极，将部分原本会进入周边的第二P型区域的位移电流分流至基极，从而加速寄生PNP管Q1的基极结电容的充电，以减少回到稳定工作状态的时间。
图5示出了根据本发明一实施例的半导体器件500的剖面结构图。在图5中，N型隔离区的第一部分403包括位于金属接触MT6下方的第二肖特基接触501；以及N型隔离区的第二部分404包括肖特基接触201。所述第二肖特基接触501与金属接触MT6构成了肖特基二极管D2，进一步抑制了寄生PNP管Q1的导通。
图6示出了根据本发明一实施例的半导体器件600的剖面结构图。在图6中，N型隔离区的第二部分404进一步包括P型接触区311，位于N型隔离区的第二部分404的表层，其中P型接触区311的部分区域位于金属接触MT1的下方。在部分实施例中，P型接触区311的全部区域位于金属接触MT1的下方。
图7示出了根据本发明一实施例的半导体器件700的剖面结构图。与图6所示的半导体器件600相比，图7中的N型隔离区的第一部分403包括位于金属接触MT6下方的第二肖特基接触701，其中，所述第一部分403进一步包括位于N型隔离区表层的P型接触区711，并且P型接触区711的部分区域位于金属接触MT6下方。在部分实施例中，P型接触区711可被省略。
图8示出了根据本发明一实施例的半导体器件800的剖面结构图。在图8中，肖特基接触区201的金属接触MT1延伸至N型隔离区的第一部分403，第二部分404及P型保护环，其中，所述P型保护环包括位于金属接触MT1下方的P型接触区407。
图9示出了根据本发明一实施例的半导体器件900的剖面结构图。在图9中，P型保护环的P型接触区901延伸至N型隔离区的第一部分403和第二部分404，以提升寄生的肖特基二极管D1和D2的击穿电压。
在本发明部分实施例中，P型掩埋层并不是必需的。当不需要P型掩埋层时，其位置可被上方的半导体区域或其他具有恰当的半导体浓度的区域所取代。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (20)

1.一种半导体器件，包括：
P型体区，耦接至第一电压；
位于P型体区下方的第一P型掩埋层；
包围P型体区和第一P型掩埋层的N型区域；
包围N型区域的P型区域；以及
P型保护环，嵌入至N型区域，将N型区域分为第一部分和第二部分，其中所述第一部分位于P型体区和P型保护环之间，所述第二部分位于P型保护环和P型区域之间；其中，
所述N型区域的第二部分具有肖特基接触区，所述肖特基接触区通过金属接触耦接至第二电压。
2.如权利要求1所述的半导体器件，其中所述P型区域包括：
P型衬底；
位于P型衬底之上的第二P型掩埋层；以及
位于第二P型掩埋层之上的P阱。
3.如权利要求2所述的半导体器件，其中所述P型区域还包括位于第二P型掩埋层和P型衬底之间的P型外延层。
4.如权利要求1所述的半导体器件，还包括位于N型区域的第二部分的上表层的P型接触区，其中所述位于N型区域的第二部分的上表层的P型接触区的部分区域位于N型区域的第二部分的金属接触下方。
5.一种半导体器件，包括：
第一P型区域，耦接至第一电压；
包围第一P型区域的N型区域，耦接至第二电压；以及
包围N型区域的第二P型区域；其中
所述N型区域具有肖特基接触区，所述肖特基接触区通过金属接触耦接至第二电压。
6.如权利要求5所述的半导体器件，其中所述第一P型区域包括P型体区，其中所述P型体区位于半导体器件的漏极区和N型区域之间。
7.如权利要求6所述的半导体器件，其中所述第一P型区域还包括P型掩埋层，所述P型掩埋层位于P型体区下方。
8.如权利要求5所述的半导体器件，其中，所述第二P型区域包括P型衬底和P阱。
9.如权利要求5所述的半导体器件，其中所述N型区域包括位于P型衬底上方的N型隔离层和位于N型隔离层上方的N型隔离区，其中所述N型隔离区位于第一P型区域和第二P型区域之间。
10.如权利要求5所述的半导体器件，其中所述N型区域还包括位于N型区域的上表层的P型接触区，其中，所述P型接触区的部分区域位于所述N型区域的金属接触的下方。
11.一种半导体器件，包括：
第一P型区域，耦接至第一电压；
包围第一P型区域的N型区域，耦接至第二电压；
包围N型区域的第二P型区域；以及
P型保护环，嵌入至N型区域，将N型区域分成第一部分和第二部分，其中所述第一部分位于第一P型体区和P型保护环之间，所述第二部分位于P型保护环和第二P型区域之间；其中
所述N型区域的第二部分具有第一肖特基接触区，通过金属接触耦接至第二电压。
12.如权利要求11所述的半导体器件，其中所述P型保护环的金属接触耦接至N型区域的第一部分的金属接触。
13.如权利要求11所述的半导体器件，其中所述N型区域的第二部分还包括位于N型区域的第二部分表层的P型接触区，其中所述位于N型区域的第二部分表层的P型接触区的部分区域位于N型区域的第二部分的金属接触的下方。
14.如权利要求11所述的半导体器件，其中所述N型区域的第一部分包括位于N型区域的第一部分的金属接触下方的第二肖特基接触区。
15.如权利要求14所述的半导体器件，其中所述N型区域的第一部分还包括位于N型区域的第一部分表层的P型接触区，其中所述位于N型区域的第一部分表层的P型接触区的部分区域位于N型区域的第一部分的金属接触的下方。
16.如权利要求14所述的半导体器件，其中所述N型区域的第二部分还包括位于N型区域的第二部分表层的P型接触区，其中所述位于N型区域的第二部分表层的P型接触区的部分区域位于N型区域的第二部分的金属接触的下方。
17.如权利要求11所述的半导体器件，其中所述第一肖特基接触区的金属接触延伸至N型区域的第一部分和第二部分以及P型保护环上方。
18.如权利要求17所述的半导体器件，其中所述P型保护环包括位于P型保护环的金属接触下方的P型接触区。
19.如权利要求18所述的半导体器件，其中所述P型保护环的P型接触区延伸至N型区域的第二部分。
20.如权利要求18所述的半导体器件，其中：
N型区域的第一部分具有位于N型区域的第一部分的金属接触下方的第二肖特基接触区；以及
所述P型保护环的P型接触区延伸至N型区域的第一部分和第二部分。
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