CN113257808B - 一种芯片衬底外延片 - Google Patents

一种芯片衬底外延片 Download PDF

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CN113257808B
CN113257808B CN202110532783.8A CN202110532783A CN113257808B CN 113257808 B CN113257808 B CN 113257808B CN 202110532783 A CN202110532783 A CN 202110532783A CN 113257808 B CN113257808 B CN 113257808B
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黄永锋
殷玉喆
刘伟
何力
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Chengdu Zhixin Electronic Technology Co ltd
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Abstract

本发明公开了一种芯片衬底外延片,对芯片无源电路衬底外延片进行定制。电阻采用Iso/Mesa电阻,电阻区下方采用低掺杂浓度或未掺杂的衬底,取消衬底外延片上的沟道层,由高阻的势垒层或缓冲层纵向填充该沟道层。电感采用空气桥电感。电容采用支撑柱支撑电容。本发明芯片电阻具有更高的方块电阻,能实现更精密的Iso/Mesa电阻值控制,能够实现更少的漏电、更好的隔离效果和更好的噪声特性;芯片电容和电感具备更高的单位容值和电感值,更高的Q值,更小的电磁泄露和噪声;在此新型衬底外延片上制作的芯片具备更高的输出功率和效率,更高的可靠性。芯片面积小,降低了芯片成本。

Description

一种芯片衬底外延片
技术领域
本发明涉及射频微波晶体管领域,是一种针对芯片不同功能区域进行衬底外延片优化,尤其是无源区性能优化定制衬底外延片的技术。
背景技术
现有技术设计生产的射频微波芯片是在三五族化合物半导体上实现,例如GaAs、GaN、InP、SiC等,或者硅基化合物半导体上实现的,例如体硅CMOS和SOI衬底等。现有半导体芯片衬底,在衬底及外延片表面是各向同性的,即不同衬底表面上各个位置上的垂直结构和电性能是相同的。例如GaAs、GaN、InP、SiC等衬底,还有硅基半导体如体硅CMOS和SOI衬底等均是如此,这样做的原因主要是由于成本方面的考虑。在衬底进行MOCVD或MBE外延生长的时候,把多个衬底放入反应炉中一起生长,由于生长气体的化学反应产生的外延生长在反应炉内的各个衬底表面基本相同,因此生长出的外延片结构也是相同的。
射频微波芯片采用的衬底结构主要有两种:pHEMT和HBT,现有技术制作的各向同性衬底外延片结构如图1、2所示,其中图1所示为GaAs pHEMT衬底结构,图2所示为GaAs HBT衬底结构。
现有衬底外延技术的结构特征是:
(1)在衬底之上依次通过外延工艺生长多层材料;
(2)衬底水平方向各处的垂直外延结构相同。
现有衬底外延技术存在的问题是:
随着5G、Wifi6、CV2X、NBIoT等新型通信技术的发展,对射频微波芯片性能要求越来越高,当前的衬底外延片技术存在如下不足,难以针对芯片上无源电路不同功能需要,优化定制水平方向非均匀衬底外延片的技术。典型例如:
(1)芯片电阻难以优化
现有水平方向均匀的衬底外延片,隔离区Mesa厚度和离子注入浓度都要根据有源区的需求重点优化,不会专门针对Mesa电阻做优化。
(2)芯片电感难以优化
芯片上的电感用于匹配电路。困扰芯片电感的一个问题是Q值太低,只有10~20之间,影响匹配电路效果。如果针对芯片电感优化,希望电感下面的衬底外延结构是空心的,或者相对介电常数接近1(空气)。考虑到其他有源电路的需求,在各向同性的衬底外延片上,难以专门针对芯片电感的需求做优化。
(3)芯片电容难以优化
现有技术制作的电容,由于下方的衬底外延片没有优化,存在介质漏电通道到衬底外延片背面的金属层,导致芯片上电容失效。还会造成电容密度低、Q值低等问题,造成芯片上匹配电路性能恶化,芯片输出功率和效率下降。
发明内容
本发明的发明目的在于:针对上述存在的问题,提供一种芯片衬底外延片,根据芯片上无源电路不同功能需要,优化定制水平方向非均匀衬底外延片,以实现芯片的高Q值、抗干扰和高性能。
本发明采用的技术方案如下:
一种芯片衬底外延片,芯片衬底外延片为水平方向非均匀衬底外延结构,无源电路区和有源电路区的衬底外延片结构不同,无源电路包括电阻、电感和电容。
进一步的,所述电阻为Iso/Mesa电阻,电阻区下方采用低掺杂浓度或未掺杂的衬底,取消衬底外延片上的沟道层,由高阻的势垒层或缓冲层纵向填充该沟道层。
进一步的,电阻区下方衬底外延片的制作工艺包括:
降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度;
在制作衬底外延片时,取消沟道层;
在制作衬底外延片时,由高阻的势垒层或缓冲层纵向填充沟道层。
进一步的,所述电感为空气桥电感。
进一步的,电感区下方衬底外延片的制作工艺包括:
生长衬底外延片时,在电感区进行选择性生长,只保留若干用于支撑电感传输线的支撑柱;
在电感区的支撑柱之间覆盖光阻层;
在电感区的支撑柱和所述光阻层之上制作电感传输线;
刻蚀掉所述光阻层。
进一步的,所述生长衬底外延片时,在电感区进行选择性生长,只保留若干用于支撑电感传输线的支撑柱,包括:
生长衬底外延片时,取消电感下方衬底外延片的沟道层,由高阻的势垒层或缓冲层纵向填充沟道层;在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑电感传输线的支撑柱。
进一步的,所述电容为支撑柱支撑电容,电容区的支撑柱为空气隔离。
进一步的,电容区下方衬底外延片的制作工艺包括:
生长衬底外延片时,在电容区进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱;
在电容区的支撑柱之间覆盖光阻层;
在电感区的支撑柱和光阻层之上制作M1/M2电容电极;
刻蚀掉光阻层。
进一步的,所述生长衬底外延片时,在电容区进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱,包括:
生长衬底外延片时,取消电容下方衬底外延片的沟道层,由高阻的势垒层或缓冲层纵向填充沟道层;在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱。
综上所述,由于采用了上述技术方案,本发明的有益效果是:
1、本发明的芯片衬底外延片,电阻具有更高的方块电阻,能实现更精密的Iso/Mesa电阻值控制,能够实现更少的漏电和更好的隔离效果。
2、本发明的芯片衬底外延片,电感的设计使得芯片具备更高的Q值,且因Q值提高,大大减小了电磁干扰、寄生参数恶化等问题,提升芯片上匹配电路性能,提高芯片输出功率和效率。
3、本发明的芯片衬底外延片,电容的设计使得芯片具备更高的Q值,和更高的可靠性。
4、本发明的芯片衬底外延片,电阻、电感和电容均设计为更小的面积,从而整体上减小了芯片的面积,降低了芯片的成本。具备高Q值、抗干扰、高性能等优点,既可以在三五族化合物半导体上实现,例如GaAs、GaN、InP、SiC等,也可以在硅基化合物半导体上实现,例如体硅CMOS和SOI衬底等。可应用于5G、Wifi6、CV2X、NBIoT新型通信系统等领域,具备广阔的应用前景。
附图说明
本发明将通过例子并参照附图的方式说明,其中:
图1是现有技术中GaAs pHEMT衬底结构示意图。
图2是现有技术中GaAs HBT衬底结构示意图。
图3是本发明GaAs pHEMT衬底结构示意图。
图4是本发明GaAs HBT衬底结构示意图。
具体实施方式
本说明书中公开的所有特征,或公开的所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以以任何方式组合。
本说明书(包括任何附加权利要求、摘要)中公开的任一特征,除非特别叙述,均可被其他等效或具有类似目的的替代特征加以替换。即,除非特别叙述,每个特征只是一系列等效或类似特征中的一个例子而已。
本发明中的芯片衬底外延片,根据无源电路不同功能需要,优化定制芯片上水平方向非均匀衬底外延片,芯片上无源电路主要包括电阻、电感和电容。
芯片的电阻主要有两种:薄膜电阻和Iso/Mesa电阻。薄膜电阻是在已有衬底外延片上再生长薄膜电阻层以形成芯片上电阻的技术,不涉及衬底外延片的优化;Iso/Mesa电阻是在已有衬底外延片上通过离子注入等方法控制表面电阻率而形成的芯片电阻,是可以通过衬底外延片来进行优化的。现有技术制作的薄膜电阻精度高但方块电阻低,50欧姆左右;现有技术制作的Iso/Mesa电阻是利用衬底外延片的高阻层,典型如Mesa层来制作电阻,优点是方块电阻高,300Ω以上。
现有技术设计的电阻的特征:
1)制作的均匀衬底外延片,在水平方向上各处的Mesa层方块电阻相同。典型如:用于开关用途的Dmode pHEMT芯片电路,子栅极之间需要1MΩ以上电阻隔离,通常采用Mesa电阻实现。
2)由于现有技术制作的衬底外延片在水平方向上各向同性,因此在衬底外延片制作过程中,不需要光罩mask,不需要有图形定义的通过和遮挡的掩膜版,在衬底外延片上均匀生长即可。
现有技术没有针对芯片上电路的不同功能应用优化。具体而言,现有水平方向均匀的衬底外延片,隔离区Mesa厚度和离子注入浓度都要根据有源区的需求重点优化,不会专门针对Mesa电阻做优化,300Ω就是针对有源区优化的结果。现有设计设计的电阻存在以下问题:(1)现有技术设计的隔离电阻,由于Mesa电阻的方块电阻只有300Ω左右,要实现1MΩ的隔离电阻,长度要1mm左右,占用芯片面积大,成本高。(2)由于占用面积大,会和其他层金属上下交叉,会造成电磁干扰等问题。(3)阻值控制精度差,一致性不好,片上一致性和阻值控制误差通常在15%以上,影响芯片成品率。(4)现有技术制作的电阻,由于下面有衬底外延层,没有经过优化,存在漏电、寄生电容等干扰,且噪声较高。
现有设计中芯片上电感是在芯片上做环状传输绕圈,然后中心抽头引出形成的。现有技术制作的电感下方的衬底外延片没有针对性优化,是在衬底外延片的高阻层Iso/Mesa层上利用M1/M2构成的传输线制作电感。
现有技术设计的电感没有针对芯片上电感的性能要求进行优化,存在以下问题:(1)现有技术制作的电感,由于下方的衬底外延片没有优化,相对介电常数较高,在常规电感值时电感面积很大。目前无论是硅基CMOS-RF芯片、硅基SOI-RF芯片、化合物半导体GaAs、GaN芯片,芯片上电感面积要大大超过晶体管本身的面积。典型地,GaAs芯片上2nH电感,面积要接近度要1mm2左右。(2)由于占用面积大,浪费了芯片面积,因此成本高。(3)现有技术制作的电感,由于下方的衬底外延片没有优化,相对介电常数较高,造成电感Q值很低,通常只有15以内。而非芯片的绕线电感、SMT表贴电感的Q值可以达到70以上。(4)芯片上电感Q值很低时,造成电感的天线效应明显,和电路其他其他层金属耦合严重,会造成电磁干扰、寄生电容、寄生电阻等寄生参数恶化等问题。(5)芯片上电感Q值很低时,造成芯片上匹配电路性能恶化,造成芯片输出功率和效率的降低。
现有技术设计的电容是在芯片上制作介质层,两边用M1/M2金属层引出形成的。现有技术制作的电容下方的衬底外延片没有针对性优化,是在衬底外延片的高阻层Iso/Mesa层上利用M1/M2中间夹层介质层制作电容。
现有技术设计的电容没有针对芯片上电感的性能要求进行优化,存在以下问题:(1)现有技术制作的电容,由于下方的衬底外延片没有优化,存在介质漏电通道到衬底外延片背面的金属层,导致芯片上电容失效。(2)现有技术制作的电容,由于下方的衬底外延片没有优化,在电容引线用M1/M2金属与背面金属之间存在寄生介质电容,会降低芯片电容容值,导致芯片电容面积过大。(3)由于占用面积大,浪费了宝贵的芯片面积,因此成本高。(4)现有技术制作的电容,由于下方的衬底外延片没有优化,存在漏电通道或寄生电容,造成电容Q值很低,通常只有15以内。而非芯片的绕线电容、SMT表贴电容的Q值可以达到70以上。(5)芯片上电容Q值很低时,造成芯片上匹配电路性能恶化,造成芯片输出功率和效率的降低。
本发明实施例中,对有源电路区仍采用Meas层制作电阻,且采用离子注入方法进行优化,在有源区(有源电路区)仍然针对有源区要求优化衬底Mesa层的厚度和离子注入深度和浓度,保持原有Mesa方块电阻,例如300Ω左右。这样做的目的是仍然保证芯片的有源晶体管电性能处于不变的状态,衬底外延片优化仅限于电阻、电感、电容等无源电路部分。
在一些实施例中,电阻采用Iso/Mesa电阻(即在Iso/Mesa电阻的基础上进行优化设计),对电阻区衬底外延片的优化设计方案为:
电阻区下方采用低掺杂浓度或未掺杂的衬底,取消衬底外延片上的沟道层,由高阻的势垒层或缓冲层纵向填充该沟道层。结合已有的离子注入或Mesa工艺,提高Iso/Mesa电阻区的方块电阻到1kΩ以上。实现该结构电阻区衬底外延片的工艺包括:
(1)降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度
Iso/Mesa电阻区下方衬底外延片仅起到隔离作用,并不需要生成2D电子气(pHEMT)或PN结(HBT),因此现有技术的水平方向各向同性衬底外延片的有源区相关功能对Iso/Mesa电阻区是没有用处的。本实施例通过降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度(甚至取消掺杂),配合现有技术的离子注入或Mesa工艺,可以有效提升表面电阻率,且控制更精细,解决现有技术Iso/Mesa电阻值误差大、一致性不好的问题。
(2)取消沟道层
现有技术的水平方向各向同性衬底外延片的有源区相关功能对Iso/Mesa电阻区是没有用处的。本实施例在制作衬底外延片时,通过光罩mask,或者有图形定义的通过和遮挡的掩膜版,在衬底外延片上取消沟道层,定制衬底外延片。
(3)由高阻的势垒层或缓冲层纵向填充沟道层
本实施例在制作衬底外延片时,通过光罩mask,或者有图形定义的通过和遮挡的掩膜版,在衬底外延片上由高阻的势垒层或缓冲层纵向填充沟道层,定制衬底外延片。
最终,衬底外延片结构在芯片上无源电路电阻区和有源区分别优化。整个衬底外延片不是水平方向各向同性的,而是存在厚度和电性能差别。典型地,电阻区下方的衬底外延片为低掺杂或未掺杂,且没有沟道层(pHEMT)。对HBT,是取消Base重掺杂层。
通过上述对电阻区衬底外延片的设计,可以实现以下效果:
(1)更高的方块电阻
本实施例通过降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度,在同样的离子注入或Mesa工艺下,可以有效提升方块电阻率,至少达到1kΩ以上。
(2)更精密的Iso/Mesa电阻值控制
现有技术Iso/Mesa电阻值误差大、一致性不好。本实施例通过降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度,配合现有技术的离子注入或Mesa工艺,可以有效提升方块电阻,且控制更精细,解决现有技术Iso/Mesa电阻值误差大、一致性不好的问题。
(3)更少的漏电,更好的隔离效果
由于取消了沟道层,漏电通道得到抑制,因此本实施例制作的Iso/Mesa电阻有更少的漏电,更低的寄生电容,具备更好的隔离效果。且噪声大大降低。
(4)更小的芯片面积、更低的成本
Iso/Mesa电阻的方块电阻提升到1kΩ以上,开关栅极隔离用电阻的长度显著降低,典型值小于300um。减小了芯片面积,降低了成本。
在一些实施例中,对电感区衬底外延片的优化设计方案为:
本发明电感设计为空气桥(AirBridge)电感。实现该结构电阻区衬底外延片的工艺包括:
(1)生长衬底外延片时,在电感区进行选择性生长
对芯片上电感下方的衬底外延片进行优化,取消沟道层,由高阻的势垒层或缓冲层纵向填充沟道层。在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑电感传输线的支撑柱(Pillar)。
(2)在电感区的支撑柱(Pillar)之间覆盖光阻层SPAN(也可以是其它光阻层)
光阻层SPAN的作用是为了填满支撑柱(Pillar)之间空隙,以便在上面制作形成电感的传输线线圈。
(3)在电感区的支撑柱(Pillar)和SPAN之上制作电感线圈(电感传输线)
(4)刻蚀掉光阻层SPAN,形成芯片空气桥电感
典型地,采用湿法刻蚀掉光阻层SPAN,形成仅有支撑柱(Pillar)支撑的芯片空气桥电感。
最终,芯片的电感区下方大部分是空气,形成空气桥电感。典型地,电容区下方的衬底外延片仅存在若干支撑柱,且没有沟道层(pHEMT)。对HBT,是取消Base重掺杂层。芯片空气桥电感效果图如图3、4所示,其中,附图3为GaAs pHEMT衬底结构(左侧:有源区;右侧:电感/电容区),附图4为GaAs HBT衬底结构。
通过上述对电感区衬底外延片的设计,可以实现以下效果:
(1)更小的电感面积
本实施例通过定制衬底,在电感区形成介质支撑柱(Pillar),在电感区下方大部分是空气,降低了相对介电常数,可以用更小的芯片面积实现常规电感值。典型地,2nH左右芯片电感占用的面积,可以从现有技术的1mm2左右降低到300μm×300μm左右。
(2)更高的Q值
本实施例通过定制衬底,在电感区形成介质支撑柱(Pillar),在电感区下方大部分是空气,降低了相对介电常数,可以有效提高芯片电感的Q值,可以从现有技术的Q值15以内提升到40以上。
(3)本实施例芯片上电感Q值的提高,造成电感的天线效应明显降低,和电路其他其他层金属耦合降低,可以大大减小电磁干扰、寄生参数恶化等问题。
(4)本实施例芯片上电感Q值的提高,可以提升芯片上匹配电路性能,并提高芯片输出功率和效率。
在一些实施例中,对电容区衬底外延片的优化设计方案为:
本实施例的电容设计为支撑柱支撑电容,电容区的支撑柱为空气隔离,即支撑柱之间形成空气层,电容下方大部分是空气,与电感区衬底外延片结构类似。实现该结构电阻区衬底外延片的工艺包括:
(1)生长衬底外延片时,在电容区进行选择性生长
对芯片上电容下方的衬底外延片进行优化,取消沟道层,由高阻的势垒层或缓冲层纵向填充沟道层。在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱(Pillar)。
(2)在电容区的支撑柱(Pillar)之间覆盖光阻层SPAN(或其它光阻层)光阻层SPAN的作用是为了填满支撑柱之间空隙,以便在上面制作形成电容的电极。
(3)在电容区的支撑柱和SPAN之上制作M1/M2电容电极
(4)刻蚀掉光阻层SPAN,形成支撑柱支撑电容
典型地,采用湿法刻蚀掉光阻层SPAN,形成仅有支撑柱支撑的芯片支撑柱支撑电容。
最终,电容下方大部分是空气,支撑柱支撑电容效果图如图3、4所示。整个衬底外延片不是水平方向各向同性的,而是存在厚度和电性能差别。典型地,电容区下方的衬底外延片仅存在若干支撑柱,且没有沟道层(pHEMT)。对HBT,是取消Base重掺杂层。
通过上述对电容区衬底外延片的设计,可以实现以下效果:
(1)更小的电容面积
本实施例通过定制衬底,在电容区形成介质支撑柱,在电容区下方大部分是空气,大大减小了电容电极和衬底背面金属之间的寄生电容,可以用更小的芯片面积实现常规电容值。
(2)更高的Q值
本是实施例通过定制衬底,在电容区形成介质支撑柱(Pillar),在电容区下方大部分是空气,大大减小了电容电极和衬底背面金属之间的寄生电容,可以有效提高芯片电容的Q值,可以从现有技术的Q值15以内提升到40以上。
(3)更高的电容可靠性
本实施例通过定制衬底,在电容区形成介质支撑柱(Pillar),在电容区下方大部分是空气,且取消了pHEMT的沟道层,以及HBT的Base重掺杂层。大大减小了电容漏电通道,可以大大提升电容可靠性,以及系统级可靠性。
需要说明的是,本发明实施例中,除电阻区下方降低了衬底外延片的掺杂浓度外,电感区和电容区下方衬底外延片也可降低掺杂浓度或不掺杂。
本发明并不局限于前述的具体实施方式。本发明扩展到任何在本说明书中披露的新特征或任何新的组合,以及披露的任一新的方法或过程的步骤或任何新的组合。

Claims (6)

1.一种芯片衬底外延片,其特征在于,芯片衬底外延片为水平方向非均匀衬底外延结构,无源电路区和有源电路区的衬底外延片结构不同,无源电路包括电阻、电感和电容;
所述电阻为Iso/Mesa电阻,电阻区下方采用低掺杂浓度或未掺杂的衬底,取消衬底外延片上的沟道层,由高阻的势垒层或缓冲层纵向填充该沟道层;
所述电感为空气桥电感;
所述电容为支撑柱支撑电容,电容区的支撑柱为空气隔离。
2.如权利要求1所述的芯片衬底外延片,其特征在于,电阻区下方衬底外延片的制作工艺包括:
降低Iso/Mesa电阻区下方衬底外延片的掺杂浓度;
在制作衬底外延片时,取消沟道层;
在制作衬底外延片时,由高阻的势垒层或缓冲层纵向填充沟道层。
3.如权利要求1所述的芯片衬底外延片,其特征在于,电感区下方衬底外延片的制作工艺包括:
生长衬底外延片时,在电感区进行选择性生长,只保留若干用于支撑电感传输线的支撑柱;
在电感区的支撑柱之间覆盖光阻层;
在电感区的支撑柱和所述光阻层之上制作电感传输线;
刻蚀掉所述光阻层。
4.如权利要求3所述的芯片衬底外延片,其特征在于,所述生长衬底外延片时,在电感区进行选择性生长,只保留若干用于支撑电感传输线的支撑柱,包括:
生长衬底外延片时,取消电感下方衬底外延片的沟道层,由高阻的势垒层或缓冲层纵向填充沟道层;在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑电感传输线的支撑柱。
5.如权利要求1所述的芯片衬底外延片,其特征在于,电容区下方衬底外延片的制作工艺包括:
生长衬底外延片时,在电容区进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱;
在电容区的支撑柱之间覆盖光阻层;
在电容区的支撑柱和光阻层之上制作M1/M2电容电极;
刻蚀掉光阻层。
6.如权利要求5所述的芯片衬底外延片,其特征在于,所述生长衬底外延片时,在电容区进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱,包括:
生长衬底外延片时,取消电容下方衬底外延片的沟道层,由高阻的势垒层或缓冲层纵向填充沟道层;在生长势垒层、缓冲层时利用定义了通过和阻挡图形的掩膜版,进行选择性生长,只保留若干用于支撑M1/M2电容电极的支撑柱。
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