CN113257673A - 一种基于浅刻蚀的微结构金属图形剥离制备方法 - Google Patents

一种基于浅刻蚀的微结构金属图形剥离制备方法 Download PDF

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CN113257673A
CN113257673A CN202110058761.2A CN202110058761A CN113257673A CN 113257673 A CN113257673 A CN 113257673A CN 202110058761 A CN202110058761 A CN 202110058761A CN 113257673 A CN113257673 A CN 113257673A
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substrate
microstructure
etching
metal
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何磊磊
邓军
冯媛媛
许晓芳
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Beijing University of Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67253Process monitoring, e.g. flow or thickness monitoring

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Abstract

本发明公开了一种基于浅刻蚀的微结构金属图形剥离制备方法,属于半导体光电子或微细加工领域。本发明将常规的曝光‑溅射/蒸发‑剥离工艺改变为曝光‑浅刻蚀‑溅射/蒸发‑剥离工艺,实现微结构金属图形的制备,工艺具有更好的可靠性和重复性。刻蚀工艺可以迅速的消除微小图形中残留的光刻胶底膜,避免了底膜引起的微图形的剥离。通过对刻蚀时间和参数的控制,在清除残胶的同时,可以清除材料表面吸附的各种杂质,并在材料表面形成很浅的刻蚀图形,使下一步溅射/蒸发的薄金属与材料表面结合的牢固,大幅降低了后续剥离工艺对金属微结构图形的损伤,保证了工艺的可靠性和重复性。

Description

一种基于浅刻蚀的微结构金属图形剥离制备方法
技术领域
本发明是在半导体器件表面制备微结构金属图形时的一种新的工艺技术,具体涉及制作超构表面结构时利用浅刻蚀技术实现微结构薄金属图形的无损剥离,属于半导体光电器件微细加工技术领域。
背景技术
随着光电子器件的飞速发展,将超表面结构应用于光电子器件表面,实现对器件光电特性的调控已经成为研究的热点。基于超表面结构的光电子器件以其调控灵活多样,器件结构简单、体积小、重量轻、便于集成化、阵列化等优点,已成为新的发展方向。
目前,用于制作超表面金属微结构的工艺方法一般为光刻-腐蚀工艺或者光刻-溅射/蒸发-剥离工艺。由于超表面金属微结构的图形非常小,光刻后的胶图形也非常小,显影中的侧向曝光引起的光刻胶图形形变很严重,在对金属腐蚀时的侧向钻蚀会进一步加剧图形的形变,因此光刻-腐蚀工艺在进行微结构薄金属图形制备时,图形畸变严重,成品率不高。采用光刻-溅射/蒸发-剥离工艺时,光刻图形与前述方法正好相反,微小的图形容易导致曝光不足,显影后图形中残留光刻胶底膜,导致在最后的剥离工艺中,金属微结构图形被剥离掉。
发明内容
针对制备金属微结构图形中光刻-溅射/蒸发-剥离工艺的缺点,本发明提出光刻-浅刻蚀-溅射/蒸发-剥离工艺,实现高质量金属微结构图形制备。具体包括以下步骤:
(1)通过基片(利用MBE或MOCVD在GaAs衬底上生长GaAs/AlGaAs 量子阱对而成的基片)清洗程序,将基片放入装有丙酮的烧杯煮沸两遍、无水乙醇煮沸两遍、去离子水冲洗35次,去除基片表面吸附的灰尘和油脂。
(2)在温度为100℃的烘台静置5min烘干基片,蒸发掉基片表面可能引入的水分和易挥发物质。
(3)通过对甩胶机转速以及光刻胶性质的控制在基片上旋涂一层厚度仅为1055nm的AZ 5214反转光刻胶,目的是在光刻精度为1um的MJB 3光刻机下,光刻出1um的图形。
(4)烘台前烘50s后,进行15s泛曝、40s曝光以及30s显影得到基片上带有微结构图形的光刻胶。
(5)利用ICP干法刻蚀工艺,在ICP中通入SiCl4气体30sccm,通过光刻胶作掩模对基片上的预成型的光刻胶微结构图形进行浅刻蚀5s,会将微结构图形转移到基片上,基片上的图形深度大概为75nm~100nm左右,图形边沿区别于湿法腐蚀,比较垂直整齐。
(6)利用溅射或蒸发在进行浅刻蚀后的基片表面淀积150nm金属层。
(7)将基片放入丙酮或去胶液中对金属层进行剥离,得到成型的金属微结构。
与现有技术相比较,本发明的重点是在溅射/蒸发薄金属前,采用ICP或RIE 等干法刻蚀技术对曝光后的表面进行浅刻蚀处理,这样做的优点是:
1)刻蚀工艺可以迅速的消除微小图形中残留的光刻胶底膜,避免了底膜引起的微图形的剥离。
2)通过对刻蚀时间和参数的控制,在清除残胶的同时,可以清除材料表面吸附的各种杂质,并在材料表面形成很浅的刻蚀图形,使下一步溅射/蒸发的薄金属与材料表面结合的牢固,大幅降低了后续剥离工艺对金属微结构图形的损伤,保证了工艺的可靠性和重复性。
附图说明
下面结合附图及实施例对本发明做进一步详细说明。
图1:在清洗后的基片上先涂一层薄光刻胶。
图2:利用标准的紫外曝光工艺,将掩模板上的图形通过曝光、显影等一系列工艺,转移到薄光刻胶上。
图3:用ICP或RIE等干法刻蚀工艺对基片进行浅刻蚀。
图4:用溅射/蒸发在基片表面制备一层薄金属层。
图5:利用剥离工艺去除光刻胶和依附在光刻胶上的金属,得到所需的金属微结构图形。
图6:最后形成的金属微结构图形阵列。
图7:淀积金属层的结构图。
图8:刻蚀后的微结构图。
图9:金属微结构图。
具体实施方式
本发明采用的技术方案为一种微结构金属图形完整剥离的工艺方法,工艺步骤如下:将准备好的衬底,丙酮乙醇煮沸清洗2遍,去离子水冲洗35次。该基片是利用MBE或MOCVD在GaAs衬底上生长GaAs/AlGaAs量子阱对而成。静置在100℃的烘台烘5分钟,然后5214反转胶甩胶,甩胶机转速2000/7000rad/min,甩胶时间30s,充分利用甩胶机转速和5214反转胶性质,可控制光刻胶厚度为 1055nm。前烘50秒,烘干光刻胶里面的溶剂。将烘干的带有光刻胶的基片和光刻版紧密贴合,使用MJB3光刻机泛曝15s,中烘1分20秒使胶变性反转。曝光40s,根据湿度调控显影条件,大概显影时间范围:30s~35s。打胶2分钟。ICP 刻蚀,刻蚀条件:SiCl4气体通量30sccm,刻蚀时间5秒。ICP干法刻蚀出来的图形边缘比较垂直溅射Au150nm,将芯片放入剥离液超声10分钟。丙酮乙醇煮沸清洗2遍,去离子水冲洗35次。

Claims (4)

1.一种基于浅刻蚀的微结构金属图形剥离制备方法,其特征在于,(1)通过基片清洗程序,将基片放入装有丙酮的烧杯煮沸两遍、无水乙醇煮沸两遍、去离子水冲洗,去除基片表面吸附的灰尘和油脂;
(2)在烘台静置烘干基片,蒸发掉基片表面可能引入的水分和易挥发物质;
(3)通过对甩胶机转速以及光刻胶性质的控制在基片上旋涂一层厚度仅为1055nm的AZ5214反转光刻胶,目的是在光刻精度为1um的MJB 3光刻机下,光刻出1um的图形;
(4)烘台前烘50s后,进行15s泛曝、40s曝光以及30s显影得到基片上带有微结构图形的光刻胶;
(5)利用ICP干法刻蚀工艺,在ICP中通入SiCl4气体30sccm,通过光刻胶作掩模对基片上的预成型的光刻胶微结构图形进行浅刻蚀5s,会将微结构图形转移到基片上,基片上的图形深度大概为75nm~100nm左右,图形边沿区别于湿法腐蚀,比较垂直整齐;
(6)利用溅射或蒸发在进行浅刻蚀后的基片表面淀积150nm金属层;
(7)将基片放入丙酮或去胶液中对金属层进行剥离,得到成型的金属微结构。
2.根据权利要求1的一种基于浅刻蚀的微结构金属图形剥离制备方法,其特征在于,在溅射/蒸发金属前,采用ICP或RIE干法刻蚀工艺对材料表面进行预处理,去除残胶和表面吸附的其他杂质,使表面更清洁,提高金属与表面的粘附性。
3.根据权利要求1的一种基于浅刻蚀的微结构金属图形剥离制备方法,其特征在于,采用ICP或RIE干法刻蚀工艺对材料表面进行浅刻蚀,使表面变得粗糙,增加金属与表面的粘附性。
4.根据权利要求1的一种基于浅刻蚀的微结构金属图形剥离制备方法,其特征在于,采用ICP或RIE干法刻蚀工艺对材料表面进行浅刻蚀,刻蚀深度在几到十几纳米,保证表面粗糙度。
CN202110058761.2A 2021-01-16 2021-01-16 一种基于浅刻蚀的微结构金属图形剥离制备方法 Pending CN113257673A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5830774A (en) * 1996-06-24 1998-11-03 Motorola, Inc. Method for forming a metal pattern on a substrate
CN101436540A (zh) * 2007-10-30 2009-05-20 Wj通信公司 使蚀刻底切最小化及提供清洁金属剥离的方法
CN103094096A (zh) * 2011-11-07 2013-05-08 上海华虹Nec电子有限公司 一种用于形成半导体器件金属图形的剥离工艺方法
CN106707381A (zh) * 2017-03-19 2017-05-24 北京工业大学 一种微透镜阵列制作的工艺方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5830774A (en) * 1996-06-24 1998-11-03 Motorola, Inc. Method for forming a metal pattern on a substrate
CN101436540A (zh) * 2007-10-30 2009-05-20 Wj通信公司 使蚀刻底切最小化及提供清洁金属剥离的方法
CN103094096A (zh) * 2011-11-07 2013-05-08 上海华虹Nec电子有限公司 一种用于形成半导体器件金属图形的剥离工艺方法
CN106707381A (zh) * 2017-03-19 2017-05-24 北京工业大学 一种微透镜阵列制作的工艺方法

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