CN113253529A - Array substrate with double-gate structure, display panel and electronic device - Google Patents
Array substrate with double-gate structure, display panel and electronic device Download PDFInfo
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract
The present disclosure provides an array substrate, a display panel and an electronic device of a dual gate structure, the array substrate including: the pixel structure comprises a plurality of grid lines and a plurality of data lines, wherein two columns of sub-pixel regions are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel regions; the sum of the first capacitance and the second capacitance of each sub-pixel region in each pixel group in the array substrate is the same. The sum value of the first capacitor and the second capacitor corresponding to all sub-pixel regions in the pixel group is the same by adjusting the related structure of each sub-pixel region in each pixel group in the array substrate, so that the sub-pixel regions are guaranteed to have the same floating degree due to the grid line jump voltage, the brightness change of all sub-pixel regions is the same, the generation of shaking marks is avoided, the better display effect is achieved, and the use experience of a user is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate with a dual gate structure, a display panel, and an electronic device.
Background
With the continuous upgrade of the ultra-high definition video industry, 4K televisions are basically popularized in the market, and the 8K television market is also initially large. In the 8K product, the number of data lines is large, which results in a large number of Chip On Film (COF) lines and an increase in panel cost, and the design of the packaging material and the whole machine is difficult due to the excessive number of COF lines. In the prior art, in order to reduce the production cost, a thin film transistor liquid crystal display (TFT-LCD) with a dual gate structure is provided, in which the number of COFs is reduced by increasing the number of gate lines (gates) and reducing the number of data lines, and then the number of corresponding driving chips is reduced, so as to achieve the purpose of reducing the production cost.
However, the voltage of the pixels is influenced to float when the gate voltage jumps, so that the brightness of each column of pixels is different when the polarities of the pixels are different, and when a user shakes his head to observe a display screen, the user easily loses frames and shakes his head, thereby influencing the display effect of the screen and the user experience.
Disclosure of Invention
An object of the present disclosure is to provide an array substrate, a display panel and an electronic device with a dual-gate structure, so as to solve the problem in the prior art that a head-shaking pattern is easily generated due to gate voltage jump.
The embodiment of the disclosure adopts the following technical scheme: an array substrate of a dual gate structure, comprising at least: the pixel structure comprises a plurality of grid lines and a plurality of data lines, wherein two columns of sub-pixel regions are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel regions; the sum of the first capacitance and the second capacitance of each sub-pixel region in each pixel group in the array substrate is the same; the pixel group is a plurality of sub-pixel regions arranged between two adjacent data lines according to a 2 x 2 matrix array; the first capacitor is a capacitor between the grid line part corresponding to each sub-pixel region and the source electrode and the drain electrode of the sub-pixel region; the second capacitor is a capacitor between the gate line portion corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region.
In some embodiments, in each pixel group, at least one overlapping area between the gate corresponding to the sub-pixel region and the source and drain of the sub-pixel region is different from the overlapping area of other sub-pixel regions in the pixel group.
In some embodiments, the width of the source and drain of at least one of the sub-pixel regions in each of the pixel groups is different from the width of the source and drain of other sub-pixel regions in the pixel group; and the width of the source and drain of the sub-pixel region is the width of the overlapped part between the source and drain of the sub-pixel region and the grid of the sub-pixel region.
In some embodiments, in the pixel group, the sub-pixel region in the first row and the first column in the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column in the matrix array is a second sub-pixel region, the sub-pixel region in the second row and the first column in the matrix array is a third sub-pixel region, and the sub-pixel region in the second row and the second column in the matrix array is a fourth sub-pixel region; the source-drain width of the fourth sub-pixel region is greater than the source-drain width of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than the source-drain widths of the second sub-pixel region and the third sub-pixel region, and the source-drain width of the second sub-pixel region is greater than the source-drain width of the third sub-pixel region.
In some embodiments, the length of the source and drain of at least one of the sub-pixel regions in each of the pixel groups is different from the length of the source and drain of other sub-pixel regions in the pixel group; the length of the source and drain electrodes of the sub-pixel region is the length of the overlapped part between the source and drain electrodes of the sub-pixel region and the grid electrode of the sub-pixel region.
In some embodiments, in the pixel group, the sub-pixel region in the first row and the first column in the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column in the matrix array is a second sub-pixel region, the sub-pixel region in the second row and the first column in the matrix array is a third sub-pixel region, and the sub-pixel region in the second row and the second column in the matrix array is a fourth sub-pixel region; the source-drain length of the fourth sub-pixel region is greater than that of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than that of the second sub-pixel region and that of the third sub-pixel region, and the source-drain length of the second sub-pixel region is greater than that of the third sub-pixel region.
In some embodiments, the distance between the gate line portion of at least one of the sub-pixel regions in each of the pixel groups and the edge of the pixel electrode on the side of the sub-pixel region close to the gate line is different from the distances of the other sub-pixel regions in the pixel group.
In some embodiments, in the pixel group, the sub-pixel region in the first row and the first column in the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column in the matrix array is a second sub-pixel region, the sub-pixel region in the second row and the first column in the matrix array is a third sub-pixel region, and the sub-pixel region in the second row and the second column in the matrix array is a fourth sub-pixel region; the distance of the third sub-pixel region is greater than the distance of any other sub-pixel region in the pixel group, the distance of the second sub-pixel region is greater than the distances of the first sub-pixel region and the fourth sub-pixel region, and the distance of the first sub-pixel region is greater than the distance of the fourth sub-pixel region.
In some embodiments, the gate line of at least one of the sub-pixel regions in each of the pixel groups is provided with a groove structure at a side close to the pixel electrode of the sub-pixel region.
In some embodiments, the cross-section of the groove structure comprises at least one of the following shapes: rectangular, semicircular, and zigzag.
Embodiments of the present disclosure also provide a display panel, which at least includes the array substrate of the dual gate structure as described above.
An embodiment of the present disclosure further provides an electronic device, which includes at least the display panel as described above.
The beneficial effects of this disclosed embodiment lie in: the sum values of the first capacitor and the second capacitor corresponding to all sub-pixel regions in each pixel group are the same by adjusting the related structures of the sub-pixel regions in each pixel group in the array substrate, so that the sub-pixel regions are guaranteed to have the same floating degree due to the grid line jump voltage, the brightness change of all the sub-pixel regions is the same, the generation of shaking marks is avoided, the better display effect is achieved, and the use experience of a user is improved.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a partial schematic view of a dual gate array substrate according to the prior art;
FIG. 2 is a diagram illustrating floating pixel voltages in a first sub-pixel region according to the prior art;
FIG. 3 is a schematic diagram of a portion of a pixel connection of a dual gate structure array substrate in the prior art;
FIG. 4 is a schematic diagram of two brightness levels of a pixel of a dual-gate array substrate in the prior art;
FIG. 5 is a schematic diagram of a pixel set according to a first embodiment of the disclosure;
FIG. 6 is a schematic diagram illustrating source-drain width adjustment in a first embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating source-drain length adjustment in a first embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating gate line adjustment according to a first embodiment of the disclosure.
Detailed Description
Various aspects and features of the disclosure are described herein with reference to the drawings.
It will be understood that various modifications may be made to the embodiments of the present application. Accordingly, the foregoing description should not be construed as limiting, but merely as exemplifications of embodiments. Other modifications will occur to those skilled in the art within the scope and spirit of the disclosure.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and, together with a general description of the disclosure given above, and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.
These and other characteristics of the present disclosure will become apparent from the following description of preferred forms of embodiment, given as non-limiting examples, with reference to the attached drawings.
It should also be understood that, although the present disclosure has been described with reference to some specific examples, a person of skill in the art shall certainly be able to achieve many other equivalent forms of the disclosure, having the characteristics as set forth in the claims and hence all coming within the field of protection defined thereby.
The above and other aspects, features and advantages of the present disclosure will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the disclosure that may be embodied in various forms. Well-known and/or repeated functions and structures have not been described in detail so as not to obscure the present disclosure with unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present disclosure in virtually any appropriately detailed structure.
The specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the disclosure.
Fig. 1 shows a partial layout of a dual gate structure array substrate in the prior art. As for the first sub-pixel region (pixel 1 in the first row and the first column in fig. 1), the gate of the TFT is connected to the gate line 1(G1), the source and drain of the TFT are connected to the data line 1(D1), and the drain of the TFT is connected to its own pixel electrode, as analyzed by the pixel structure in fig. 1. During actual display, G1 controls Pixel1 to be turned on first, when G1 is turned off, the voltage of a grid line jumps, and the Pixel voltage of a first sub-Pixel region is pulled down by delta Vp1 due to parasitic capacitance Cgs between the grid electrode and a source drain electrode of a TFT; when G2 is turned off, the pixel voltage of the first sub-pixel region is pulled down by Δ Vp 1' again due to the gate line voltage transition of the next row, and thus the pixel voltage of the first sub-pixel region is pulled up twice, as shown in fig. 2. For the second sub-pixel region (pixel 2 in the first row and the second column in fig. 1), the gate voltage jump when G2 is turned off causes its pixel voltage to be pulled down by Δ Vp 2; similarly, the third sub-pixel region (pixel 3 in the first column of the second row in fig. 1) will have its pixel voltage pulled down twice due to the turning off of G3 and G4, which are Δ Vp3 and Δ Vp 3', respectively, and the fourth sub-pixel region (pixel 4 in the second column of the second row in fig. 1) will have its pixel voltage pulled down Δ Vp4 due to the turning off of G4.
Fig. 3 shows a schematic diagram of a part of pixel connection of a double gate structure array substrate in the prior art. Due to the TFT placement and the different connection with the pixel, the solid bold line in fig. 3 represents the region where the gate line portion corresponding to the first sub-pixel region to 4 corresponds to its own pixel electrode, this region corresponds to the lateral capacitance Cgp, which, based on the capacitor formula C ═ S/d, under the condition that the distance d between the two side electrode plates of the capacitor is not changed, the larger the opposite area S between the two side electrode plates is, the larger the capacitance value C of the capacitor is, therefore, for the first sub-pixel region and the third sub-pixel region, the capacitance value Cgp1 of the lateral capacitance 1 of the first sub-pixel region is smaller than the capacitance value Cgp2 of the lateral capacitance 3 of the third sub-pixel region, and the capacitance value Cgp1 'of the lateral capacitance 2 of the first sub-pixel region is smaller than the capacitance value Cgp 2' of the lateral capacitance 4 of the third sub-pixel region, so that Δ Vp3 is larger than Δ Vp1, and Δ Vp3 'is larger than Δ Vp 1'. According to the change situation that the voltage jump of the grid line of the pixel and the next grid line of the pixel pulls the voltage of the pixel and the position situation of the TFT of each pixel, when the actual display is carried out, the brightness degree of one column of the pixels is as shown in figure 4, when two continuous columns of the pixels are bright or dark, the pixels have brightness difference in the display process of the display screen, and when a person shakes the head to observe the display screen, the shaking marks appear when the frame is lost.
In order to solve the above problem, a first embodiment of the present disclosure provides an array substrate with a dual gate structure, where the array substrate at least includes a plurality of gate lines and a plurality of data lines, two columns of sub-pixel regions are disposed between two adjacent data lines, and two gate lines are disposed between two adjacent rows of sub-pixel regions. In general, the gate lines are arranged along the horizontal direction, the data lines are arranged along the vertical direction, two columns of sub-pixel regions are arranged between the two data lines, and two rows of gate lines are arranged between two adjacent rows of sub-pixel regions; in other embodiments, the gate lines may be disposed along a vertical direction, the data lines may be disposed along a horizontal direction, two rows of sub-pixel regions are disposed between two adjacent rows of data lines, and two rows of gate lines are correspondingly disposed between two adjacent rows of sub-pixel regions.
In order to solve the problem of poor display effects such as the wiggle pattern, the related structures of the sub-pixel regions in the array substrate, such as the arrangement of the position and the size of the corresponding grid line, the arrangement of the size and the position of the source and the drain, can be adjusted, so that the sum values of the first capacitor and the second capacitor of all the sub-pixel regions in the same pixel group are the same, and the brightness of the grid line voltage of each pixel region in the group is the same after jumping; in practical implementation, the error between the sum of the first capacitor and the second capacitor of any one sub-pixel region in the group and the sum of the first capacitor and the second capacitor of other sub-pixel regions in the group is within a preset error range, so that the problem of uneven brightness caused by voltage jump of the gate line is reduced as much as possible. As shown in a portion enclosed by a dotted line in fig. 5, the first capacitance in this embodiment is a capacitance between the gate corresponding to each sub-pixel region and the source/drain of the sub-pixel region, that is, a parasitic capacitance Cgs exists between the gate and the source/drain, and the second capacitance is a capacitance between the gate line corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region, that is, a lateral capacitance Cgp. The same Cgs + Cgp value in each sub-pixel region in the pixel group can compensate the problem of inconsistent pixel electrode floating in the sub-pixel region caused by the difference of TFT station positions.
It should be noted that the preset error range may be adjusted according to the size of the array substrate, the size of the sub-pixel region, or the first capacitor and the second capacitor of each sub-pixel region, which is not specifically limited in this embodiment; under the ideal condition, the sum of the first capacitance and the second capacitance of each sub-pixel area in the pixel group can be ensured to be consistent, so that a better display optimization effect is achieved.
In a pixel group shown in fig. 5, there may be a difference between the second capacitances of each sub-pixel region, and in practical implementation, any one sub-pixel region in the pixel group may be selected as a reference, and the sum value may be adjusted by adjusting the values of the first capacitances of the other three sub-pixel regions in the group. Specifically, the first capacitor is a parasitic capacitor between the gate and the source and the drain of the sub-pixel region, and the size of the capacitance value is related to the distance between the gate and the source and the drain and the facing area. In some embodiments, due to the difference between the second capacitances of each sub-pixel region, after the reference pixel is determined, at least one overlapping area between the gate and the source and the drain of the sub-pixel region in the current pixel group should be different from the overlapping area between the gate and the source and the drain of other sub-pixel regions in the group, so as to adjust the first capacitance of the sub-pixel region. In practical implementation, the overlapping area between the gate and the source and drain of two sub-pixel regions in a pixel group is usually required to be adjusted, or according to practical requirements, in combination with factors such as the pixel size and the TFT standing position in the array substrate, the first capacitors of all sub-pixel regions in the pixel group may also be adjusted at the same time, which is not specifically limited in this embodiment.
In some embodiments, the adjustment of the overlapping area between the source and drain and the gate thereof may be achieved by adjusting the width of the source and drain portion of the sub-pixel region in the pixel group. Fig. 6 shows a schematic diagram of the arrangement of the gate portion and the source and drain portions of the sub-pixel region, each sub-pixel region is independently controlled by a corresponding TFT, the TFT includes a gate, a source, and a drain, the gate is connected to the gate line and has a coincidence region with the source and drain, a channel is provided between the source and drain, when a voltage is applied to the gate, the channel between the source and drain is turned on, and further the source and drain are turned on, so that the sub-pixel region is turned on, and when the gate voltage is turned off, the corresponding sub-pixel region is turned off. The U-like structure and the L-like structure in fig. 6 are the source and the drain of the TFT in the sub-pixel region, and specifically, which end is the source and which end is the drain can be set according to actual conditions, and the portion overlapping with the source and drain regions is the gate, and the gate is directly connected to or integrally manufactured with the gate line. Specifically, when the overlap area between the source and drain electrodes and the grid electrode is adjusted, the part of the L-shaped structure, which is overlapped with the grid electrode, can be directly adjusted, so that the adjustment mode is simplified, and meanwhile, the calculation is convenient.
Further, in a pixel group, at least one source-drain width of a sub-pixel region is different from the source-drain width of other sub-pixel regions in the pixel group, wherein the source-drain width of a sub-pixel region mainly refers to the width of a superposed part between the source-drain of the sub-pixel region and the gate of the sub-pixel region. Specifically, in combination with the position where each sub-pixel region is disposed and the configuration of the TFT in this embodiment, when the source-drain width of the fourth sub-pixel region is greater than the source-drain width of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than the source-drain widths of the second sub-pixel region and the third sub-pixel region, and the source-drain width of the second sub-pixel region is greater than the source-drain width of the third sub-pixel region, the sum of the first capacitance and the second capacitance of each sub-pixel region may be substantially kept the same, as shown in fig. 6, with the third sub-pixel region as a reference, the source-drain width of the third sub-pixel region is 5 micrometers, the source-drain width of the fourth sub-pixel region is 9 micrometers, the source-drain width of the first sub-pixel region not shown in fig. 6 is 6.5 micrometers, the source-drain width of the second sub-pixel region is 6 micrometers, at this time, the sum of the first capacitor and the second capacitor corresponding to each determined sub-pixel region can be kept consistent basically, and the generation of shaking marks is avoided when the grid line voltage jumps.
In some embodiments, the adjustment of the overlapping area between the source and drain and the gate thereof may also be achieved by adjusting the length of the source and drain portion of the sub-pixel region in the pixel group. Specifically, the source-drain length of at least one sub-pixel region in a pixel group is different from the source-drain lengths of other sub-pixel regions in the pixel group, wherein the source-drain length of a sub-pixel region mainly refers to the length of the overlapped part between the source-drain of the sub-pixel region and the gate of the sub-pixel region. Specifically, in combination with the position where each sub-pixel region is arranged and the configuration of the TFT in this embodiment, when the source-drain length of the fourth sub-pixel region is greater than the source-drain length of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than the source-drain lengths of the second sub-pixel region and the third sub-pixel region, and the source-drain length of the second sub-pixel region is greater than the source-drain length of the third sub-pixel region, the sum of the first capacitance and the second capacitance of each sub-pixel region may be substantially kept the same, as shown in fig. 7, with the third sub-pixel region as a reference, the source-drain length of the third sub-pixel region is 19.35 micrometers, while the source-drain length of the fourth sub-pixel region is 22.35 micrometers, the source-drain length of the first sub-pixel region not shown in fig. 7 is 20.85 micrometers, the source-drain length of the second sub-pixel region is 20.35 micrometers, at this time, the sum of the first capacitor and the second capacitor of each sub-pixel region is kept consistent, and the generation of shaking marks is avoided when the grid line voltage jumps.
It should be understood that, taking the first capacitance or the second capacitance between the first sub-pixel region and the third sub-pixel region as an example, with reference to fig. 3, the second capacitance Cgp1 of the first sub-pixel region is smaller than the capacitance Cgp2 of the second capacitance of the third sub-pixel region, and Cgp1 'is smaller than Cgp 2', so to ensure that the sum of the first capacitance and the second capacitance between the first sub-pixel region and the third sub-pixel region is the same, the first capacitance of the first sub-pixel region needs to be larger than the first capacitance of the third sub-pixel region, and with reference to the capacitor formula, the larger the facing area S between the two side plates is, the larger the capacitance C of the capacitor is, and therefore, the lifting of the first capacitance of the first sub-pixel region can be achieved by lifting the overlapping area between the gate and the source and drain of the first sub-pixel region. Specifically, in this embodiment, the adjustment of the first capacitance value is correspondingly achieved by adjusting the width or the length of the source and drain, and the adjustment range can be determined by combining the difference of the second capacitance values between the sub-pixel regions.
In addition, the above-mentioned parameter values adjusted by the source and drain corresponding to each sub-pixel region described in the embodiment of adjusting the source and drain width and the source and drain length are only one possible adjustment parameter in implementation, and in actual use, a person skilled in the art can perform autonomous adjustment according to the parameter condition of the actual array substrate, as long as the Cgs + Cgp values of all sub-pixel regions in the same pixel group are substantially the same.
In some embodiments, the adjustment of the sum value may also be achieved by adjusting the value of the second capacitance without changing the first capacitance. The second capacitance is a lateral capacitance between the gate line portion of the sub-pixel region and its own pixel electrode, and referring to a calculation formula of the capacitor, it may actually be also possible to adjust a capacitance value by adjusting a coincidence area between the electrode plates at two sides and a distance between the electrode plates. Specifically, in combination with the position where each sub-pixel region is disposed and the configuration of the TFT in this embodiment, when the distance of the third sub-pixel region is greater than the distance of any other sub-pixel region in the pixel group, the distance of the second sub-pixel region is greater than the distances of the first sub-pixel region and the fourth sub-pixel region, and the distance of the first sub-pixel region is greater than the distance of the fourth sub-pixel region, the sum of the first capacitance and the second capacitance of each sub-pixel region may be substantially consistent.
It should be understood that, taking the first capacitance or the second capacitance between the first sub-pixel region and the third sub-pixel region as an example, the second capacitance Cgp1 of the first sub-pixel region is smaller than the capacitance Cgp2 of the second capacitance of the third sub-pixel region, and Cgp1 'is smaller than Cgp 2', so that if the sum of the first capacitance or the second capacitance between the first sub-pixel region and the third sub-pixel region is ensured to be the same, the sum of the second capacitance and the sum of the first capacitance and the second capacitance of the third sub-pixel region can be maintained to be substantially the same as the sum of the first sub-pixel region by directly reducing the second capacitance of the third sub-pixel region without changing the first capacitance of the sub-pixel region. In combination with the capacitor formula, under the condition that the dead area S between the two side electrode plates is not changed, the larger the distance d between the electrode plates is, the smaller the capacitance value C of the capacitor is, and therefore, the capacitance value of the second capacitor can be reduced by increasing the distance between the grid line part of the third sub-pixel region and the pixel electrode of the third sub-pixel region. Specifically, the present embodiment correspondingly achieves adjustment of the second capacitance value by adjusting the distance between the gate line portion of the pixel region and its own pixel electrode, and the adjustment amplitude can be determined by combining the difference of the first capacitance values between the sub-pixel regions.
Furthermore, a groove structure can be arranged on the surface of one side of the grid line part close to the pixel electrode, the corresponding position of the groove is equivalent to increase the distance between the grid line part and the pixel electrode, the second capacitance value is adjusted, the Cgs + Cgp value of the win-win sub-pixel region can be adjusted by arranging the groove structure in at least one sub-pixel region in the pixel group, the groove structures with different sizes are correspondingly arranged according to the difference between the sub-pixel regions, the Cgs + Cgp value of all the sub-pixel regions in the pixel group can be consistent, the display effect among pixels can be optimized, and the generation of shaking marks can be avoided. In practical use, the cross-sectional shape of the groove structure may be any one of a rectangle, a semicircle, a sawtooth shape, and the like, and the actual size and shape of the groove structure may be adjusted according to requirements, which is not limited in this embodiment.
In some embodiments, for a certain pixel group or certain pixel groups, while adjusting the distance between the gate electrode of the sub-pixel region in the group and the pixel electrode adjacent to the gate electrode, a groove structure may be further provided to achieve a better adjustment effect, as shown in fig. 8, the distance between the edge of the pixel electrode and the position where the groove is not provided at the gate line portion of the third sub-pixel region is 5.4 micrometers, and the groove structure is a rectangular groove with a size of 5 × 10 micrometers, so that the distance between the edge of the pixel electrode and the bottom of the groove is 10.4 micrometers, and corresponding to the same pixel group, the first sub-pixel region, the second sub-pixel region, and the fourth sub-pixel region are not provided with a groove structure (not shown in fig. 8), and the distances between the gate line portion and the edge of the respective pixel electrode are 7 micrometers, 7.4 micrometers, and 5.4 micrometers, respectively.
According to the embodiment, the sum values of the first capacitor and the second capacitor corresponding to all sub-pixel regions in the pixel group are the same by adjusting the related structure of each sub-pixel region in each pixel group in the array substrate, so that the sub-pixel regions are guaranteed to have the same floating degree due to the jump voltage of the grid line, the brightness change of all the sub-pixel regions is the same, the generation of shaking marks is avoided, a better display effect is achieved, and the use experience of a user is improved.
A second embodiment of the present disclosure provides a display panel, for example, a liquid crystal display panel based on a thin film transistor, where the display panel at least has the array substrate with the dual-gate structure provided in the first embodiment of the present disclosure, and sum values of first capacitors and second capacitors corresponding to all sub-pixel regions in a pixel group are the same by adjusting related structures of each sub-pixel region in each pixel group in the array substrate, so as to ensure that the sub-pixel regions have the same floating degree of pixel voltage due to gate line jump voltage, so that brightness changes of all sub-pixel regions are the same, generation of shaking marks is avoided, a better display effect is achieved, and user experience is improved.
A third embodiment of the present disclosure provides an electronic device, for example, a display screen of a computer or a television, an all-in-one device, a tablet computer, and the like, where the electronic device includes at least the display panel provided in the second embodiment of the present disclosure, and adjusts a sum of first capacitors and second capacitors corresponding to all sub-pixel regions in a pixel group based on a related structure of the sub-pixel regions of an array substrate in the display panel, so as to ensure that the sub-pixel regions have the same floating degree of pixel voltage due to a gate line jump voltage, so that brightness changes of all sub-pixel regions are the same, generation of a shaking line is avoided, a better display effect is achieved, and user experience is improved.
While the present disclosure has been described in detail with reference to the embodiments, the present disclosure is not limited to the specific embodiments, and those skilled in the art can make various modifications and alterations based on the concept of the present disclosure, and the modifications and alterations should fall within the scope of the present disclosure as claimed.
Claims (12)
1. An array substrate of a dual gate structure, comprising: the pixel structure comprises a plurality of grid lines and a plurality of data lines, wherein two columns of sub-pixel regions are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel regions;
the sum of the first capacitance and the second capacitance of each sub-pixel region in each pixel group in the array substrate is the same; wherein the content of the first and second substances,
the pixel group is a plurality of sub-pixel regions arranged between two adjacent data lines according to a 2 x 2 matrix array;
the first capacitor is a capacitor between the grid line part corresponding to each sub-pixel region and the source electrode and the drain electrode of the sub-pixel region;
the second capacitor is a capacitor between the gate line portion corresponding to each sub-pixel region and the pixel electrode of the sub-pixel region.
2. The array substrate according to claim 1, wherein an overlapping area between a gate corresponding to at least one of the sub-pixel regions and a source/drain of the sub-pixel region in each of the pixel groups is different from the overlapping area of other sub-pixel regions in the pixel group.
3. The array substrate according to claim 2, wherein the width of the source/drain of at least one of the sub-pixel regions in each of the pixel groups is different from the width of the source/drain of the other sub-pixel regions in the pixel group; and the width of the source and drain of the sub-pixel region is the width of the overlapped part between the source and drain of the sub-pixel region and the grid of the sub-pixel region.
4. The array substrate of claim 3, wherein in the pixel group, the sub-pixel region in the first row and the first column of the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column is a second sub-pixel region, the sub-pixel region in the second row and the first column is a third sub-pixel region, and the sub-pixel region in the second row and the second column is a fourth sub-pixel region;
the source-drain width of the fourth sub-pixel region is greater than the source-drain width of any other sub-pixel region in the pixel group, the source-drain width of the first sub-pixel region is greater than the source-drain widths of the second sub-pixel region and the third sub-pixel region, and the source-drain width of the second sub-pixel region is greater than the source-drain width of the third sub-pixel region.
5. The array substrate according to claim 2, wherein the length of the source/drain of at least one of the sub-pixel regions in each of the pixel groups is different from the length of the source/drain of the other sub-pixel regions in the pixel group; the length of the source and drain electrodes of the sub-pixel region is the length of the overlapped part between the source and drain electrodes of the sub-pixel region and the grid electrode of the sub-pixel region.
6. The array substrate of claim 5, wherein in the pixel group, the sub-pixel region in the first row and the first column of the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column is a second sub-pixel region, the sub-pixel region in the second row and the first column is a third sub-pixel region, and the sub-pixel region in the second row and the second column is a fourth sub-pixel region;
the source-drain length of the fourth sub-pixel region is greater than that of any other sub-pixel region in the pixel group, the source-drain length of the first sub-pixel region is greater than that of the second sub-pixel region and that of the third sub-pixel region, and the source-drain length of the second sub-pixel region is greater than that of the third sub-pixel region.
7. The array substrate of claim 1, wherein a distance between the gate line portion of at least one of the sub-pixel regions in each of the pixel groups and an edge of the pixel electrode on a side of the sub-pixel region close to the gate line is different from distances of other sub-pixel regions in the pixel group.
8. The array substrate of claim 7, wherein in the pixel group, the sub-pixel region in the first row and the first column of the matrix array is a first sub-pixel region, the sub-pixel region in the first row and the second column is a second sub-pixel region, the sub-pixel region in the second row and the first column is a third sub-pixel region, and the sub-pixel region in the second row and the second column is a fourth sub-pixel region;
the distance of the third sub-pixel region is greater than the distance of any other sub-pixel region in the pixel group, the distance of the second sub-pixel region is greater than the distances of the first sub-pixel region and the fourth sub-pixel region, and the distance of the first sub-pixel region is greater than the distance of the fourth sub-pixel region.
9. The array substrate of claim 1, wherein the gate line of at least one of the sub-pixel regions in each of the pixel groups is provided with a groove structure at a side close to the pixel electrode of the sub-pixel region.
10. The array substrate of claim 9, wherein the cross-section of the groove structure comprises at least one of the following shapes: rectangular, semicircular, and zigzag.
11. A display panel comprising at least an array substrate of the double gate structure as claimed in any one of claims 1 to 10.
12. An electronic device characterized in that it comprises at least a display panel as claimed in claim 11.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113985671A (en) * | 2021-10-28 | 2022-01-28 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN114690495A (en) * | 2022-03-23 | 2022-07-01 | 苏州华星光电技术有限公司 | Pixel structure and display panel |
| CN116520615A (en) * | 2023-05-31 | 2023-08-01 | 绵阳惠科光电科技有限公司 | Display panel and display device |
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2021
- 2021-06-21 CN CN202110685647.2A patent/CN113253529A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113985671A (en) * | 2021-10-28 | 2022-01-28 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN113985671B (en) * | 2021-10-28 | 2023-09-29 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN114690495A (en) * | 2022-03-23 | 2022-07-01 | 苏州华星光电技术有限公司 | Pixel structure and display panel |
| CN114690495B (en) * | 2022-03-23 | 2023-09-26 | 苏州华星光电技术有限公司 | Pixel structure and display panel |
| CN116520615A (en) * | 2023-05-31 | 2023-08-01 | 绵阳惠科光电科技有限公司 | Display panel and display device |
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