JPH04348324A - Liquid crystal display element - Google Patents

Liquid crystal display element

Info

Publication number
JPH04348324A
JPH04348324A JP3179736A JP17973691A JPH04348324A JP H04348324 A JPH04348324 A JP H04348324A JP 3179736 A JP3179736 A JP 3179736A JP 17973691 A JP17973691 A JP 17973691A JP H04348324 A JPH04348324 A JP H04348324A
Authority
JP
Japan
Prior art keywords
sub
pixel
electrode
liquid crystal
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3179736A
Other languages
Japanese (ja)
Other versions
JP2909266B2 (en
Inventor
Yasuhiro Ukai
育弘 鵜飼
Tomihisa Sunada
富久 砂田
Toshiya Inada
利弥 稲田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Corp
Original Assignee
Hosiden Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Corp filed Critical Hosiden Corp
Priority to JP17973691A priority Critical patent/JP2909266B2/en
Publication of JPH04348324A publication Critical patent/JPH04348324A/en
Application granted granted Critical
Publication of JP2909266B2 publication Critical patent/JP2909266B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve the display performance by increasing the degree of freedom of the design of capacity division voltages applied to liquid crystal capacitors prescribed by plural subordinate picture element electrodes of respective picture elements. CONSTITUTION:The respective picture element electrodes of the liquid crystal display element are divided into the subordinate picture element electrodes 41, 42..., which are mutually separated by a gap Ga; and a control capacitor electrode 2 is provided at least partially opposite across the respective subordinate picture element electrodes and a 1st insulating film 3. A control capacitor electrode 2 form control capacitors in series with liquid crystal capacitors that the subordinate picture element electrodes 41, 42... form with a counter common electrode 6. An additional capacitor electrode 12 faces the subordinate picture element electrodes 41, 42... partially across a 2nd insulating film 11 is formed and then additional capacitors which are equivalently to the liquid crystal capacitors are connected.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は画素が複数の副画素に
分割され、多階調表示が可能な液晶表示素子の画素の構
成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a pixel of a liquid crystal display element in which a pixel is divided into a plurality of sub-pixels and is capable of displaying multiple gradations.

【0002】0002

【従来の技術】この種の従来技術として、米国特許第4
,840460号(特開平2−12「液晶表示装置の画
素および液晶表示装置における画素のグレースケールを
実現する方法」)が公知である。即ち、図1に液晶表示
パネルの1つの画素領域をパネルと垂直に切出して示す
ように、ガラスのような透明基板1の内面に制御コンデ
ンサ電極2が形成され、その制御コンデンサ電極2の上
から透明基板1の全面に渡って絶縁膜3が形成される。 その絶縁膜3上に4等分割された方形状の副画素電極4
1 乃至44 が形成される。これらの副画素電極と間
隔をおいて対向して設けられたガラスなどの透明基板5
の内面に共通電極6が形成され、共通電極6と副画素電
極4i (i=1〜4)との間に液晶7が封入されてい
る。制御コンデンサ電極2、副画素電極4i 及び共通
電極6はITOなどで作られた透明な電極である。この
ようにして1画素は副画素電極41 〜44 と対応し
て、副画素F1 〜F4 に4分割される。図2に示す
ように各副画素電極4i と制御コンデンサ電極2との
間に絶縁膜3を誘電体とする制御コンデンサCciが形
成され、また副画素電極4i と共通電極6との間に液
晶7を誘電体とする液晶コンデンサCLCi が形成さ
れている。図1の画素の電気的等価回路を図3に示す。 符号Cci及びCLCi を静電容量を表わすのに流用
すると、 CC1>CC2>CC3>CC4          
(1)となるように、制御コンデンサ電極2の各副画素
電極4i と重なる面積が調整されている。
[Prior Art] As a prior art of this type, US Patent No. 4
, No. 840460 (Japanese Unexamined Patent Publication No. 2-12 "Pixels of liquid crystal display device and method for realizing gray scale of pixels in liquid crystal display device") is known. That is, as shown in FIG. 1, where one pixel area of a liquid crystal display panel is cut out perpendicularly to the panel, a control capacitor electrode 2 is formed on the inner surface of a transparent substrate 1 such as glass, and a control capacitor electrode 2 is formed on the inner surface of a transparent substrate 1 such as glass. An insulating film 3 is formed over the entire surface of the transparent substrate 1. A rectangular sub-pixel electrode 4 divided into four equal parts on the insulating film 3
1 to 44 are formed. A transparent substrate 5 made of glass or the like is provided facing these sub-pixel electrodes at a distance.
A common electrode 6 is formed on the inner surface of the pixel, and a liquid crystal 7 is sealed between the common electrode 6 and the sub-pixel electrodes 4i (i=1 to 4). The control capacitor electrode 2, subpixel electrode 4i, and common electrode 6 are transparent electrodes made of ITO or the like. In this way, one pixel is divided into four sub-pixels F1 to F4 corresponding to the sub-pixel electrodes 41 to 44. As shown in FIG. 2, a control capacitor Cci using an insulating film 3 as a dielectric is formed between each sub-pixel electrode 4i and a control capacitor electrode 2, and a liquid crystal 7 is formed between each sub-pixel electrode 4i and a common electrode 6. A liquid crystal capacitor CLCi is formed using the dielectric material CLCi. FIG. 3 shows an electrical equivalent circuit of the pixel in FIG. 1. When the symbols Cci and CLCi are used to represent capacitance, CC1>CC2>CC3>CC4
The area of the control capacitor electrode 2 overlapping with each sub-pixel electrode 4i is adjusted so that (1) is obtained.

【0003】制御コンデンサ電極2は図1の画素と隣接
して透明基板1上に形成されている薄膜トランジスタ(
TFT)8のドレイン電極Dに接続されている(図2)
。制御コンデンサ電極2と共通電極6との間には所定の
電圧Va がTFT8を介して供給される。TFT8が
オンに制御されたとき、各副画素Fi において供給電
圧Va は制御コンデンサCCiの両端電圧VCiと液
晶コンデンサCLCi の両端電圧VLCi とに分圧
される。VLCi は
The control capacitor electrode 2 is a thin film transistor (thin film transistor) formed on the transparent substrate 1 adjacent to the pixel in FIG.
Connected to the drain electrode D of TFT) 8 (Figure 2)
. A predetermined voltage Va is supplied between the control capacitor electrode 2 and the common electrode 6 via the TFT 8. When the TFT 8 is turned on, the supply voltage Va in each sub-pixel Fi is divided into the voltage VCi across the control capacitor CCi and the voltage VLCi across the liquid crystal capacitor CLCi. VLCi is

【0004】0004

【数1】 と表わされる。各制御コンデンサCCiの容量を(1)
 式のように設定することによって、各液晶コンデンサ
CLCi の両端電圧VLCi は VLC1 >VLC2 >VLC3 >VLC4   
             (3)に設定される。
It is expressed as [Equation 1]. The capacity of each control capacitor CCi is (1)
By setting as shown in the formula, the voltage VLCi across each liquid crystal capacitor CLCi becomes VLC1 > VLC2 > VLC3 > VLC4
(3) is set.

【0005】液晶の光透過が飽和状態となる電圧をVU
 、閾電圧をVL とすると、図4に示すように画素に
供給する電圧Va の大きさによって、液晶コンデンサ
CLCi の両端電圧VLCi は以下のような場合が
存在する。 (a) 全てのi=1〜4に対しVLCi =0の場合
。このときVa =0である。 (b) VLC1 =VU ,VLC2 =VL の場
合。VLC3 ,VLC4 はVL 以下である。この
時の供給電圧Va をVa1で表わす。 (c) VLC2 =VU ,VLC3 =VL の場
合。この時の供給電圧Va をVa2で表わす。 (d) VLC3 =VU ,VLC4 =VL の場
合。この時のVa をVa3で表わす。 (e) VLC4 =VU の場合。この時のVa を
Va4で表わす。
[0005] The voltage at which the light transmission of the liquid crystal is saturated is VU.
Assuming that the threshold voltage is VL, as shown in FIG. 4, depending on the magnitude of the voltage Va supplied to the pixel, the voltage VLCi across the liquid crystal capacitor CLCi may be as follows. (a) When VLCi = 0 for all i = 1 to 4. At this time, Va=0. (b) When VLC1 = VU and VLC2 = VL. VLC3 and VLC4 are below VL. The supply voltage Va at this time is represented by Va1. (c) When VLC2 = VU and VLC3 = VL. The supply voltage Va at this time is represented by Va2. (d) When VLC3 = VU and VLC4 = VL. Va at this time is expressed as Va3. (e) When VLC4 = VU. Va at this time is expressed as Va4.

【0006】供給電圧Vaiは、 Va1>Va2>Va3>Va4>0        
(4)である。供給電圧Va の大きさを変化させて多
階調表示が行われる。
[0006] The supply voltage Vai is as follows: Va1>Va2>Va3>Va4>0
(4). Multi-gradation display is performed by changing the magnitude of the supply voltage Va.

【0007】[0007]

【発明が解決しようとする課題】従来の技術では、副画
素Fi において、画素に供給する電圧Va がVai
のとき、液晶コンデンサCLCi の両端電圧VLCi
 は液晶の光透過が飽和する電圧VU に等しくなるよ
うに設定される。即ち、
[Problems to be Solved by the Invention] In the conventional technology, in the sub-pixel Fi, the voltage Va supplied to the pixel is Vai
When , the voltage VLCi across the liquid crystal capacitor CLCi
is set to be equal to the voltage VU at which the light transmission of the liquid crystal is saturated. That is,

【0008】[0008]

【数2】 各制御コンデンサCCiはその容量が(5) 式を満足
するように、副画素電極4i と重なる面積が設定され
る。(5) 式からわかるようにある副画素4i の液
晶コンデンサVLCi に印加される電圧を非常に小さ
くするには対応するその制御コンデンサCCiの容量を
小さくしなければならない。即ち副画素電極4i と重
なる制御コンデンサ電極2の面積を小さくする必要があ
る。しかしながら、この重なる面積が小さくなればなる
ほど(上述の例ではCC4の重なる面積が最も小さい)
、パターンずれなどによる副画素電極41 〜44 と
制御コンデンサ電極2の重なる面積のばらつきによって
容量値CCiの誤差が大きくなる。液晶コンデンサ電圧
VLCi は光透過の飽和電圧VU に対する偏差が大
きくなり、このため多階調表示の誤差が大きくなり、表
示品位が著しく低下する問題があった。
##EQU00002## The area of each control capacitor CCi overlapping with the sub-pixel electrode 4i is set so that its capacitance satisfies equation (5). As can be seen from equation (5), in order to make the voltage applied to the liquid crystal capacitor VLCi of a certain subpixel 4i very small, the capacitance of the corresponding control capacitor CCi must be made small. That is, it is necessary to reduce the area of the control capacitor electrode 2 that overlaps with the sub-pixel electrode 4i. However, the smaller this overlapping area becomes (in the above example, the overlapping area of CC4 is the smallest)
, the error in the capacitance value CCi increases due to variations in the overlapping area of the sub-pixel electrodes 41 to 44 and the control capacitor electrode 2 due to pattern misalignment or the like. The liquid crystal capacitor voltage VLCi has a large deviation from the light transmission saturation voltage VU, which increases the error in multi-gradation display, resulting in a problem that the display quality is significantly degraded.

【0009】また、副画素電極4i は画素電極を単に
行方向及び列方向に分割して形成しているので、副画素
が1つのみオンとなっている状態と複数の副画素がオン
となっている状態ではオン領域の中心が異なり、表示画
像の品質が良くなかった。この発明の第1の目的は制御
コンデンサ容量の製造ばらつきの影響による多階調表示
品位の低下が少ない液晶表示素子を提供することである
Furthermore, since the sub-pixel electrode 4i is formed by simply dividing the pixel electrode in the row and column directions, there are two conditions: when only one sub-pixel is on and when multiple sub-pixels are on. The center of the on-region was different in the state where the monitor was on, and the quality of the displayed image was poor. A first object of the present invention is to provide a liquid crystal display element in which multi-gradation display quality is less degraded due to manufacturing variations in control capacitor capacitance.

【0010】この発明の第2の目的は画素のオン領域が
増減してもその中心が移動せず、画像表示品位の優れた
液晶表示素子を提供することである。
A second object of the present invention is to provide a liquid crystal display element whose center does not move even if the on-area of a pixel increases or decreases, and which has excellent image display quality.

【0011】[0011]

【課題を解決するための手段】この発明の第1の観点に
よれば、各画素を構成する複数の互いに分離された副画
素電極が液晶を挟んで第2基板上の共通電極と対向して
第1基板上に配され、それら間に液晶コンデンサを形成
し、副画素電極の少くとも1つと第1絶縁膜を介して対
向する制御コンデンサ電極が第1基板と副画素電極の間
に設けられており、それによって上記少くとも1つの副
画素電極が上記共通電極との間に形成する液晶コンデン
サに直列に接続された制御コンデンサを形成し、上記制
御コンデンサ電極と共通電極との間に駆動電圧が供給さ
れるように構成された画素を有する液晶表示素子におい
て、この発明では、上記少くとも1つの副画素電極と第
2絶縁膜を介して対向するように付加コンデンサ電極が
形成され、それによって上記液晶コンデンサに等価的に
並列な付加コンデンサを形成している。
[Means for Solving the Problems] According to a first aspect of the present invention, a plurality of mutually separated sub-pixel electrodes constituting each pixel face a common electrode on a second substrate with a liquid crystal interposed therebetween. A control capacitor electrode is disposed on the first substrate, forming a liquid crystal capacitor therebetween, and facing at least one of the subpixel electrodes with a first insulating film interposed therebetween. The at least one sub-pixel electrode thereby forms a control capacitor connected in series with the liquid crystal capacitor formed between the at least one sub-pixel electrode and the common electrode, and a driving voltage is applied between the control capacitor electrode and the common electrode. In a liquid crystal display element having a pixel configured to be supplied with An additional capacitor is formed equivalently in parallel to the liquid crystal capacitor.

【0012】この発明の第2の観点によれば、各画素を
構成する複数の互いに分離された副画素電極が液晶を挟
んで第2基板上の共通電極と対向して第1基板上に配さ
れ、それら間に液晶コンデンサを形成し、副画素電極の
少くとも1つと第1絶縁膜を介して対向する制御コンデ
ンサ電極が第1基板と副画素電極の間に設けられており
、それによって上記少くとも1つの副画素電極が上記共
通電極との間に形成する液晶コンデンサに直列に接続さ
れた制御コンデンサを形成し、上記制御コンデンサ電極
と共通電極との間に駆動電圧が供給されるように構成さ
れた画素を有する液晶表示素子において、この発明では
、上記複数の副画素電極は、中央副画素領域と、その周
囲をほぼ同心状に囲む少なくとも1つのループ状副画素
領域を規定するように形成されている。
According to the second aspect of the present invention, a plurality of mutually separated sub-pixel electrodes constituting each pixel are arranged on the first substrate opposite to a common electrode on the second substrate with the liquid crystal interposed therebetween. A control capacitor electrode is provided between the first substrate and the sub-pixel electrode, forming a liquid crystal capacitor therebetween, and facing at least one of the sub-pixel electrodes with a first insulating film interposed therebetween. At least one sub-pixel electrode forms a control capacitor connected in series to a liquid crystal capacitor formed between the common electrode, and a driving voltage is supplied between the control capacitor electrode and the common electrode. In the liquid crystal display element having the configured pixels, in the present invention, the plurality of sub-pixel electrodes define a central sub-pixel region and at least one loop-shaped sub-pixel region substantially concentrically surrounding the central sub-pixel region. It is formed.

【0013】[0013]

【作用】この発明の第1の観点によれば、制御コンデン
サと直列に接続された液晶コンデンサに対して等価的に
並列に付加コンデンサが接続されるので、制御コンデン
サ電極及び付加コンデンサ電極のいずれの面積を変化さ
せてもその液晶コンデンサを構成する液晶に印加される
容量分割電圧を制御することができ、それだけ画素の設
計の自由度が大となる。
[Operation] According to the first aspect of the present invention, since the additional capacitor is connected equivalently in parallel to the liquid crystal capacitor connected in series with the control capacitor, neither the control capacitor electrode nor the additional capacitor electrode Even if the area is changed, the capacitance division voltage applied to the liquid crystal constituting the liquid crystal capacitor can be controlled, which increases the degree of freedom in pixel design.

【0014】この発明の第2の観点によれば、各画素を
構成する副画素が互いに同心状に配置されるので、副画
素の表示状態を変化させてもオン領域の中心は画素のほ
ぼ中心に固定されており、表示画像の品質を改善できる
According to the second aspect of the present invention, since the sub-pixels constituting each pixel are arranged concentrically with each other, even if the display state of the sub-pixels is changed, the center of the on area remains approximately at the center of the pixel. is fixed to improve the quality of the displayed image.

【0015】[0015]

【実施例】この発明の実施例をその1画素領域を切出し
て図5に示し、図1と対応する部分に同じ符号を付し、
重複説明を省略する。この実施例においては、制御コン
デンサ電極2は副画素電極相互間の十字ギャップGaと
全長に渡って重なると共に、この例ではほぼ長方形の画
素領域の四隅をそれぞれ所定の大きさ除去した太十字状
にITOで形成される。従って副画素電極間のギャップ
においては制御コンデンサ電極2に与えられる電圧によ
り液晶が駆動される。この発明の第1の観点によれば、
付加コンデンサ電極12と副画素電極4i (i=1〜
4)との間に絶縁膜11を誘電体とする付加コンデンサ
CSiが図6に示すように形成される。即ち、十字のギ
ャップGaで互いに分離された副画素電極41 〜44
 上に窒化シリコン(SiNx )などの絶縁膜11を
介して付加コンデンサ電極12が、この例ではアルミニ
ウムでU字状に形成される。U字状の付加コンデンサ電
極12はこれら副画素電極41 〜44 上を順次通過
していくよう形成されている。更に各行のそれぞれの画
素の付加コンデンサ電極12は図示しない配線により順
次接続され、液晶表示素子の動作時に一定の電位が与え
られる。
[Embodiment] An embodiment of the present invention is shown in FIG. 5 by cutting out one pixel area thereof, and parts corresponding to those in FIG. 1 are given the same reference numerals.
Omit duplicate explanations. In this embodiment, the control capacitor electrode 2 overlaps the entire length of the cross gap Ga between the sub-pixel electrodes, and is shaped like a thick cross by removing a predetermined amount from each of the four corners of a substantially rectangular pixel area in this example. Made of ITO. Therefore, in the gap between the sub-pixel electrodes, the liquid crystal is driven by the voltage applied to the control capacitor electrode 2. According to the first aspect of this invention,
Additional capacitor electrode 12 and sub-pixel electrode 4i (i=1~
4), an additional capacitor CSi using the insulating film 11 as a dielectric is formed as shown in FIG. That is, the sub-pixel electrodes 41 to 44 are separated from each other by a cross-shaped gap Ga.
An additional capacitor electrode 12 is formed thereon with an insulating film 11 made of silicon nitride (SiNx) or the like in a U-shape, made of aluminum in this example. The U-shaped additional capacitor electrode 12 is formed to pass over these sub-pixel electrodes 41 to 44 one after another. Furthermore, the additional capacitor electrodes 12 of each pixel in each row are sequentially connected by wiring (not shown), and a constant potential is applied during operation of the liquid crystal display element.

【0016】図5の画素の電気的等価回路は図7に示す
ように表わされる。即ち、付加コンデンサCSiは図示
してない配線により一定電位に保持されるため、等価的
には液晶コンデンサCLCi と並列に接続されている
。制御コンデンサ電極2と共通電極6との間に印加され
る駆動電圧Va は制御コンデンサ容量CCiと、液晶
コンデンサ容量CLCi 及び付加コンデンサ容量CS
iの合成容量CLCi +CSiとにより分圧され、液
晶コンデンサCLCi に印加される電圧VLCi は
The electrical equivalent circuit of the pixel in FIG. 5 is shown in FIG. That is, since the additional capacitor CSi is held at a constant potential by wiring (not shown), it is equivalently connected in parallel with the liquid crystal capacitor CLCi. The driving voltage Va applied between the control capacitor electrode 2 and the common electrode 6 is determined by the control capacitor capacitance CCi, the liquid crystal capacitor capacitance CLCi, and the additional capacitor capacitance CS.
The voltage VLCi that is divided by the combined capacitance CLCi +CSi of i and is applied to the liquid crystal capacitor CLCi is

【0017】[0017]

【数3】 で表わされる。従来例では液晶コンデンサ電圧VLCi
 を設定するのを、制御コンデンサ容量CCiの調整の
みで行っていたが、この発明では付加容量CSiの調整
が併用される。例えばコンデンサCLC4 の両端電圧
VLC4 がVLC1 〜VLC4 の中で最も小さく
設定される場合、CC4が小さくされると共にCS4は
大きく設定され、これにより(6) 式のCC4/(C
LC4 +CS4+CC4)の値がi=1〜3の場合よ
り最も小さく設定される。このように付加コンデンサC
Siを併用すると、制御コンデンサ容量CCiは従来の
ようにあまり小さくせず、製造ばらつきの影響が問題に
ならない程度にとどめられる。付加コンデンサ電極12
は製造ばらつきによりその位置がずれても、各副画素電
極4i と重なる面積があまり変らないようにして容量
値の製造ばらつきを小さく抑えるのが望ましい。
It is expressed as [Equation 3]. In the conventional example, the liquid crystal capacitor voltage VLCi
was set by adjusting only the control capacitor capacitance CCi, but in the present invention, adjustment of the additional capacitance CSi is also used. For example, when the voltage VLC4 across the capacitor CLC4 is set to the smallest among VLC1 to VLC4, CC4 is made smaller and CS4 is set larger, so that CC4/(C
LC4+CS4+CC4) is set to the smallest value than when i=1 to 3. In this way, the additional capacitor C
When Si is used in combination, the control capacitor capacitance CCi is not made so small as in the conventional case, and the influence of manufacturing variations can be kept to a level where it does not become a problem. Additional capacitor electrode 12
Even if the position of the sub-pixel electrode 4i is shifted due to manufacturing variations, it is desirable that the area overlapping with each sub-pixel electrode 4i does not change much, so that manufacturing variations in capacitance values can be suppressed to a small level.

【0018】太十字状制御コンデンサ電極2は副画素電
極相互間のギャップと重なっているので、これらのギャ
ップ上の液晶には、制御コンデンサ電極2と共通電極6
との間に印加される電圧Va が絶縁膜3,11と液晶
7とで分圧され、電圧Va の大きさによって、この液
晶部分を光透過或いは光遮断の状態に制御し、副画素電
極と同様に多階調表示に寄与するようにする。これによ
り画素の開口率が向上される。
Since the thick cross-shaped control capacitor electrode 2 overlaps the gap between the sub-pixel electrodes, the control capacitor electrode 2 and the common electrode 6 are connected to the liquid crystal above these gaps.
The voltage Va applied between the insulating films 3 and 11 and the liquid crystal 7 is divided between the insulating films 3 and 11 and the liquid crystal 7, and depending on the magnitude of the voltage Va, this liquid crystal portion is controlled to transmit or block light, and is connected to the sub-pixel electrode. Similarly, it is made to contribute to multi-gradation display. This improves the aperture ratio of the pixel.

【0019】なお、制御コンデンサCC1〜CC4のう
ち、最大容量を形成する副画素電極41 の領域の液晶
には最大の電圧が印加されることになる。画素に供給さ
れる電圧Va を一定とした時に、この最大電圧をでき
るだけ大とするには制御コンデンサ電極2は副画素電極
41 の全面と対向して重なる形状にすればよいが、副
画素電極41 と制御コンデンサ電極2とを電気的に接
続することもできる。後述の実施例はこの場合に当り、
制御コンデンサCC1の容量を無限大にしたのと等価で
ある。その場合は制御コンデンサ電極2と副画素電極4
1 との重なりは任意でよく、重なりが無くてもよい。 電圧対透過率特性の設計 副画素F1 〜F4 の電圧対透過率特性を上述のよう
に付加コンデンサ容量CSiと制御コンデンサ容量CC
iとにより制御することによって、画素全体の透過率特
性を設計する自由度が増え、種々の好ましい特性を得る
ことができる。 (イ)副画素F1 〜F4 の特性を図8のAのように
電圧軸の方向に間隔をあけて設定することにより、画素
の総合特性を図8のBのように階段状にすることができ
る。 (ロ)副画素F1 〜F4 の特性を図9のAのように
、副画素Fi の光透過率が90%となるときの印加電
圧Va と副画素Fi+1 の光透過率が10%となる
ときの印加電圧Va とが等しくなるように副画素F1
 〜F4 の特性を設定すれば、画素の総合特性は図9
のBに示すように直線状となり、その傾斜を副画素に分
割しない場合より緩やかにすることができる。このよう
にすると、各副画素Fi の図9のAにおける直線から
の透過率の偏差は、図9のBの総合特性においては結果
としてより小さく圧縮された特性となり直線性が改善さ
れる。また画素の総合特性の直線領域も、図9のAにお
ける個々の特性より広くなる。このため通常液晶表示素
子をビテオ信号の表示器として用いるとき、印加電圧値
を調整して直線性を補正する所謂γ(ガンマ)補正が不
要となる。また電圧対透過率特性が緩やかであるため、
ビデオ表示等を行なうとき、ソースバスに信号を供給す
る駆動ICの出力偏差に対するマージンを大きくできる
。図9のAに示すようにそれぞれの副画素の電圧対透過
率特性を設定すると、図9のBに示すように画素の透過
率が飽和する電圧を図8のBの場合より低く抑えられ、
より低電圧駆動が可能となる。 (ハ)カラー表示用のTN形液晶表示素子の本質的な特
性として旋光分散に基づいてR,G,Bの各色毎に画素
の電圧対透過率特性が図10のAに示すように異なるこ
とが知られているが、この発明によれば、画素の電圧対
透過率特性の設計の自由度が増えたため所望の特性に設
計するのが容易となり、図10のBのように各色ともほ
ぼ同じ特性に補正できる。なおこの補正は画素が副画素
に分割されない場合でも、制御コンデンサ容量CC と
付加容量CS とにより液晶コンデンサ電圧  VLC
=Va CC /(CLC+CS +CC )を各色毎
に調整できるので、上記と同様の補正が可能である。
Note that among the control capacitors CC1 to CC4, the maximum voltage is applied to the liquid crystal in the region of the sub-pixel electrode 41 that forms the maximum capacitance. When the voltage Va supplied to the pixel is constant, in order to make this maximum voltage as large as possible, the control capacitor electrode 2 should be shaped so that it faces and overlaps the entire surface of the subpixel electrode 41. and the control capacitor electrode 2 can also be electrically connected. The examples described below correspond to this case,
This is equivalent to making the capacitance of the control capacitor CC1 infinite. In that case, control capacitor electrode 2 and subpixel electrode 4
The overlap with 1 may be arbitrary, and there may be no overlap. Design of voltage vs. transmittance characteristics The voltage vs. transmittance characteristics of subpixels F1 to F4 are determined by the additional capacitor capacitance CSi and the control capacitor capacitance CC as described above.
By controlling by i, the degree of freedom in designing the transmittance characteristics of the entire pixel increases, and various preferable characteristics can be obtained. (B) By setting the characteristics of the sub-pixels F1 to F4 at intervals in the voltage axis direction as shown in A of FIG. 8, the overall characteristics of the pixels can be made step-like as shown in B of FIG. can. (b) The characteristics of the sub-pixels F1 to F4 are as shown in A in FIG. 9, where the applied voltage Va is when the light transmittance of the sub-pixel Fi is 90% and when the light transmittance of the sub-pixel Fi+1 is 10%. subpixel F1 so that the applied voltage Va of
If the characteristics of ~F4 are set, the overall characteristics of the pixel are as shown in Figure 9.
As shown in B of FIG. 2, the pixel becomes a straight line, and its slope can be made gentler than when the pixel is not divided into subpixels. In this way, the deviation of the transmittance of each sub-pixel Fi from the straight line in A of FIG. 9 results in a smaller compressed characteristic in the overall characteristic of B in FIG. 9, and the linearity is improved. Furthermore, the linear region of the overall characteristic of the pixel is also wider than the individual characteristics in A of FIG. Therefore, when a liquid crystal display element is normally used as a video signal display, so-called γ (gamma) correction, which corrects linearity by adjusting the applied voltage value, is not necessary. In addition, since the voltage vs. transmittance characteristics are gentle,
When performing video display or the like, it is possible to increase the margin for output deviation of the drive IC that supplies signals to the source bus. When the voltage vs. transmittance characteristics of each sub-pixel are set as shown in A of FIG. 9, the voltage at which the pixel transmittance is saturated can be suppressed to a lower level than in the case of B of FIG. 8, as shown in B of FIG.
Lower voltage driving becomes possible. (c) As an essential characteristic of a TN type liquid crystal display element for color display, the voltage versus transmittance characteristics of the pixel differ for each color of R, G, and B based on optical rotation dispersion, as shown in A in Figure 10. However, according to this invention, the degree of freedom in designing the voltage vs. transmittance characteristics of the pixel has increased, making it easier to design the desired characteristics, and as shown in B in FIG. 10, each color is almost the same. Can be corrected according to characteristics. Note that this correction applies even if a pixel is not divided into subpixels, since the liquid crystal capacitor voltage VLC is adjusted by the control capacitor capacitance CC and additional capacitance CS.
Since =Va CC /(CLC+CS +CC) can be adjusted for each color, the same correction as above is possible.

【0020】これ迄の説明では画素を4個の副画素に分
割する場合を示したが、一般にはn(2以上の整数)個
に分割できることは明らかである。この発明の第2の観
点によれば、各画素を分割した複数の副画素の領域を互
いに同心状に配置する。例えば、図5と対応するものに
同じ符号を付けて図11に示すように、ITOの画素電
極は方形ループ状のギャプGaにより2つの方形ループ
状副画素電極41,42 に同心状に分割されている。 副画素電極41 の中央は方形窓Wが形成されている。 制御コンデンサ電極2は図12に示すように、副画素電
極41 のほぼ半分の領域とは重ならないように穴2a
が形成され、その穴2a以外で副画素電極41,42 
及び方形窓Wと絶縁膜3を介して対抗するよう画素のほ
ぼ全領域に渡ってITOにより形成されている。この例
では中央窓Wにおいて絶縁膜3を介して電気的に露出さ
れる制御コンデンサ電極2の領域は副画素領域F1 を
規定する。従って、制御コンデンサ電極2と共通電極6
との間に印加する駆動電圧Vaを増加していくと、最初
に中央窓Wの副画素領域F1 がオンとなり、次に副画
素電極41 が規定する副画素領域F2 が追加的にオ
ンとなり、最後に副画素電極42 が規定する副画素領
域F3 が追加的にオンとなる。このようにオン領域が
増減してもそのオン領域の中心位置は画素のほぼ中央に
固定しているため、各画素がこのように構成された液晶
表示素子によれば人間の視覚にとって見易い画像を表示
でき、また図1のように画素電極を行方向及び列方向に
分割した場合に比べて画像の表示品質が良いことが実験
で確かめられた。 他の実施例 各画素を2つの副画素で構成し、第1の副画素電極を制
御コンデンサ電極に接続した場合のこの発明の第1と第
2の観点の組み合わせによる実施例の平面図、そのA−
A断面図及びB−B断面図を図13,図14及び図15
に、図5,図6と対応する部分に同じ符号を付して示す
。透明基板1上に島状に遮光層13が形成される。遮光
層13はTFTに光が入射しないようにするものである
。透明基板1及び遮光層13上に酸化シリコン(SiO
2 )のような絶縁膜14が形成され、その上にループ
状の制御コンデンサ電極2がITOなどにより形成され
る。制御コンデンサ電極2及び絶縁膜14上に酸化シリ
コンのような絶縁膜15が形成され、その上にITOな
どによりソースバス21、ソース電極21a、ドレイン
電極22、副画素電極41 ,42 が形成される。副
画素電極41 は制御コンデンサ電極2上の絶縁膜15
に形成されたコンタクトホール15Hにおいて、制御コ
ンデンサ電極2に接触して形成され、互いに導通状態と
される。また副画素電極41 はTFT8のドレイン電
極22迄延長され、互いに連結される。ソース電極21
a及びドレイン電極22にまたがってアモルファスシリ
コンなどの半導体層23が形成される。半導体層23及
び副画素電極41 ,42 上にまたがって窒化シリコ
ン(SiNx )などのゲート絶縁膜24が形成され、
その上に例えばアルミニウムによりゲートバス25、ゲ
ート電極25a、付加コンデンサ電極12が同時に形成
される。
Although the explanation so far has shown the case where a pixel is divided into four sub-pixels, it is clear that it can generally be divided into n (an integer of 2 or more). According to the second aspect of the invention, a plurality of subpixel regions obtained by dividing each pixel are arranged concentrically with each other. For example, as shown in FIG. 11 with the same reference numerals assigned to those corresponding to those in FIG. 5, an ITO pixel electrode is concentrically divided into two rectangular loop-shaped subpixel electrodes 41 and 42 by a rectangular loop gap Ga. ing. A rectangular window W is formed in the center of the subpixel electrode 41 . As shown in FIG. 12, the control capacitor electrode 2 is formed in a hole 2a so as not to overlap with approximately half of the sub-pixel electrode 41.
is formed, and sub-pixel electrodes 41 and 42 are formed in areas other than the hole 2a.
The pixel is formed of ITO over almost the entire area of the pixel so as to face the rectangular window W with the insulating film 3 interposed therebetween. In this example, the region of the control capacitor electrode 2 that is electrically exposed through the insulating film 3 at the central window W defines a sub-pixel region F1. Therefore, the control capacitor electrode 2 and the common electrode 6
When the driving voltage Va applied between the two subpixel electrodes 41 and 41 is increased, the subpixel region F1 of the center window W is first turned on, and then the subpixel region F2 defined by the subpixel electrode 41 is additionally turned on. Finally, the subpixel region F3 defined by the subpixel electrode 42 is additionally turned on. Even if the on-area increases or decreases in this way, the center position of the on-area is fixed at approximately the center of the pixel, so a liquid crystal display element in which each pixel is configured in this way can produce images that are easy to see for human eyes. Experiments have confirmed that the display quality of the image is better than that in the case where the pixel electrodes are divided into rows and columns as shown in FIG. Other Embodiments A plan view of an embodiment according to the combination of the first and second aspects of the present invention in which each pixel is configured with two sub-pixels and the first sub-pixel electrode is connected to a control capacitor electrode. A-
A cross-sectional view and B-B cross-sectional view are shown in Figures 13, 14, and 15.
In the figure, parts corresponding to those in FIGS. 5 and 6 are denoted by the same reference numerals. A light shielding layer 13 is formed in an island shape on the transparent substrate 1. The light shielding layer 13 prevents light from entering the TFT. Silicon oxide (SiO
An insulating film 14 as shown in 2) is formed, and a loop-shaped control capacitor electrode 2 is formed thereon using ITO or the like. An insulating film 15 such as silicon oxide is formed on the control capacitor electrode 2 and the insulating film 14, and a source bus 21, a source electrode 21a, a drain electrode 22, and subpixel electrodes 41 and 42 are formed thereon using ITO or the like. . The subpixel electrode 41 is the insulating film 15 on the control capacitor electrode 2.
The contact hole 15H formed in the contact hole 15H is formed in contact with the control capacitor electrode 2, and is electrically connected to the control capacitor electrode 2. Further, the subpixel electrode 41 is extended to the drain electrode 22 of the TFT 8 and connected to each other. Source electrode 21
A semiconductor layer 23 made of amorphous silicon or the like is formed spanning the electrode 22 and the drain electrode 22 . A gate insulating film 24 made of silicon nitride (SiNx) or the like is formed over the semiconductor layer 23 and the sub-pixel electrodes 41 and 42.
Thereon, a gate bus 25, a gate electrode 25a, and an additional capacitor electrode 12 are simultaneously formed of aluminum, for example.

【0021】上述のようにTFT8、副画素電極41 
,42 等が形成された透明基板1は共通電極6が内面
に形成されている透明基板5と対向して配され、それら
の基板間に液晶7が封入される。ソースバス21とゲー
トバス25の交叉部、及びソースバス21と付加コンデ
ンサ電極12の交叉部には島状半導体層23a及び23
bがゲート絶縁膜24の下に積層して形成され、絶縁性
を高めている。ゲートバス25とソースバス21の交叉
点の近傍にTFT8が形成される。左右のソースバス2
1及び上下のゲートバス25で囲まれた領域内に小面積
の副画素電極41 と大面積の副画素電極42が形成さ
れる。制御コンデンサ電極2は副画素電極42 の周縁
部を囲むと共にその周縁部と重なってループ状に形成さ
れる。副画素電極41 と制御コンデンサ電極2とは既
に述べたようにコンタクトホール15Hで互いに電気的
に接続される。
As mentioned above, the TFT 8 and the sub-pixel electrode 41
, 42, etc., is disposed opposite to a transparent substrate 5 having a common electrode 6 formed on its inner surface, and a liquid crystal 7 is sealed between these substrates. At the intersection between the source bus 21 and the gate bus 25 and at the intersection between the source bus 21 and the additional capacitor electrode 12, there are island-shaped semiconductor layers 23a and 23.
b is formed in a stacked manner under the gate insulating film 24 to improve insulation. A TFT 8 is formed near the intersection of the gate bus 25 and the source bus 21 . Left and right source bus 2
A sub-pixel electrode 41 with a small area and a sub-pixel electrode 42 with a large area are formed in a region surrounded by the gate bus 1 and the upper and lower gate buses 25. The control capacitor electrode 2 is formed in a loop shape, surrounding the periphery of the sub-pixel electrode 42 and overlapping with the periphery. As already mentioned, the subpixel electrode 41 and the control capacitor electrode 2 are electrically connected to each other through the contact hole 15H.

【0022】副画素電極41 に接続された制御コンデ
ンサ電極2は副画素電極42 を囲んで同心状に配置さ
れているので、液晶表示素子の駆動時にTFT8を通し
てある電圧Va が与えられた時にまず副画素42 を
囲む制御コンデンサ電極2の領域(副画素41 領域も
含む)がオン(光透過)となり、電圧Va をそれより
所定値だけ高くすると更に副画素42 の領域もオンと
なる。前述のように画素の表示領域を同心的に制御する
と図5のように副画素を縦、横に配置した場合より表示
品位がよい。
Since the control capacitor electrode 2 connected to the sub-pixel electrode 41 is arranged concentrically surrounding the sub-pixel electrode 42, when a certain voltage Va is applied through the TFT 8 when driving the liquid crystal display element, the sub-pixel electrode 2 is first connected to the sub-pixel electrode 41. The region of the control capacitor electrode 2 surrounding the pixel 42 (including the sub-pixel 41 region) is turned on (light transmission), and when the voltage Va is increased by a predetermined value, the region of the sub-pixel 42 is also turned on. When the display area of the pixels is controlled concentrically as described above, the display quality is better than when the sub-pixels are arranged vertically and horizontally as shown in FIG.

【0023】付加コンデンサ電極12はゲート絶縁膜2
4を介して副画素電極42 上に形成されている。付加
コンデンサ電極12はこの実施例ではH字状をしており
、その水平部12Cが制御コンデンサ電極2のほぼ中央
を水平に横切って延び、その両端部にそれぞれ垂直部1
2A,12Bが設けられている。垂直部12A,12B
は制御コンデンサ電極2の側縁と重なって延びている。 水平部12Cは両端が延長されてゲートバス25の延長
方向に隣接する画素の付加コンデンサ電極12と接続さ
れている。液晶表示素子の動作時には全ての画素のこれ
ら付加コンデンサ電極12は水平部12Cの延長端に一
定の直流電圧を与えることによりあらかじめ決めた一定
電位に保持される。制御コンデンサ電極2は、副画素電
極41 ,42 間のギャップGaと重なるように配さ
れる。
[0023] The additional capacitor electrode 12 is connected to the gate insulating film 2.
4 on the sub-pixel electrode 42. The additional capacitor electrode 12 has an H-shape in this embodiment, and its horizontal portion 12C extends horizontally across approximately the center of the control capacitor electrode 2, and has vertical portions 1 at both ends thereof.
2A and 12B are provided. Vertical parts 12A, 12B
extends overlapping the side edges of the control capacitor electrode 2. Both ends of the horizontal portion 12C are extended and connected to the additional capacitor electrodes 12 of adjacent pixels in the extending direction of the gate bus 25. During operation of the liquid crystal display element, these additional capacitor electrodes 12 of all pixels are maintained at a predetermined constant potential by applying a constant DC voltage to the extended end of the horizontal portion 12C. The control capacitor electrode 2 is arranged so as to overlap the gap Ga between the sub-pixel electrodes 41 and 42.

【0024】制御コンデンサ電極2と副画素電極42 
との間に制御コンデンサCC2が形成されるが、制御コ
ンデンサ電極2と副画素電極41 とは電気的に短絡さ
れているので、制御コンデンサCC1は形成されない(
或いはCC1は形成されているが両端が短絡されている
と見ることもできる)。付加コンデンサ電極12と副画
素電極42 との間に付加容量CS2が形成される。こ
の例では、副画素電極41 と付加コンデンサ電極12
との間に直接付加容量CS1を形成せず、代りに制御コ
ンデンサ電極2(副画素電極41 と接続されている)
と付加コンデンサ電極12との間に形成される。副画素
電極41 と共通電極6との間に液晶コンデンサCLC
1aが、副画素電極間のギャップGaと対向する制御コ
ンデンサ電極2と共通電極6との間に液晶コンデンサC
LC1bが、また副画素電極42 と共通電極6との間
に液晶コンデンサCLC2 がそれぞれ形成される。従
って図13,図14及び図15の実施例における画素の
電気的等価回路は図16に示すものとなる。
Control capacitor electrode 2 and subpixel electrode 42
However, since the control capacitor electrode 2 and the sub-pixel electrode 41 are electrically short-circuited, the control capacitor CC1 is not formed (
Alternatively, it can be seen that CC1 is formed but both ends are short-circuited). An additional capacitor CS2 is formed between the additional capacitor electrode 12 and the sub-pixel electrode 42. In this example, a subpixel electrode 41 and an additional capacitor electrode 12
No additional capacitance CS1 is formed directly between the control capacitor electrode 2 (connected to the sub-pixel electrode 41) instead.
and the additional capacitor electrode 12. A liquid crystal capacitor CLC is connected between the sub-pixel electrode 41 and the common electrode 6.
1a is a liquid crystal capacitor C between the control capacitor electrode 2 and the common electrode 6 facing the gap Ga between the sub-pixel electrodes.
A liquid crystal capacitor CLC2 is formed between the sub-pixel electrode 42 and the common electrode 6. Therefore, the electrical equivalent circuit of the pixel in the embodiments shown in FIGS. 13, 14 and 15 is as shown in FIG.

【0025】図13の例では、制御コンデンサ電極2が
副画素電極42 の周縁部と重ねられる寸法は12μm
 程度であるが、もし従来例のように付加容量を併用し
ない構成にすると、この重ねられる寸法は例えば 1.
5μm 程度と極めて小さくする必要があり、パターン
ずれなどに対する製造マージンが取れなくなる。図13
から分るように、付加コンデンサ電極12の垂直部12
A,12Bはその幅方向の中間において制御コンデンサ
2の両側縁と重なっているので、付加コンデンサ電極1
2の上下及び左右方向の製造上の位置ずれに対しては、
副画素電極42 と重なる面積及び制御コンデンサ電極
2(副画素電極41 と接続されている)と重なる面積
は共にほとんど変化しない。従ってパターンずれなどに
よる製造ばらつきに対し付加コンデンサ容量CS1,C
S2はほぼ一定に保たれる。なおこの付加コンデンサC
S1,CS2は信号電荷保持のための蓄積容量として作
用するものであり、リーク電流が増大する高温動作での
表示の安定性向上などに寄与する。
In the example of FIG. 13, the dimension at which the control capacitor electrode 2 overlaps the peripheral edge of the sub-pixel electrode 42 is 12 μm.
However, if a configuration is adopted in which additional capacitance is not used as in the conventional example, the dimensions of this overlap would be, for example, 1.
It needs to be extremely small, about 5 .mu.m, and it is difficult to ensure a manufacturing margin against pattern misalignment. Figure 13
As can be seen, the vertical portion 12 of the additional capacitor electrode 12
Since A and 12B overlap both side edges of the control capacitor 2 at the middle in the width direction, the additional capacitor electrode 1
Regarding manufacturing positional deviations in the vertical and horizontal directions of 2.
Both the area overlapping with the sub-pixel electrode 42 and the area overlapping with the control capacitor electrode 2 (connected to the sub-pixel electrode 41) hardly change. Therefore, additional capacitor capacitance CS1,C
S2 is kept approximately constant. Note that this additional capacitor C
S1 and CS2 act as storage capacitors for holding signal charges, and contribute to improving display stability during high-temperature operation where leakage current increases.

【0026】図13,図14及び図15においては副画
素電極42 を囲むように制御コンデンサ電極2が形成
されているが、図13に対応するものを図17に簡略化
して示すように、制御コンデンサ電極2を島状に中央に
配置し、その周縁と重なりかつ囲むように副画素電極4
2 を形成してもよい。その場合は印加電圧Vaを増加
していくと中央の副画素領域がオンとなり、次にその外
周の副画素領域もオンとなる。
In FIGS. 13, 14, and 15, the control capacitor electrode 2 is formed to surround the sub-pixel electrode 42, but as shown in FIG. 17, the control capacitor electrode 2 corresponding to FIG. A capacitor electrode 2 is arranged in the center in the form of an island, and a sub-pixel electrode 4 is arranged so as to overlap and surround the periphery of the capacitor electrode 2.
2 may be formed. In that case, as the applied voltage Va is increased, the central sub-pixel region is turned on, and then the sub-pixel regions on its outer periphery are also turned on.

【0027】更に、図18に断面でのみ示すように、図
13,図14及び図15の実施例におけるTFT8のソ
ース電極21a及びドレイン電極22を制御コンデンサ
電極2と同じ層に形成し、副画素電極41 と制御コン
デンサ電極2を連続した一体構造に形成することもでき
る。図13,図14及び図15の実施例では副画素電極
42 の上に付加コンデンサ電極12を設けたが、図1
9及び図20に示すように副画素電極41 ,42 の
下の制御コンデンサ電極2と同じ面に設けてもよい。即
ち、図19及び図20に示す実施例においては図13に
おける方形ループ状の制御コンデンサ電極2の一部を除
去して通路2Aを形成し、その通路2Aを変形H形付加
コンデンサ電極12の水平部12Cが通され、H形電極
12の垂直部12Aと12Bはそれぞれ方形ループ状電
極2の外側と内側に配置されている。またこの実施例に
おいては副画素電極41 はその両側縁が制御コンデン
サ電極2の側縁及び付加コンデンサ電極12と重なるよ
うに形成され、かつほぼ長方形の副画素電極42 の長
側辺と間隔Gaをおいて平行にほぼ全長に沿って延びて
いる。H状付加コンデンサ電極12の垂直部12Aはそ
の両端が延長されそれぞれ上下に隣接する画素の付加コ
ンデンサ電極の垂直部12Aに接続され、液晶表示素子
の動作時には付加コンデンサ電極12は一定の電位に保
持される。 この実施例におけるそれぞれの容量の接続等価回路も図
16に示すものと全く同じになる。
Furthermore, as shown only in cross section in FIG. 18, the source electrode 21a and drain electrode 22 of the TFT 8 in the embodiments of FIGS. 13, 14, and 15 are formed in the same layer as the control capacitor electrode 2, and the subpixel It is also possible to form the electrode 41 and the control capacitor electrode 2 into a continuous integral structure. In the embodiments shown in FIGS. 13, 14, and 15, the additional capacitor electrode 12 is provided on the sub-pixel electrode 42, but in the embodiments shown in FIGS.
9 and 20, it may be provided on the same surface as the control capacitor electrode 2 under the sub-pixel electrodes 41 and 42. That is, in the embodiment shown in FIGS. 19 and 20, a passage 2A is formed by removing a part of the rectangular loop-shaped control capacitor electrode 2 in FIG. The vertical portions 12A and 12B of the H-shaped electrode 12 are arranged on the outside and inside of the square loop-shaped electrode 2, respectively. Further, in this embodiment, the sub-pixel electrode 41 is formed so that its both sides overlap with the side edges of the control capacitor electrode 2 and the additional capacitor electrode 12, and has a distance Ga from the long side of the substantially rectangular sub-pixel electrode 42. and extends parallel to each other along almost the entire length. Both ends of the vertical portion 12A of the H-shaped additional capacitor electrode 12 are extended and connected to the vertical portions 12A of the additional capacitor electrodes of the vertically adjacent pixels, and the additional capacitor electrode 12 is maintained at a constant potential during operation of the liquid crystal display element. be done. The connection equivalent circuit of each capacitor in this embodiment is also exactly the same as that shown in FIG.

【0028】上述した各実施例においてはすべての副画
素電極41 ,42 ,…に対しそれぞれ付加コンデン
サCS1,CS2,…を設けた場合を示したが、場合に
よっては少くとも1つの副画素電極には付加コンデンサ
を接続しなくてもよい。例えば図13,図14及び図1
5に示す実施例において付加コンデンサCS1を省略し
た実施例を簡略化して図21,図22及び図23に示す
。この実施例においては付加コンデンサ電極12はほぼ
長方形の副画素電極42 の一側縁部とゲート絶縁膜2
4を介して重なるようにゲートバス25と平行に同じ材
料(例えばアルミニウム)で同時に形成されている。副
画素電極41 は図13,図14及び図15の実施例と
同様に絶縁膜15に形成されたコンタクトホール15H
を通して制御コンデンサ電極2に接続されている。制御
コンデンサ電極2は付加コンデンサ電極12と互いに重
なっておらず、従ってこの実施例においては副画素電極
41には付加コンデンサが接続されていない。この実施
例の画素の電気的等価回路は図16において付加コンデ
ンサCS1を除去したものと同一である。
In each of the above-mentioned embodiments, the case is shown in which additional capacitors CS1, CS2, . . . are provided for all the sub-pixel electrodes 41, 42, . There is no need to connect an additional capacitor. For example, FIGS. 13, 14 and 1
A simplified embodiment in which the additional capacitor CS1 is omitted from the embodiment shown in FIG. 5 is shown in FIGS. 21, 22, and 23. In this embodiment, the additional capacitor electrode 12 consists of one side edge of the substantially rectangular sub-pixel electrode 42 and the gate insulating film 2.
They are simultaneously formed of the same material (for example, aluminum) in parallel with the gate bus 25 so as to overlap with each other through the gate bus 25. The subpixel electrode 41 is formed in the contact hole 15H formed in the insulating film 15 as in the embodiments of FIGS. 13, 14, and 15.
It is connected to the control capacitor electrode 2 through. The control capacitor electrode 2 and the additional capacitor electrode 12 do not overlap each other, so that in this embodiment no additional capacitor is connected to the sub-pixel electrode 41. The electrical equivalent circuit of the pixel in this embodiment is the same as that in FIG. 16 with the additional capacitor CS1 removed.

【0029】同様に図19,図20に示す実施例におい
て付加コンデンサCS1を除去した実施例を簡略化して
図24,図25及び図26に示す。この実施例では付加
コンデンサ電極12はITOにより制御コンデンサ電極
2と同じ面に同時に形成され、副画素電極42 と重な
るようにソースバス21と同じ方向に延長されている。 副画素電極41 は絶縁膜15に形成されたコンタクト
ホール15Hを通して制御コンデンサ電極2に接続され
ているが付加コンデンサ電極12とは互いに重ならない
。従って副画素電極41 には付加コンデンサが接続さ
れておらず、画素の電気的等価回路は図16において付
加コンデンサCS1を除去したものと同一である。
Similarly, a simplified embodiment in which the additional capacitor CS1 is removed from the embodiment shown in FIGS. 19 and 20 is shown in FIGS. 24, 25, and 26. In this embodiment, the additional capacitor electrode 12 is formed of ITO on the same surface as the control capacitor electrode 2 and extends in the same direction as the source bus 21 so as to overlap with the sub-pixel electrode 42 . The subpixel electrode 41 is connected to the control capacitor electrode 2 through a contact hole 15H formed in the insulating film 15, but does not overlap with the additional capacitor electrode 12. Therefore, no additional capacitor is connected to the sub-pixel electrode 41, and the electrical equivalent circuit of the pixel is the same as that in FIG. 16 with the additional capacitor CS1 removed.

【0030】前述のようにこの発明の第1の観点の原理
による付加コンデンサの効果はその付加コンデンサが接
続される副画素電極に対する制御コンデンサの設計自由
度を高める点にある。従って図21,図22及び図23
の実施例及び図24,図25及び図26の実施例から明
らかなように制御コンデンサが直列に接続されない副画
素電極に対してはこの発明の原理を適用できないので、
付加コンデンサを設けなくてもよい。しかしながら付加
コンデンサを接続することにより液晶コンデンサの容量
が増加し、それだけ電荷を多く蓄積できるので周知のよ
うに高温におけるリーク電流の増大に対し電圧低下を遅
くする効果が得られる。
As described above, the effect of the additional capacitor according to the principle of the first aspect of the present invention is that it increases the degree of freedom in designing the control capacitor for the sub-pixel electrode to which the additional capacitor is connected. Therefore, FIGS. 21, 22 and 23
As is clear from the embodiment and the embodiments of FIGS. 24, 25, and 26, the principle of the present invention cannot be applied to subpixel electrodes in which control capacitors are not connected in series.
There is no need to provide an additional capacitor. However, by connecting an additional capacitor, the capacitance of the liquid crystal capacitor increases, and a correspondingly larger amount of charge can be stored.As is well known, this has the effect of slowing down the voltage drop in response to an increase in leakage current at high temperatures.

【0031】[0031]

【発明の効果】以上説明したように、この発明の第1の
観点によれば複数の副画素のうち少くとも1つの副画素
Fi においては従来の制御コンデンサCCiと共に付
加コンデンサCSiが液晶コンデンサCLCi の両端
電圧VLCi を決定するのに用いられ、その副画素の
電圧対透過率特性の設計自由度がそれだけ増加する。こ
のため制御コンデンサ電極2はパターンずれなどによる
容量誤差の影響が問題になるほど、副画素電極4i と
重なる面積を小さくする必要がなくなり、各液晶コンデ
ンサ電圧VLCi を従来より精度よく設定することが
できる。このため画素の多階調表示を従来より正確に行
うことができ、表示品位を向上できる。この付加コンデ
ンサの併用によって各副画素の電圧対透過率特性を精度
よく設定することができるので、画素の総合的な電圧対
透過率特性の直線性を向上することが容易となり、直線
性補正のため従来行っていた所謂γ補正が不要となる。 また同じ理由からカラーTN形液晶表示素子における旋
光分散に起因する、色の異なる画素間の電圧対透過率特
性のずれを容易に補正できる。
As explained above, according to the first aspect of the present invention, in at least one subpixel Fi among a plurality of subpixels, the additional capacitor CSi is connected to the liquid crystal capacitor CLCi together with the conventional control capacitor CCi. This is used to determine the voltage VLCi across the subpixel, and the degree of freedom in designing the voltage versus transmittance characteristic of that subpixel increases accordingly. Therefore, it is no longer necessary to reduce the area of the control capacitor electrode 2 overlapping with the sub-pixel electrode 4i to such an extent that the influence of capacitance error due to pattern misalignment becomes a problem, and each liquid crystal capacitor voltage VLCi can be set more accurately than before. Therefore, multi-gradation display of pixels can be performed more accurately than before, and display quality can be improved. By using this additional capacitor together, the voltage vs. transmittance characteristics of each subpixel can be set with high precision, making it easy to improve the linearity of the overall voltage vs. transmittance characteristics of the pixel, and linearity correction. Therefore, the so-called γ correction that has been performed in the past becomes unnecessary. Further, for the same reason, deviations in voltage versus transmittance characteristics between pixels of different colors caused by optical rotation dispersion in a color TN type liquid crystal display element can be easily corrected.

【0032】この発明の第2の観点によれば、各画素は
複数の副画素が同心状に配置されるように構成されるの
で画像の表示品質を高めることができる。
According to the second aspect of the present invention, since each pixel is configured such that a plurality of sub-pixels are arranged concentrically, the display quality of the image can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】従来の液晶表示素子における画素構成を示す斜
視図である。
FIG. 1 is a perspective view showing a pixel configuration in a conventional liquid crystal display element.

【図2】図1の各電極間に形成される静電容量を示す図
である。
FIG. 2 is a diagram showing capacitance formed between each electrode in FIG. 1;

【図3】図1の画素の電気的等価回路を示す図である。FIG. 3 is a diagram showing an electrical equivalent circuit of the pixel in FIG. 1;

【図4】図1の副画素Fi (i=1〜4)における印
加電圧Va対液晶コンデンサ電圧VLCi 特性を示す
図である。
4 is a diagram showing the applied voltage Va vs. liquid crystal capacitor voltage VLCi characteristic in the subpixel Fi (i=1 to 4) in FIG. 1; FIG.

【図5】この発明の第1の観点にもとずく実施例におけ
る画素構成を示す斜視図である。
FIG. 5 is a perspective view showing a pixel configuration in an embodiment based on the first aspect of the invention.

【図6】図5における各電極間に形成される静電容量を
示す図である。
6 is a diagram showing capacitance formed between each electrode in FIG. 5. FIG.

【図7】図5の画素の電気的等価回路を示す図である。FIG. 7 is a diagram showing an electrical equivalent circuit of the pixel in FIG. 5;

【図8】Aは図5の各副画素の電圧対透過率特性の一例
を示す図であり、BはAの総合電圧対透過率特性を示す
図である。
8A is a diagram showing an example of the voltage vs. transmittance characteristic of each subpixel in FIG. 5, and B is a diagram showing the overall voltage vs. transmittance characteristic of A. FIG.

【図9】Aは図5の各副画素の電圧対透過率特性の他の
例を示す図であり、BはAの総合電圧対透過率特性を示
す図である。
9A is a diagram showing another example of the voltage vs. transmittance characteristic of each subpixel in FIG. 5, and B is a diagram showing the overall voltage vs. transmittance characteristic of A. FIG.

【図10】AはTN形カラー液晶表示素子におけるR,
G,Bの各画素の一般的な電圧対透過率特性を示す図で
あり、Bはこの発明の液晶表示素子におけるR,G,B
の各画素の電圧対透過率特性の一例を示す図である。
[Fig. 10] A is R in a TN type color liquid crystal display element,
FIG. 3 is a diagram showing general voltage versus transmittance characteristics of each pixel of G and B, and B is a diagram showing general voltage versus transmittance characteristics of each pixel of G and B;
FIG. 3 is a diagram showing an example of voltage versus transmittance characteristics of each pixel in FIG.

【図11】この発明の第2の観点にもとずく画素構成の
実施例を示す斜視図である。
FIG. 11 is a perspective view showing an example of a pixel configuration based on a second aspect of the invention.

【図12】図11における制御コンデサ電極の平面図で
ある。
FIG. 12 is a plan view of the control capacitor electrode in FIG. 11;

【図13】この発明の他の実施例の要部を示す平面図で
ある。
FIG. 13 is a plan view showing essential parts of another embodiment of the invention.

【図14】図13のA−A断面図である。FIG. 14 is a sectional view taken along line AA in FIG. 13;

【図15】図13のB−B断面図である。FIG. 15 is a sectional view taken along line BB in FIG. 13;

【図16】図13,図14及び図15の画素の電気的等
価回路を示す図である。
16 is a diagram showing an electrical equivalent circuit of the pixels in FIGS. 13, 14, and 15. FIG.

【図17】図13に対応する変形実施例を簡略化して示
す平面図である。
17 is a simplified plan view of a modified embodiment corresponding to FIG. 13; FIG.

【図18】図13,図14及び図15の実施例の変形例
を示す断面図である。
18 is a sectional view showing a modification of the embodiment of FIGS. 13, 14 and 15. FIG.

【図19】この発明の更に他の実施例を示す平面図であ
る。
FIG. 19 is a plan view showing still another embodiment of the invention.

【図20】図19のA−A断面図である。FIG. 20 is a sectional view taken along line AA in FIG. 19;

【図21】更に他の実施例の平面図である。FIG. 21 is a plan view of still another embodiment.

【図22】図21におけるA−A断面図である。FIG. 22 is a sectional view taken along line AA in FIG. 21;

【図23】図21におけるB−B断面図である。FIG. 23 is a sectional view taken along line BB in FIG. 21;

【図24】更に他の実施例の平面図である。FIG. 24 is a plan view of still another embodiment.

【図25】図24におけるA−A断面図である。25 is a sectional view taken along line AA in FIG. 24. FIG.

【図26】図24におけるB−B断面図である。26 is a sectional view taken along line BB in FIG. 24. FIG.

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】  各画素の領域の一部を占める少なくと
も1つの副画素電極が第2基板上の共通電極と液晶を挟
んで対向して第1基板上に形成された第1絶縁膜上に配
され、上記少くとも1つの副画素電極と上記第1絶縁膜
を介して少くとも一部が対向する制御コンデンサ電極が
設けられており、それによって上記少くとも1つの副画
素電極が上記共通電極との間に形成する液晶コンデンサ
に直列に接続された制御コンデンサを形成し、上記制御
コンデンサ電極と上記共通電極との間に駆動電圧が供給
されるように構成された上記画素を有する液晶表示素子
において、上記少くとも1つの副画素電極と第2絶縁膜
を介して対向するように付加コンデンサ電極が形成され
、それによって上記液晶コンデンサに等価的に並列な付
加コンデンサを形成していることを特徴とする液晶表示
素子。
1. At least one sub-pixel electrode occupying a part of the area of each pixel is disposed on a first insulating film formed on a first substrate, facing a common electrode on a second substrate with a liquid crystal interposed therebetween. A control capacitor electrode is provided which is arranged at least partially opposite to the at least one sub-pixel electrode with the first insulating film interposed therebetween, so that the at least one sub-pixel electrode is connected to the common electrode. A liquid crystal display element having the pixel configured to form a control capacitor connected in series to a liquid crystal capacitor formed between the pixel and the control capacitor, and a driving voltage being supplied between the control capacitor electrode and the common electrode. An additional capacitor electrode is formed to face the at least one sub-pixel electrode via a second insulating film, thereby forming an additional capacitor equivalently parallel to the liquid crystal capacitor. A liquid crystal display element.
【請求項2】  各画素の領域の一部を占める少なくと
も1つの副画素電極が第2基板上の共通電極と液晶を挟
んで対向して第1基板上に形成された絶縁膜上に配され
、上記少なくとも1つの副画素電極と上記絶縁膜を介し
て少くとも一部が対向する制御コンデンサ電極が設けら
れておりそれによって上記少くとも1つの副画素電極が
上記共通電極との間に形成する液晶コンデンサに直列に
接続された制御コンデンサを形成し、上記制御コンデン
サ電極と上記共通電極との間に駆動電圧が供給されるよ
うに構成された上記画素を有する液晶表示素子において
、上記少くとも1つの副画素電極と上記制御コンデンサ
電極は一方が他方をほぼ囲むと共に少なくとも周縁で上
記絶縁膜を介して互いに重なるように同心状に配され、
それによって島状の第1副画素領域とそれをほぼ囲むル
ープ状の第2副画素領域とを規定していることを特徴と
する液晶表示素子。
2. At least one sub-pixel electrode occupying a part of the area of each pixel is arranged on an insulating film formed on the first substrate and facing a common electrode on the second substrate with the liquid crystal interposed therebetween. , a control capacitor electrode at least partially facing the at least one sub-pixel electrode with the insulating film interposed therebetween is provided, whereby the at least one sub-pixel electrode is formed between the at least one sub-pixel electrode and the common electrode. A liquid crystal display element having the pixel configured to form a control capacitor connected in series to a liquid crystal capacitor, and a driving voltage being supplied between the control capacitor electrode and the common electrode, the two sub-pixel electrodes and the control capacitor electrode are arranged concentrically so that one substantially surrounds the other and overlaps each other at least at the periphery with the insulating film interposed therebetween;
A liquid crystal display element characterized in that this defines an island-shaped first sub-pixel region and a loop-shaped second sub-pixel region that substantially surrounds the island-shaped first sub-pixel region.
【請求項3】  上記第1副画素領域は上記第2副画素
領域の内側に規定された上記制御コンデンサ電極の領域
の一部であり、上記副画素電極は上記第1副画素領域を
ほぼ囲むループ状に形成されている請求項2記載の液晶
表示素子。
3. The first sub-pixel region is part of a region of the control capacitor electrode defined inside the second sub-pixel region, and the sub-pixel electrode substantially surrounds the first sub-pixel region. 3. The liquid crystal display element according to claim 2, wherein the liquid crystal display element is formed in a loop shape.
【請求項4】  上記第1副画素領域は上記第2副画素
領域の内側に配置された上記少なくとも1つの副画素電
極であり、上記制御コンデンサ電極は上記少なくとも1
つの副画素電極をほぼ囲む領域を有し、上記第2副画素
領域を規定している請求項2記載の液晶表示素子。
4. The first sub-pixel region is the at least one sub-pixel electrode disposed inside the second sub-pixel region, and the control capacitor electrode is the at least one sub-pixel electrode disposed inside the second sub-pixel region.
3. The liquid crystal display element according to claim 2, further comprising a region substantially surrounding two sub-pixel electrodes, defining said second sub-pixel region.
【請求項5】  上記少なくとも1つの副画素電極とギ
ャップで隔てられたもう1つの副画素電極が設けられ、
上記もう1つの副画素電極と上記制御コンデンサ電極と
は電気的に接続されている請求項1記載の液晶表示素子
5. Another sub-pixel electrode separated from the at least one sub-pixel electrode by a gap,
2. The liquid crystal display element according to claim 1, wherein said another sub-pixel electrode and said control capacitor electrode are electrically connected.
【請求項6】  上記制御コンデンサ電極は、上記少な
くとも1つの副画素電極の周縁部をほぼ囲むと共にその
周縁部と重なって形成されている請求項5記載の液晶表
示素子。
6. The liquid crystal display element according to claim 5, wherein the control capacitor electrode substantially surrounds and overlaps the peripheral edge of the at least one sub-pixel electrode.
【請求項7】  上記少なくとも1つの副画素電極は上
記制御コンデンサ電極の周縁部をほぼ囲むと共にその周
縁部と重なるように形成されている請求項5記載の液晶
表示素子。
7. The liquid crystal display element according to claim 5, wherein said at least one sub-pixel electrode is formed to substantially surround and overlap a peripheral edge of said control capacitor electrode.
【請求項8】  上記第2絶縁膜は上記少なくとも1つ
の副画素電極の上から上記第1基板のほぼ全面に渡って
形成されており、その上に上記付加コンデンサ電極が形
成されている請求項1記載の液晶表示素子。
8. The second insulating film is formed over substantially the entire surface of the first substrate from above the at least one sub-pixel electrode, and the additional capacitor electrode is formed thereon. 1. The liquid crystal display element according to 1.
【請求項9】  上記もう1つの副画素電極は上記制御
コンデンサ電極と一体に同一面上に形成されている請求
項5記載の液晶表示素子。
9. The liquid crystal display element according to claim 5, wherein the other sub-pixel electrode is formed integrally with the control capacitor electrode on the same plane.
【請求項10】  上記第2絶縁膜は上記第1絶縁膜に
より兼用されており、上記制御コンデンサ電極と上記付
加コンデンサ電極は同一面上に形成されている請求項1
記載の液晶表示素子。
10. The second insulating film is also used by the first insulating film, and the control capacitor electrode and the additional capacitor electrode are formed on the same surface.
The liquid crystal display element described above.
【請求項11】  上記もう1つの副画素電極と上記制
御コンデンサ電極とは上記第1絶縁膜に形成したコンタ
クトホールを通して互いに接続されている請求項5記載
の液晶表示素子。
11. The liquid crystal display element according to claim 5, wherein the other sub-pixel electrode and the control capacitor electrode are connected to each other through a contact hole formed in the first insulating film.
【請求項12】  上記もう1つの副画素電極は上記少
なくとも1つの副画素電極と同一面に互いにギャップに
より分離されて形成され、上記制御コンデンサ電極は上
記ギャップとそのほぼ全長に渡って重なる領域を有する
請求項5記載の液晶表示素子。
12. The other sub-pixel electrode is formed on the same plane as the at least one sub-pixel electrode and separated from each other by a gap, and the control capacitor electrode has a region that overlaps the gap over substantially the entire length thereof. 6. The liquid crystal display element according to claim 5.
【請求項13】  上記付加コンデンサ電極は上記行配
列及び列配列のいずれか一方の方向に隣接する上記画素
の上記付加コンデンサ電極に接続される延長部を有して
いる請求項1記載の液晶表示素子。
13. The liquid crystal display according to claim 1, wherein said additional capacitor electrode has an extension portion connected to said additional capacitor electrode of said pixel adjacent to said pixel in one direction of said row arrangement or column arrangement. element.
【請求項14】  各画素の領域の一部をそれぞれ占め
る複数の副画素電極が第2基板上の共通電極と液晶を挟
んで対向して第1基板上に形成された絶縁膜上に配され
、上記複数の副画素電極と上記絶縁膜を介してそれぞれ
少くとも一部が対向する制御コンデンサ電極が設けられ
ておりそれによって上記複数の副画素電極が上記共通電
極との間にそれぞれ形成する液晶コンデンサにそれぞれ
直列に接続された制御コンデンサを形成し、上記制御コ
ンデンサ電極と上記共通電極との間に駆動電圧が供給さ
れるように構成された上記画素を有する液晶表示素子に
おいて、上記複数の副画素電極は中央の島状の1つを他
の少なくとも1つがほぼ囲むと共に少なくとも周縁で上
記絶縁膜を介して互いに重なるように同心状に配され、
それによって中央の島状の第1副画素領域とそれをほぼ
囲むループ状の第2副画素領域とを規定していることを
特徴とする液晶表示素子。
14. A plurality of sub-pixel electrodes each occupying a part of the area of each pixel are arranged on an insulating film formed on the first substrate and facing a common electrode on the second substrate with the liquid crystal interposed therebetween. , a liquid crystal display including a control capacitor electrode at least partially facing each of the plurality of sub-pixel electrodes via the insulating film, whereby each of the plurality of sub-pixel electrodes is formed between the plurality of sub-pixel electrodes and the common electrode. In the liquid crystal display element having the pixel configured such that a control capacitor is connected in series with each capacitor and a driving voltage is supplied between the control capacitor electrode and the common electrode, The pixel electrodes are arranged concentrically so that at least one other island-shaped one substantially surrounds one in the center and overlaps each other at least at the periphery with the insulating film interposed therebetween;
A liquid crystal display element characterized in that a central island-shaped first sub-pixel region and a loop-shaped second sub-pixel region substantially surrounding the central island-shaped first sub-pixel region are defined.
JP17973691A 1990-07-23 1991-07-19 Liquid crystal display device Expired - Lifetime JP2909266B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17973691A JP2909266B2 (en) 1990-07-23 1991-07-19 Liquid crystal display device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2-194632 1990-07-23
JP02194632 1990-07-23
JP17973691A JP2909266B2 (en) 1990-07-23 1991-07-19 Liquid crystal display device

Publications (2)

Publication Number Publication Date
JPH04348324A true JPH04348324A (en) 1992-12-03
JP2909266B2 JP2909266B2 (en) 1999-06-23

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ID=26499498

Family Applications (1)

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Country Status (1)

Country Link
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US6809338B2 (en) 2000-03-17 2004-10-26 Seiko Epson Corporation Electro-optical device
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