CN113224037A - 半导体封装体及其制造方法 - Google Patents

半导体封装体及其制造方法 Download PDF

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Publication number
CN113224037A
CN113224037A CN202010723278.7A CN202010723278A CN113224037A CN 113224037 A CN113224037 A CN 113224037A CN 202010723278 A CN202010723278 A CN 202010723278A CN 113224037 A CN113224037 A CN 113224037A
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metal layer
metal
layer
disposed
semiconductor package
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CN113224037B (zh
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泽登昭仁
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明涉及一种半导体封装体及其制造方法。本实施方式的半导体封装体具备衬底。半导体芯片设置于衬底上。树脂层在衬底上被覆半导体芯片。金属膜被覆树脂层的正面及侧面。金属膜是具备第1～第4金属层的积层膜。第1金属层被覆树脂层。第2金属层包含与第1金属层不同的材料。第3金属层包含构成第2金属层的第1金属材料与不同于该第1金属材料的第2金属材料的合金。第4金属层被覆第2或第3金属层。

Description

半导体封装体及其制造方法
相关申请案的引用
本申请案基于2020年02月04日提出申请的在先日本专利申请案第2020-017171号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本实施方式涉及一种半导体封装体及其制造方法。
背景技术
为了抑制由半导体装置产生的EMI(Electro Magnetic Interference，电磁干扰)，有时会在半导体封装体的表面形成金属膜作为电磁遮罩。这种金属膜被保护膜被覆，但在对半导体装置进行特性检查等时，有时会刮掉保护膜而导致金属膜露出。
发明内容
一实施方式提供一种能够保护作为电磁遮罩的金属膜并抑制其露出的半导体封装体及其制造方法。
本实施方式的半导体封装体具备衬底。半导体芯片设置于衬底上。树脂层在衬底上被覆半导体芯片。金属膜被覆树脂层的正面及侧面。金属膜是具备第1～第4金属层的积层膜。第1金属层被覆树脂层。第2金属层包含与第1金属层不同的材料。第3金属层包含构成第2金属层的第1金属材料与不同于该第1金属材料的第2金属材料的合金。第4金属层被覆第2或第3金属层。
根据所述构成，能够提供一种能够保护作为电磁遮罩的金属膜并抑制其露出的半导体封装体及其制造方法。
附图说明
图1是表示第1实施方式的半导体封装体的构成的一例的剖视图。
图2是更详细地表示图1的框A2的构成的剖视图。
图3是表示金属膜的更详细构成的剖视图。
图4A是表示第1实施方式的半导体封装体的制造方法的一例的流程图。
图4B是表示第1实施方式的半导体封装体的制造方法的一例的流程图。
图5是表示第2实施方式的金属膜的更详细构成的剖视图。
图6是表示第3实施方式的金属膜的更详细构成的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。在以下的实施方式中，配线衬底的上下方向表示将半导体芯片的搭载面设为上的情况下的相对方向，有时不同于依据重力加速度的上下方向。附图是示意图或概念图，各部分的比率等未必与实际相同。在说明书及附图中，针对与上文就已出现图所述的要素相同的要素，标注同一符号并适当省略详细说明。
(第1实施方式)图1是表示第1实施方式的半导体封装体的构成的一例的剖视图。半导体封装体100c在其内部用树脂材料将半导体芯片30、50密封。半导体芯片30、50例如可为NAND(Not AND，与非)型闪存的存储器芯片或控制存储器芯片的控制器芯片等。
配线衬底10具有第1面10A、相对于第1面10A位于相反侧的第2面10B、及位于第1面10A与第2面10B之间的侧面10C。在配线衬底10的内部设置有配线层13～16(参照图2)及将配线层间绝缘的层间绝缘膜17(参照图2)。层间绝缘膜17可为玻璃环氧树脂或陶瓷等。即，配线衬底10例如可为使用玻璃环氧树脂的印刷衬底或插入式衬底等。
在配线衬底10的第1面10A上积层有半导体芯片30、50。半导体芯片30通过粘着层20粘着在配线衬底10的第1面10A上。半导体芯片50通过粘着层40粘着在半导体芯片30上。粘着层20、40可为糊状或膜状树脂，例如NCP(Non Conductive Paste，非导电膏)、DAF(DieAttach Film，芯片粘结膜)。此外，所积层的半导体芯片数可多于2个，也可少于2个。
配线衬底10具有与其内部配线中任一个电连接的焊垫12。半导体芯片30具有与形成于其表面上之半导体元件中任一个电连接的焊垫32。半导体芯片50具有与形成于其表面上之半导体元件中任一个电连接的焊垫52。焊垫12、32、52例如通过接合线60连接。配线衬底10的除焊垫12以外的第1面10A被未图示的阻焊剂等绝缘膜被覆。
树脂层70在配线衬底10上密封并保护半导体芯片30、50及接合线60。另外，树脂层70未设置于配线衬底10的侧面10C。
金属膜90被覆树脂层70的正面及侧面。金属膜90被覆至配线衬底10的侧面10C为止，在侧面10C上与配线衬底10的配线的一部分电连接。
图2是更详细地表示图1的框A2的构成的剖视图。配线衬底10包含配线层13～16作为配线层的一部分。配线层16设置于第2面10B侧。在配线层16的上方设置有配线层15。在配线层15的上方设置有配线层13、14。配线衬底10还可包含其它配线层。在配线层13～16之间设置有层间绝缘膜17，将配线层13～16相互电绝缘。此外，配线层13可与焊垫12连接，或者作为焊垫12发挥功能。配线层16也可在第2面10B侧作为焊垫发挥功能。
在配线衬底10的侧面10C，一部分配线层14、15从层间绝缘膜17露出。从层间绝缘膜17露出的配线层14、15例如连接到指定电压(例如，接地极)。金属膜90被覆配线衬底10的侧面10C，与配线层14、15电连接。由此，金属膜90经由配线层14、15而接地。由此，金属膜90能够发挥作为电磁遮罩的功能。
图3是表示金属膜90的更详细构成的剖视图。此外，图3中仅示出了半导体封装体100c的上部。被树脂层70的正面及侧面被覆的金属膜90构成为多个金属层91～94的积层膜。
作为第1金属层的金属层91被覆树脂层70的正面及侧面。金属层91例如使用不锈钢、含镍或钛的金属材料。金属层91的膜厚例如约为100nm～300nm。
作为第2金属层的金属层92设置于金属层91上，介隔金属层91而被覆树脂层70的正面及侧面。金属层92的材料与金属层91、93及94不同，是电阻比金属层91、93及94低的金属材料。金属层92例如使用铜、镍或钛等金属材料。
作为第3金属层的金属层93设置于金属层92上，介隔金属层91、92而被覆树脂层70的正面及侧面。金属层93包含构成金属层92的金属材料与不同于该金属材料的其它金属材料的合金。金属层93例如使用以铜、镍或钛为基础材料且包含铝(Al)、钴(Co)、铬(Cr)、锗(Ge)、铟(In)、镁(Mg)、锰(Mn)、镍(Ni)、硅(Si)、锡(Sn)、钛(Ti)、锌(Zn)、钼(Mo)、铁(Fe)中至少任一种附加材料的合金。其中，在基础材料为镍的情况下，附加材料设为除镍以外的材料。另外，在基础材料为钛的情况下，附加材料设为除钛以外的材料。金属层93中包含的附加材料可为1～20原子百分比(at.％)。由此，金属层93能够设为以金属层92的金属材料为基础材料且以其它金属材料为附加材料的合金。像这样，通过将金属层93设为以金属层92的金属材料为基础的合金，金属层92与金属层93的密接性提高，金属层93不容易从金属层92剥离。
另外，通过将金属层93设为这种合金材料，金属层93的结晶粒径小于金属层92的结晶粒径。例如，金属层93的粒径小于0.10μm，金属膜92的粒径为0.10μm以上。通过减小金属层93的粒径，成膜在金属层93上的作为第4金属层的金属层94的结晶粒径也会变小。因为最外层的金属层94的粒径较小，所以金属层93与金属层94的密接性提高，金属层94不容易从金属层93剥离。即，金属层94能够更确实地保护金属层93。金属层92、93的合计膜厚例如约为0.45μm～2.5μm。
像这样，通过使以金属层92的金属材料为基础的粒径较小的金属层93介置于金属层92与金属层94之间，金属层92～94的密接性得以改善。由此，即使从金属层94的外侧被刮伤，金属层92也不容易露出。
另外，金属层92是在150度以上的高温下成膜，其结晶粒径大于金属层93的结晶粒径。因为金属层92的粒径大于金属层93的粒径，所以金属层92的电阻值低于金属层93的电阻值。因此，通过将金属层92与图2的配线层14、15电连接，能够提高电磁遮罩的效果。此外，金属层92的电阻值低于金属层91、93、94中任一金属层的电阻值。金属层92可与配线衬底10的配线层14、15直接连接，也可经由金属层91连接。
金属层94设置于金属层93上，介隔金属层91～93而被覆树脂层70的正面及侧面。金属层94将金属层93上被覆，成为半导体封装体100c的最外层。金属层94例如使用不锈钢、含镍或钛的金属材料。金属层94的材料可与金属层91相同。金属层94的膜厚例如约为100nm～300nm。
在未设置有包含合金的金属层93的情况下，金属膜92的粒径较大，因此，金属层94的粒径也会变大，金属膜92与金属膜94的密接性会变差。在此情况下，因刮伤而容易导致金属膜92露出。
相对于此，根据本实施方式，被覆树脂层70的金属膜90成为金属层91～94的积层膜。在金属层91与金属层94之间设置有多个金属层92、93的积层膜，金属层93成为金属层92的金属材料与其它金属材料的合金。由此，金属层93、94的粒径小于金属层92的粒径，能够提高金属层92～94的密接性。
另外，金属层92的粒径大于金属层93的粒径，因此，金属层92的电阻值低于金属层93的电阻值。由此，电磁遮罩的效果提高。其结果为，本实施方式的半导体封装体100c能够提高电磁遮罩的功能，并且确实地保护金属层92而抑制其露出。
接着，对本实施方式的半导体封装体100c的制造方法进行说明。
图4A及图4B是表示第1实施方式的半导体封装体的制造方法的一例的流程图。
在图4A的步骤S1中，在图1的配线衬底10的第1面10A上经由粘着层20而设置有半导体芯片30。在半导体芯片30上经由粘着层40而设置有半导体芯片50。此时，多个配线衬底10仍为连结状态，未针对各半导体封装体的每一个单片化。
接着，将配线衬底10等离子体洗净后，利用接合线60将配线衬底10的焊垫12、半导体芯片30的焊垫32、及半导体芯片50的焊垫52连接。接合线60例如为Au线、Cu线、Ag线、覆Pd的Cu线等金属线。
此外，半导体芯片30、50相对于第1面10A沿大致垂直方向积层，但半导体芯片也可并排配置于第1面10A上。
接着，在步骤S2中，在配线衬底10上设置树脂层70，将半导体芯片30、50、接合线60密封。树脂层70是热固性树脂，例如可为环氧树脂或丙烯酸系树脂。树脂层70可为含有未图示无机填料的树脂材料。无机填料例如为二氧化硅、即氧化硅。除了二氧化硅以外，无机填料例如也可添加氢氧化铝、碳酸钙、氧化铝、氮化硼、氧化钛、钛酸钡等。
在步骤S3中，使用刀片以各半导体封装体为单位将配线衬底10单片化。
在步骤S4中，对单片化的半导体封装体的树脂层70的上表面进行标记。标记是采用激光标记器刻印(engraving)产品名、制造者、批号等。
在步骤S5中，配线衬底10被放入烘箱中进行烘烤处理。烘烤处理例如在100度至260度之间的温度进行处理。通过烘烤处理，能够使树脂层70中包含的水分蒸发，而提高下述金属膜90的密接性。另外，通过焊料的熔点温度以下、例如260度以下的烘烤处理，而抑制接合部分、配线、晶体管等的可靠性变差。
在步骤S6中，将多个配线衬底10堆载于未图示的托盘上。接着，在步骤S7中，多个配线衬底10在载置于托盘上的状态下被搬入压力低于大气压的减压腔室中。多个配线衬底10例如在150度至260度之间的温度进行烘烤处理。
接着，配线衬底10被搬送到蚀刻腔室中。在步骤S8中，树脂层70在蚀刻腔室中被蚀刻。树脂层70例如使用含有氩(Ar)及氮(N)的等离子体进行蚀刻(溅射蚀刻)。氩与氮的流量比例如可设为3：7～7：3。如果脱离该范围，那么存在树脂层70与金属膜90的密接性降低的情况。通过该蚀刻，相对于无机填料将树脂层75选择性地蚀刻1～100nm左右。由于无机填料与金属膜90的密接性较高，因而通过使无机填料露出，树脂层70与金属膜90的密接性提高。
接着，配线衬底10被导入成膜腔室中。在步骤S9中，金属膜90形成在树脂层70的上表面及侧面、及配线衬底10的侧面10C。金属膜90是例如使用溅镀法，在多个配线衬底10载置于托盘的状态下形成。
如上所述，金属膜90是金属层91～94的积层膜。金属层91～94是在同一减压腔室内，一边改变溅镀的材料源，一边连续成膜。如图4B所示，首先将金属层91成膜在树脂层70上(S91)。例如，在使用不锈钢作为金属层91的情况下，使用不锈钢源进行溅镀。不锈钢膜的膜厚例如为100nm～300nm。接着，将金属层92成膜在金属层91上(S92)。例如在使用铜作为金属层92的情况下，使用铜源进行溅镀。此时，成膜温度为150度以上，优选为200℃以上。由此，金属层92的铜的粒径比在小于150度的低温下成膜的铜的粒径大。因此，金属层92的电阻相对较低。
在将配线衬底10载置于对150度以上的温度不具耐受性的树脂带上进行溅镀的情况下，当然需要在小于150度的温度下使金属膜90成膜。因此，金属膜90的粒径变小，电阻值变得相对较高。
相对于此，在本实施方式中，将配线衬底10搭载于比树脂带对高温具耐受性的托盘而进行溅镀处理。因此，能够在150度以上、优选为200℃的高温下使金属层92成膜，能够增大其粒径。其结果为，金属层92的电阻相对较低。
接着，使金属层93成膜在金属层92上。例如，在使用铜合金作为金属层93的情况下，使用铜合金源进行溅镀。此时，温度可小于150度。由此，金属层93的铜合金的粒径变得相对较小。由此，金属层93与金属层92的密接性提高。另外，由于金属层93的粒径较小，因而能够具有相对较平坦的表面。此外，金属层92、93的总膜厚例如为0.45μm～2.5μm。
接着，使金属层94成膜在金属层93上。例如，在使用不锈钢作为金属层94的情况下，使用不锈钢源进行溅镀。不锈钢膜的膜厚例如为100nm～300nm。此时，金属层94也随着基底的金属层93而成为相对较平坦且粒径较小的膜。由此，金属层94与金属层93的密接性提高。
此外，金属层91～94也可通过CVD(Chemical Vapor Deposition，化学气相沉积)法、真空蒸镀法、离子镀覆法形成。
通过以上的制造方法而完成第1实施方式的半导体封装体100c。
根据本实施方式，金属层92在相对较高温下成膜，金属层92的粒径变得相对较大。因此，金属层92的电阻值降低，能够提高作为电磁遮罩的功能。另一方面，被覆金属层92的金属层93、94的粒径小于金属层92的粒径。由此，金属层92～94的密接性提高。
(第2实施方式)
图5是表示第2实施方式的金属膜90的更详细构成的剖视图。在第2实施方式中，金属层92、93的位置关系相反。即，作为第3金属层的金属层93设置于金属层91上，作为第2金属层的金属层92设置于金属层93上。作为第4金属层的金属层94设置于金属层92上。第2实施方式的其它构成可与第1实施方式的对应构成相同。
金属层93设置于金属层91上，介隔金属层91而被覆树脂层70的正面及侧面。金属层93的材料包含与第1实施方式的金属层93的材料相同的合金。因此，金属层93、92的密接性提高。
金属层92成膜在金属层93上。因此，存在金属层92的粒径小于第1实施方式的金属层92的情况。在此情况下，形成于金属层92上的金属层94的粒径也会变小，金属层92与金属层94的密接性提高。金属层92的材料可与第1实施方式的金属层92的材料相同。
金属层94设置于金属层92上，被覆金属层92。金属层94的材料可与第1实施方式的金属层94相同。
根据第2实施方式，虽然在金属层91与金属层94之间，金属层92、93的位置关系相反，但是金属层92～94的密接性提高。
另外，金属层92的粒径小于第1实施方式的粒径。但是，通过使用电阻值足够低的材料作为金属层92，能够将金属层92的电阻值抑制得较低。由此，能够维持电磁遮罩的效果。其结果为，第2实施方式能够取得与第1实施方式相同的效果。
此外，第2实施方式的金属膜90只要使第1实施方式的金属膜90的金属层92、93的成膜顺序颠倒即可。
(第3实施方式)
图6是表示第3实施方式的金属膜90的更详细构成的剖视图。第3实施方式不同于第1实施方式的方面在于，作为第5金属层的金属层95设置于作为第1金属层的金属层91与作为第2金属层的金属层92之间。第3实施方式的其它构成可与第1实施方式相同。
金属层95设置于金属层91上。金属层95是以介隔金属层91而被覆树脂层70的上表面及侧面的方式设置。金属层95例如使用金属层92的金属材料和与该金属材料不同的金属材料的合金。金属层95例如使用以铜、镍或钛为基础材料且包含铝(Al)、钴(Co)、铬(Cr)、锗(Ge)、铟(In)、镁(Mg)、锰(Mn)、镍(Ni)、硅(Si)、锡(Sn)、钛(Ti)、锌(Zn)、钼(Mo)、铁(Fe)中至少任一种附加材料的合金。其中，在基础材料为镍的情况下，附加材料设为除镍以外的材料。另外，在基础材料为钛的情况下，附加材料设为除钛以外的材料。金属层95的材料可与金属层93相同，但材料也可不同。第3实施方式可以说是第1及第2实施方式的组合。
像这样，在第3实施方式中，金属膜90成为5层积层构造，在金属层91与金属层94之间设置有3层金属层95、92、93。由此，金属层92～95的密接性提高，金属膜90对刮伤的耐受性提高。另外，第3实施方式能够取得第1及第2实施方式的效果。
此外，第3实施方式的金属膜90只要在第1实施方式的金属层92成膜之前在与金属层93的成膜相同条件下使金属层95成膜在金属层91上即可。
已对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意图限定发明的范围。这些实施方式能够以其它各种形态实施，在不脱离发明主旨的范围内，能够进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨内，同样包含在权利要求书中记载的发明及其均等的范围内。

Claims (20)

1.一种半导体封装体，具备：
衬底；
半导体芯片，设置于所述衬底上；
树脂层，在所述衬底上被覆所述半导体芯片；及
金属膜，被覆所述树脂层的正面及侧面；且
所述金属膜是积层膜，包含：
第1金属层，被覆所述树脂层；
第2金属层，包含不同于所述第1金属层的材料；
第3金属层，包含构成所述第2金属层的第1金属材料与不同于该第1金属材料的第2金属材料的合金；及
第4金属层，被覆所述第2或第3金属层。
2.根据权利要求1所述的半导体封装体，其中所述第2金属层设置于所述第1金属层上，
所述第3金属层设置于所述第2金属层上，
所述第4金属层设置于所述第3金属层上。
3.根据权利要求1所述的半导体封装体，其中所述第3金属层设置于所述第1金属层上，
所述第2金属层设置于所述第3金属层上，
所述第4金属层设置于所述第2金属层上。
4.根据权利要求1所述的半导体封装体，其还具备第5金属层，所述第5金属层设置于所述第1金属层上，且包含所述第1金属材料与不同于该第1金属材料的第3金属材料的合金，
所述第2金属层设置于所述第5金属层上，
所述第3金属层设置于所述第2金属层上，
所述第4金属层设置于所述第3金属层上。
5.根据权利要求1所述的半导体封装体，其中所述第2金属层的粒径大于所述第3金属层的粒径。
6.根据权利要求4所述的半导体封装体，其中所述第2金属层的粒径大于所述第3及第5金属层的粒径。
7.根据权利要求1所述的半导体封装体，其中所述第2金属层的电阻值低于所述第1、第3及第4金属层的电阻值。
8.根据权利要求7所述的半导体封装体，其中所述第2金属层的电阻值低于所述第1、第3～第5金属层的电阻值。
9.根据权利要求1所述的半导体封装体，其中至少所述第2金属层设置于所述衬底的侧面，且与所述衬底的配线的一部分连接。
10.根据权利要求1所述的半导体封装体，其中所述第1金属层是不锈钢、含镍或钛的金属材料，
所述第2金属层是含铜、镍或钛的金属材料，
所述第3金属层是以铜、镍或钛为基础材料且包含铝(Al)、钴(Co)、铬(Cr)、锗(Ge)、铟(In)、镁(Mg)、锰(Mn)、镍(Ni)、硅(Si)、锡(Sn)、钛(Ti)、锌(Zn)、钼(Mo)、铁(Fe)中至少任一种附加材料(其中，在所述基础材料为镍的情况下，所述附加材料中镍除外，在所述基础材料为钛的情况下，所述附加材料中钛除外)的合金。
11.一种半导体封装体的制造方法，具备如下步骤：
将半导体芯片搭载于衬底上；
利用树脂层被覆所述半导体芯片；
利用第1金属层被覆所述树脂层的正面及侧面；
在150度以上的温度将第2金属层成膜，所述第2金属层包含不同于所述第1金属层的材料；
将第3金属层成膜，所述第3金属层包含构成所述第2金属层的第1金属材料与不同于该第1金属材料的第2金属材料的合金；
利用第4金属层被覆所述第2或第3金属层。
12.根据权利要求11所述的方法，其中所述第2金属层成膜在所述第1金属层上，
所述第3金属层成膜在所述第2金属层上，
所述第4金属层成膜在所述第3金属层上。
13.根据权利要求11所述的方法，其中所述第3金属层成膜在所述第1金属层上，
所述第2金属层成膜在所述第3金属层上，
所述第4金属层成膜在所述第2金属层上。
14.根据权利要求11所述的方法，其还具备如下步骤：
将第5金属层成膜在所述第1金属层上，所述第5金属层包含所述第1金属材料与不同于该第1金属材料的第3金属材料的合金，
所述第2金属层设置于所述第5金属层上，
所述第3金属层设置于所述第2金属层上，
所述第4金属层设置于所述第3金属层上。
15.根据权利要求11所述的方法，其中所述第2金属层的粒径大于所述第3金属层的粒径。
16.根据权利要求14所述的方法，其中所述第2金属层的粒径大于所述第3及第5金属层的粒径。
17.根据权利要求11所述的方法，其中所述第2金属层的电阻值低于所述第1、第3及第4金属层的电阻值。
18.根据权利要求14所述的方法，其中所述第2金属层的电阻值低于所述第1、第3～第5金属层的电阻值。
19.根据权利要求11所述的方法，其中至少所述第2金属层设置于所述衬底的侧面，且与所述衬底的配线的一部分连接。
20.根据权利要求11所述的方法，其中所述第1金属层是不锈钢、含镍或钛的金属材料，
所述第2金属层是含铜、镍或钛的金属材料，
所述第3金属层是以铜、镍或钛为基础材料且包含铝(Al)、钴(Co)、铬(Cr)、锗(Ge)、铟(In)、镁(Mg)、锰(Mn)、镍(Ni)、硅(Si)、锡(Sn)、钛(Ti)、锌(Zn)、钼(Mo)、铁(Fe)中至少任一种附加材料(其中，在所述基础材料为镍的情况下，所述附加材料中镍除外，在所述基础材料为钛的情况下，所述附加材料中钛除外)的合金。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1810068A (zh) * 2003-06-19 2006-07-26 波零公司 印刷电路板的emi吸收屏蔽
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法
US20170345793A1 (en) * 2016-05-26 2017-11-30 Shinko Electric Industries Co., Ltd. Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243122A (ja) 2006-03-06 2007-09-20 Be-Spputer Co Ltd スパッタリング法によるシールド膜の成膜方法及び成膜されたシールド膜
US7989928B2 (en) 2008-02-05 2011-08-02 Advanced Semiconductor Engineering Inc. Semiconductor device packages with electromagnetic interference shielding
JP6777423B2 (ja) * 2016-04-28 2020-10-28 新科實業有限公司ＳＡＥ Ｍａｇｎｅｔｉｃｓ（Ｈ．Ｋ．）Ｌｔｄ． 電子部品モジュールおよびその製造方法
JP6571124B2 (ja) 2017-03-30 2019-09-04 太陽誘電株式会社 電子部品モジュールの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1810068A (zh) * 2003-06-19 2006-07-26 波零公司 印刷电路板的emi吸收屏蔽
CN105552061A (zh) * 2014-10-22 2016-05-04 日月光半导体制造股份有限公司 半导体封装元件
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法
US20170345793A1 (en) * 2016-05-26 2017-11-30 Shinko Electric Industries Co., Ltd. Semiconductor device

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