CN113223954A - Method for improving wafer burrs caused by groove etching - Google Patents
Method for improving wafer burrs caused by groove etching Download PDFInfo
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- CN113223954A CN113223954A CN202110447798.4A CN202110447798A CN113223954A CN 113223954 A CN113223954 A CN 113223954A CN 202110447798 A CN202110447798 A CN 202110447798A CN 113223954 A CN113223954 A CN 113223954A
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- 238000005530 etching Methods 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005406 washing Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 239000002253 acid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for improving wafer burrs caused by groove etching, which comprises the steps of providing a silicon substrate, and forming a hard mask layer on the silicon substrate; grinding the hard mask layer to enable the height of the central area of the upper surface of the hard mask layer to be lower than that of the edge area; forming a photoresist layer in the ground central area of the hard mask layer; exposing and developing the photoresist layer to form a photoresist pattern for manufacturing the groove; etching the hard mask layer according to the photoresist pattern, wherein the central area of the hard mask layer is formed into a plurality of hard mask grooves; and etching the silicon substrate according to the hard mask grooves to form a plurality of grooves. According to the invention, the hard mask layer in the prior art is thickened, and one step of grinding the hard mask area is added before the groove etching, so that the hard mask at the edge washing position of the wafer is thicker than the surface in the wafer edge washing position, and thus a certain amount of hard mask is reserved after the hard mask is etched to be used as a barrier layer for etching the edge groove, and the purpose of eliminating the rough edge of the silicon substrate of the wafer is achieved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving wafer burrs caused by groove etching.
Background
In the semiconductor manufacturing process, in some products with Trench structures, silicon burrs (Si Grass) exist at the edge of the etched Trench (Trench Etch) due to various reasons, and the silicon burrs (Si Grass) break and contaminate the products after the acid tank cleaning process, or cross-contaminate subsequent products through the acid tank, so that the yield and reliability of the products are affected.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving wafer burrs caused by trench etching, so as to solve the problem of burrs generated on the edge of a wafer after the trench is formed by the wafer etching in the prior art.
To achieve the above and other related objects, the present invention provides a method for improving wafer burrs caused by trench etching, comprising:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate;
grinding the hard mask layer to enable the height of the central area of the upper surface of the hard mask layer to be lower than that of the edge area;
step three, forming a photoresist layer in the ground central area of the hard mask layer;
exposing and developing the photoresist layer to form a photoresist pattern for manufacturing a groove;
fifthly, etching the hard mask layer according to the photoresist pattern, wherein the central area of the hard mask layer is formed into a plurality of hard mask grooves;
and sixthly, etching the silicon substrate according to the hard mask grooves to form a plurality of grooves.
Preferably, the method for forming the hard mask layer in the first step is a deposition method.
Preferably, the height of the photoresist layer in the third step is consistent with the height of the hard mask layer edge.
Preferably, the photoresist pattern formed in step four is used to fabricate a plurality of the trenches.
Preferably, in the fifth step, the height of the hard mask layer after the edge region is etched is consistent with the height of the central region.
Preferably, the edge region of the hard mask layer in the fifth step is used as a barrier layer for etching the silicon substrate.
Preferably, after the silicon substrate is etched in the sixth step, the edge of the hard mask layer covers the silicon substrate.
Preferably, the hard mask layer in the step one is used as a barrier layer for etching the silicon substrate.
As described above, the method for improving wafer burrs caused by trench etching according to the present invention has the following beneficial effects: according to the invention, the hard mask layer in the prior art is thickened, and one step of grinding the hard mask area is added before the groove etching, so that the hard mask at the edge washing position of the wafer is thicker than the surface in the wafer edge washing position, and thus a certain amount of hard mask is reserved after the hard mask is etched to be used as a barrier layer for etching the edge groove, and the purpose of eliminating the rough edge of the silicon substrate of the wafer is achieved.
Drawings
FIG. 1 is a schematic structural diagram of a hard mask layer on a silicon substrate according to the present invention;
FIG. 2 is a schematic diagram of a structure of a hard mask layer after polishing in the present invention;
FIG. 3 is a schematic diagram of a structure for forming a photoresist pattern according to the present invention;
FIG. 4 is a schematic structural diagram of a hard mask trench formed by etching the hard mask layer according to the present invention;
FIG. 5 is a schematic structural view illustrating a trench formed by etching a silicon substrate according to the present invention;
FIG. 6 is a flow chart of a method for improving wafer burrs caused by trench etching according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Fig. 6 shows a flowchart of a method for improving wafer burrs caused by trench etching according to the present invention. The method at least comprises the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic structural diagram of a hard mask layer on a silicon substrate according to the present invention. In the first step, the silicon substrate 01 is provided, and then the hard mask layer (HM)02 is formed on the silicon substrate 01.
Further, the method for forming the hard mask layer in the first step of this embodiment is a deposition method.
Further, the hard mask layer in the first step of this embodiment is used as a barrier layer for etching the silicon substrate.
Grinding the hard mask layer to enable the height of the central area of the upper surface of the hard mask layer to be lower than that of the edge area; as shown in fig. 2, fig. 2 is a schematic structural view of the hard mask layer after being polished according to the present invention. In the step, the hard mask layer 02 is ground, so that the height of the central area of the upper surface of the hard mask layer 02 is lower than that of the edge area. Fig. 2 shows a partial cross section of the silicon substrate, where the rightmost side of the structure is the edge of the silicon substrate, the leftmost side of the structure is the central region of the silicon substrate, the hard mask layer located on the central region of the silicon substrate is the central region of the hard mask layer, and after the upper surface of the hard mask layer is ground in the second step, the height of the central region is lower than that of the edge region.
Step three, forming a photoresist layer in the ground central area of the hard mask layer; in the third step, the photoresist layer is formed in the central area of the ground hard mask layer, and further, in the third step of the present embodiment, the height of the photoresist layer is consistent with the height of the edge of the hard mask layer. That is, the height of the upper surface of the photoresist layer on the central region of the hard mask layer is consistent with the height of the upper surface of the edge region of the hard mask layer.
Exposing and developing the photoresist layer to form a photoresist pattern for manufacturing a groove; as shown in fig. 3, fig. 3 is a schematic structural view illustrating a photoresist pattern formed in the present invention. In the fourth step, after exposing and developing the photoresist, a photoresist pattern 03 as shown in fig. 3 is formed. Further, the photoresist pattern formed in step four of this embodiment is used to fabricate a plurality of trenches. While the photoresist pattern is formed in this step, as shown in fig. 3, the edge of the hard mask layer 02 is not covered by the photoresist.
Fifthly, etching the hard mask layer according to the photoresist pattern, wherein the central area of the hard mask layer is formed into a plurality of hard mask grooves; as shown in fig. 4, fig. 4 is a schematic structural diagram illustrating a hard mask trench formed by etching the hard mask layer according to the present invention. In the fifth step, the hard mask layer is etched according to the photoresist pattern 03, and then the central area of the hard mask layer is formed into a hard mask groove as shown in fig. 4, while the edge of the hard mask layer located at the edge of the silicon substrate is not etched.
Further, as shown in fig. 4, in the fifth step of this embodiment, the height of the etched edge region of the hard mask layer is consistent with the height of the center region.
Further, the edge region of the hard mask layer in step five of this embodiment is used as a barrier layer for etching the silicon substrate.
And sixthly, etching the silicon substrate according to the hard mask grooves to form a plurality of grooves. In the sixth step, the silicon substrate is etched according to the hard mask trench as shown in fig. 4 to form a plurality of trenches (referred to as trenches of the silicon substrate) as shown in fig. 5, and fig. 5 is a schematic structural diagram illustrating the trenches formed by etching the silicon substrate in the present invention.
Further, after the silicon substrate is etched in the sixth step of this embodiment, the edge of the hard mask layer covers the silicon substrate. It can be seen that the silicon substrate edge (wafer edge) is blocked from etching by being covered by the hard mask layer. And a certain amount of hard mask is reserved after the hard mask is etched to be used as a barrier layer for etching the edge groove, so that the aim of eliminating burrs of the wafer silicon substrate is fulfilled.
In summary, the hard mask layer in the prior art is thickened, and a step of grinding the hard mask area is added before the trench etching, so that the hard mask at the edge washing position of the wafer is thicker than the surface, and a certain amount of hard mask is reserved after the hard mask is etched to be used as a barrier layer for etching the edge trench, thereby achieving the purpose of eliminating the rough edge of the wafer silicon substrate. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for improving wafer burrs caused by groove etching is characterized by comprising the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate;
grinding the hard mask layer to enable the height of the central area of the upper surface of the hard mask layer to be lower than that of the edge area;
step three, forming a photoresist layer in the ground central area of the hard mask layer;
exposing and developing the photoresist layer to form a photoresist pattern for manufacturing a groove;
fifthly, etching the hard mask layer according to the photoresist pattern, wherein the central area of the hard mask layer is formed into a plurality of hard mask grooves;
and sixthly, etching the silicon substrate according to the hard mask grooves to form a plurality of grooves.
2. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: the method for forming the hard mask layer in the first step is a deposition method.
3. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: and in the third step, the height of the photoresist layer is consistent with that of the edge of the hard mask layer.
4. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: the photoresist pattern formed in step four is used to fabricate a plurality of the trenches.
5. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: and fifthly, the height of the etched edge area of the hard mask layer is consistent with the height of the central area.
6. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: and fifthly, taking the edge area of the hard mask layer as a barrier layer for etching the silicon substrate.
7. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: and sixthly, after the silicon substrate is etched, covering the edge of the hard mask layer on the silicon substrate.
8. The method for improving wafer flash caused by trench etching as claimed in claim 1, wherein: and the hard mask layer in the step one is used as a barrier layer for etching the silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110447798.4A CN113223954B (en) | 2021-04-25 | 2021-04-25 | Method for improving wafer burrs caused by groove etching |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110447798.4A CN113223954B (en) | 2021-04-25 | 2021-04-25 | Method for improving wafer burrs caused by groove etching |
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| CN113223954A true CN113223954A (en) | 2021-08-06 |
| CN113223954B CN113223954B (en) | 2022-12-23 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227100A (en) * | 2012-01-31 | 2013-07-31 | 上海华虹Nec电子有限公司 | Method for improving super junction depth groove etching process |
| CN106158594A (en) * | 2015-04-16 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method and technique for applying thereof |
| CN107887323A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(北京)有限公司 | Interconnection structure and its manufacture method |
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2021
- 2021-04-25 CN CN202110447798.4A patent/CN113223954B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227100A (en) * | 2012-01-31 | 2013-07-31 | 上海华虹Nec电子有限公司 | Method for improving super junction depth groove etching process |
| CN106158594A (en) * | 2015-04-16 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method and technique for applying thereof |
| CN107887323A (en) * | 2016-09-30 | 2018-04-06 | 中芯国际集成电路制造(北京)有限公司 | Interconnection structure and its manufacture method |
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| CN113223954B (en) | 2022-12-23 |
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