CN118248624A - Method for manufacturing SOI substrate lead-out - Google Patents
Method for manufacturing SOI substrate lead-out Download PDFInfo
- Publication number
- CN118248624A CN118248624A CN202410074160.4A CN202410074160A CN118248624A CN 118248624 A CN118248624 A CN 118248624A CN 202410074160 A CN202410074160 A CN 202410074160A CN 118248624 A CN118248624 A CN 118248624A
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- Prior art keywords
- layer
- substrate
- forming
- interlayer dielectric
- etching
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- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 117
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method for leading out an SOI substrate, which comprises the steps of providing a substrate, forming an insulating layer and a silicon layer positioned on the insulating layer on the substrate, forming shallow trench isolation on the substrate to define an active region, forming a grid structure and source and drain regions positioned on two sides of the grid structure on the silicon layer, and forming a groove for leading out the substrate on the silicon layer and the insulating layer below the silicon layer; forming a first etching stop layer on the substrate, and forming a first interlayer dielectric layer on the first etching stop layer, so that the active region and the first interlayer dielectric layer on the groove form a height difference; forming a second etching stop layer on the first interlayer dielectric layer, and forming a second interlayer dielectric layer on the second etching stop layer; and forming a contact hole on the second interlayer dielectric layer by photoetching and first etching, wherein the first etching is stopped on the second etching stop layer. The invention can ensure that the contact hole on the groove is completely contacted with the substrate; the method of the present invention does not require multiple exposures.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method for leading out an SOI substrate.
Background
Referring to fig. 1 and 2, when forming a MOS device on an soi (silicon on insulator) device, a buried oxide layer of the contact Kong Dachuan on the trench is generally required to conduct away charges in the substrate, and since the contact hole on the trench is deeper, it is generally required to increase the CD (critical dimension) of the contact hole on the trench to increase the etching rate, so that the contact hole on the active region and the contact hole on the trench connect the gate structure, the active region and the substrate at the same time.
Although the etching rate is increased by increasing the CD of the contact hole on the trench, there is often an incomplete contact with the silicon substrate in the contact hole on the edge portion trench due to the excessive difference in height between the top silicon layer and the substrate silicon.
In order to solve the above problems, a novel method for manufacturing the SOI substrate lead-out needs to be proposed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing an SOI substrate, which is used to solve the problem that in the prior art, the etching rate is increased by increasing the CD of the contact hole on the trench, but the contact hole on the trench at the edge portion often has incomplete contact with the silicon substrate due to the excessively large difference between the silicon layer at the top and the silicon level of the substrate.
To achieve the above and other related objects, the present invention provides a method for manufacturing an SOI substrate lead-out, comprising:
Providing a substrate, wherein an insulating layer and a silicon layer positioned on the insulating layer are formed on the substrate, shallow trench isolation is formed on the substrate to define an active region, a grid structure and source and drain regions positioned on two sides of the grid structure are formed on the silicon layer, and a groove for leading out the substrate is formed on the silicon layer and the insulating layer below the silicon layer;
forming a first etching stop layer on the substrate, and forming a first interlayer dielectric layer on the first etching stop layer, so that the active region and the first interlayer dielectric layer on the groove form a height difference;
Forming a second etching stop layer on the first interlayer dielectric layer, and forming a second interlayer dielectric layer on the second etching stop layer;
forming a contact hole on the second interlayer dielectric layer by photoetching and first etching, wherein the first etching is stopped on the second etching stop layer;
Fifthly, continuing to etch the bottom of the contact hole by utilizing second etching, so that the bottom of the contact hole is in contact with the substrate at the bottoms of the grid structure, the source region, the drain region and the groove;
and step six, forming a metal layer filling the contact hole by deposition and grinding.
Preferably, the substrate in the first step is a silicon substrate.
Preferably, the material of the insulating layer in the first step is silicon dioxide.
Preferably, the gate structure in the first step includes a gate layer and sidewall structures located on two sides of the gate layer.
Preferably, the material of the first etching stop layer in the second step is silicon nitride.
Preferably, the material of the first interlayer dielectric layer in the second step is silicon dioxide.
Preferably, the material of the second etching stop layer in the third step is silicon nitride.
Preferably, the material of the second interlayer dielectric layer in the third step is silicon dioxide.
Preferably, the first and second etching methods in the fourth and fifth steps are dry etching methods.
Preferably, the material of the metal layer in the sixth step is tungsten.
As described above, the method for manufacturing an SOI substrate lead-out according to the present invention has the following advantageous effects:
the invention can ensure that the contact hole on the groove is completely contacted with the substrate; the method of the present invention does not require multiple exposures.
Drawings
FIG. 1 is a schematic top view of a prior art contact hole on an active region and a prior art contact hole on a trench;
FIG. 2 is a schematic diagram of a prior art contact Kong Poumian over a contact hole and a trench over an active region;
FIG. 3 is a schematic illustration of the process flow of the present invention;
FIG. 4 is a schematic illustration of the formation of trenches in accordance with the present invention;
FIG. 5 is a schematic diagram illustrating the formation of a first interlayer dielectric layer according to the present invention;
FIG. 6 is a schematic diagram of forming a second interlayer dielectric layer according to the present invention;
FIG. 7 is a schematic diagram of a first etch according to the present invention;
FIG. 8 is a schematic diagram of a second etching process according to the present invention;
FIG. 9 is a schematic view of a metal layer formed according to the present invention;
FIG. 10 is a schematic view of a polishing metal layer according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 3, the present invention provides a method for manufacturing an SOI substrate lead-out, comprising:
Providing a substrate 101, wherein an insulating layer 102 and a silicon layer 103 positioned on the insulating layer 102 are formed on the substrate 101, shallow trench 105 isolation is formed on the substrate 101 to define an active region, the active region is a main circuit region in a chip, a gate structure and source and drain regions positioned on two sides of the gate structure are formed on the silicon layer 103, a groove 105 for leading out the substrate 101 is formed on the silicon layer 103 and the insulating layer 102 below the silicon layer 103, a structure shown in fig. 4 is formed, the groove 105 is a peripheral groove contact hole region, and the peripheral groove contact hole region surrounds the main circuit region;
In some embodiments of the present invention, the substrate 101 in step one is a silicon substrate.
In some embodiments of the present invention, the material of the insulating layer 102 in the first step is silicon dioxide.
In some embodiments of the present invention, the gate structure in the first step includes a gate layer and sidewall structures located on both sides of the gate layer. For example, the gate layer may include a gate oxide layer and a gate polysilicon layer 103 formed on the gate oxide layer, the sidewall structure may be one or more layers, and the material of the sidewall may include at least one of silicon dioxide or silicon nitride. The gate layer may also be a metal gate structure. The gate structure may be any other known structure, and is not particularly limited herein.
Step two, forming a first etching stop layer 106 on the substrate 101, and forming a first interlayer dielectric layer 107 on the first etching stop layer 106, so that a height difference is formed between the active region and the first interlayer dielectric layer 107 on the trench 105, and a structure as shown in fig. 5 is formed;
in some embodiments of the present invention, the material of the first etching stop layer 106 in the second step is silicon nitride.
In some embodiments of the present invention, the material of the first interlayer dielectric layer 107 in the second step is silicon dioxide.
Step three, forming a second etching stop layer 108 on the first interlayer dielectric layer 107, and forming a second interlayer dielectric layer 109 on the second etching stop layer 108 to form a structure as shown in fig. 6;
In some embodiments of the present invention, the material of the second etch stop layer 108 in step three is silicon nitride.
In some embodiments of the present invention, the material of the second interlayer dielectric layer 109 in the third step is silicon dioxide.
Forming a contact hole 111 on the second interlayer dielectric layer 109 by using photolithography and first etching, specifically forming a photoresist layer 110 on the second interlayer dielectric layer 109, opening the photoresist layer 110 by using photolithography to define a forming position of the contact hole 111, and etching the second interlayer dielectric layer 109 to form the contact hole 111, wherein the first etching is stopped on the second etching stop layer 108, i.e. the depth of the contact hole 111 on the trench 105 is greater than the depth of the contact hole 111 on the active region, so as to form a structure as shown in fig. 7;
In some embodiments of the present invention, the method of the first etching of the fourth step is dry etching.
Step five, continuing to etch the bottom of the contact hole 111 by using the second etching, so that the bottom of the contact hole 111 contacts the gate structure, the source and drain regions and the substrate 101 at the bottom of the trench 105 to form a structure as shown in fig. 8, wherein photoresist is removed completely in the etching process, and if the photoresist still exists, the residual photoresist layer 110 needs to be removed;
in some embodiments of the invention, the method of the second etching in the fifth step is dry etching.
Step six, a metal layer 112 filling the contact hole 111 is formed by deposition and grinding. Specifically, the metal layer 112 filling the contact hole 111 is formed by deposition, the structure shown in fig. 9 is formed, and then the metal layer 112 is polished onto the second interlayer dielectric layer 109 by a chemical mechanical planarization polishing method, so as to form the structure shown in fig. 10. The invention can ensure that the contact hole 111 on the groove 105 is completely contacted with the substrate 101; the method of the present invention does not require multiple exposures.
In some embodiments of the present invention, the material of the metal layer 112 in the sixth step is tungsten. The material of the metal layer 112 may be any other known conductive material, such as copper.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the contact hole on the groove can be ensured to be completely contacted with the substrate; the method of the present invention does not require multiple exposures.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method for manufacturing an SOI substrate lead-out is characterized by comprising at least:
Providing a substrate, wherein an insulating layer and a silicon layer positioned on the insulating layer are formed on the substrate, shallow trench isolation is formed on the substrate to define an active region, a grid structure and source and drain regions positioned on two sides of the grid structure are formed on the silicon layer, and a groove for leading out the substrate is formed on the silicon layer and the insulating layer below the silicon layer;
forming a first etching stop layer on the substrate, and forming a first interlayer dielectric layer on the first etching stop layer, so that the active region and the first interlayer dielectric layer on the groove form a height difference;
Forming a second etching stop layer on the first interlayer dielectric layer, and forming a second interlayer dielectric layer on the second etching stop layer;
forming a contact hole on the second interlayer dielectric layer by photoetching and first etching, wherein the first etching is stopped on the second etching stop layer;
Fifthly, continuing to etch the bottom of the contact hole by utilizing second etching, so that the bottom of the contact hole is in contact with the substrate at the bottoms of the grid structure, the source region, the drain region and the groove;
and step six, forming a metal layer filling the contact hole by deposition and grinding.
2. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: the substrate in the first step is a silicon substrate.
3. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: the material of the insulating layer in the first step is silicon dioxide.
4. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: the gate structure in the first step includes a gate layer and sidewall structures located on two sides of the gate layer.
5. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and in the second step, the material of the first etching stop layer is silicon nitride.
6. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and in the second step, the material of the first interlayer dielectric layer is silicon dioxide.
7. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and in the third step, the material of the second etching stop layer is silicon nitride.
8. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and in the third step, the material of the second interlayer dielectric layer is silicon dioxide.
9. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and step four and step five, the first and second etching methods are dry etching.
10. The method for manufacturing an SOI substrate lead-out according to claim 1, characterized in that: and step six, the material of the metal layer is tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410074160.4A CN118248624A (en) | 2024-01-17 | 2024-01-17 | Method for manufacturing SOI substrate lead-out |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410074160.4A CN118248624A (en) | 2024-01-17 | 2024-01-17 | Method for manufacturing SOI substrate lead-out |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118248624A true CN118248624A (en) | 2024-06-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410074160.4A Pending CN118248624A (en) | 2024-01-17 | 2024-01-17 | Method for manufacturing SOI substrate lead-out |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118248624A (en) |
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2024
- 2024-01-17 CN CN202410074160.4A patent/CN118248624A/en active Pending
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