CN115954270A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN115954270A CN115954270A CN202310004174.4A CN202310004174A CN115954270A CN 115954270 A CN115954270 A CN 115954270A CN 202310004174 A CN202310004174 A CN 202310004174A CN 115954270 A CN115954270 A CN 115954270A
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Abstract
The application provides a preparation method of a semiconductor device, which comprises the following steps: forming a top metal layer on the semiconductor layer; forming an insulating layer on the semiconductor layer to cover the first metal structure and the second metal structure, wherein the lowest part of the upper surface of the insulating layer is higher than the top surface of the top metal layer; planarizing the insulating layer; etching the insulating layer to form a first groove, wherein the first groove is positioned above the second metal structure, and the bottom surface of the first groove is higher than the top surface of the second metal structure; and etching the insulating layer to form a second groove, deepening the first groove until the second metal structure is exposed at the bottom, and arranging the second groove at intervals with the first metal structure and the second metal structure in the horizontal direction. According to the method, the thickness of the insulating layer is increased, the planarization process is added at the same time, the insulating layer above the second metal structure is opened through step-by-step etching, the insulating layer above the first metal structure can be well protected in the process, the probability of damage of the first metal structure is reduced, and the product yield is favorably improved.
Description
Technical Field
The application belongs to the technical field of semiconductors and relates to a preparation method of a semiconductor device.
Background
Semiconductor devices are fabricated layer by means of planar processes. For a logic device, firstly, a region (active area) for preparing a transistor is divided on a substrate, then an N-type region and a P-type region are realized through ion implantation, secondly, a grid is made, and then ion implantation is carried out again to complete a source (source) and a drain (drain) of each transistor. This part of the process flow is for implementing N-type and P-type field effect transistors on the substrate, also referred to as front end of line (FEOL). Corresponding to the back end of line (BEOL) process, the BEOL process is used to build several layers of conductive metal lines, and different layers of metal lines are connected by columnar metal.
In a semiconductor manufacturing process, a Top Metal (Top Metal) is an indispensable part. In the wafer level production process, when the oxide layer on some top metal structures is removed, the oxide layer above other top metal structures with special patterns to be protected is easily damaged, and further the top metal structures with special patterns are easily damaged, so that the quality problem is caused.
Therefore, how to improve the manufacturing method of the semiconductor device to improve the yield rate of the product becomes an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a method for manufacturing a semiconductor device, which is used to solve the problem that the yield is reduced due to the easy damage of the top metal structure by the conventional manufacturing method.
To achieve the above and other related objects, the present application provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor layer, and forming a top metal layer on the semiconductor layer, wherein the top metal layer comprises a first metal structure and a second metal structure which are arranged at intervals in the horizontal direction;
forming an insulating layer on the semiconductor layer, wherein the insulating layer covers the first metal structure and the second metal structure, and the lowest position of the upper surface of the insulating layer is higher than the top surface of the top metal layer;
flattening the insulating layer to obtain an insulating plane, wherein the insulating plane is higher than the top surface of the top metal layer;
etching the insulating layer to form a first groove, wherein the first groove is positioned above the second metal structure, and the bottom surface of the first groove is higher than the top surface of the second metal structure;
and etching the insulating layer to form a second groove, deepening the first groove until the bottom of the first groove is exposed out of the second metal structure, wherein the second groove is arranged at intervals with the first metal structure and the second metal structure in the horizontal direction.
Optionally, the method comprises the following steps:
forming a first mask layer on the insulation plane, and patterning the first mask layer to obtain a first opening, wherein the first opening is positioned above the second metal structure;
etching the insulating layer based on the first opening to obtain a first groove, wherein the bottom surface of the first groove is higher than the top surface of the second metal structure;
forming a second mask layer on the insulating plane, and patterning the second mask layer to obtain a second opening and a third opening which are arranged at intervals, wherein the second opening is positioned above the second metal structure, and the insulating layer above the first metal structure is still covered with the second mask layer;
and etching the insulating layer based on the second opening and the third opening until the second metal structure is exposed from the bottom of the first groove, and obtaining the second groove in the insulating layer in the area where the third opening is located.
Optionally, before forming the second mask layer on the insulating plane, the first mask layer remaining after forming the first groove is removed.
Optionally, the first mask layer includes a photoresist layer, and the second mask layer includes a photoresist layer.
Optionally, the third opening is located between the first metal structure and the second metal structure in a horizontal direction.
Optionally, after the insulating layer is etched based on the second opening and the third opening until the second metal structure is exposed from the bottom of the first groove, a portion of the second mask layer still remains on the insulating layer above the first metal structure.
Optionally, the width of the first metal structure is smaller than the width of the second metal structure.
Optionally, the first metal structure comprises a metal line and the second metal structure comprises a pad.
Optionally, a material of the insulating layer includes silicon oxide.
Optionally, the method for etching the insulating layer to obtain the first groove includes at least one of dry etching and wet etching, and the method for etching the insulating layer until the bottom of the first groove exposes the second metal structure and obtains the second groove includes at least one of dry etching and wet etching.
As described above, according to the manufacturing method of the semiconductor device, the thickness of the insulating layer is increased, the planarization process is added, and the insulating layer above the second metal structure is opened through step-by-step etching. In the second etching step, besides the insulating layer above the second metal structure, the insulating layer in other required areas can be etched together.
Drawings
Fig. 1 is a schematic view showing a structure to be etched provided in a method for manufacturing a semiconductor device.
Fig. 2 is a schematic view illustrating a method of manufacturing a semiconductor device in which a photoresist layer is formed to cover an insulating layer.
Fig. 3 is a schematic diagram illustrating a method for manufacturing a semiconductor device, in which the photoresist layer is patterned to obtain a photoresist layer opening exposing the insulating layer above the second metal structure, and then the insulating layer is etched based on the photoresist layer opening to expose the second metal structure.
Fig. 4 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to the present application.
Fig. 5 is a schematic diagram illustrating a top metal layer formed on the semiconductor layer and an insulating layer formed on the semiconductor layer according to the method for manufacturing a semiconductor device of the present application.
Fig. 6 is a schematic view showing a process for planarizing the insulating layer to obtain an insulating plane according to the method for manufacturing a semiconductor device of the present application.
Fig. 7 is a schematic view illustrating a first mask layer formed on the insulating plane and patterned to obtain a first opening according to the method of manufacturing a semiconductor device of the present application.
Fig. 8 is a schematic diagram illustrating that the insulating layer is etched based on the first opening to obtain a first groove in the method for manufacturing a semiconductor device according to the present application.
Fig. 9 is a schematic diagram illustrating a second mask layer formed on the insulating plane and patterned to obtain second and third openings arranged at intervals according to the method for manufacturing a semiconductor device of the present application.
Fig. 10 is a schematic diagram illustrating that the insulating layer is etched until the second metal structure is exposed at the bottom of the first groove and a second groove is formed in the insulating layer in the region where the third opening is located according to the method for manufacturing a semiconductor device of the present application.
Description of the element reference numerals
S1 to S5
101. Semiconductor layer
102. First metal structure
103. Second metal structure
104. Insulating layer
105. Photoresist layer
201. Semiconductor layer
202. First metal structure
203. Second metal structure
204. Insulating layer
205. First mask layer
206. A first opening
207. The first groove
208. Second mask layer
209. Second opening
210. Third opening
211. Second groove
M insulating plane
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, quantity and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1 to 3, a method for manufacturing a semiconductor device includes the following steps:
(1) As shown in fig. 1, a structure to be etched is provided, which includes a semiconductor layer 101, a first metal structure 102, a second metal structure 103, and an insulating layer 104, wherein a width of the first metal structure 102 is much smaller than a width of the second metal structure 103, a portion of the insulating layer 104 on the second metal structure 103 is relatively flat, and a portion on the first metal structure 102 has a protruding tip.
(2) As shown in fig. 2, a photoresist layer 105 is formed to cover the insulating layer 104.
(3) As shown in fig. 3, the photoresist layer 105 is patterned to obtain a photoresist layer opening exposing the insulating layer above the second metal structure 103, and then the insulating layer 104 is etched based on the photoresist layer opening to expose the second metal structure 103.
In the above method for manufacturing a semiconductor device, due to the special pattern (such as a single metal line) of the first metal structure 102 and the thinner photoresist layer covering on the first metal structure 102, the insulation layer on the first metal structure 102 is easily exposed and damaged, and the first metal structure 102 is easily damaged to cause quality problems. Accordingly, the present application improves upon the semiconductor processing steps to address the above-mentioned problems.
Referring to fig. 4, a process flow diagram of a method for fabricating a semiconductor device according to the present application is shown, which includes the following steps:
s1: providing a semiconductor layer, and forming a top metal layer on the semiconductor layer, wherein the top metal layer comprises a first metal structure and a second metal structure which are arranged at intervals in the horizontal direction;
s2: forming an insulating layer on the semiconductor layer, wherein the insulating layer covers the first metal structure and the second metal structure, and the lowest position of the upper surface of the insulating layer is higher than the top surface of the top metal layer;
s3: flattening the insulating layer to obtain an insulating plane, wherein the insulating plane is higher than the top surface of the top metal layer;
s4: etching the insulating layer to form a first groove, wherein the first groove is positioned above the second metal structure, and the bottom surface of the first groove is higher than the top surface of the second metal structure; .
S5: and etching the insulating layer to form a second groove, deepening the first groove until the bottom of the first groove is exposed out of the second metal structure, wherein the second groove is arranged at intervals with the first metal structure and the second metal structure in the horizontal direction.
Referring to fig. 5, the steps S1 and S2 are executed: providing a semiconductor layer 201, forming a top metal layer on the semiconductor layer, wherein the top metal layer comprises a first metal structure 202 and a second metal structure 203 which are arranged at intervals in the horizontal direction, and forming an insulating layer 204 on the semiconductor layer 201, the insulating layer 204 covers the first metal structure 202 and the second metal structure 203, and the lowest position of the upper surface of the insulating layer 204 is higher than the top surface of the top metal layer.
As an example, the semiconductor layer 201 may be pre-fabricated with a transistor structure, a conductive interconnection structure, and other required structures. The material of the top metal layer includes but is not limited to copper or aluminum.
As an example, the first metal structure 202 and the second metal structure 203 have different patterns. In this embodiment, the width of the first metal structure 202 is smaller than the width of the second metal structure 203.
As an example, the first metal structure 202 includes a metal line, and the second metal structure 203 includes a pad. In this embodiment, the first metal structure 202 is a single metal line adjacent to the second metal structure 203.
By way of example, the insulating layer 204 is formed by chemical vapor deposition, physical vapor deposition or other suitable methods, and the material of the insulating layer 204 includes, but is not limited to, silicon oxide.
Referring to fig. 6 again, the step S3 is executed: the insulating layer 204 is planarized using Chemical Mechanical Polishing (CMP) or other suitable method to obtain an insulating plane M that is higher than the top surface of the top metal layer.
Referring to fig. 7 and 8, the step S4 is executed: the insulating layer 204 is etched to form a first groove 207, the first groove 207 is located above the second metal structure 203, and the bottom surface of the first groove 207 is higher than the top surface of the second metal structure 203.
As an example, as shown in fig. 7, a first mask layer 205 is formed on the insulation plane M, and the first mask layer 205 is patterned to obtain a first opening 206, wherein the first opening 206 is located above the second metal structure 203.
As an example, the first mask layer 205 includes a photoresist layer, the first mask layer 205 is patterned by a photolithography process such as exposure and development to obtain the first opening 206, and the bottom surface of the first opening 206 exposes the insulating layer 204.
As an example, as shown in fig. 8, the insulating layer 204 is etched based on the first opening 206 to obtain the first groove 207, and a bottom surface of the first groove 207 is higher than a top surface of the second metal structure 203.
As an example, the method for etching the insulating layer 204 to obtain the first groove 207 includes at least one of dry etching and wet etching.
As an example, during the etching of the insulating layer 204 to obtain the first recess 207, the thickness of the first masking layer 205 is thinned, but still covers the insulating layer above the first metal structure 202.
Referring to fig. 9 and 10 again, the step S5 is executed: and etching the insulating layer 204 to form a second groove 211, deepening the first groove 207 until the bottom of the first groove 207 exposes the second metal structure 203, wherein the second groove 207 is arranged at an interval with the first metal structure 202 and the second metal structure 203 in the horizontal direction.
For example, as shown in fig. 9, a second mask layer 208 is formed on the insulating plane M, and the second mask layer 208 is patterned to obtain second openings 209 and third openings 210 arranged at intervals, wherein the second openings 209 are located above the second metal structures 203, and the insulating layer above the first metal structures 202 is still covered with the second mask layer 208.
As an example, before forming the second mask layer 208 on the insulating plane M, the first mask layer 205 remaining after forming the first recess 207 is removed.
As an example, the second mask layer 208 includes a photoresist layer, the second mask layer 208 is patterned by photolithography processes such as exposure and development to obtain the second opening 209 and the third opening 210, and the insulating layer 204 is exposed on bottom surfaces of the second opening 209 and the third opening 210.
As an example, the third opening 210 is located between the first metal structure 202 and the second metal structure 203 in a horizontal direction or other desired etching region.
As an example, as shown in fig. 10, the insulating layer 204 is etched based on the second opening 209 and the third opening 210 until the second metal structure 203 is exposed at the bottom of the first groove 207, and a second groove 211 is obtained in the insulating layer 204 in the area where the third opening 210 is located.
As an example, the method for etching the insulating layer 204 until the bottom of the first groove 207 exposes the second metal structure 203 and obtaining the second groove 211 includes at least one of dry etching and wet etching.
As an example, after the insulating layer 204 is etched based on the second opening 209 and the third opening 210 until the second metal structure 203 is exposed at the bottom of the first groove 207, a portion of the second mask layer 208 still remains on the insulating layer 204 above the first metal structure 202, that is, the insulating layer 204 above the first metal structure 202 can be well protected, so that the probability of damaging the first metal structure 202 is reduced.
In summary, according to the manufacturing method of the semiconductor device, the thickness of the insulating layer is increased, the planarization process is added, and the insulating layer above the second metal structure is opened through step-by-step etching. In the second etching step, the insulating layer in other desired areas except the insulating layer above the second metal structure can be etched together. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor layer (201), and forming a top metal layer on the semiconductor layer (201), wherein the top metal layer comprises a first metal structure (202) and a second metal structure (203) which are arranged at intervals in the horizontal direction;
forming an insulating layer (204) on the semiconductor layer (201), wherein the insulating layer (204) covers the first metal structure (202) and the second metal structure (203), and the lowest position of the upper surface of the insulating layer (204) is higher than the top surface of the top metal layer;
planarizing the insulating layer (204) to obtain an insulating plane (M) which is higher than the top surface of the top metal layer;
etching the insulating layer (204) to form a first groove (207), wherein the first groove (207) is positioned above the second metal structure (203), and the bottom surface of the first groove (207) is higher than the top surface of the second metal structure (203);
and etching the insulating layer (204) to form a second groove (211), deepening the first groove (207) until the bottom of the first groove (207) exposes the second metal structure (203), wherein the second groove (207) is arranged at intervals with the first metal structure (202) and the second metal structure (203) in the horizontal direction.
2. A method for manufacturing a semiconductor device according to claim 1, comprising the steps of:
forming a first mask layer (205) on the insulation plane (M) and patterning the first mask layer (205) to obtain a first opening (206), the first opening (206) being located above the second metal structure (203);
etching the insulating layer based on the first opening (206) to obtain the first groove (207), wherein the bottom surface of the first groove (207) is higher than the top surface of the second metal structure (203);
forming a second mask layer (208) on the insulation plane (M), and patterning the second mask layer (208) to obtain second openings (209) and third openings (210) which are arranged at intervals, wherein the second openings (209) are located above the second metal structure (203), and the insulation layer (204) above the first metal structure (202) is still covered with the second mask layer (208);
etching the insulating layer (204) based on the second opening (209) and the third opening (210) until the bottom of the first recess (207) reveals the second metal structure (203), and obtaining the second recess (207) in the insulating layer (204) in the region of the third opening (207).
3. The method for manufacturing a semiconductor device according to claim 2, wherein: before forming the second mask layer (208) on the insulation plane (M), the first mask layer (205) remaining after forming the first groove (207) is removed.
4. The method for manufacturing a semiconductor device according to claim 2, wherein: the first masking layer (205) comprises a photoresist layer and the second masking layer (208) comprises a photoresist layer.
5. The method for manufacturing a semiconductor device according to claim 2, wherein: the third opening (210) is located between the first metal structure (202) and the second metal structure (203) in a horizontal direction.
6. The method for manufacturing a semiconductor device according to claim 2, wherein: after etching the insulating layer (204) based on the second opening (209) and the third opening (210) until the bottom of the first recess (207) reveals the second metal structure (203), a portion of the second mask layer (208) remains on the insulating layer (204) above the first metal structure (202).
7. The method for manufacturing a semiconductor device according to claim 1, wherein: the width of the first metal structure (202) is smaller than the width of the second metal structure (203).
8. The method for manufacturing a semiconductor device according to claim 1, wherein: the first metal structure (202) comprises a metal line and the second metal structure (203) comprises a bond pad.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: the material of the insulating layer (204) comprises silicon oxide.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: the method for etching the insulating layer (204) to obtain the first groove (207) comprises at least one of dry etching and wet etching, and the method for etching the insulating layer (204) until the second metal structure (203) is exposed at the bottom of the first groove (207) and obtaining the second groove (211) comprises at least one of dry etching and wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310004174.4A CN115954270A (en) | 2023-01-03 | 2023-01-03 | Preparation method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310004174.4A CN115954270A (en) | 2023-01-03 | 2023-01-03 | Preparation method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115954270A true CN115954270A (en) | 2023-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310004174.4A Pending CN115954270A (en) | 2023-01-03 | 2023-01-03 | Preparation method of semiconductor device |
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| CN (1) | CN115954270A (en) |
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- 2023-01-03 CN CN202310004174.4A patent/CN115954270A/en active Pending
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