CN113190078A - Constant current source driving circuit and control method thereof - Google Patents

Constant current source driving circuit and control method thereof Download PDF

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CN113190078A
CN113190078A CN202110495062.4A CN202110495062A CN113190078A CN 113190078 A CN113190078 A CN 113190078A CN 202110495062 A CN202110495062 A CN 202110495062A CN 113190078 A CN113190078 A CN 113190078A
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tubes
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CN113190078B (en
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不公告发明人
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Chengdu Lipson Microelectronics Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract

The invention discloses a control method of a constant current source driving circuit and the constant current source driving circuit, wherein the constant current source driving circuit comprises a current mirror consisting of a current input unit and a current output unit, and the output current of the current output unit is divided into at least 2 output intervals; the control method comprises the following steps: the access number of MOS tubes in the current input unit and the current output unit is controlled according to the output interval, and the requirements are met: output interval 1: the total number of the MOS tubes connected into the current input unit is controlled to be X1, and the total number of the MOS tubes connected into the current output unit is controlled to be Z1; output interval 2: the total number of the MOS tubes connected into the current input unit is controlled to be X2, and the total number of the MOS tubes connected into the current output unit is controlled to be Z2; wherein, X1/Z1 is X2/Z2 is … … Xn/Zn, and X1-Xn are not equal.

Description

Constant current source driving circuit and control method thereof
Technical Field
The invention relates to the technical field of constant current source generation, in particular to a constant current source driving circuit and a control method thereof.
Background
Fig. 1 shows a constant current source driving generation circuit in a constant current source driving chip of a commonly used LED display screen, in which R1 is an external resistor of the driving chip. The length ratio of the single tube width of the PMOS1 is equal to that of the single tube width of the PMOS2, and the ratio of the number of the PMOS in parallel is X: Y. The current flowing through PMOS2 is IOUT, and the constant current source is generated according to the following principle, assuming that the gain of the amplifier in the figure is infinite:
1. generating a required reference potential VREF from the Bandgap;
the drain potential of PMOS1 is clamped to VREF by amplifier AMP1, so the source-drain current flowing through PMOS1 is: i ═ VREF/R1;
and 3, the PMOS2 and the PMOS1 form a current mirror, and the current ratio of the current mirror (the source-drain current of the PMOS2 is greater than the source-drain current of the PMOS 1) is Y/X, so that the source-drain current of the PMOS2 is as follows:
Figure BDA0003053906690000011
from the formula of IOUT, the size and accuracy of IOUT are affected by the ratio of the number X and Y of parallel PMOS1 and PMOS 2. X, Y directly affects the output range of the IOUT.
In order to adjust the output range of IOUT, the size of PMOS1 is generally fixed, and the size of PMOS2 is changed, i.e., X is fixed and Y is changed. That is, the prior art adopts the mirror image ratio to be adjusted, and the adjusting mode has the following problems:
since the input current is determined by VREF and external resistor R1, the size of X, Y determines the number of parallel transistors, and thus the current passing through a single MOS transistor. The parameters of the single tube of each channel of PMOS1 and PMOS2 need to satisfy the requirement of normal operation at the maximum output current, and when the output current is minimum, | VGS | (absolute value of VGS) of the single MOS of the channels of PMOS1 and PMOS2 is very small, so that the single MOS cannot operate at the optimum precision state, which may deteriorate the two sets of current mirrors mentioned above, and also deteriorate the precision of the output constant current source. The value of Y/X is critical to the operating state of the current mirror.
Disclosure of Invention
The invention aims to provide a constant current source driving circuit and a control method thereof, wherein the number of PMOS tubes connected in parallel at the input end and the output end of a current mirror is regulated under the constraint condition that the output current IOUT (image ratio) is constant, so that a single PMOS tube always works in a reasonable precision state, the consistency of the output current is ensured, and the precision of the current mirror is improved.
The invention is realized by the following technical scheme:
the control method of the constant current source driving circuit comprises a current mirror unit, the current mirror unit comprises a current input unit and a current output unit,
the control method of the constant current source driving circuit comprises a current mirror composed of a current input unit and a current output unit,
the output current of the current output unit is divided into at least 2 output intervals;
the control method comprises the following steps: the access number of MOS tubes in the current input unit and the current output unit is controlled according to the output interval, and the requirements are met:
output interval 1: the total number of the MOS tubes connected into the current input unit is controlled to be X1, and the total number of the MOS tubes connected into the current output unit is controlled to be Z1;
output interval 2: the total number of the MOS tubes connected into the current input unit is controlled to be X2, and the total number of the MOS tubes connected into the current output unit is controlled to be Z2;
……
output interval n: the total number of the MOS tubes connected into the current input unit is controlled to be Xn, and the total number of the MOS tubes connected into the current output unit is controlled to be Zn;
wherein, X1/Z1 is X2/Z2 is … … Xn/Zn, and X1-Xn are not equal.
Further, the technical scheme is as follows:
the total number access control mode of the MOS tubes comprises the following steps:
mode 1: all MOS tubes are regarded as single tubes and are independently controlled to be accessed;
mode 2: all the MOS tubes are divided into partitions to obtain at least 2 MOS tube partitions, each MOS tube partition is used as an integral area to be controlled to be accessed integrally, and meanwhile, the MOS tubes in each MOS tube partition are used as single tubes to be controlled to be accessed independently.
Further, the technical scheme is as follows:
the current input unit is: a first MOS transistor device;
the current output unit is: at least 2 MOS device devices connected in parallel, comprising:
a second MOS device forming a first current mirror with the first MOS device;
a third MOS device forming a second current mirror with the first MOS device;
the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source;
output interval 1: the total number of the accessed MOS tubes in the first MOS tube device is controlled to be X1, and the second MOS tube device and the third MOS tube device are controlled to be accessed to form double-current-mirror access, at the moment, the number of the accessed MOS tubes in the second MOS tube device is controlled to be Y1, the number of the accessed MOS tubes in the third MOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output interval 2: the total number of the connected MOS tubes in the first MOS tube device is controlled to be X2, one of the second MOS tube device and the third MOS tube device is controlled to be connected to form single-current-mirror connection, the number of the connected MOS tubes in the second MOS tube device is controlled to be Y1 or 0, the number of the connected MOS tubes in the third MOS tube device is controlled to be 0 or Y2, and Z2 is Y1+0 or 0+ Y2.
It should be noted that, in the present application, there are several output intervals and the current output unit includes several MOS devices connected in parallel.
Further, the technical scheme is as follows:
the first MOS tube device consists of 2 groups of MOS tube devices connected in parallel, and is defined as an A group and a B group, and each group consists of the same number of MOS tubes connected in parallel;
the second MOS tube device and the third MOS tube device are respectively formed by connecting 1 group of MOS tubes with the same quantity in parallel;
output interval 1: the group A and the group B are controlled to be accessed, and the number of the accessed MOS tubes in the group A and the group B is controlled as follows: xA′、XB' the total number of the connected MOS transistors in the first MOS transistor device is controlled to be X1, and X1 is XA′+XB'; the second MOS tube device and the third MOS tube device are controlled to be connected to form dual-current mirror connection, at the moment, the number of the connected MOS tubes in the second MOS tube device is controlled to be Y1, the number of the connected MOS tubes in the third MOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output ofInterval 2: one of the group A and the group B is controlled to be accessed, and the number of the accessed MOS tubes in the group A and the group B is controlled as follows: "XA', 0' or "0, XB' the total number of the MOS tubes connected in the first MOS tube device is controlled to be X2 ═ XA'+ 0' or "0 + XB' "; one of the second MOS device and the third MOS device is controlled to be connected, the number of the connected MOS transistors in the second MOS device is controlled to be Y1 or 0, the number of the connected MOS transistors in the third MOS device is controlled to be 0 or Y2, and Z2 is "Y1 '+ 0" or "0 + Y2'".
A constant current source driving circuit includes a current input unit and a current output unit;
the current input unit is: the first MOS tube device is used for outputting a reference current I;
the current output unit is: at least two sets of MOS device devices in parallel, comprising:
a second MOS device forming a first current mirror with the first MOS device;
a third MOS device forming a second current mirror with the first MOS device;
and the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source.
Further, the technical scheme is as follows:
the first MOS tube device, the second MOS tube device and the third MOS tube device are all composed of MOS tubes with the same single tube width-length ratio, and the number ratio of the MOS tubes is X: Y1: Y2;
the MOS tubes form the first MOS tube device, the second MOS tube device and the third MOS tube device in a parallel or serial connection mode.
The first MOS tube device consists of 2 groups of MOS tube devices connected in parallel, and is defined as an A group and a B group, and each group consists of the same number of MOS tubes connected in parallel;
the second MOS tube device and the third MOS tube device are respectively formed by connecting 1 group of MOS tubes with the same quantity in parallel.
Further, the technical scheme is as follows:
a switch element is arranged between the second MOS tube device or the third MOS tube device and the first MOS tube device; the switching element is closed, and the second MOS tube device and the third MOS tube device are connected to work; the switch element is disconnected, and the second MOS tube device or the third MOS tube device is switched on to work.
The switching element consists of a transmission gate TG4 and a fourth MOS tube;
the transmission gate TG4 is connected in series between the first MOS tube device and the second MOS tube device or between the first MOS tube device and the third MOS tube device;
correspondingly, the source and drain of the fourth MOS transistor are connected between the gate and source of the second MOS transistor device, or between the gate and source of the third MOS transistor device;
the input signal of the transmission gate TG4 is IB _ N, the output signal is IB _ P, and IB _ P is input to the gate of the fourth MOS transistor and satisfies IB _ P being 0 when IB _ N is 1 and IB _ P being 1 when IB _ N is 0.
Further, the technical scheme is as follows:
the number of the MOS tubes connected with the first MOS tube device, the second MOS tube device and the third MOS tube device is adjustable, and the adjusting mode comprises processor control, register configuration or a control circuit.
The control circuit includes:
the main control branch circuit is formed by connecting a first inverter and a second inverter in series, a main control signal PGATE _ SEL < n:0> is input into the first inverter, the first inverter outputs a reverse main control signal ps _ n < n:0>, and the second inverter outputs a forward main control signal ps _ p < n:0 >;
the A group control circuit consists of a transmission GATE TG1 and a first switching device tube, wherein an adjusting signal MOS _ GATE outputs a modulation instruction pgate < n:0> through a transmission GATE TG1, the modulation instruction pgate < n:0> is output to the grid electrode of each POMS tube of the A group through the first switching device, a forward main control signal ps _ p < n:0> is used as a trigger signal of the first switching device, and a reverse main control signal ps _ n < n:0> and a forward main control signal ps _ p < n:0> are respectively used as control signals of the transmission GATE TG 1;
the transmission GATE TG2 and the transmission GATE TG3 are connected in series, an adjusting signal MOS _ GATE is input by the transmission GATE TG2, an adjusting instruction pgate2< n:0> is output through the transmission GATE TG3, the adjusting instruction pgate2< n:0> is output to the grid electrode of each POMS tube of the group B through the third switching device, the forward main control signal ps _ p serves as a trigger signal of the third switching device, an input signal of the transmission GATE TG2 is IB _ n, an output signal is IB _ p, the IB _ p serves as a control signal of the second switching device, when the transmission GATE TG2 is turned off, the second switching device is closed, the adjusting instruction pgate2< n:0> is turned over, and each POMS tube of the group B is not conducted;
wherein, the number of MOS tubes in the group A or the group B is n + 1.
Further, the technical scheme is as follows:
the first switching device, the second switching device and the third switching device are MOS tubes.
Further, the technical scheme is as follows:
the circuit also comprises a reference voltage module and an amplifier, wherein the reference voltage module is connected with the amplifier;
the output end of the amplifier is connected to the grids of the first MOS tube device, the second MOS tube device and the third MOS tube device;
the drain electrode of the first MOS device is connected with an external resistor R1, the potential of the first MOS device is clamped to VREF by the amplifier, so that the reference current I output by the first MOS device is VREF/R1;
the drain electrodes of the second MOS tube device and the third MOS tube device are connected in common to be used as output current ends, so that the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source;
the sources of the first MOS tube device, the second MOS tube device and the third MOS tube device are connected with a power supply AVDD.
The design principle of the invention is as follows:
the output current of the current output unit is divided into a plurality of output sections, and the mirror ratios of the plurality of output sections have equal characteristics. The user can select the output interval with the optimal precision according to the 'required output current', so that the optimal adaptation effect is achieved.
The invention relates to control of a current output interval (output range) of a constant current source driving circuit of an LED display screen, aiming at reducing the number of called and accessed PMOS tubes when the output current of the adjustable constant current source driving circuit is the same as the preset output current, thereby ensuring the precision and adapting to the output interval with the optimal precision.
In order to obtain different image ratios, the conventional driving current is realized by the following steps: the current output unit can be independently adjusted, namely Y is adjusted; the current input unit can be independently adjusted, namely X is adjusted; the current input unit and the current output unit may also be regulated simultaneously, respectively, X, Y. Particularly the manner of simultaneous adjustment X, Y, where X, Y is the independent adjustment dimension, there is no binding relationship between the two, and at the same time, the adjustment is only triggered when a new LED is selected. The number of the PMOS tubes is adjusted in the invention, but not in order to enable the constant current source driving circuit to adapt to different image ratios, and when the PMOS tubes are adjusted X, Y at the same time, the adjustment ratio follows the constraint relation. The image ratio of the drive circuit to be switched in is unchanged from the preset image ratio, so that the image ratio with less switching in quantity is selected. It can be understood that: the two methods are different, the facing objects are different, and the using time is different.
Compared with the prior art, the invention has the following advantages and beneficial effects: the number of the PMOS tubes connected with the input end and the output end of the current mirror in parallel is adjusted simultaneously, so that a single PMOS tube in the access circuit is always in a reasonable working state, the consistency of a constant current source output by a control system is ensured, and the precision of a current environment is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic diagram of the prior art.
Fig. 2 is a schematic diagram of embodiment 4 of the present invention.
Fig. 3 is a constant current source driving circuit diagram of embodiment 4 of the present invention.
Fig. 4 is a circuit diagram of a current input unit according to embodiment 4 of the present invention.
Fig. 5 is a circuit diagram of a current output unit according to embodiment 4 of the present invention.
Fig. 6 is a schematic diagram of embodiment 5 of the present invention.
Fig. 7 is a schematic diagram of the output section 1 according to embodiment 6 of the present invention.
Fig. 8 is a circuit diagram of a current input unit and a current output unit according to embodiment 6 of the present invention.
Fig. 9 is a schematic diagram of output section 2 according to embodiment 6 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
See fig. 2-9. The MOS tube in the invention can be a PMOS tube or an NMOS tube, so as to be suitable for a common anode chip and a common cathode chip, and the working principles of the MOS tube and the common anode chip are the same.
The MOS transistor is taken as a PMOS transistor for example as follows:
the control method of the constant current source driving circuit comprises a current mirror unit, and the current mirror unit comprises a current input unit and a current output unit.
The control method of the constant current source driving circuit comprises a current mirror composed of a current input unit and a current output unit,
the output current of the current output unit is divided into at least 2 output intervals;
the control method comprises the following steps: the number of the accessed PMOS tubes in the current input unit and the current output unit is controlled according to the output interval, and the requirements are met:
output interval 1: the total number of the PMOS tubes connected into the current input unit is controlled to be X1, and the total number of the MOS tubes connected into the current output unit is controlled to be Z1;
output interval 2: the total number of the PMOS tubes connected into the current input unit is controlled to be X2, and the total number of the PMOS tubes connected into the current output unit is controlled to be Z2;
……
output interval n: the total number of the PMOS tubes connected into the current input unit is controlled to be Xn, and the total number of the PMOS tubes connected into the current output unit is controlled to be Zn;
wherein, X1/Z1 is X2/Z2 is … … Xn/Zn, and X1-Xn are not equal.
Here, n is greater than or equal to 2, for simplicity, in the following embodiments, 2 output intervals are taken as an example for description, and the implementation manner of greater than 2 output intervals is completely the same as that of 2 output intervals, that is, the MOS transistors in the output unit are divided into how many groups by several output intervals, for example, 3 output intervals, the output unit includes 3 groups of MOS devices, and 4 output intervals include 4 groups of MOS devices.
The total number access control mode of the PMOS tubes comprises the following steps:
mode 1: all PMOS tubes are regarded as single tubes and are independently controlled to be accessed;
mode 2: and partitioning all the PMOS tubes to obtain at least 2 PMOS tube partitions, taking each PMOS tube partition as an integral area to be controlled and accessed integrally, and simultaneously taking the PMOS tubes in each PMOS tube partition as single tubes to be controlled and accessed independently.
The present invention can be implemented by freely combining the above 2 modes.
Such as: all PMOS tubes in the current input unit are regarded as single tubes and are independently controlled to be connected, and all PMOS tubes of the current output unit are divided into regions; in order to adapt to the fact that the total number of the current input units which are controlled to be connected in independently is different, the current output units are controlled to be connected in different integral areas in an integral mode.
For another example: all PMOS tubes in the current input unit are regarded as single tubes and are independently controlled to be connected, and all PMOS tubes in the current output unit are regarded as single tubes and are independently controlled to be connected; in order to adapt to the fact that the total number of the current input units which are independently controlled to be connected is different, the total number of the current output units which are independently controlled to be connected is different.
For another example: all PMOS tubes of the current input unit are divided into regions, all PMOS tubes in the current output unit are regarded as single tubes and are controlled to be connected in an independent mode, and in order to adapt to the fact that the number of whole regions which are controlled to be connected in an integrated mode by the current input unit is different, the total number of the whole regions which are controlled to be connected in an independent mode by the current output unit is different.
For another example: all PMOS tubes of the current input unit are divided into partitions, and all PMOS tubes of the current output unit are divided into partitions; in order to adapt to the different number of the whole areas controlled and connected by the current input unit as a whole (the different number of the whole areas connected can cause the different total number of the whole areas connected by the current input unit), the current output unit is controlled and connected with the whole areas with different number as a whole.
Example 2
See fig. 2-9.
According to the implementation guidance, the following specific implementation modes of the current input unit and the current output unit can be obtained:
preferably, the current input unit is: a first PMOS transistor device having a first gate electrode and a second gate electrode,
the current output unit is: a second PMOS device and a third PMOS device connected in parallel (corresponding to the case of 2 output intervals);
a second PMOS device forming a first current mirror with the first PMOS device;
a third PMOS device forming a second current mirror with the first PMOS device;
the source-drain total current of the second PMOS tube device and the third PMOS tube device is used as the output current IOUT of the constant current source;
output interval 1: the total number of the accessed PMOS tubes in the first PMOS tube device is controlled to be X1, the second PMOS tube device and the third PMOS tube device are controlled to be accessed to form double-current-mirror access, at the moment, the number of the accessed PMOS tubes in the second PMOS tube device is controlled to be Y1, the number of the accessed PMOS tubes in the third PMOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output interval 2: the total number of the connected PMOS tubes in the first PMOS tube device is controlled to be X1, one of the second PMOS tube device and the third PMOS tube device is controlled to be connected to form single-current-mirror connection, the number of the connected PMOS tubes in the second PMOS tube device is controlled to be Y1 or 0, the number of the connected PMOS tubes in the third PMOS tube device is controlled to be 0 or Y2, and Z2 is Y1+0 or 0+ Y2.
Y1＝Y2＝Y。
Preferably, the first PMOS device is composed of 2 groups of PMOS devices connected in parallel, defined as a group a and a group B, each group being composed of the same number of PMOS devices connected in parallel;
the second PMOS tube device and the third PMOS tube device are respectively formed by connecting 1 group of PMOS tubes with the same quantity in parallel;
output interval 1: a group and B group are controlled to be accessed, the number of PMOS tubes accessed in A group and B group is controlled as follows: xA′、XB' the total number of connected PMOS transistors in the first PMOS transistor device is controlled to be X1, X1 ═ XA′+XB'; the second PMOS tube device and the third PMOS tube device are controlled to be connected to form double-current-mirror connection, at the moment, the number of the connected PMOS tubes in the second PMOS tube device is controlled to be Y1, the number of the connected PMOS tubes in the third PMOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output interval 2: one of the group A and the group B is controlled to be accessed, and the number of the accessed PMOS tubes in the group A and the group B is controlled as follows: "XA', 0' or "0, XB' the total number of the PMOS tubes connected in the first PMOS tube device is controlled to be X2 ═ XA'+ 0' or "0 + XB' "; one of the second PMOS transistor device and the third PMOS transistor device is controlled to be connected, the number of connected PMOS transistors in the second PMOS transistor device is controlled to be Y1 or 0, the number of connected PMOS transistors in the third PMOS transistor device is controlled to be 0 or Y2, and Z2 is "Y1 '+ 0" or "0 + Y2'".
Preferably, XA＝XB＝X，Y1＝Y2＝Y。
Preferably, the current input unit is a first PMOS transistor device,
the current output unit is a second PMOS transistor device,
a second PMOS device forming a current mirror with the first PMOS device;
and the source-drain total current of the second PMOS device is used as the output current IOUT of the constant current source.
Output interval 1: the total number of the accessed PMOS tubes in the first PMOS tube device is controlled to be X1, and the number of the accessed PMOS tubes in the second PMOS tube device is controlled to be Z1;
output interval 2: the total number of the accessed PMOS tubes in the first PMOS tube device is controlled to be X2, and the number of the accessed PMOS tubes in the second PMOS tube device is controlled to be Z2.
Preferably, the first PMOS device and the second PMOS device are each composed of 1 group of PMOS devices connected in parallel, and are divided into two groups, the two groups of the first PMOS device are defined as group a1 and group B1, and the two groups of the second PMOS device are defined as group a2 and group B2;
output interval 1: the A1 group and the B1 group of the first PMOS tube devices are controlled to be switched in, and the number of the switched-in PMOS tubes in the A1 group and the B1 group is controlled as follows: xA1′、XB1' the total number of connected PMOS transistors in the first PMOS transistor device is controlled to be X1, X1 ═ XA1′+XB1'; the A2 group and the B2 group of the second PMOS tube devices are controlled to be switched in, and the number of the switched-in PMOS tubes in the A2 group and the B2 group is controlled as follows: y isA2′、YB2' the number of connected PMOS transistors in the second PMOS transistor device is controlled to be Z1, and Z1 is YA2′+YB2′；
Output interval 2: one of the groups a1 and B1 of the first PMOS transistor devices is controlled to be connected, and the number of connected PMOS transistors in the groups a1 and B1 is controlled as follows: "XA1', 0' or "0, XB1' the total number of the PMOS tubes connected in the first PMOS tube device is controlled to be X2 ═ XA1'+ 0' or "0 + XB1' "; one of the groups a2 and B2 of the second PMOS transistor devices is controlled to be switched in, and the number of the switched-in PMOS transistors in the groups a2 and B2 is controlled as follows: "Y" isA2', 0' or "0, YB2', the number of the PMOS pipe that inserts in the second PMOS pipe device is controlled as Z2, Z2 ═ YA2' +0 ' or 0 ' + YA2′。
Example 3
See fig. 2-9.
The present invention also provides a constant current source driving circuit, including:
the constant current source driving circuit comprises a current mirror consisting of a current input unit and a current output unit.
Wherein,
the current input unit is: in the output interval 1, the total number of the accessed PMOS tubes is controlled to be X1;
the current output unit is: in the output interval 1, the total number of the accessed PMOS tubes is controlled to be Z1;
the current input unit is: in the output interval 2, the total number of the accessed PMOS tubes is controlled to be X2;
the current output unit is: in the output interval 2, the total number of the accessed PMOS tubes is controlled to be Z2;
......；
wherein, X1/Z1 ═ X2/Z2 ═ … … Xn/Zn, X1-Xn are not equal, and the concrete performance can be 10/5 ═ 20/10 ═ 30/15, and the like.
Preferably, the total number of the accessed PMOS transistors is as follows:
mode 1: all PMOS tubes are regarded as single tubes and are independently controlled to be accessed;
mode 2: and partitioning all the PMOS tubes to obtain at least 2 PMOS tube partitions, taking each PMOS tube partition as an integral area to be controlled and accessed integrally, and simultaneously taking the PMOS tubes in each PMOS tube partition as single tubes to be controlled and accessed independently.
Example 4
See figures 2-5.
On the basis of the above embodiment 3, in order to support that the current input unit and the current output unit can achieve the above state, the present invention makes the following structural constraints on the current input unit and the current output unit as follows:
preferably, the current input unit is: the first PMOS tube device is used for outputting a reference current I;
the current output unit is: a second PMOS device and a third PMOS device connected in parallel;
a second PMOS device forming a first current mirror with the first PMOS device;
a third PMOS device forming a second current mirror with the first PMOS device;
and the source-drain total current of the second PMOS device and the third PMOS device is used as the output current IOUT of the constant current source.
Preferably, the first PMOS transistor device, the second PMOS transistor device and the third PMOS transistor device are all formed by PMOS transistors with equal single-transistor width-length ratio, and the number ratio of the PMOS transistors is X: Y1: Y2;
the PMOS tubes form the first PMOS tube device, the second PMOS tube device and the third PMOS tube device in a parallel or series connection mode.
Preferably, the first MOS device is composed of 2 groups of MOS devices connected in parallel, defined as a group a and a group B, each group being composed of the same number of MOS devices connected in parallel; the second MOS tube device and the third MOS tube device are respectively formed by connecting 1 group of MOS tubes with the same quantity in parallel.
Preferably, the number of the PMOS tubes connected to the second PMOS tube device and the third PMOS tube device is adjustable, and the adjusting mode comprises processor control, register configuration or a control circuit;
a switch element is arranged between the second PMOS tube device or the third PMOS tube device and the first PMOS tube device; the switch element is closed, and the second PMOS tube device and the third PMOS tube device are switched on to work; the switch element is disconnected, and the second PMOS tube device or the third PMOS tube device is switched on to work.
Preferably, the switching element is composed of a transmission gate TG4 and a fourth PMOS transistor;
the transmission gate TG4 is connected in series between the first PMOS device and the second PMOS device or between the first PMOS device and the third PMOS device;
correspondingly, the source and drain of the fourth PMOS tube are connected between the gate and source of the second PMOS tube device or between the gate and source of the third PMOS tube device;
the input signal of the transmission gate TG4 is IB _ N, the output signal is IB _ P, and IB _ P is input to the gate of the fourth PMOS transistor and satisfies IB _ P being 0 when IB _ N is 1 and IB _ P being 1 when IB _ N is 0.
Since the current output unit is divided into 2 PMOS transistor partitions, the purpose of the switching element is to: after the current output unit is divided into 2 PMOS transistor partitions, the second PMOS transistor device is regarded as a first PMOS transistor partition, the third PMOS transistor device is regarded as a second PMOS transistor partition, and the switching element can determine that 1 of the second PMOS transistor device or the third PMOS transistor device is connected as an entire region. Thus, there are 2 states for the current output unit, state 1: through the control of the switching element, the second PMOS device and the third PMOS device are in dual-zone access, state 2: through the control of the switching element, only the second PMOS tube device or the third PMOS tube device is switched in at the single zone, so that the change of the total switching-in number of the PMOS tubes of the current output unit is realized, namely the change from Z1 to Z2, wherein Z1 (double zone switched in) > Z2 (single zone switched in). The switching element is thus a structure specific to the invention, which is used for access control to different partitions.
Preferably, the number of the PMOS transistors connected to the first PMOS transistor device, the second PMOS transistor device, and the third PMOS transistor device is adjustable, and the adjusting mode includes processor control, register configuration, or a control circuit.
Preferably, the control circuit includes:
the main control branch circuit is formed by connecting a first inverter and a second inverter in series, a main control signal PGATE _ SEL < n:0> is input into the first inverter, the first inverter outputs a reverse main control signal ps _ n < n:0>, and the second inverter outputs a forward main control signal ps _ p < n:0 >;
the group A control circuit consists of a transmission GATE TG1 and a first switching device tube, a regulating signal PMOS _ GATE outputs a modulation instruction pgate < n:0> through a transmission GATE TG1, the modulation instruction pgate < n:0> is output to the grid electrode of each POMS tube of the group A through the first switching device, the forward main control signal ps _ p < n:0> is used as a trigger signal of the first switching device, and the reverse main control signal ps _ n < n:0> and the forward main control signal ps _ p < n:0> are respectively used as control signals of the transmission GATE TG 1;
the transmission GATE TG2 and the transmission GATE TG3 are connected in series, an adjusting signal PMOS _ GATE is input by the transmission GATE TG2, an adjusting instruction pgate2< n:0> is output through the transmission GATE TG3, the adjusting instruction pgate2< n:0> is output to the grid electrode of each POMS tube of the group B through the third switching device, the forward main control signal ps _ p serves as a trigger signal of the third switching device, an input signal of the transmission GATE TG2 is IB _ n, an output signal is IB _ p, the IB _ p serves as a control signal of the second switching device, when the transmission GATE TG2 is turned off, the second switching device is closed, the adjusting instruction pgate2< n:0> is turned over, and each POMS tube of the group B is not conducted;
wherein, the number of the PMOS tubes in the group A or the group B is n + 1.
Optionally, in some embodiments, the first switching device, the second switching device, and the third switching device are PMOS transistors.
The first PMOS tube devices are divided into A group and B group, and the purpose of arranging the transmission gate TG1 and the first switch device tube, arranging the transmission gate TG2, the transmission gate TG3, the second switch device and the third switch device is to realize access control on the A group and the B group. The purpose of setting the switch element is the same as that of dividing the current input unit into 2 PMOS tube subareas, wherein, A group is regarded as the first PMOS tube subarea, B group is regarded as the second PMOS tube subarea,
the "transmission gate TG1 and the first switching device tube" may decide that group a is accessed as an integral region.
"the transmission gate TG2, the transmission gate TG3, the second switching device and the third switching device" can determine that the group B is accessed as an integral area; the "transmission gate TG1 and the first switching device transistor" and the "transmission gate TG2, transmission gate TG3, the second switching device and the third switching device" cooperate with each other, so that the current input unit has 2 states, a state 1 (corresponding to an output interval 1): group a and group B are in dual zone access, state 2 (corresponding to output interval 2): only the group A is accessed in a single area, so that the change of the total access number of the PMOS tubes of the current output unit is realized, namely the change from Z1 to Z2, wherein Z1 (double-area accessed) > Z2 (single-area accessed). Therefore, "the transmission gate TG1 and the first switching device transistor" and "the transmission gate TG2, the transmission gate TG3, the second switching device, and the third switching device" are structures unique to the present invention, and are used for access control to different partitions.
Meanwhile, based on the above structure, IB _ n, IB _ P, IB _ N, IB _ P are mutually matched, so that when the group a and the group B are simultaneously accessed, the second PMOS transistor device and the third PMOS transistor device are simultaneously accessed, so that when only the group a is accessed, the second PMOS transistor device or the third PMOS transistor device is accessed; so that the POMS tube of the current mirror can follow the adjustment. Wherein IB _ N and IB _ N may be the same signal or independent signals, and IB _ P may be the same signal or independent signals. Preferably, IB _ n, IB _ P and IB _ N, IB _ P are the same set of signals, i.e. synchronous control of X and Z is achieved, in which case IB _ n is IB _ N, IB _ P is IB _ P. Alternatively, the control may be performed independently by using different signals.
Preferably, the device also comprises a reference voltage module and an amplifier, wherein the reference voltage module is connected with the amplifier;
the output end of the amplifier is connected to the grid electrodes of the first PMOS tube device, the second PMOS tube device and the third PMOS tube device;
the drain electrode of the first PMOS device is connected with an external resistor R1, the potential of the first PMOS device is clamped to VREF by the amplifier, so that the reference current I output by the first PMOS device is VREF/R1;
the drain electrodes of the second PMOS device and the third PMOS device are connected in common to be used as output current ends, so that the source-drain total current of the second PMOS device and the third PMOS device is used as the output current IOUT of the constant current source;
the sources of the first PMOS transistor device, the second PMOS transistor device and the third PMOS transistor device are connected with a power supply AVDD.
Still further, as shown in fig. 2, 3, 4 and 5,
fig. 2 is a constant current source driving generation circuit in a constant current source driving chip of an LED display panel according to this embodiment.
R1 in fig. 3 is an external resistor of the driver chip. The single-transistor width-length ratios of the PMOS1, the PMOS2 and the PMOS3 are equal, and the total source-drain currents of the PMOS2 and the PMOS3 are IOUT.
The first PMOS device, the second PMOS device, and the third PMOS device in fig. 2 correspond to PMOS1, PMOS2, and PMOS3 in fig. 3, respectively;
in fig. 2, a parallel control signal is provided, and the parallel control signal is used for controlling a path where the second PMOS transistor device or the third PMOS transistor device is connected to the output end of the reference voltage output unit, or may be understood as a path where the gate of the first PMOS transistor device and the gate of the second PMOS transistor device or the third PMOS transistor device are controlled, where a switch element is disposed on the path, and then the parallel control signal determines the effectiveness of the switch element, so as to determine that 1 of the second PMOS transistor device and the third PMOS transistor device is controlled to be connected.
In fig. 2, there is a first control signal, the first control signal includes a class 2 signal, the class 1 signal controls one of the group a and the group B of the first PMOS transistor device to be accessed, and the class 2 signal controls the access of a single PMOS transistor in the group a and the group B.
Correspondingly, the parallel control signals in FIG. 2 correspond to IB-P, IB-N in FIG. 3, the type 1 signals in FIG. 2 correspond to IB-P, IB-N in FIG. 3, and the type 2 signals correspond to PGATE _ SEL <5:0> (PGATE _ SEL < N:0>) in FIG. 3;
the reference voltage input unit in fig. 2 corresponds to the amplifier AMP1 in fig. 3, and its gain is infinite;
the constant current source is generated according to the following principle:
generating a required reference potential VREF from a reference voltage module Bandgap;
the drain potential of PMOS1 is clamped to VREF by amplifier AMP1, so the source-drain current flowing through PMOS1 is: i ═ VREF/R1;
the number of MOS tubes of the current input unit PMOS1 of the current mirror is not fixed, namely the number Z1 of parallel connection is not fixed, is controlled and is controlled by a logic signal PGATE _ SEL <5:0 >;
the total access quantity of MOS (metal oxide semiconductor) tubes of the current output units PMOS2 and PMOS3 of the current mirror is not fixed, namely the parallel access number Z2 is not fixed and is controlled. However, the number of connected PMOS2 is fixed, which is Y1, and the number of connected PMOS3 is fixed, which is Y2, and is generally set to Y1 ═ Y2 ═ Y;
the operation of the PMOS3 is controlled by a transmission gate TG4 and a PMOS4, which are controlled by two logics of IB _ N and IB _ P; let IB _ N, IB _ P be 1 at high level and 0 at low level.
When IB _ P is 0 and IB _ N is 1, TG4 is turned off in fig. 3, PMOS4 is turned on, PMOS3 is not operated, and the number of parallel transistors Z2 at the output end is Y; when IB _ P is 1 and IB _ N is 0, TG4 is turned on in fig. 2, PMOS4 is turned off, PMOS3 operates normally, and the number of parallel transistors Z2 is 2Y, Y1+ Y2 at the output end;
PMOS2, PMOS3 and PMOS1 form a current mirror.
The specific structure of PMOS1 in FIG. 3 is shown in FIG. 4, the total number of connected PMOS tubes in PMOS1 is set as X, but PMOS1 includes group A and group B, and the specific number of connected PMOS tubes is PGATE _ SEL<5:0>Control (enable instruction) in which both of the group a and the group B are accessed when the section 1 is output, and the number of accesses to the group a can be set to XA', the access number of the B group is XB', when X1 is equal to XA′+XB', generally set up XA′＝XB' -X, then X1 ═ 2X; in the output interval 2, one of the group a and the group B is accessed, and taking the group a access and the group B not access as examples, the number of accesses of the group a may be set as XA', the access number of the B group is 0, and X2 is XA' +0, with X being generally setA′＝XBAnd' -X, then X2-X.
The specific control principle is as follows:
in fig. 3, the source terminals of PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11 and PM12 are all connected to AVDD power, the drain terminals are all connected to PMOS _ D pins, and the gate terminals thereof are connected to pgate <5:0> or pgate2<5:0> signals. The PM1, PM2, PM3, PM4, PM5 and PM6 are distributed according to the number of parallel pipes of 2, 4, 8, 16, 32 and 64; PM7, PM8, PM9, PM10, PM11 and PM12 are distributed according to the number of parallel pipes of 2, 4, 8, 16, 32 and 64.
Six groups of PMOSs, namely PM1, PM2, PM3, PM4, PM5 and PM6, form a cluster of current mirrors, and the grid end voltages of the six groups of PMOSs are connected with five voltage signals of pgate <5:0 >. pgate <5:0> represents the six PMOS _ GATE voltage signals pgate <0>, pgate <1>, pgate <2>, pgate <3>, pgate <4>, pgate <5> whose inputs are controlled by transmission GATEs TG1<6:0 >.
Six groups of PMOSs, namely PM7, PM8, PM9, PM10, PM11 and PM12, form a cluster of current mirrors, and the grid end voltages of the six groups of PMOSs are connected with five voltage signals pgate2<5:0 >. pgate2<5:0> represents the six PMOS _ GATE voltage signals pgate2<0>, pgate2<1>, pgate2<2>, pgate2<3>, pgate2<4>, pgate2<5 >.
The PMOS _ GATE signals are controlled by PGATE _ SEL <5:0>, where PGATE _ SEL <5:0> represents the six signals PGATE _ SEL <0>, PGATE _ SEL <1>, PGATE _ SEL <2>, PGATE _ SEL <3>, PGATE _ SEL <4>, and PGATE _ SEL <5 >. The six signals are controlled by controlling TG1<5:0> and PM13<5:0> to control PM1, PM2, PM3, PM4, PM5 and PM 6; and the GATE terminals of the two clusters of current mirror MOS, namely PM7, PM8, PM9, PM10, PM11 and PM12 are controlled to be connected with the voltage of PMOS _ GATE or not by controlling TG3<5:0> and PM15<5:0 >. Wherein PGATE _ SEL <0> controls the gate terminal voltages of PM1 and PM7, PGATE _ SEL <1> controls the gate terminal voltages of PM2 and PM8, PGATE _ SEL <2> controls the gate terminal voltages of PM3 and PM9, PGATE _ SEL <3> controls the gate terminal voltages of PM4 and PM10, PGATE _ SEL <4> controls the gate terminal voltages of PM5 and PM11, and PGATE _ SEL <5> controls the gate terminal voltages of PM6 and PM 12. However, the gate voltages of the current mirrors in the cluster PM7-PM12 are also controlled by transmission gates TG2<5:0> and PM14<5:0>, and TG2<5:0> and PM14<5:0> are controlled by the opposite pair of signals IB _ P and IB _ N.
When IB _ P is 1, IB _ N is 0;
the transmission GATE TG2 is turned on, the PM14 is turned off, and pgate2<5:0> is all equal to the potential of PMOS _ GATE, so that the PMOS with the GATE terminal pgate2<5:0> and the PMOS with the GATE terminal pgate <5:0> jointly participate in the adjustment of the parallel number ratio of the current mirrors.
At this time, as can be seen from the circuit relationship in fig. 3, when PM1 is turned on, PM7 is necessarily turned on; when PM2 is on, PM8 is necessarily on; when PM3 is on, PM9 is necessarily on; when PM4 is on, PM10 is necessarily on; when PM5 is on, PM11 is necessarily on; when PM6 is on, PM12 is necessarily on. Therefore, when the second cluster of current mirrors is in operation, the total number of parallel connected tubes of the PMOS1 is equal to the number of parallel connected tubes of the first cluster plus the number of parallel connected tubes of the second cluster.
In the circuit, the number of parallel transistors PM1 is PM7, PM2 is PM8, PM3 is PM9, PM4 is PM10, PM5 is PM11, and PM6 is PM12, so that the total number of parallel mos transistors of PMOS 1: x2 [ | P <0> -1| 21+ | P <1> -1| 22+ | P <2> -1| 23+ | P <3> -1| 24+ | [ P <4> -1| 25+ | P <5> -1| 26+ ], + | P < n > -1| 2n +1 ];
in this state, the total number X of parallel tubes of the current mirror is selected from 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, and the adjustment step is 4.
When IB _ P is 0, IB _ N is 1;
transmission gate TG2 is OFF, PM14 is ON, pgate2<5:0> is all high, so all the PMOSes with their gate terminals connected to pgate2<5:0> are not ON. The transmission gate TG1 is controlled by the signal in PGATE _ SEL <5:0> only to control the parallel number of current mirrors: assuming that the high-low level of PGATE _ SEL < n > is represented by P < n >, if PGATE _ SEL < n > is high, P < n > is 1; if PGATE _ SEL < n > is low, P < n > is 0. Therefore, the number of the parallel tubes of the current mirror branch controlled by PGATE _ SEL < n > is | P < n > -1 |. times.2n + 1.
The total number X of PMOS1 parallel mos tubes in FIG. 3 is represented as: x ═ P <0> -1|, 21+ | P <1> -1|, 22+ | P <2> -1|, 23+ | P <3> -1|, 24+ | P <4> -1|, 25+ | P <5> -1|, 26+ ], + | P < n > -1|, 2n + 1|
Therefore, the total number X of parallel tubes of the current mirror cluster controlled by TG1<5:0> is selected from 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62 and 64, and the adjustment step size is 2.
From the above analysis it follows that:
when IB _ P is 1 and IB _ N is 0, the number of pipes operated by PMOS1 is: x2 [ | P <0> -1| 21+ | P <1> -1| 22+ | P <2> -1| 23+ | P <3> -1| 24+ | [ P <4> -1| 25+ | P <5> -1| 26+. + | P < n > -1| 2n +1], and m3 is on at this time, so that the current mirror output PMOS2 and PMOS3 operate, and thus Z ═ 2Y;
Figure BDA0003053906690000151
when IB _ P is 0 and IB _ N is 1, the number of pipes operated by PMOS1 is: x ═ P <0> -1 |. 21+ | P <1> -1 |. 22+ | P <2> -1 |. 23+ | P <3> -1 |. 24+ | P <4> -1 |. 25+ | P <5> -1 |. 26+. + | P < n > -1 |. 2n +1, and POSM3 is off, so that only PMOS2 works at the current mirror output, so that Z ═ Y;
Figure BDA0003053906690000152
it can be derived that:
Figure BDA0003053906690000161
the output current IOUT does not change in both cases. Since the source and drain voltages of PMOS1, PMOS2, PMOS3 are all constant,
when the number of the parallel tubes of the PMOS is increased, the current passing through a single MOS tube is reduced, and the VGS voltage of the MOS tube is reduced;
when the number of parallel tubes of the PMOS is reduced, the current passing by a single MOS tube is increased, and the VGS voltage of the MOS tube is increased.
It can be seen that the structure and the control method can reduce the number of the parallel-connected tubes of the PMOS when the output current IOUT is not changed, so that the VGS voltage is increased, the purpose of controlling the voltage of the grid end of the MOS tubes by controlling the parallel-connected number of the MOS tubes is achieved, and the MOS works in a reasonable state. Therefore, the design ensures that the MOS transistor | VGS | is proper in size, ensures the output consistency and improves the accuracy of the current mirror.
Example 5
As shown in figure 6 of the drawings,
embodiment 2 is obtained by adding control signals to PMOS2 (second PMOS device) and PMOS3 (third PMOS device) on the basis of embodiment 1, respectively: the second control signal and the third control signal are used for controlling the access of a single PMOS tube.
In this way, the total number of the connected MOS transistors of the current output units PMOS2 and PMOS3 of the current mirror is not fixed and is controlled, and the number of the connected MOS transistors of PMOS2 and PMOS3 is not fixed and is controlled by the second control signal and the third control signal.
Example 6
As shown in fig. 7, 8 and 9;
with reference to figures 7 and 9 of the drawings,
the current input unit is a first PMOS tube device,
the current output unit is a second PMOS transistor device,
the first PMOS transistor device and the second PMOS transistor device are connected to the amplifier AMP1 in the manner shown in example 1.
A second PMOS device forming a current mirror with the first PMOS device;
and the source-drain total current of the second PMOS device is used as the output current IOUT of the constant current source.
The first PMOS device and the second PMOS device are respectively composed of PM1, PM2, PM3, PM4, PM5 and PM6, the source terminals of PM1, PM2, PM3, PM4, PM5 and PM6 are all connected with AVDD power supplies, the drain terminals of the PM1, PM2, PM3, PM4, PM5 and PM6 are all connected with PMOS _ D pins, and the gate terminals of the PM1, PM2 and PM _ D pins are connected with pgate <5:0> or pgate2<5:0> signals. The PM1, PM2, PM3, PM4, PM5 and PM6 are distributed according to the number of parallel pipes of 2, 4, 8, 16, 32 and 64.
Output interval 1: the total number of the accessed PMOS tubes in the first PMOS tube device is controlled to be X1, and the number of the accessed PMOS tubes in the second PMOS tube device is controlled to be Z1;
output interval 2: the total number of the accessed PMOS tubes in the first PMOS tube device is controlled to be X2, and the number of the accessed PMOS tubes in the second PMOS tube device is controlled to be Z2.
As can be seen, the first PMOS device and the second PMOS device are each made up of 1 group of PMOS devices connected in parallel and divided into two groups, the two groups of the first PMOS device are defined as group a1 and group B1, and the two groups of the second PMOS device are defined as group a2 and group B2;
wherein, the first PMOS device has PM1, PM2, and PM3 defined as group a1, the first PMOS device has PM4, PM5, and PM6 defined as group B1, the second PMOS device has PM1, PM2, and PM3 defined as group a2, and the second PMOS device has PM4, PM5, and PM6 defined as group B2;
when the group a1 and the group B1 of the first PMOS transistor devices are controlled to be switched in, and the PM1 and the PM4 are selected to be switched in, the number of the switched-in PMOS transistors in the group a1 and the group B1 is controlled as follows: xA1′＝2、XB1' 16, the total number of PMOS transistors connected to the first PMOS transistor device is controlled to X1, and X1 is controlled to XA1′+XB1' -18; the A2 group and the B2 group of the second PMOS tube devices are controlled to be switched in, and PM1 is switched in and PM4 is switched in, the number of the switched-in PMOS tubes in the A2 group and the B2 group is controlled as follows: y isA2′＝2、YB2' 16, the number of connected PMOS tubes in the second PMOS device is controlled to be Z1-YA2′+YB2′＝18；
When one of the a1 group and the B1 group of the first PMOS transistor devices is controlled to be switched in and the PM1 is selected to be switched in, the number of the switched-in PMOS transistors in the a1 group and the B1 group is controlled as follows: "XA1'2, 0', the total number of connected PMOS tubes in the first PMOS tube device is controlled to be X2-2; one of the groups A2 and B2 of the second PMOS tube devices is controlled to be switched in, and PM1 is selected to be switched in, the number of the PMOS tubes switched in the groups A2 and B2 is controlled as follows: "Y" isA2'2, 0', and the number of connected PMOS tubes in the second PMOS device is controlled to be Z2-2.
Wherein, X1/Z1 ═ 18/18 ═ X2/Z2 ═ 2/2.
The output current IOUT does not change in both cases. Since the source and drain voltages of PMOS1 and PMOS2 are constant,
when the number of parallel tubes of the PMOS is reduced, the current passing by a single MOS tube is increased, and the VGS voltage of the MOS tube is increased.
It can be seen that the structure and the control method can reduce the number of the parallel-connected tubes of the PMOS when the output current IOUT is not changed, so that the VGS voltage is increased, the purpose of controlling the voltage of the grid end of the MOS tubes by controlling the parallel-connected number of the MOS tubes is achieved, and the MOS works in a reasonable state. Therefore, the design ensures that the MOS transistor | VGS | is proper in size, ensures the output consistency and improves the accuracy of the current mirror.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (13)

1. A control method of a constant current source driving circuit, the constant current source driving circuit includes a current mirror composed of a current input unit and a current output unit, characterized in that,
the output current of the current output unit is divided into at least 2 output intervals;
the control method comprises the following steps: the access number of MOS tubes in the current input unit and the current output unit is controlled according to the output interval, and the requirements are met:
output interval 1: the total number of the MOS tubes connected into the current input unit is controlled to be X1, and the total number of the MOS tubes connected into the current output unit is controlled to be Z1;
output interval 2: the total number of the MOS tubes connected into the current input unit is controlled to be X2, and the total number of the MOS tubes connected into the current output unit is controlled to be Z2;
……
output interval n: the total number of the MOS tubes connected into the current input unit is controlled to be Xn, and the total number of the MOS tubes connected into the current output unit is controlled to be Zn;
wherein, X1/Z1 is X2/Z2 is … … Xn/Zn, and X1-Xn are not equal.
2. The control method of a constant current source drive circuit according to claim 1,
the total number access control mode of the MOS tubes comprises the following steps:
mode 1: all MOS tubes are regarded as single tubes and are independently controlled to be accessed;
mode 2: all the MOS tubes are divided into partitions to obtain at least 2 MOS tube partitions, each MOS tube partition is used as an integral area to be controlled to be accessed integrally, and meanwhile, the MOS tubes in each MOS tube partition are used as single tubes to be controlled to be accessed independently.
3. The control method of a constant current source drive circuit according to claim 1 or 2,
the current input unit is: a first MOS transistor device;
the current output unit is: at least 2 MOS device devices connected in parallel, comprising:
a second MOS device forming a first current mirror with the first MOS device;
a third MOS device forming a second current mirror with the first MOS device;
the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source;
output interval 1: the total number of the accessed MOS tubes in the first MOS tube device is controlled to be X1, and the second MOS tube device and the third MOS tube device are controlled to be accessed to form double-current-mirror access, at the moment, the number of the accessed MOS tubes in the second MOS tube device is controlled to be Y1, the number of the accessed MOS tubes in the third MOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output interval 2: the total number of the connected MOS tubes in the first MOS tube device is controlled to be X2, one of the second MOS tube device and the third MOS tube device is controlled to be connected to form single-current-mirror connection, the number of the connected MOS tubes in the second MOS tube device is controlled to be Y1 or 0, the number of the connected MOS tubes in the third MOS tube device is controlled to be 0 or Y2, and Z2 is Y1+0 or 0+ Y2.
4. The control method of a constant current source drive circuit according to any one of claims 1 to 3,
the first MOS tube device consists of 2 groups of MOS tube devices connected in parallel, and is defined as an A group and a B group, and each group consists of the same number of MOS tubes connected in parallel;
the second MOS tube device and the third MOS tube device are respectively formed by connecting 1 group of MOS tubes with the same quantity in parallel;
output interval 1: the group A and the group B are controlled to be accessed, and the number of the accessed MOS tubes in the group A and the group B is controlled as follows: xA′、XB' the total number of the connected MOS transistors in the first MOS transistor device is controlled to be X1, and X1 is XA′+XB'; the second MOS tube device and the third MOS tube device are controlled to be connected to form dual-current mirror connection, at the moment, the number of the connected MOS tubes in the second MOS tube device is controlled to be Y1, the number of the connected MOS tubes in the third MOS tube device is controlled to be Y2, and Z1 is Y1+ Y2;
output interval 2: one of the group A and the group B is controlled to be accessed, and the number of the accessed MOS tubes in the group A and the group B is controlled as follows: "XA', 0' or "0, XB' the total number of the MOS tubes connected in the first MOS tube device is controlled to be X2 ═ XA'+ 0' or "0 + XB' "; one of the second MOS device and the third MOS device is controlled to be connected, the number of the connected MOS transistors in the second MOS device is controlled to be Y1 or 0, the number of the connected MOS transistors in the third MOS device is controlled to be 0 or Y2, and Z2 is "Y1 '+ 0" or "0 + Y2'".
5. A constant current source driving circuit is characterized by comprising a current input unit and a current output unit;
the current input unit is: the first MOS tube device is used for outputting a reference current I;
the current output unit is: at least two sets of MOS device devices in parallel, comprising:
a second MOS device forming a first current mirror with the first MOS device;
a third MOS device forming a second current mirror with the first MOS device;
and the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source.
6. The constant current source drive circuit according to claim 5,
the first MOS tube device, the second MOS tube device and the third MOS tube device are all composed of MOS tubes with the same single tube width-length ratio, and the number ratio of the MOS tubes is X: Y1: Y2;
the MOS tubes form the first MOS tube device, the second MOS tube device and the third MOS tube device in a parallel or serial connection mode.
7. The constant current source driving circuit according to claim 5 or 6, wherein the first MOS device comprises 2 groups of MOS devices connected in parallel, defined as group A and group B, each group comprising the same number of MOS devices connected in parallel;
the second MOS tube device and the third MOS tube device are respectively formed by connecting 1 group of MOS tubes with the same quantity in parallel.
8. The constant current source driving circuit according to any one of claims 5 to 7,
a switch element is arranged between the second MOS tube device or the third MOS tube device and the first MOS tube device; the switching element is closed, and the second MOS tube device and the third MOS tube device are connected to work; the switch element is disconnected, and the second MOS tube device or the third MOS tube device is switched on to work.
9. The constant current source drive circuit according to claim 8, wherein the switching element is composed of a transmission gate TG4 and a fourth MOS transistor;
the transmission gate TG4 is connected in series between the first MOS tube device and the second MOS tube device or between the first MOS tube device and the third MOS tube device;
correspondingly, the source and drain of the fourth MOS transistor are connected between the gate and source of the second MOS transistor device, or between the gate and source of the third MOS transistor device;
the input signal of the transmission gate TG4 is IB _ N, the output signal is IB _ P, and IB _ P is input to the gate of the fourth MOS transistor and satisfies IB _ P being 0 when IB _ N is 1 and IB _ P being 1 when IB _ N is 0.
10. The constant current source driving circuit according to claim 9, wherein the number of the MOS transistors connected to the first MOS device, the second MOS device, and the third MOS device is adjustable, and the adjustment manner includes processor control, register configuration, or control circuit.
11. The constant current source drive circuit according to claim 10, wherein the control circuit comprises:
the main control branch circuit is formed by connecting a first inverter and a second inverter in series, a main control signal PGATE _ SEL < n:0> is input into the first inverter, the first inverter outputs a reverse main control signal ps _ n < n:0>, and the second inverter outputs a forward main control signal ps _ p < n:0 >;
the A group control circuit consists of a transmission GATE TG1 and a first switching device tube, wherein an adjusting signal MOS _ GATE outputs a modulation instruction pgate < n:0> through a transmission GATE TG1, the modulation instruction pgate < n:0> is output to the grid electrode of each POMS tube of the A group through the first switching device, a forward main control signal ps _ p < n:0> is used as a trigger signal of the first switching device, and a reverse main control signal ps _ n < n:0> and a forward main control signal ps _ p < n:0> are respectively used as control signals of the transmission GATE TG 1;
the transmission GATE TG2 and the transmission GATE TG3 are connected in series, an adjusting signal MOS _ GATE is input by the transmission GATE TG2, an adjusting instruction pgate2< n:0> is output through the transmission GATE TG3, the adjusting instruction pgate2< n:0> is output to the grid electrode of each POMS tube of the group B through the third switching device, the forward main control signal ps _ p serves as a trigger signal of the third switching device, an input signal of the transmission GATE TG2 is IB _ n, an output signal is IB _ p, the IB _ p serves as a control signal of the second switching device, when the transmission GATE TG2 is turned off, the second switching device is closed, the adjusting instruction pgate2< n:0> is turned over, and each POMS tube of the group B is not conducted;
wherein, the number of MOS tubes in the group A or the group B is n + 1.
12. The constant current source driving circuit according to claim 11, wherein the first switching device, the second switching device, and the third switching device are MOS transistors.
13. The constant current source driving circuit according to any one of claims 5 to 12,
the circuit also comprises a reference voltage module and an amplifier, wherein the reference voltage module is connected with the amplifier;
the output end of the amplifier is connected to the grids of the first MOS tube device, the second MOS tube device and the third MOS tube device;
the drain electrode of the first MOS device is connected with an external resistor R1, the potential of the first MOS device is clamped to VREF by the amplifier, so that the reference current I output by the first MOS device is VREF/R1;
the drain electrodes of the second MOS tube device and the third MOS tube device are connected in common to be used as output current ends, so that the source-drain total current of the second MOS tube device and the third MOS tube device is used as the output current IOUT of the constant current source;
the sources of the first MOS tube device, the second MOS tube device and the third MOS tube device are connected with a power supply AVDD.
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CN109842389A (en) * 2017-11-28 2019-06-04 锐迪科微电子（上海）有限公司 A kind of radio-frequency power amplifier and its power control circuit
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CN112290799A (en) * 2020-12-30 2021-01-29 深圳市南方硅谷半导体有限公司 Linear voltage converter and power supply system

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CN1407726A (en) * 2001-08-31 2003-04-02 松下电器产业株式会社 Driving circuit
CN109842389A (en) * 2017-11-28 2019-06-04 锐迪科微电子（上海）有限公司 A kind of radio-frequency power amplifier and its power control circuit
US20190384337A1 (en) * 2018-06-18 2019-12-19 Analog Devices Global Unlimited Company Lossless current balancing and sharing between paralleled linear voltage regulators
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