CN113176494A - Preparation method of three-dimensional memory failure sample - Google Patents
Preparation method of three-dimensional memory failure sample Download PDFInfo
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- CN113176494A CN113176494A CN202110443764.8A CN202110443764A CN113176494A CN 113176494 A CN113176494 A CN 113176494A CN 202110443764 A CN202110443764 A CN 202110443764A CN 113176494 A CN113176494 A CN 113176494A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2898—Sample preparation, e.g. removing encapsulation, etching
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Abstract
The invention discloses a preparation method of a three-dimensional memory failure sample, belonging to the field of failure analysis of integrated circuits, and the preparation method of the three-dimensional memory failure sample comprises the following steps: step one, removing a metal layer on the surface of a chip; placing the chip with the metal layer removed on a sample table of mechanical grinding equipment; adjusting the position of the sample stage to enable the target analysis area of the chip to be positioned right below the micro-polishing grinding head; adjusting the position of a micro-polishing grinding head to enable the micro-polishing grinding head to contact the surface of the chip, wherein the contact angle between the micro-polishing grinding head and the surface of the chip is 45 degrees; and step five, setting the moving distance of the micro-polishing grinding head, and then starting the micro-polishing grinding head to rotate. According to the invention, the arc-shaped side wall structure is realized by combining high-precision mechanical grinding and ion beam focusing, the number of three-dimensional stacking layers can be accurately counted under a vertical visual angle, and compared with a vertical side wall structure, a failure position can be found more quickly and accurately, so that the analysis efficiency and accuracy are improved.
Description
Technical Field
The invention relates to the field of failure analysis of integrated circuits, in particular to a preparation method of a three-dimensional memory failure sample.
Background
The three-dimensional memory greatly improves the storage density of a chip unit area by a method of vertically manufacturing a circuit in silicon, and the storage capacity is greatly improved. Currently, three-dimensional memory technology has evolved to 128-layer stacks, and has not yet advanced to over 200 layers in the future. The three-dimensional matrix structure can increase the chip capacity, but puts higher demands on the analysis technology. The three-dimensional storage structure is composed of a series of basic storage unit matrixes which are respectively controlled by Bit Line (B/L) and Word Line (W/L), the B/L and the W/L are distributed on 2 vertical sections, the size of one basic storage unit is less than 100nm, and one storage unit in the vertical direction forms a Channel Hole.
In the current commonly used three-dimensional memory analysis positioning process, corresponding B/L and W/L are found on a chip design Layout paper according to an electrical test result, the distance between the chip design Layout paper and the chip edge is measured, a 100X 100um area is selected as an analysis target area by taking a measurement point coordinate (X, Y) as a center, the surface of the chip is preprocessed by using laser or FIB (focused ion beam), the analysis target area is marked, then a Top Metal layer of the area is removed, the number of W/L layers is searched according to Channel Hole, and finally 1-2W/L layers above the target W/L are positioned, and finally slice analysis or plane sampling is carried out by using the FIB. And the target W/L is located from the target area surface down, in a vertical configuration, as shown in fig. 4.
The main problems of the existing method are that when the W/L layer above the target W/L layer is removed, the number of layers to be removed needs to be continuously confirmed to help confirm the target position, and the vertical slotted structure and the layer stacking information are all on the vertical side wall and cannot be observed from the right top, and the lateral observation is needed, because the thickness of each layer is only about 100nm, the lateral visual angle is easy to generate the situation of counting error, so that the failure positioning deviation is caused, and the lateral measurement has higher difficulty and longer time consumption.
Disclosure of Invention
1. Technical problem to be solved
Aiming at the problems in the prior art, the invention aims to provide a preparation method of a failure sample of a three-dimensional memory, which has the advantages of high analysis efficiency and high accuracy, and solves the problems that when a W/L layer above a target W/L layer is removed, the number of layers to be removed needs to be continuously confirmed to help confirm the target position, and due to a vertical slotted structure, layer stacking information is on a vertical side wall, cannot be observed from the right top, and needs to be observed laterally, because the thickness of each layer is only about 100nm, the lateral visual angle is easy to generate the situation of counting error, so that failure positioning deviation is caused, and lateral measurement is difficult and consumes long time.
2. Technical scheme
In order to solve the above problems, the present invention adopts the following technical solutions.
A preparation method of a three-dimensional memory failure sample comprises the following steps:
step one, removing a metal layer on the surface of a chip;
placing the chip with the metal layer removed on a sample table of mechanical grinding equipment;
adjusting the position of the sample stage to enable the target analysis area of the chip to be positioned right below the micro-polishing grinding head;
adjusting the position of a micro-polishing grinding head to enable the micro-polishing grinding head to contact the surface of the chip, wherein the contact angle between the micro-polishing grinding head and the surface of the chip is 45 degrees;
step five, setting the moving distance of the micro-polishing grinding head, then starting the micro-polishing grinding head to rotate, grinding the target analysis area of the chip, and simultaneously monitoring the displacement of the micro-polishing grinding head;
step six, stopping polishing when the micro-polishing grinding head reaches two layers of Word Line (W/L) above the target layer;
seventhly, moving out the micro-polishing grinding head, and confirming the actual removal depth and the layer number;
step eight, transferring the sample into a focused ion beam device, and carrying out ion beam bombardment on the polished area;
step nine, stopping the ion beam when the target position is reached;
and step ten, vertically or horizontally slicing the sample, and analyzing.
Preferably, the mechanical grinding device in the second step is composed of a control system, a Z-axis motor, a rotary motor, a micro-polishing grinding head and a sample table, wherein the control system controls the positions of the sample table and the micro-polishing grinding head and controls the rotating speeds of the Z-axis motor and the rotary motor.
Preferably, a force feedback module is installed on the rotary motor, and the grinding pressure data is transmitted to a control system for monitoring.
Preferably, the micro-polishing grinding head in the third step has a size of 0.4 mm.
Preferably, in the fifth step, the rotation speed of the micro-polishing grinding head is 2000rpm, and the displacement control precision of the micro-polishing grinding head is 40 nm.
Preferably, the two layers of Word Line (W/L) in the sixth step are 400 nm.
3. Advantageous effects
Compared with the prior art, the invention has the advantages that:
(1) this scheme, slope is polished and is controlled for the fluting of polishing perpendicularly more easily, and the in-process of polishing more conveniently removes the head of polishing and calculates the number of piles and the degree of depth of polishing, has improved the efficiency that the chip was polished, the convenient preparation to the sample.
(2) According to the scheme, the arc-shaped side wall structure is realized by combining high-precision mechanical grinding and focused ion beams, the number of layers can be accurately counted by stacking three dimensions under a vertical visual angle, and the failure position can be found more quickly and accurately by comparing the vertical side wall structure, so that the analysis efficiency and the accuracy are improved.
Drawings
FIG. 1 is a schematic view of a mechanical polishing apparatus according to the present invention;
FIG. 2 is a schematic diagram of a chip after being polished by a mechanical polishing apparatus;
FIG. 3 is a schematic view of a wafer after polishing by a focused ion beam apparatus;
FIG. 4 is a schematic illustration of slotting for analytical positioning of a prior art three-dimensional memory.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "top/bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "sleeved/connected," "connected," and the like are to be construed broadly, e.g., "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1-4, a method for preparing a three-dimensional memory failure sample includes the following steps:
step one, removing a metal layer on the surface of a chip;
placing the chip with the metal layer removed on a sample table of mechanical grinding equipment;
adjusting the position of the sample stage to enable the target analysis area of the chip to be positioned right below the micro-polishing grinding head;
adjusting the position of a micro-polishing grinding head to enable the micro-polishing grinding head to contact the surface of the chip, wherein the contact angle between the micro-polishing grinding head and the surface of the chip is 45 degrees;
step five, setting the moving distance of the micro-polishing grinding head, then starting the micro-polishing grinding head to rotate, grinding the target analysis area of the chip, and simultaneously monitoring the displacement of the micro-polishing grinding head;
step six, stopping polishing when the micro-polishing grinding head reaches two layers of Word Line (W/L) above the target layer;
seventhly, moving out the micro-polishing grinding head, and confirming the actual removal depth and the layer number;
step eight, transferring the sample into a focused ion beam device, and carrying out ion beam bombardment on the polished area;
step nine, stopping the ion beam when the target position is reached;
and step ten, vertically or horizontally slicing the sample, and analyzing. .
Furthermore, the mechanical grinding equipment in the second step is composed of a control system, a Z-axis motor, a rotary motor, a micro-polishing grinding head and a sample table, wherein the control system controls the positions of the sample table and the micro-polishing grinding head and controls the rotating speeds of the Z-axis motor and the rotary motor.
Furthermore, a force feedback module is installed on the rotating motor, and polishing pressure data are transmitted to a control system to be monitored.
Further, the size of the micro-polishing grinding head in the third step is 0.4 mm.
Furthermore, in the fifth step, the rotation speed of the micro-polishing grinding head is 2000rpm, and the displacement control precision of the micro-polishing grinding head is 40 nm.
Further, the two layers of Word Line (W/L) in the sixth step are 400 nm.
The working principle is as follows: firstly removing a metal layer on the surface of a chip, then placing the chip with the metal layer removed on a sample table of a mechanical grinding device, adjusting the position of the sample table to enable a target analysis area of the chip to be positioned under a micro-polishing grinding head with the size of 0.4mm, adjusting the position of the micro-polishing grinding head to enable the micro-polishing grinding head to be in contact with the surface of the chip, enabling a contact angle between the grinding head and the surface of the chip to be 45 degrees, then setting the moving distance of the grinding head, controlling the displacement of the grinding head to be 40nm, starting the grinding head to rotate at a rotating speed of 2000rpm, grinding the target analysis area of the chip, simultaneously monitoring the displacement of the grinding head, stopping grinding when the grinding head reaches 400nm (two layers of WL + SiO2) above a target layer, then removing the grinding head, confirming the actual removal depth and the number of layers, transferring a sample into a focused ion beam device, carrying out ion beam bombardment on the grinding area, monitoring the number of layers while reaching the target position, and stopping ion beam when reaching the target position, and vertically or horizontally slicing the sample, analyzing, and transversely presenting all vertical structures in the horizontal direction by utilizing the arc-shaped side wall, so that rapid and accurate layer number confirmation and positioning can be realized.
The foregoing is only a preferred embodiment of the present invention; the scope of the invention is not limited thereto. Any person skilled in the art should be able to cover the technical scope of the present invention by equivalent or modified solutions and modifications within the technical scope of the present invention.
Claims (6)
1. A preparation method of a three-dimensional memory failure sample is characterized by comprising the following steps: the method comprises the following steps:
step one, removing a metal layer on the surface of a chip;
placing the chip with the metal layer removed on a sample table of mechanical grinding equipment;
adjusting the position of the sample stage to enable the target analysis area of the chip to be positioned right below the micro-polishing grinding head;
adjusting the position of a micro-polishing grinding head to enable the micro-polishing grinding head to contact the surface of the chip, wherein the contact angle between the micro-polishing grinding head and the surface of the chip is 45 degrees;
step five, setting the moving distance of the micro-polishing grinding head, then starting the micro-polishing grinding head to rotate, grinding the target analysis area of the chip, and simultaneously monitoring the displacement of the micro-polishing grinding head;
step six, stopping polishing when the micro-polishing grinding head reaches two layers of Word Line (W/L) above the target layer;
seventhly, moving out the micro-polishing grinding head, and confirming the actual removal depth and the layer number;
step eight, transferring the sample into a focused ion beam device, and carrying out ion beam bombardment on the polished area;
step nine, stopping the ion beam when the target position is reached;
and step ten, vertically or horizontally slicing the sample, and analyzing.
2. The method for preparing the three-dimensional memory failure sample according to claim 1, wherein the method comprises the following steps: and the mechanical grinding equipment in the second step consists of a control system, a Z-axis motor, a rotary motor, a micro-polishing grinding head and a sample table, wherein the control system controls the positions of the sample table and the micro-polishing grinding head and controls the rotating speeds of the Z-axis motor and the rotary motor.
3. The method for preparing a three-dimensional memory failure sample according to claim 2, wherein: and a force feedback module is arranged on the rotating motor and used for transmitting the polishing pressure data to a control system for monitoring.
4. The method for preparing the three-dimensional memory failure sample according to claim 1, wherein the method comprises the following steps: and the micro-polishing grinding head in the third step is 0.4mm in size.
5. The method for preparing the three-dimensional memory failure sample according to claim 1, wherein the method comprises the following steps: in the fifth step, the rotation speed of the micro-polishing grinding head is 2000rpm, and the displacement control precision of the micro-polishing grinding head is 40 nm.
6. The method for preparing the three-dimensional memory failure sample according to claim 1, wherein the method comprises the following steps: and in the sixth step, the two layers of Word Line (W/L) are 400 nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117476490A (en) * | 2023-10-31 | 2024-01-30 | 胜科纳米(苏州)股份有限公司 | Three-dimensional section sample of packaged chip and preparation method thereof |
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