JP4799465B2 - Semiconductor wafer, semiconductor device manufacturing apparatus, semiconductor device manufacturing method, and semiconductor wafer manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor wafer having an ID mark for identifying an individual wafer attached to the outer periphery of the wafer, and a method for manufacturing the semiconductor wafer. Furthermore, the present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus using the semiconductor wafer.

Usually, in a series of manufacturing processes of a semiconductor device, several hundred processes are required to manage manufacturing conditions. In such a manufacturing process, it is necessary to set various and strict manufacturing conditions for each process. Management of these manufacturing processes is performed by marking made of numerals, letters, bar codes, or the like, which is attached to a part of the surface of the semiconductor wafer.
The marking usually consists of a number or symbol indicating the manufacturing history in order to identify the wafer. As marking, a soft mark stamped on the front surface and a hard mark stamped on the back surface are generally known. Each of them consists of a plurality of concave dot marks formed by irradiating a laser beam to locally ablate silicon. That is, the marking is formed by irradiating a semiconductor wafer with a continuous pulse laser beam via an optical system.
The marking is limited to an extremely narrow area so as not to obstruct the element forming area as much as possible. However, in order to ensure the visibility of the operator, markings of several mm × several cm size are currently engraved, and the loss on the substrate surface is large.
In general, the dot mark is formed by irradiating a laser beam of high energy to melt and remove a part of the surface of the semiconductor wafer in a spot shape. In this case, the melted and removed silicon (particles) is scattered around the dot mark and redeposited on the wafer surface. This particle hinders element formation and has a great influence on the quality of the product.
Furthermore, soft marks formed on the wafer surface are flattened by repeated deposition processes and chemical mechanical polishing (CMP) processes, resulting in a poor recognition rate. The hard mark formed on the back surface of the wafer forms a slight unevenness on the back surface of the wafer to induce defocusing in lithography, and increases the work of turning the wafer over to detect the hard mark.
As a new marking method that replaces the above technique, Patent Documents 1 to 5 and the like propose a method of imprinting a very small mark on a bevel portion formed on the outer peripheral portion of a wafer. For example, a technique is disclosed in which a very fine mark pattern formed using liquid crystal is irradiated with a laser and a mark is imaged on a bevel portion through an optical system. Since the laser has energy just before ablation occurs, there is no generation of particles.
Japanese Patent Laid-Open No. 08-276284 Japanese Patent Laid-Open No. 08-243765 JP 07-164170 A JP 05-309482 A JP 05-42379 A

  The conventional marking method described above has the following problems. Semiconductor wafers have individual markings indicating manufacturing numbers, but in the semiconductor manufacturing process, they are generally managed in batches grouped into 25 or less. The processing conditions of the semiconductor wafer are determined for each grouped batch, whether batch processing or single wafer processing. Since individual batches are managed as if they have followed the same manufacturing history in the semiconductor manufacturing process, process conditions are set to include variations in individual semiconductor wafers.

  Therefore, the process condition becomes a redundant condition such as setting a long process time. In an extreme case, an extra process may be added. Therefore, problems such as degradation of product performance and increase of manufacturing costs arise.

  The marking imprinted on the semiconductor wafer is usually managed by the host computer for each batch. Product types, manufacturing processes, process conditions, measurement data in the manufacturing process, and the like are processed while being exchanged with the host computer. However, since this exchange with the host computer takes a very long time, at present, only the process condition for each batch is called. Therefore, it is difficult to reflect measurement data such as the film thickness of each semiconductor wafer in each manufacturing process in the process conditions of each semiconductor wafer in the next manufacturing process.

  The present invention has been made to solve the problems of the prior art as described above, and its purpose is to reduce the performance variation between wafers and to provide a high throughput semiconductor wafer, its manufacturing method, and its semiconductor wafer. A manufacturing method of a semiconductor device to be manufactured and an apparatus for manufacturing a semiconductor device are provided.

In order to achieve the above object, the first feature of the present invention is that a first main surface on which a semiconductor element is formed is a circle, a bevel formed on the outer periphery of the wafer, a bevel attached to the bevel. And a reference ID mark indicating the crystal orientation of the wafer, and the bevel portion includes a first bevel portion located on the first main surface side of the wafer and a second main surface side facing the first main surface. The reference ID mark is a semiconductor wafer attached to each of the first bevel part and the second bevel part .

According to a second aspect of the present invention, a wafer having a circular first main surface on which a semiconductor element is formed, a reference ID mark indicating a crystal orientation of the wafer, and a part of the outer peripheral portion of the wafer. A recess having a bottom surface that is inclined with respect to the first main surface and a second crystal plane that is formed on the bottom surface of the recess and that is different from the first crystal surface that is exposed on the first main surface are formed. It is a semiconductor wafer having an etch pit. Etch pits remain even after the wafer is polished.

A third feature of the present invention is that an etching process in which an etching rate varies depending on a crystal orientation, wherein a concave portion whose bottom surface is inclined with respect to a first main surface of a wafer on which a semiconductor element is formed is formed in a part of the outer peripheral portion of the wafer Is applied to the wafer to form an etch pit on the bottom surface of the recess, obtain the crystal orientation of the recess from the shape of the etch pit, and attach a reference ID mark indicating the crystal orientation of the wafer on the wafer. That is. In the etch pit, a second crystal plane different from the first crystal plane exposed on the first main surface is exposed.

According to a fourth aspect of the present invention, there is provided a wafer stage, a light source for irradiating light on a main surface of the wafer placed on the wafer stage, and an intensity of light scattered by etch pits formed on the main surface of the wafer. A light receiving element that measures the rotational angle dependence of the scattered light intensity, a mark stamper that attaches a reference ID mark indicating the crystal orientation of the wafer on the wafer, at least a wafer stage, The semiconductor device manufacturing apparatus includes a chamber that covers and hides a wafer, a light source, and a light receiving element and blocks light entering from the outside. The light receiving element has a ring-shaped light receiving surface that surrounds the outer periphery of the light emission port and is inclined with respect to the light irradiation direction.

A fifth feature of the present invention is that a single crystal ingot is sliced to form a wafer, and an alkaline solution is used to remove large waviness of the main surface with respect to the main surface of the wafer. Etching is performed at different etching rates depending on the crystal orientation, and the crystal orientation of the wafer is measured using etch pits formed on the main surface of the wafer by this etching treatment, and a reference ID mark indicating the crystal orientation of the wafer is placed on the wafer. It is a method for manufacturing a semiconductor wafer in which etch pits are removed.

A sixth feature of the present invention is that a bevel portion is formed on the outer peripheral portion of a base wafer having a circular outer periphery, and a reference ID mark for indicating the crystal orientation of the SOI layer wafer is attached to the bevel portion. An SOI layer wafer having a reference position indicating an orientation is formed, an insulating layer is formed on the first main surface of the SOI layer wafer, and the reference ID mark and the reference position are aligned with each other for the base wafer and the SOI layer. This is a method for manufacturing a semiconductor wafer that is bonded to the first main surface of the wafer.

  As described above in detail, the present invention has the following effects.

  (1) A semiconductor wafer that has been marked on the bevel portion of the outer peripheral portion of the wafer to indicate information related to the product formed on the wafer, and the marking is in each manufacturing step of each product, Since the markings are applied as many times as necessary, for example, it is possible to adopt optimum process conditions for each of the manufacturing processes at high speed without requiring access to the host computer. Can be suppressed.

  (2) In a semiconductor wafer in which an ID mark for identifying the wafer is provided on a bevel portion on the outer periphery of the wafer, the ID mark is formed in a smoothed area on the surface of the bevel portion. Even on a semiconductor wafer having no reference position in advance, the mark can be read at high speed.

  (3) In a semiconductor wafer in which a plurality of ID marks for identifying the wafer are provided on the outer periphery of the wafer, each ID mark has the same contents, and the position of the wafer is changed in the lateral direction. Since the position is also changed in the thickness direction, precise measurement of the wafer bevel shape is not required, and it is possible to improve the marking throughput without requiring advanced techniques.

  (4) In a semiconductor wafer in which an ID mark for identifying the wafer is provided on the bevel portion of the outer peripheral portion of the wafer, the ID mark is formed on the left and right sides of the reference position of the bevel portion. The time for reading the wafer ID during the process can be shortened, and the productivity can be increased.

  (5) In an SOI wafer in which an oxide film and a single crystal silicon layer are sequentially arranged on a substrate wafer, an ID mark for identifying the wafer is provided in the region of the substrate wafer. It does not cause problems such as generation, and marking is possible in the same way as a normal wafer. Furthermore, compared with the conventional manufacturing method, it can provide industrially cheaply without adding an additional process and without an increase in cost.

  (6) A step of smoothing the surface by irradiating a part of the bevel surface of the outer periphery of the wafer with a laser beam and a step of forming a dot mark in the smoothed region are performed. Since the dot mark formed on a part of the bevel surface of the outer peripheral portion is illuminated while illuminating the bevel surface, the light quantity is monitored, and the position where the light quantity is maximum is detected as the formation area of the dot mark. Position detection of minute dot marks formed on the bevel portion of the wafer can be performed at high speed. Furthermore, additional writing of dot marks with a high recognition rate can be realized even on a wafer surface with irregularities in the semiconductor device manufacturing process.

  (7) Since the semiconductor manufacturing process is managed by the marking performed using the marking method of the semiconductor device of the present invention, a very large amount of process information has been managed by one identification number (mark) so far. In contrast to the management method that required a very long time to read out the necessary information during the manufacturing process, the process information is marked on the bevel part of each wafer, so the necessary information can be read out in a short time. Become.

  Furthermore, by reading the marking with each semiconductor manufacturing equipment, it is possible to feed forward the process information of each wafer to the next process in a short time, and to build a process according to the fluctuation of each process. It becomes possible to suppress variations in the performance of the apparatus. In particular, even in an immature process such as a manufacturing process in the technology development stage, conditions can be set individually, so that it can be applied to a production line quickly.

(First embodiment)
FIG. 1 is a partial external view of a semiconductor wafer according to the first embodiment of the present invention. The semiconductor wafer according to the first embodiment includes a wafer 11, a bevel portion 12 formed on the outer peripheral portion of the wafer 11, a product 15 formed on the wafer 11, and an ID attached to the bevel portion 12. And marks (14a-d). Here, the ID mark (14a-d) indicates at least the product 15, the manufacturing conditions of the product 15, and the inspection result of the product 15. Here, the product 15, the manufacturing conditions of the product 15, and the inspection result of the product 15 are defined as “information about the product”. The ID mark (14a-d) is marked as many times as necessary during each manufacturing process of each product. The “information about the product” includes the lot number or manufacturing order of the product formed on the wafer, the function of the product, and the inspection result of the manufacturing process.

  The outer peripheral portion of the wafer 11 is meant to include the outer peripheral portion of the front surface of the wafer 11 where the semiconductor integrated circuit is not formed, the side surface of the wafer 11, and the outer peripheral portion of the back surface of the wafer 11. The product 15 is intended to include all products manufactured in a series of semiconductor manufacturing processes for forming a desired semiconductor integrated circuit on the surface of the wafer 11. Specifically, the product 15 includes an n-type or p-type semiconductor region formed on the surface of the wafer 11, films made of an insulator, a semiconductor, and a conductor deposited on the wafer 11, and these films. Are selectively removed to include a pattern processed into a desired shape.

  More specifically, a thermal oxide film formed by thermally oxidizing the wafer 11 in a clean atmosphere at a high temperature, an insulating film such as an oxide film or a nitride film deposited on the wafer 11 by a CVD method, coating / curing, etc. Resist film formed, resist pattern formed by exposure / development of resist film, pattern made of insulator formed by selectively etching insulating film using resist pattern as mask, ion implantation of impurity element, thermal diffusion, etc. The product 15 referred to here includes a semiconductor region and a semiconductor film having a predetermined conductivity type and conductivity formed by the above. That is, the product 15 is a product formed by depositing a film, adding impurities, patterning, and etching to form transistors, capacitors, or metal wirings connecting these elements on the wafer 11. Showing things.

  Further, the information indicated by the ID mark 14 includes information regarding the wafer 11 itself. Specifically, the ID mark 14 includes a manufacturing history and manufacturing conditions of a wafer manufactured through a slicing process and a lapping process from the manufacture of a single crystal ingot, and attributes and characteristics of the wafer 11 itself. The ID mark is used as a reference mark (hereinafter referred to as “reference ID mark”) for indicating the crystal orientation in the main surface of the wafer by being attached to a specific portion on the wafer. The reference ID mark will be described in detail in the sixth to eleventh embodiments.

  The ID mark 14 may be any one of alphanumeric characters, one-dimensional codes, and two-dimensional codes. In the embodiment of the present invention, a case of a two-dimensional code will be described unless otherwise specified. The two-dimensional code is composed of a plurality of dot marks. The dot mark has, for example, a convex shape having a width of about 5 μm and a height of about 0.5 μm. The two-dimensional code is composed of a plurality of dot marks arranged in a matrix such as 8 vertically and 32 horizontally, 16 vertically and 16 horizontally, and has information on the product 15. The size of the two-dimensional code is generally extremely fine, such as about 100 to 200 μm in width and about 50 to 100 μm in length. Therefore, it cannot be read with human eyes. Therefore, in the embodiment, the ID mark 14 is read using a dedicated reader.

  In order to imprint and read the ID mark 14, a reference position in the wafer 11 is necessary. The notch 13 can be used as a reference position. The notch 13 is a reference object formed to indicate the crystal orientation of the wafer 11, and is formed on the outer periphery of the wafer 11. In addition, since the ID mark 14 is engraved on the bevel portion 12 of the wafer 11, the ID mark 14 of the plurality of wafers 11 can be continuously read in a state of being contained in the wafer cassette.

  Next, a method for manufacturing a semiconductor device manufactured using the semiconductor wafer shown in FIG. 1 will be described.

  (A) First, at the beginning of a series of semiconductor manufacturing processes, the identification code (ID mark) 14a of the wafer 11 itself is imprinted on the bevel portion 12 formed on the outer peripheral portion of the wafer 11. The ID mark 14a has information on the product type, the manufacturing location, the manufacturing start date, the manufacturing process to be used, and the person in charge of manufacturing in addition to the information on the product. Is stamped at a position of about 100 μm from the edge of the substrate. The plurality of dot marks constituting the ID mark 14a are formed by irradiating the bevel portion 12 with a continuous pulse laser beam via an optical system and locally melting the surface of the bevel portion 12.

  (B) Then, a series of semiconductor manufacturing processes is started based on the ID mark 14a. For example, the process first starts with an oxidation process and is continued with a chemical vapor deposition (CVD) process that serves as a mask for pattern formation. Here, the film thickness of the mask material formed on the wafer 11 is measured for each wafer 11 in the batch. The measured value of the film thickness is collected by the host computer as the film thickness value of each wafer 11, and at the same time, the ID mark 14b indicating the measured value of the film type and the film thickness is added next to the ID mark 14a.

  In the prior art, the film thickness of a test piece selected from one batch is measured. And the film thickness value of the test piece was collected by the host computer as a typical film thickness of the batch. Since the film thickness value of the test piece is handled as a film thickness value representative of the plurality of grouped wafers 11, the film thickness value of each wafer 11 varies with respect to the film thickness value of the test piece. Therefore, the manufacturing conditions in the next manufacturing process are set empirically in consideration of variations in the film thickness values of the wafers 11.

  (C) Thereafter, the mask material is patterned using a resist, and sent to a dry etching process to be processed. At that time, the ID mark 14a is read by the ID mark reading device provided in the dry etching apparatus. Then, pattern information, film type, film thickness information, and the like are given to the dry etching apparatus, and an optimum etching process condition for each wafer 11 is selected.

  (D) After various cleaning steps, the first main surface of the wafer 11 is selectively etched, and a CVD film in the groove of the formed silicon substrate is buried to form element isolation.

  Next, after forming a well by ion implantation, the process proceeds to a transistor process. A gate electrode is formed after forming the gate insulating film. Also in the process of forming the gate electrode, an ID mark 14c indicating the film thickness information of the electrode film formed by the CVD method is additionally written next to the mark 14b, as in the previous mask process. By feeding back the film thickness information of the electrode film to the dry etching process, the overetching time can be controlled in each wafer 11.

  (E) Further, in the step of forming the source / drain, an ID mark 14d indicating the film thickness information of the oxide film serving as the cover film is additionally written next to the ID mark 14c. The ID mark 14d adjusts the optimum ion implantation conditions for each wafer 11 and reduces variations in transistor characteristics.

  (F) Also, in the single-wafer wet etching process, an ID mark indicating film thickness information is additionally written on the bevel portion 12 as in the dry etching process. The etching time is set in each wafer 11 by the ID mark indicating the film thickness information, and the finished shape can be made constant.

  As described above, a plurality of ID marks (14 a to 14 d) representing information related to a product formed in each manufacturing process are sequentially added to the bevel portion 12 formed on the outer peripheral portion of the wafer 11. For example, individual ID marks (14a to 14d) are continuously imprinted at a certain distance, for example, every 100 μm. The reading device can access the latest information located at the rightmost position with reference to the notch 13 based on the regular arrangement information of the ID marks (14a to 14d).

  An ID mark 14 is directly stamped on each wafer 11. In the subsequent manufacturing process, the ID mark 14 stamped on the wafer 11 is read, and manufacturing conditions are set for each wafer 11. It is possible to select optimum process conditions for each wafer 11 without accessing the host computer, and to suppress manufacturing variations occurring between wafers in a batch. The marking positions of the ID marks (14a to 14d) are set so as to be stamped at 45 degrees, 90 degrees, or 180 degrees with respect to the notches 13 if regularity is provided. It doesn't matter.

  Also, a very large amount of process information is managed by one recognition code (ID mark) 14, and it takes a very long time to read out information necessary during the manufacturing process. On the other hand, since the process information of each manufacturing process is imprinted on the bevel portion 12, necessary information can be read out in a short time.

  Further, the ID mark (14a-d) is read by each semiconductor manufacturing apparatus. Thereby, the process information of each wafer 11 can be fed forward to the next process in a short time, and a process corresponding to the fluctuation of each manufacturing process can be assembled. Therefore, it becomes possible to suppress the performance variation of the semiconductor device manufactured by the semiconductor wafer to which the ID mark (14a-d) is attached. In particular, even in an immature process such as a manufacturing process in the technological development stage, manufacturing conditions can be set individually, so that it can be applied to a production line quickly.

(Modification 1 of the first embodiment)
In the first embodiment, information on products is sequentially added as ID marks (14a to 14d) for each product 15, and ID marks (14a to 14d) having information necessary for individual manufacturing processes. ) Was selectively read. However, through the series of semiconductor manufacturing processes, the information included in the initial ID mark 14a is also included in the ID marks (14b to 14d) attached in the subsequent manufacturing process, thereby recognizing the ready-made product 15. It can also be updated from upstream to downstream as one ID mark. That is, a new ID mark including information related to a product formed after the ID mark is attached and information indicated by the ID mark attached first is attached adjacent to the ID mark attached previously. You can also.

  For example, in FIG. 1, a product recognition code (ID mark) 14 a is first imprinted on the right of the notch 13. Next, after a desired process, a new ID mark 14b including the obtained film thickness information including the initial ID mark 14a is imprinted to the right of the initial product recognition code (ID mark) 14a. The semiconductor manufacturing apparatus recognizes the ID mark 14b at the first right end of the bevel portion 12 as the latest information.

  In the first embodiment, since each piece of information is divided into individual ID marks (14a to 14d), there is an advantage that it can be stamped with a matrix having a small capacity. On the other hand, in the first modification of the first embodiment, since all information is newly imprinted, the capacity of the matrix increases, but all process information from one ID mark (14a-d). It has the advantage that it can be pulled out at once.

(Modification 2 of the first embodiment)
An example in which the first embodiment is applied to a case where a semiconductor wafer in which various products are mixedly flowed to the production line will be described. In an LSI manufacturing process, an element isolation process such as shallow trench isolation (STI) is usually performed first, and then a wiring formation process is performed through a gate formation process, a contact formation process, and a capacitor formation process.

  A method for managing a wafer for each module will be described. As shown in FIG. 1, first, an ID mark 14 a representing an identification number is imprinted on the wafer 11. Then, the process proceeds to an STI mask formation process through an oxidation process and a CVD process. At this time, as described in the first embodiment, an ID mark 14b indicating a process condition such as a mask film thickness is imprinted on the wafer 11. The individual ID marks 14b are read by a reactive ion etching (RIE) apparatus, whereby optimum conditions for the individual semiconductor wafers 11 are set and mask processing is performed.

  Subsequently, an insulating film is embedded in the STI trench through an Si etching process, an oxidation process, and a filling process. Next, before proceeding to the chemical mechanical polishing (CMP) process, the oxide film thickness to be polished is measured, and an ID mark 14 c representing the value is imprinted on the wafer 11. Based on the ID mark 14 c, the CMP polishing time is optimized for each individual wafer 11.

  After that, the element separation by STI is completed through a cleaning process. At this time, an ID mark 14d indicating what kind of mask or process the element separation substrate is formed on the bevel portion 12 of the wafer 11 Engrave it. Then, the wafer 11 on which the element isolation is formed is prepared, and the process proceeds to the next process according to the demand for the product. The wafer 11 is managed by the stamped ID mark 14d.

  Similarly, after the gate formation, an ID mark 14d representing information including a mask until gate formation, process conditions, inspection results, and the like is imprinted when the gate formation is completed, and the wafer is managed by the ID mark 14d. By managing the wafer 11 in this way, it is possible to adopt a production system that can flexibly respond to product demand.

(Modification 3 of the first embodiment)
An example applied to the chip management method when the wafer process is completed and the process proceeds to the assembly process will be described. In the chip inspection process after the wafer process is completed, the semiconductor integrated circuit device on the semiconductor wafer is divided into good chips and defective chips. The process information included in the ID marks (14a to 14d) shown in the first embodiment and the modifications 1 and 2 thereof, the position information of the semiconductor chip on the wafer 11, and a new ID mark including the inspection result are stored in the semiconductor. Attached to each chip.

  After forming the semiconductor chip by cutting the wafer 11, it is generally difficult to collect the wafer process information, the chip position information on the wafer, and the inspection result for each chip for each semiconductor chip. It is. This makes it difficult to analyze defects after becoming a semiconductor chip.

  By applying an ID mark capable of managing these pieces of information collectively to a semiconductor chip and managing the semiconductor chip using this ID mark, it is possible to facilitate the analysis of defects in the semiconductor chip. Further, even when a defect occurs in a semiconductor chip that has been put on the market, since all information is included in the ID mark stamped on the semiconductor chip, failure analysis can be facilitated.

(Second Embodiment)
In the second embodiment, a method for attaching an ID mark to a semiconductor wafer will be described. 2A to 2C are flowcharts showing a marking method for a semiconductor wafer according to the second embodiment of the present invention.

  (A) The dot mark forming method according to the second embodiment is executed at the beginning of the manufacturing process of the semiconductor device. First, as shown in FIG. 2A, the wafer 16 to be used has a surface whose bevel portion has a larger roughness than the element formation region. Specifically, the bevel portion has a size of 0.2 μm and a step of 0. It has unevenness 17 of 2 μm.

  (B) For this wafer 16, as shown in FIG. 2B, for example, the image of the He-Ne laser light 18 having a Gaussian-shaped energy density distribution is shifted from the surface of the bevel portion. Scan a part. As a result, the laser irradiation surface is smoothed in the process in which the unevenness 17 on the surface of the bevel portion irradiated with the laser beam 18 is melted and recrystallized.

  (C) Next, as shown in FIG. 2C, for example, He-Ne laser light 19 having a Gaussian-shaped energy density distribution is irradiated in a state of being imaged on the surface of the bevel portion. As a result, in the process of melting and recrystallizing the surface of the wafer 16, for example, a dot mark 20 made of a minute protrusion having a size of 5 μm and a step of 0.5 μm is imprinted. By imprinting a plurality of dot marks 20, a two-dimensional code (ID mark) can be formed. The two-dimensional code is composed of dot marks of 8 vertical x 32 horizontal or 16 vertical x 16 horizontal.

  While illuminating the bevel portion of the wafer 16, the amount of reflected light is monitored by a CCD camera. The position where the amount of reflected light is maximum is directly detected as the area where the dot mark 20 is formed. In this way, the dot mark 20 is read.

  In the related technology, the dot mark is formed based on the notch of the wafer in order to facilitate reading of the dot mark. For this reason, when reading the dot mark, use a semiconductor laser or the like to find the notch position on the wafer, then move the dot mark formation area to the camera position based on this notch position. It was. In the case where the wafer itself has no reference notch, the dot mark formation area could not be found.

  However, in the second embodiment, since the mark formation area is smoothed before the dot mark 20 is formed, the position detection of the minute dot mark 20 formed on the bevel portion of the wafer 16 is performed at high speed. In addition, additional writing of the dot mark 20 with a high recognition rate can be realized even on a wafer surface on which irregularities are generated during the semiconductor manufacturing process. Even when the wafer 16 itself does not have a notch serving as a reference position, the dot mark 20 can be read at high speed. According to the marking method of the semiconductor wafer according to the second embodiment, the dot mark 20 can be read at high speed even on a semiconductor wafer in which the wafer itself does not have a reference position in advance. Therefore, it is possible to shorten the time for reading the ID mark during the semiconductor manufacturing process.

(Modification of the second embodiment)
In the second embodiment, the dot mark forming method at the beginning of the manufacturing process of the semiconductor device has been described. In the modification of the second embodiment, a method of adding dot marks during the manufacturing process of the semiconductor device will be described.

  2A to 2C, the silicon substrate (wafer) 16 is etched during the manufacturing process of the semiconductor device to form unevenness 17 having a size of 2 μm and a step of 0.2 μm on the surface of the wafer 16. As in the second embodiment, the surface of the wafer 16 on which the irregularities 17 are formed is irradiated and scanned with a laser 18 whose image is shifted from the surface of the wafer 16. Then, a dot mark 20 composed of minute protrusions is formed by a laser 19 imaged on the surface of the wafer 16.

  As described above, by smoothing the mark formation region before the dot mark 20 is formed, it is possible to add the dot mark 20 with high recognizability even during the manufacturing process of the semiconductor device. .

(Third embodiment)
In the first and second embodiments and their modifications, the ID mark 14 does not specify which position on the bevel portion is to be stamped. However, in some cases, the ID mark 14 must be stamped on the outermost peripheral portion of the wafer in the bevel portion. This is because if the ID mark is engraved in a portion near the wafer surface where the product 25 in the bevel portion is formed, it is highly likely to disappear in the CMP process frequently used in the recent semiconductor manufacturing process. . Therefore, in the third embodiment, the marking position of the ID mark 14 and the number of ID marks 14 in the bevel portion will be described.

  FIG. 3 is a partial external view of a semiconductor wafer according to the third embodiment. In the semiconductor wafer according to the third embodiment, three ID marks (24a to 24c) having the same contents are imprinted on the outer peripheral portion 22 of the wafer 21 with reference to the notch 23 formed on the outer peripheral portion of the wafer 21. ing. One ID mark 24 is a rectangle of 30 μm × 140 μm square. The three ID marks (24a to 24c) are imprinted with a shift of 30 μm in the vertical and horizontal directions. Even if the ID mark 24c stamped in the vicinity of the front surface of the wafer 21 disappears in the CMP process, the ID mark 24a stamped on the portion near the wafer back surface of the bevel portion 22 remains and can be read.

  In the third embodiment, a region to be marked on the wafer outer peripheral portion 22 is roughly detected by using, for example, a laser displacement meter or light reflection. That is, the shape of the bevel portion of the wafer outer peripheral portion 22 is not accurately measured after the notch 23 is found. Therefore, as shown in FIG. 4, the first area to be marked on the wafer outer peripheral portion 22 can be detected in only 2 seconds. Using the area to be marked as a reference, a plurality of ID marks (24a to 24c) having the same contents are stamped at three locations with a certain distance in the wafer thickness direction, as well as changing the position in the lateral direction. The total time required for the marking is 20 seconds. However, the time required for marking one wafer is 36 seconds.

  As described above, according to the third embodiment, it is not necessary to precisely measure the shape of the bevel portion of the wafer 21, and the mark marking throughput can be improved correspondingly. Mark marking can be performed in less than half of the time required compared to the comparative example described below.

(Comparative example of the third embodiment)
In order to prevent the ID mark from disappearing in the CMP process, the bevel portion is also required to be stamped on a portion near the wafer side surface as far as possible from the wafer surface. For this purpose, the bevel portion of the wafer is precisely measured, and a laser beam is irradiated aiming at a portion close to the wafer end portion.

  Specifically, first, a wafer is transferred and a notch is detected. And as shown in FIG. 5, the shape of the bevel part 27 is calculated | required by irradiating light to the bevel part 27 of the wafer 26, and capturing reflected light. Next, a region 28 that can be regarded as a plane approximately is searched. In order to search for the region 28 that can be regarded as a flat surface, the measurement of the bevel portion 27 must be precise, and therefore a long time is required. For example, as shown in FIG. 4, the time for imprinting the ID mark itself is 6 seconds, but it takes 60 seconds to measure the shape of the bevel portion 27 (including a search for an area that can be regarded as a plane). . Two seconds and four seconds are required for inspection and wafer transfer, respectively, and the total time required to imprint an ID mark on one wafer is 80 seconds. The measurement of the shape of the bevel portion 27 occupies most of them.

  As described above, according to the third embodiment, it is possible to improve the ID mark marking throughput by measuring the shape of the bevel portion by a simple method without requiring an advanced technique and apparatus. .

(Modification 1 of 3rd Embodiment)
In the first modification of the third embodiment, an example in which the number of ID marks to be engraved is two will be described. By setting the number of ID marks to two, the time required for processing one wafer is reduced from 36 seconds (when the number of ID marks is three) to 30 seconds. The concern at this time is whether or not the ID mark can be read with sufficient accuracy. In order to confirm this, 3 spots were stamped on 12 of 24 wafers, and only 2 spots were stamped on the remaining 12 wafers.

  At this time, each ID mark is engraved at intervals of 30 μm in the vertical and horizontal directions when imprinted at three locations, and at an interval of 50 μm in the vertical and lateral directions when engraved at two locations. Engraved.

  Using these wafers, trench type DRAMs were prepared, and after completion of the bit line formation process, the wafers were extracted and subjected to ID mark reading tests. The result is shown in FIG.

  In the “reading result” column, “◯” is marked when the ID mark can be read, and “X” is marked when the ID mark cannot be read. The column “Reading position” indicates how many ID marks were read when viewed from the outer periphery of the wafer. “1” is the ID mark closest to the outer periphery, and the larger the number, the farther from the outer periphery, the more the wafer surface portion. Close to. Three ID marks are attached to the wafers with wafer numbers 1 to 12, and two ID marks are attached to the wafers with wafer numbers 13 to 24.

  As shown in FIG. 6, in most cases, the ID mark closest to the outer periphery can be read. This result indicates that the ID mark can be sufficiently read without precisely measuring the bevel portion and imprinting it at an accurate position. If the shape of the outer periphery of the wafer is roughly detected and a plurality of ID marks are engraved, any one survives and any ID mark can be read in any process.

(Modification 2 of 3rd Embodiment)
FIG. 7 is a partial cross-sectional view of a semiconductor wafer according to Modification 2 of the third embodiment. As shown in FIG. 7, the bevel portion 32 is positioned on the first bevel portion 32 a positioned on the first main surface 29 side of the wafer 31 and on the second main surface 30 side facing the first main surface 29. And a second bevel portion 32b. ID marks (33a, 33b) indicating the same contents are respectively attached to the first bevel portion 32a and the second bevel portion 32b. That is, in Modification 2, ID marks (33a, 33b) having the same contents are stamped on the outer peripheral portion on the front surface side and the outer peripheral portion on the back surface side of the wafer 31, respectively. Here, the first main surface 29 indicates the surface of the wafer 31 on which the semiconductor integrated circuit is manufactured by forming a product, and the second main surface 30 indicates the back surface of the wafer 31.

  In this way, the bevel portion 32 is divided into several regions in the thickness direction of the wafer 31, and ID marks (33a, 33b) indicating the same contents are engraved in the respective regions. Even if the ID mark 33a stamped on the outer peripheral portion of the front surface 29 of the wafer 31 disappears in the CMP process, the ID mark 33b stamped on the portion near the back surface 30 of the wafer 31 remains and can be read. As a result, the time for imprinting and reading the ID mark is shortened, and the throughput can be improved.

(Fourth embodiment)
FIG. 8 is a partial external view of a semiconductor wafer according to the fourth embodiment. As shown in FIG. 8, the ID marks (37, 38) are attached to both sides of the reference position 36 formed in the bevel portion 35, respectively. The reference position 36 is a reference object or a reference symbol indicating the crystal orientation of the wafer 34. The reference object or reference symbol includes a wafer orientation flat, a notch or a fine marking. Here, an ID mark 37 indicating a manufacturing number stamped by a wafer manufacturer and an ID mark 38 stamped by a device manufacturer are stamped separately on the left and right with a notch (reference position) 36 as a boundary.

  On the other hand, as a comparative example, as shown in FIG. 9, the wafer manufacturer and the device manufacturer may be arranged on the same right side with the ID mark (39, 40) stamped on the end of the notch 36 as a reference.

  Compared to this comparative example, the semiconductor wafer marking method according to the fourth embodiment can reduce the time required for reading the ID marks 37 and 38 for the following reason.

  As shown in FIG. 9, with reference to the end of the notch 36, the wafer maker and the device maker imprint the ID marks (showing a two-dimensional code here) 39, 40 side by side on the same right side. -The size of one two-dimensional code is about 50 μm in length and about 150 μm in width. When two two-dimensional codes are arranged, the two ID marks 39 and 40 become discontinuous because the marking device and the marking device are different. Further, since the field of view of the reading device is about 300 μm, the second ID mark 40 is out of the field of view based on the notch 36. Therefore, in order to read the second ID mark 40, the camera of the reading device has to be moved slightly.

  FIG. 10 shows the result of comparing the time required for reading the first ID mark 39 and the second ID mark 40. The reading of the first ID mark 39 starts from the wafer set and consists of the detection time of the reference position 36 and the reading time. On the other hand, when the second ID mark 40 is read, it takes a very long time to read because the camera movement time (100 msec) is added.

  If the ID mark disappears and a new ID mark is engraved during the semiconductor manufacturing process, the camera must move further and take more time to become the third ID mark. become.

  As shown in FIG. 8, if the wafer manufacturer ID mark 37 and the device manufacturer ID mark 38 are engraved separately on the left and right with respect to the reference position (notch) 36, the movement of the camera is reduced at least once. Is possible. Therefore, it is possible to reduce the time required for reading by that amount.

  According to the fourth embodiment, the time for reading the ID mark during the semiconductor manufacturing process can be shortened, and the productivity can be increased. The work of adjusting the field of view of the ID mark reader can be shortened and the work efficiency can be improved. In addition, the reader may first find the reference position, and may not read the first visible ID mark, but may read the next ID mark. Even in this case, productivity can be improved by reducing the work of adjusting the field of view.

  In addition, here, the way of dividing into right and left is shown for the case where the person who stamps is a wafer maker or a device maker. However, the present invention is not limited to this. For example, a wafer ID mark indicating a manufacturing history of a wafer attached to one side of the reference position, and a manufacturing history of a product attached to the other side of the reference position. The product ID mark may be divided into

(Modification of the fourth embodiment)
The same effect as that of the fourth embodiment can be expected even if the wafer manufacturer ID mark 37 and the device manufacturer ID mark 38 shown in FIG. In particular, when a wafer maker imprints on the bevel portion on the back side of the wafer and a device maker imprints on the front bevel, another new effect can be expected.

  In a recent semiconductor manufacturing process, a CMP process is frequently used. After the CMP process, the ID mark engraved on the front-side bevel portion tends to disappear. If it disappears, it may be engraved again. However, since the ID mark to be engraved has disappeared, it is not possible to know what should be engraved.

  Therefore, the wafer manufacturer's ID mark is imprinted on the backside bevel portion that does not disappear even in the CMP process, and the device manufacturer's ID mark is imprinted on the front surface side bevel portion. In addition, information regarding the wafer and the product included in the wafer manufacturer and device manufacturer ID marks is stored in the host computer. By doing this, even if the device manufacturer's ID mark disappears during the manufacturing process, the wafer manufacturer's ID mark is read, and the corresponding device manufacturer's ID mark is downloaded from the host computer and stamped again. Is possible.

  As a countermeasure against the disappearance of the ID mark, a method of engraving the device manufacturer's serial number on the bevel portions on both the front and back sides of the wafer is also conceivable. However, imprinting two identical ID marks means that it takes twice as long as the imprinting, which is not preferable in consideration of productivity. It is more advantageous in terms of production efficiency to use an ID mark engraved by a wafer manufacturer.

(Fifth embodiment)
FIG. 11 is an overall plan view of a semiconductor wafer according to the fifth embodiment, and FIG. 12 is a perspective sectional view of an essential part thereof. As shown in FIGS. 11 and 12, the semiconductor wafer according to the fifth embodiment includes a base wafer 42 made of single crystal silicon, an insulating layer 45 disposed on the main surface of the base wafer 42, and an insulating layer. A single crystal silicon layer 41 made of single crystal silicon disposed on 45, a product 46 formed on the single crystal silicon layer 41, and a product 46 and a product 46 manufactured on the base wafer 42. This is a silicon on insulator (SOI) wafer having an ID mark 44 indicating at least the conditions and the inspection result of the product 46 and a notch 43 formed on the outer periphery of the base wafer 42. Here, a buried oxide film is used as the insulating layer 45. The single crystal silicon layer is called an SOI layer 41. The buried oxide film 45 and the SOI layer 41 are disposed on the inner portion of the base silicon wafer 42 excluding the outer peripheral portion of the base wafer 42. Therefore, the outer peripheral portion of the main surface of the base wafer 42 is exposed. A relatively wide area of the base wafer 42 is exposed at the portion where the notch 43 is formed. The ID mark 44 is attached on the main surface of the base wafer 42 where the notch 43 is formed. By forming various products 46 on the SOI layer 41 in a series of semiconductor manufacturing processes, a semiconductor integrated circuit can be manufactured on the SOI wafer.

  Next, an ID mark marking method for an SOI wafer according to the fifth embodiment will be described. First, a 200 mmφ SOI wafer is prepared. In the prepared SOI wafer, the base wafer 42, the buried oxide film 45, and the SOI layer 41 have the same planar shape. A resist pattern having the same shape as that of the SOI layer 41 shown in FIG. 11 is formed on the SOI layer 41 by photolithography. Using this resist pattern as a mask, the SOI layer 41 on the outer periphery of the wafer is etched with a KOH aqueous solution to selectively expose the buried oxide film 45 on the outer periphery of the wafer.

  Subsequently, the buried oxide film 45 is removed by etching with an HF aqueous solution to selectively expose the outer peripheral portion of the base wafer 42 including the region to which the ID mark 44 is attached. After removing the resist pattern, a plurality of dot marks having a depth of 5 μm and a diameter of 30 μm are formed around the notch 43 of the base wafer 42 by using a YAG laser to form an ID mark 44.

  When the ID mark 44 is read, the recognition rate is not different from that of the bulk wafer, and by attaching the ID mark 44 on the base silicon wafer 42, no abnormality of the dot portion occurs.

  Here, a part of the SOI layer 41 and the buried oxide film 45 of the SOI wafer are removed by etching. However, by bonding wafers with different areas in the SOI wafer creation stage, the base wafer 42 is exposed at a portion corresponding to the area difference. Therefore, the ID mark 44 may be attached to this portion. As a method of bonding the wafers, for example, there is a method of bonding the notch wafer to the base wafer 42 side and bonding the orientation flat wafer to the SOI layer 41 side. In the SIMOX method, an exposed portion of the base wafer 42 may be formed by placing a shielding plate at a place where marking is performed during oxygen ion implantation, and this portion may be marked.

  As described above, in the fifth embodiment, the ID mark 44 is formed by imprinting a plurality of dot marks with the laser on the surface of the base wafer 42 (region without the SOI layer 41 and the buried oxide film 45) in the SOI wafer. In this way, even an SOI wafer can be marked in the same way as a normal bulk wafer.

(Comparative example of the fifth embodiment)
As a comparative example, a case where a dot mark is formed by irradiating an SOI layer with a laser is shown. As shown in FIG. 13, the SOI wafer has a structure in which a base wafer 47, a buried oxide film 48, and an SOI layer 49 are laminated in order. Although the thickness of the SOI layer 49 varies depending on the device, it is generally 1 μm or less when a high-speed MOS transistor is formed. When the SOI layer 49 is irradiated with laser, the incident laser diffuses at the buried oxide film 48 and forms a relatively large dot 50 under the buried oxide film 48. The large dots 50 may cause peeling of the buried oxide film 48 and generation of dust 51 in a subsequent device process.

  In the fifth embodiment, since the laser beam is irradiated to the base wafer 42, the above problem does not occur. Moreover, it can provide industrially cheaply without adding an additional process compared with the manufacturing method of a comparative example, without an increase in cost.

  As described above, according to the fifth embodiment, marking can be performed in the same manner as in a normal wafer by suppressing the peeling of the buried oxide film 48 and the generation of dust 51 in the device process even in an SOI wafer. it can.

(Modification of the fifth embodiment)
FIG. 14 is an external view of a main part of a semiconductor wafer according to a modification of the fifth embodiment. Here, a 200 mmφ SOI wafer 52 is prepared, and a plurality of dot marks having a depth of 0.5 μm and a diameter of 5 μm are formed on a bevel portion 53a formed on the outer peripheral portion of the base wafer by using a YAG laser. It is attached. When the ID mark 54 was read, the recognition rate was not different from that of the bulk wafer, and no abnormality of the dot mark portion occurred. Note that the SOI wafer manufacturing method may be a SIMOX method or a bonding method.

(Example of notchless wafer)
In the first to fifth embodiments, the marking and reading of the ID mark indicating the information related to the product is performed based on the notch that is the reference position of the semiconductor wafer.

  However, the notch or the orientation flat may deteriorate the process controllability from the viewpoint of the shape of the semiconductor wafer and deteriorate the product performance. For example, in the lithography process, variations in resist pattern dimensions occur due to non-uniformity of the resist coating film thickness. Further, in the spin etching apparatus, the insulating film is left due to non-uniform etching amount. Further, in the oxidation / LP-CVD apparatus, when transferring wafers to the wafer boat, it is necessary to shift from the notch or the orientation flat portion with respect to the fixed claw of the wafer boat. Therefore, reference alignment must be performed in advance. That is, since there is a notch or an orientation flat, it is necessary to add a reference positioning mechanism to the manufacturing apparatus, leading to an increase in the cost of the manufacturing apparatus. In addition, since the notch becomes a singular point, the heat uniformity becomes worse. As a result of device evaluation, defective chips may concentrate near the notch.

  Compared with the wafer surface and the bevel portion, deposits such as a resist agent easily adhere to the notch portion (recessed portion) during the manufacturing process, and it is difficult to remove the deposit. Therefore, there is a high possibility that deposits released from the notch during the subsequent process contaminate the wafer as particles. In addition, since there are orientation flats and notches, it is limited to make devices in those parts, and the total number of chips (Gross) that can be taken per wafer is reduced. Since notches or orientation flats are present on the wafer, the above-described manufacturing defects may occur.

  However, the carrier mobility, the etching rate, the growth rate of the epitaxial growth layer, and the like differ depending on the crystal orientation. Therefore, from the viewpoint of improving process controllability, when the notch or orientation flat is eliminated from the semiconductor wafer, it becomes difficult to control the crystal orientation of the wafer. This causes, for example, a variation in impurity profile in the ion implantation process or a variation in mobility in the transistor, resulting in a malfunction of the product.

  Therefore, in the sixth to eleventh embodiments, the wafer is formed with a reference ID mark for recognizing the crystal orientation of the wafer as the reference position of the wafer, and there is no notch or orientation flat. A semiconductor wafer having a circular shape will be described.

(Sixth embodiment)
FIG. 15 is a plan view showing the entire first main surface of the semiconductor wafer according to the sixth embodiment. There are no notches or orientation flats on the outer periphery of the wafer 60, and the outer periphery of the wafer 60 has a circular shape. A bevel portion is formed on the outer peripheral portion of the wafer 60. A first main surface of the wafer 60 on which a product is formed is disposed inside the bevel portion. The shape of the first main surface of the wafer 60 is also circular. The plane orientation of the first main surface of the wafer 60 is (100). Accordingly, the [011] orientation line exists in the first main surface of the wafer 60. One reference ID mark 61 for recognizing the crystal orientation in the first main surface of the wafer 60 is formed on the bevel portion on the orientation line. The reference ID mark 61 may be any of alphanumeric characters, barcodes, and two-dimensional codes. For example, in the case of a matrix type two-dimensional code, it is composed of dot marks of 8 vertical x 32 horizontal or 16 vertical x 16 horizontal. Here, the description is continued for the case where the reference ID mark 61 is a two-dimensional code.

  FIG. 16 is a partially enlarged plan view of the bevel portion on which the reference ID mark 61 is formed. The reference ID mark 61 is composed of a matrix type two-dimensional code including an L-shaped guide cell 62. With reference to the position of the L-shaped guide cell 62, a crystal orientation line (for example, [011] orientation line) in the first main surface (100) is specified. Here, the L-shaped guide cell 62 is arranged in a range of ± 1.0 degrees with respect to the [011] azimuth line. That is, the L-shaped guide cell 62 is disposed so as to substantially coincide with the crystal orientation line.

  FIG. 17 is an enlarged plan view showing a matrix type two-dimensional code 61 including an L-shaped guide cell 62. The two-dimensional code 61 is a data matrix code composed of 16 × 16 dot marks. The length of one side of the rectangular two-dimensional code 61 is, for example, 100 μm. The L-shaped guide cell 62 is composed of 31 dot marks formed on two sides of the two-dimensional code 61 that are perpendicular to each other. By arranging the L-shaped guide cell 62 on the [011] azimuth line, the [011] azimuth line is specified.

  The dot mark is formed as follows. For example, He—Ne laser light having a Gaussian-shaped energy density distribution is irradiated in a state of being imaged on the wafer surface. As a result, in the process of melting and recrystallization of the wafer surface, for example, minute protrusions (dot marks) having a size of 5 μm and a step of 0.5 μm are formed. The reference ID mark 61 composed of a plurality of dot marks can be detected by a reading device equipped in an exposure device, an ion implantation device, or the like.

   As described above, by forming the ID mark 61 serving as the reference position of the wafer 60, it is possible to use a circular wafer having no notch or orientation flat and to suppress manufacturing variations between the wafers. . Therefore, it is possible to manufacture a semiconductor device with little performance variation between the wafers 60 and high throughput.

  Further, for example, in the oxidation / LP-CVD apparatus, it is possible to omit the reference position alignment at the time of wafer transfer, and the cost of the manufacturing apparatus can be reduced.

(Modification 1 of 6th Embodiment)
FIG. 18 is an external view of a semiconductor wafer according to Modification 1 of the sixth embodiment. As shown in FIG. 18, the wafer 60 is a wafer in which a circular plane orientation (100) without a notch or an orientation flat is exposed. Reference ID marks (63a to 63d) for recognizing the crystal orientation of the wafer 60 are formed at a plurality of locations on the bevel portion formed on the outer periphery of the wafer. Specifically, [011] Two reference ID marks (63b, 63d) are formed on the bevel portion on the azimuth line, and two reference ID marks (63a, 63c) are formed on the bevel portion on the [011] azimuth line. ing.

  By forming a plurality of reference ID marks, even if some reference ID marks are lost by CMP or the like, the remaining reference ID marks can be used. Further, by increasing the number of reference ID marks to be formed, the crystal orientation can be recognized with higher accuracy.

  Although FIG. 18 shows the case where all the reference ID marks (63a, 63c) are formed on the crystal orientation line, the present invention is not limited to this. For example, as shown in FIG. 19, reference ID marks (64a, 64c) may be formed between crystal orientation lines orthogonal to each other. In this case, the reference ID mark (64a, 64c) includes information indicating the positional relationship between the crystal orientation line and the L-shaped guide cell.

(Modification 2 of the sixth embodiment)
FIG. 20 is an external view of a semiconductor wafer according to Modification 2 of the sixth embodiment. A reference ID mark 65 is formed on the wafer 60 at a position shifted from the [011] azimuth line. The reference ID mark 65 includes information regarding the position coordinates with respect to the crystal orientation line. Here, the reference ID mark 65 is formed at a position shifted by 5 ° counterclockwise from the [011] azimuth line.

  FIG. 21 is an enlarged plan view of the outer periphery of the wafer 60 on which the reference ID mark 65 is formed. The reference ID mark 65 is composed of alphanumeric characters “011 + 5829TAC3”. “011” in alphanumeric characters indicates [011] bearing line. “+5” indicates that a “+” mark is formed at a position shifted by 5 ° counterclockwise from the azimuth line.

(Modification 3 of the sixth embodiment)
Similarly to the second modification of the third embodiment, the bevel portion may be divided into several regions in the thickness direction of the wafer, and reference ID marks indicating the same contents may be engraved in the respective portions. Absent.

  As shown in FIG. 7, the bevel portion 32 is located on the first bevel portion 32 a located on the first major surface 29 side of the wafer 31 and on the second major surface 30 side facing the first major surface 29. And a second bevel portion 32b. Reference ID marks (33a, 33b) indicating the same contents are respectively attached to the first bevel portion 32a and the second bevel portion 32b. That is, the reference ID marks 33a and 33b having the same contents are stamped on the outer peripheral portion on the front surface side and the outer peripheral portion on the back surface side of the wafer 31, respectively.

  In this way, the bevel portion 32 is divided into several regions in the thickness direction of the wafer 31, and a reference ID mark indicating the same content is engraved in each division. Even if the reference ID mark 33a stamped on the outer peripheral portion on the front surface 29 side of the wafer 31 disappears temporarily in the CMP process, the reference ID mark 33b stamped on the portion near the back surface 30 of the wafer 31 remains and can be read. As a result, the time for engraving and reading the reference ID mark is shortened, and the throughput can be improved.

(Seventh embodiment)
In the seventh embodiment, a semiconductor wafer is manufactured by measuring a crystal orientation line perpendicular to the crystal orientation plane expressed on the first main surface of the wafer and providing a reference ID mark at a desired position on the wafer. An apparatus and a method for manufacturing a semiconductor wafer will be described. The semiconductor wafer manufacturing apparatus according to the seventh embodiment assigns a reference ID mark to a desired position on the wafer based on the orientation measurement system for measuring the crystal orientation of the wafer and the measurement result of the crystal orientation of the wafer. Marking system.

  FIG. 22 is a block diagram showing a configuration of a semiconductor wafer manufacturing apparatus according to the seventh embodiment. The semiconductor wafer manufacturing apparatus detects an X-ray tube 80 that irradiates a second main surface opposite to the first main surface of the wafer 71 with an X-ray 72, and a two-dimensional X-ray that detects X-rays 74 scattered by the wafer 71. A line detector 75, a monitor 76 that displays a two-dimensional image (Laue image) formed by X-rays 74 scattered by the wafer 71, and a laser beam 78 is applied to the outer periphery of the wafer 71 to mark a reference ID mark. It has a laser light source 77 and a mirror 79 for forming, a measuring system for measuring a deviation angle between the irradiation position of the laser light 78 and the crystal orientation line, and a rotating system for rotating the wafer or the laser marker. The X-ray tube 80, the X-ray detector 75, and the monitor 76 correspond to an azimuth measuring system. A laser marker including the laser light source 77 and the mirror 79, a measurement system, and a rotation system correspond to a marking system. Here, the X-ray detector 75 is disposed on the first main surface side of the wafer 71, and detects the X-rays 74 that are transmitted through the wafer 71 and scattered by the wafer 71.

  An X-ray direct beam stopper 73 is disposed in a part of the X-ray detector 75. The X-ray direct beam stopper 73 prevents the X-rays 72 that are transmitted without being scattered by the wafer 71 from entering the fluorescent screen and the CCD camera 75. The wafer 71 is a circular semiconductor wafer having no notch or orientation flat for recognizing the reference position and crystal orientation. The X-ray detector 75 includes a fluorescent screen and a CCD camera arranged in parallel with the wafer 71. The fluorescent plate emits fluorescence when irradiated with X-rays. The CCD camera detects this fluorescence and converts it into an electrical signal.

  FIG. 23 is a flowchart showing a semiconductor wafer manufacturing method using the semiconductor wafer manufacturing apparatus shown in FIG. 24 to 26 show the rotation angle of the wafer 71 and the Laue image displayed on the monitor 76 in the main manufacturing process.

  (A) In step S01, a wafer 71 having a diameter of 300 mm and having a (100) crystal orientation surface exposed on the main surface of the wafer is transferred into the manufacturing apparatus. At this time, it is not necessary to align the notch or the orientation flat of the wafer 71 with respect to the wafer stage.

  (B) In step S02, the position of the wafer 71 on the wafer stage is adjusted so that the center of the wafer 71 coincides with the rotation center of the wafer stage provided with the rotation mechanism. In step S03, the second main surface of the wafer 71 is irradiated with continuous X-rays 72 from an X-ray tube 80 equipped with a molybdenum (Mo) target under conditions of a voltage of 40 kV and a current of 30 mA. X-rays 72 are scattered by the wafer 71 and guided to the fluorescent screen.

  (C) In step S04, a Laue image obtained by capturing the fluorescence of the fluorescent screen by the X-ray 74 with a CCD camera is acquired and displayed on the monitor 76. The crystal orientation line of the wafer 71 can be detected from this Laue image. 24A and 24B show the relationship between the rotation angle of the wafer 71 and the Laue image at this time.

  (D) In step S05, based on this Laue image, a deviation angle (θ) between the laser irradiation spot of the laser marker (77, 79) and the [011] azimuth line of the wafer 71 is calculated. In step S06, the wafer 71 is rotated so that the [011] orientation line of the wafer 71 and the laser irradiation spot of the laser marker (77, 79) overlap.

  (E) The wafer 71 is again irradiated with X-rays (S07), and a Laue image is acquired (S08), thereby evaluating the overlap of the laser irradiation spots on the [011] azimuth line and the laser markers (77, 79) ( S09). The relationship between the position of the wafer 71 after rotation and the Laue image is shown in FIGS. 25 (a) and 25 (b). Instead of rotating the wafer 71, the laser markers (77, 79) may be rotated. In step S10, if the deviation angle is 1 ° or more, the process returns to step S06 (wafer rotation). If the deviation angle is less than 1 °, the process proceeds to S11.

  (F) In step S11, the position where the reference ID mark is formed is detected. In step S12, as shown in FIG. 26, a reference ID mark 81 composed of a plurality of dot marks is imprinted using a laser marker (77, 79) at a position 2 mm from the edge of the wafer 71 on the [011] azimuth line. . The dot mark includes a recess formed by melting a part of the wafer 71. A reference ID mark 81 representing a mathematical expression is formed by the arrangement of a plurality of dot marks.

  (G) Thereafter, the wafer 71 is carried out of the manufacturing apparatus. The time required from the transfer of the wafer 71 into the apparatus (S01) to the unloading after the processing (S13) was 9 seconds per wafer.

  As described above, based on the Laue image obtained by irradiating the wafer with X-rays, the crystal orientation line is measured and the reference ID mark is given to the end of the wafer. Therefore, it becomes possible to put a circular wafer having no notch or orientation flat into the semiconductor manufacturing process. When various processes are performed on the wafer, the etching rate, film growth rate, and CMP polishing are better when the wafer according to the seventh embodiment is used than when the wafer is provided with a notch or orientation flat. Uniformity in the wafer surface such as speed is improved. Further, in a process in which the crystal orientation of the wafer needs to be adjusted, for example, a lithography process, the orientation can be aligned with reference to the reference ID mark.

(Modification 1 of 7th Embodiment)
In the first modification of the seventh embodiment, a case will be described in which the crystal orientation line of the wafer 71 is measured based on the Laue image formed by the X-rays 74 reflected by the wafer 71.

  FIG. 27 is a block diagram illustrating a configuration of a semiconductor wafer manufacturing apparatus according to Modification 1 of the seventh embodiment. In the manufacturing apparatus shown in FIG. 27, the X-ray detector 82 is arranged in parallel to the wafer 71 on the same side as the X-ray incident side (second main surface side) with respect to the wafer 71, and is reflected by the wafer 71. Line 74 is detected. The X-ray tube 80 includes a tungsten (W) target. The X-ray detector 82 includes an X-ray imaging tube but does not include a direct beam stopper. Other configurations are almost the same as those of the manufacturing apparatus shown in FIG. Also in the apparatus configuration shown in FIG. 27, the same operational effects as those of the seventh embodiment described above can be obtained.

(Modification 2 of 7th Embodiment)
In the second modification of the seventh embodiment, a case will be described in which the irradiation spot position of the laser light is finely adjusted by tilting the mirror 79 that reflects the laser light in the biaxial direction.

  Each drawing of FIG. 28 shows a marking system provided in the semiconductor wafer manufacturing apparatus according to the seventh embodiment. In the second modification of the seventh embodiment, the mirror 79 can be tilted parallel to the [011] azimuth line. Therefore, it is possible to irradiate the laser beam 78 from the end of the wafer 71 to a desired position. Therefore, the reference ID mark can be formed at a desired position on the [011] azimuth line. FIG. 28B shows a case where the laser beam 78 is reflected vertically by the mirror 79.

  29 are perspective views when the mirror 79 and the wafer 71 are viewed from the laser light source 77 side. The mirror 79 can also be tilted perpendicular to the [011] bearing line. Therefore, the laser beam 78 can be irradiated to a desired position from the [011] azimuth line of the wafer 71. Therefore, the reference ID mark can be formed at a desired position on the outer peripheral portion of the wafer 71. FIG. 29B shows a case where the laser beam 78 is incident on the wafer 71 perpendicularly.

  In the flowchart shown in FIG. 23, the azimuth misalignment angle is calculated (S05), the wafer is rotated (S06), and then the mirror 79 that reflects the laser beam 78 is tilted in the biaxial direction to finely adjust the irradiation spot position. Can be adjusted. Therefore, it is not necessary to repeat the steps from the wafer rotation (S06) to the azimuth misalignment determination (S10) to adjust the wafer rotation angle to the laser irradiation position with high accuracy. Once the Laue image is obtained (S08) and the azimuth deviation angle is calculated (S09), the deviation of the azimuth deviation angle can be corrected by adjusting the mirror angle thereafter.

(Modification 3 of the seventh embodiment)
In the third modification of the seventh embodiment, a case where the position on the wafer 71 where the laser beam 78 is irradiated is the end surface of the wafer 71 will be described.

  FIG. 30 shows a marking system included in the semiconductor wafer manufacturing apparatus according to Modification 3 of the seventh embodiment. Laser light 78 emitted from the laser light source 77 is emitted in a direction perpendicular to the main surface of the wafer 71. The laser beam 78 is reflected almost vertically by the mirror 79 and is irradiated onto the side surface of the wafer 71.

  31 and 32 show examples of reference ID marks formed on the side surface of the wafer 71 by the marking system shown in FIG. FIG. 31 shows a case where the reference ID mark is a two-dimensional dot matrix, and FIG. 32 shows a case where the reference ID mark has a concave shape that has no particular meaning.

  In the seventh embodiment described above and the first to third modifications thereof, the target of the X-ray tube is not limited to Mo and W, and may be copper (Cu). The X-ray detector is not limited to the fluorescent plate and the X-ray imaging tube, and for example, an X-ray CCD camera, a position sensitive proportional counter (PSPC), a channel plate, or the like may be used. The method of forming the reference ID mark on the wafer is not limited to a specific laser marker, and other methods may be used. The reference ID mark is not limited to a two-dimensional dot matrix, a concave shape not having a specific meaning, and may be an alphanumeric character or a barcode, and functions as a code for recognizing the crystal orientation line of the wafer 71. I just need it.

(Eighth embodiment)
In the eighth embodiment, a method for manufacturing a semiconductor wafer that determines the crystal orientation of a semiconductor wafer by detecting light scattering by etch pits formed by subjecting the semiconductor wafer to anisotropic etching. State.

  As shown in FIG. 35, the semiconductor wafer according to the eighth embodiment includes a wafer 91 having a circular first main surface 95 on which semiconductor elements are formed, and a bevel portion 92 formed on the outer periphery of the wafer 91. And a recess 94 that is formed in a part of the bevel portion 92 and has a bottom surface that is inclined with respect to the first main surface 95, and an etch pit that is formed on the bottom surface of the recess 94 and remains after the polishing of the wafer 91, A reference ID mark that is attached to the bevel portion 92 and indicates a crystal orientation line of the wafer 91 is provided. The etch pit is surrounded by a second crystal plane different from the first crystal plane exposed on the first main surface 95 of the wafer 91. Here, the first crystal plane indicates the (100) plane, and the second crystal plane includes the (111) plane. Of course, the crystal plane is not limited to these, and other crystal planes may be used.

  A method for manufacturing a semiconductor wafer according to the eighth embodiment will be described below with reference to FIG.

  (A) First, in step S21, a silicon single crystal ingot (boron-doped p-type (100) crystal, resistivity 5-10 Ωcm) is pulled up. Then, block processing (S23) is performed, and the silicon single crystal ingot is sliced and cut into a wafer (S24). Note that the crystal orientation of the silicon single crystal ingot is not measured, and the orientation flat or notch is not formed. The (100) plane is exposed on the main surface of the cut wafer.

  (B) Thereafter, in step S25, chamfering (beveling) of the edge of the cut surface is performed. Then, in step S26, as shown in FIG. 35, a concave portion (hereinafter referred to as “azimuth determination region”) 94 is formed in a part of the bevel portion 92.

  Specifically, as shown in FIG. 34, a bar-shaped jig 93 is pressed against a part of the bevel portion 92 while rotating, and a part of the circumference of the wafer 91 is scraped off. After scraping, an orientation determination region 94 is formed in a part of the bevel portion 92 as shown in FIG. As shown in FIG. 36A, the bottom surface of the orientation determination region 94 is inclined with respect to the first main surface 95 of the wafer on which the semiconductor element is formed. The angle α of the bottom surface of the orientation determination area 94 is set in a range of 20 to 60 °. As shown in FIG. 36 (b), an orientation determination region 94 made of a concave groove is formed on the first main surface 95 of the wafer 91. In addition, the size of the orientation determination area 94 is, for example, A × B = 0.3 mm × 0.2 mm. The orientation determination region 94 is not limited to being formed on the surface of the bevel portion, and may be formed on the back surface or side surface of the wafer 91.

  (C) Next, after wrapping the wafer 91 (S27), in step S28, one of the main purposes is to achieve high flatness by removing large waviness of the first main surface 95 of the wafer 91. An anisotropic etching process is performed using an alkaline solution. Here, the anisotropic etching process is an etching process in which the etching rate varies depending on the crystal orientation of the wafer 91. As the alkaline solution, KOH or NaOH can be used. When NaOH is used, for example, a 20% NaOH solution is etched at a temperature of 85 to 90 ° C. for 8 minutes.

  As shown in FIG. 37A, the first main surface of the wafer 91 whose (100) surface is exposed by the anisotropic etching process is surrounded by the second crystal plane including the (111) surface. An etch pit appears. The angle formed by the line intersecting the second crystal plane and the (100) plane is 125.26 °. Further, as shown in FIG. 37 (b), the etch pits formed on the (100) plane have a point-symmetric shape, and the second crystal planes 96a to 96d have substantially the same shape. .

  On the other hand, as shown in FIG. 38, the etch pits 97 are formed not only on the first main surface 95 of the wafer 91 but also on the bevel portion 92 and the bottom surface of the orientation forming region 94. Since the bottom surface of the orientation forming region 94 is inclined with respect to the (100) plane, the shape of the etch pit 97 surrounded by the second crystal plane is not point-symmetric.

  (D) Next, mirror processing is applied to the bevel portion 92 of the wafer (S30). Then, mirror processing is performed on the first and second main surfaces of the wafer using a double-sided mirror machine (S31). The etch pits 97 formed on the bottom surface of the orientation determination region 94 remain after the bevel portion 92 is polished. That is, in the bevel mirror processing (S30) and the mirror processing (S31), the etch pits formed on the first and second main surfaces and the surface of the bevel portion 92 are lost. However, the bottom surface of the orientation forming region 94 is not polished, and the etch pit 97 remains.

  (E) Next, using the semiconductor wafer manufacturing apparatus shown in FIG. 39, orientation information is given to the wafer 91 (S32). The manufacturing apparatus shown in FIG. 39 includes a wafer stage on which the wafer 91 is placed, a first rotation driving unit 103 that rotates the wafer stage around the center of the wafer 91, and a light source 98 that irradiates the orientation determination region 94 with light 99. A detector 101 that detects the light (reflected light) 100 scattered by the etch pits 97, a second rotation drive unit 104 that rotates the wafer stage around the azimuth determination area 94 irradiated with the light 99, and A computer (PC) 102 for evaluating the rotation angle dependency of the scattered light 100 detected by the detector 101 and a database in which the rotation angle dependency of the scattered light intensity by the etch pit 97 acquired over the entire circumference of the wafer 91 is registered. 106 and a laser marker 105 for engraving a reference ID mark on the outer peripheral portion of the back surface of the wafer 91. .

The light source 98, the detector 101, the second rotation drive unit 104, the computer (PC) 102, and the database 106 correspond to an orientation measurement system, and the laser marker 105 corresponds to a marking system. Here, the case where the light 99 irradiated to the azimuth | direction determination area | region 94 is white light is demonstrated. Further, a case where the irradiation range of the white light 99 is reduced to 1 mm ₂ or less will be described.

  The wafer 91 is chucked on the wafer stage. The first rotation drive unit 103 is rotated. The rotation of the first rotation drive unit 103 is stopped at a position where the white light 99 from the light source 98 is irradiated on the orientation determination region 94 formed in a part of the bevel portion. At this time, the white light 99 is also applied to the etch pits 97 formed in the orientation determination region 94. Then, the intensity of the light scattered by the etch pits 97 is detected using the detector 101 while rotating the second rotary movable unit 104. By rotating the second rotation movable unit 104, the first rotation driving unit 103, the wafer stage, and the wafer 91 rotate about the orientation determination region 94. In this way, the rotation angle dependence of the intensity of light reflected by the second crystal plane in the etch pit 97 is evaluated. That is, data relating to the rotation angle dependency of the second rotation movable unit 104 of the scattered light intensity is acquired.

  Since the bottom surface of the orientation determination area 94 is inclined with respect to the (100) plane, the orientation determination area (as shown in FIG. 40) depends on where the orientation determination area 94 is formed on the outer peripheral portion of the wafer 91. The shapes of the etch pits (97a to 97c) existing on the bottom surfaces of 94a to 94c) are different. Therefore, the rotation angle dependency of the scattered light intensity forms various profiles depending on the shape of the etch pits (97a to 97c).

  (F) Next, the crystal orientation of the orientation determination region 94 is determined by comparing the data related to the rotation angle dependency with the data in the database 106. In the database 106, data relating to the rotation angle dependency acquired for the etch pits formed over the entire periphery of the wafer 91 is registered. The data in the database 106 is created in advance by experiments or simulations.

  Specifically, the crystal orientation registered in the database 106 in which the error is minimized is obtained by comparison using the profile showing the rotation angle dependence of the scattered light intensity shown in FIG. Among the profiles related to the entire circumference stored in the database 106, the one closest to the measured profile is selected, and the crystal orientation of the profile is specified as the crystal orientation in which the etch pit to be measured exists. Therefore, it is necessary that consistency between the inclination angle of the bottom surface of the orientation determination region 94 in the experiment or simulation and the inclination angle of the bottom surface of the orientation determination region 94 processed in step S26 is required.

  (G) Next, based on the crystal orientation of the orientation determination region 94, a reference ID mark indicating crystal orientation information of the wafer 91 is beveled on the back surface of the wafer 91 (the surface opposite to the surface where the orientation determination region 94 is processed). Engrave the part. The reference ID mark is imprinted using a laser marker 105 made of, for example, a YAG high-power laser. The reference ID mark is not limited to the back surface of the wafer, but can be stamped on the front surface of the wafer and the bevel portion.

  (H) Finally, in the semiconductor device manufacturing process, at least in the first lithography process, the crystal orientation of the wafer 91 can be aligned with the reference ID mark as a reference (S34) and exposed (S35).

  As described above, the orientation determination region (concave portion) is formed on the circular semiconductor wafer 91 having no notch or orientation flat before the anisotropic etching process (S28) and the mirror polishing process (S30, S31). 94 is formed in advance. As a result, even after mirror polishing of the wafer 91, it is possible to detect crystal orientation information from etch pits in the orientation determination region (concave portion) 94 using a light scattering technique. Using the crystal orientation information from the etch pit, a reference ID mark indicating the crystal orientation can be provided on the wafer 91.

  When the crystal orientation of a wafer is obtained using the X-ray diffraction method, a measurement time of several minutes to several tens of minutes is required for each wafer, which causes a problem in throughput. Considering the current manufacturing cost of semiconductor devices, a throughput of at least about 1 minute per sheet is required. In addition, if the X-ray source is strengthened to shorten the time, the influence on the human body and the power consumption become great. On the other hand, according to the eighth embodiment, since the visible light scattering is used to detect the crystal orientation, the detection speed is improved and a throughput of 1 minute / sheet is possible. Further, compared with detection by X-ray, there is almost no influence on the human body and power consumption is low. That is, the crystal orientation can be evaluated quickly and with high accuracy by a safe method.

  As shown in FIG. 41, the throughput was improved about 5 to 10 times as compared with the method of detecting the wafer orientation by X-ray diffraction (comparative example). Further, when a dynamic random access memory (DRAM) was produced using the semiconductor wafer according to the eighth embodiment, the yield was improved.

  It is also conceivable that the crystal orientation information is laser marked by detecting the crystal orientation from the etch pits appearing on the entire surface of the wafer immediately after the alkali etching process (S28). However, in such a case, unless a relatively deep mark of 10 μm or more is formed, it will disappear in the subsequent mirror processing (S30, S31).

  Furthermore, in the eighth embodiment, a relatively shallow soft laser mark of 10 μm or less is sufficient. In addition, it is possible to perform crystal orientation alignment at the time of the first pattern exposure process in the semiconductor device manufacturing process.

  Furthermore, when marking the wafer recognition information (ID mark) on the bevel portion of the semiconductor wafer, the marking location can be created in a shape different from other bevel shapes, so that the marking accuracy is improved. Also, the recognition rate of mark reading has improved.

(Modification 1 of 8th Embodiment)
In the first modification of the eighth embodiment, a case where the intensity of light reflected by the etch pits 97 is measured at once without rotating the wafer 91 will be described.

  FIG. 42 is a block diagram illustrating a configuration of a semiconductor wafer manufacturing apparatus according to Modification 1 of the eighth embodiment. The semiconductor wafer manufacturing apparatus has a detector 108 that measures the intensity of light 100 reflected in all directions by the second crystal plane in the etch pit. The detector 108 has a detection surface arranged so as to surround the entire periphery of the white light 99 incident from the light source 98, and is formed by all the second crystal planes forming the etch pits shown in FIG. The reflected light 100 can be detected simultaneously.

  The detection surface of the detector 108 has a spherical shape, and a hole for allowing the white light 99 to pass therethrough is formed at the center thereof. The light 100 reflected by the etch pit can be detected efficiently. Therefore, it is not necessary to rotate the wafer 91 around the azimuth determination region 94 irradiated with the white light 99 as the central axis. The semiconductor wafer manufacturing apparatus does not include the second rotation drive unit 104 of FIG. 39 but includes the first rotation drive unit 103 and the XY stage 107. Other configurations of the semiconductor wafer manufacturing apparatus and the semiconductor wafer manufacturing method are the same as those in the eighth embodiment, and a description thereof will be omitted.

  The wafer 91 is placed on the wafer stage and the first rotation driving unit 103 is rotated. The rotation of the first rotation drive unit 103 is stopped at a position where the white light 99 from the light source 98 is irradiated on the orientation determination region 94 formed in a part of the bevel portion. At this time, the white light 99 is also applied to the etch pits 97 formed in the orientation determination region 94. Then, the intensity of light scattered by the etch pits 97 is simultaneously detected using the detector 108 over the entire circumference of the orientation determination region 94. At this time, the first rotation driving unit 103, the wafer stage, and the wafer 91 are not rotated.

  As described above, according to the first modification of the eighth embodiment, the same operational effects as those of the eighth embodiment can be obtained. Further, by disposing the detector 108 over the entire circumference of the orientation determination region 94, the light 100 scattered in all directions by the etch pits can be detected at a time without rotating the wafer 91 or the like. Therefore, it is possible to shorten the time required for acquiring the rotation angle dependency data of the scattered light.

(Modification 2 of the eighth embodiment)
In the eighth embodiment and its modification example 1, the profile indicating the rotation angle dependence of the scattered light intensity measured by the detector (101, 108) is compared with the profile stored in the database 106, and the orientation is The crystal orientation of the determination region 94 was obtained.

  However, as described above, the bottom surface of the orientation determination region 94 is inclined with respect to the first main surface 95 of the wafer. Therefore, the shape of the etch pits (97a to 97c) existing on the bottom surface of the orientation determination regions (94a to 94c) varies depending on where the orientation determination region 94 is formed on the outer peripheral portion of the wafer 91.

  Therefore, in the second modification of the eighth embodiment, the shape of the etch pits (97a to 97c) formed on the bottom surfaces of the orientation determination regions (94a to 94c) is measured, and the etch pits stored in the database are measured. A case where the crystal orientation of the orientation determination region is obtained by comparing with the shape will be described.

  The semiconductor wafer manufacturing apparatus according to the second modification of the eighth embodiment uses etch pits 97 formed on the bottom surface of the orientation determination region 94 in place of the detectors (101, 108) shown in FIGS. Means for measuring the shape of This shape measuring means includes a CCD camera, a photosensitive polaroid camera, and the like. The shape of the etch pit 97 to be measured indicates the planar shape of the etch pits (97a to 97c) as shown in FIG. The plane referred to here includes the first main surface 95 of the wafer or the bottom surface of the orientation determination region 94.

  The semiconductor wafer manufacturing apparatus includes a first rotation drive unit 103 and an XY stage 107, as in FIG. The other apparatus configuration is the same as that of the semiconductor wafer manufacturing apparatus shown in FIG.

  In the database 106, two-dimensional image data relating to the planar shape of etch pits formed over the entire periphery of the wafer 91 is registered. The two-dimensional image data in the database 106 is created in advance by experiments or simulations.

  The first rotation drive unit 103 is operated to irradiate the azimuth determination region 94 with white light 99. The planar shape of the etch pit 97 existing on the bottom surface of the orientation determination area 94 is measured using a shape measuring means such as a CCD camera. The measurement result is sent to the PC 102 as two-dimensional image data. Then, the PC 102 compares the measured planar shape of the etch pits with the planar shape of the etch pits in the database 106 to determine the crystal orientation of the orientation determination region 94.

  More specifically, the measured planar shape of the etch pit 97 is compared with the planar shape of the etch pit in the database 106, and the crystal orientation registered in the database 106 that minimizes the shape error is obtained. Among the planar shapes of the etch pits related to the entire circumference stored in the database 106, the one closest to the measured planar shape of the etch pits 97 is selected. Then, the crystal orientation of the selected etch pit is specified as the crystal orientation in which the etch pit 97 to be measured exists. Therefore, it is necessary that consistency between the inclination angle of the bottom surface of the orientation determination region 94 in the experiment or simulation and the inclination angle of the bottom surface of the orientation determination region 94 processed in step S26 is required.

  As described above, according to the second modification of the eighth embodiment, the same operational effects as those of the eighth embodiment can be obtained. Further, since the planar shape of the etch pit 97 is used as a comparison object, it is not necessary to measure a profile indicating the rotation angle dependency of the scattered light intensity. In other words, it is not necessary to rotate the wafer 91 or the like or to detect light scattered in all directions by the etch pits.

(Ninth embodiment)
In the ninth embodiment, an apparatus and method for measuring the crystal orientation of a wafer using a crystal defect formed on or in the wafer surface of a circular semiconductor wafer having no notch or orientation flat. explain.

  Each partial view of FIG. 43 is an enlarged photograph showing the shape of a crystal defect used in the apparatus and method according to the ninth embodiment. FIG. 43A shows a crystal defect called “Crystal Originated Particle (COP)”, and FIG. 43B shows a crystal defect called “Bulk Micro Defect” (BMD).

  The target semiconductor wafer is a wafer manufactured by the Czochralski Method (CZ method) (hereinafter referred to as “CZ wafer”) or a wafer manufactured by the epitaxial growth method (hereinafter referred to as “epitaxial wafer”). ), The crystal orientation of the wafer is measured using COP.

  On the other hand, when the target semiconductor wafer is an annealed wafer or a wafer that has been subjected to IG heat treatment in advance, the crystal orientation of the wafer is measured using BMD. COP has an octahedral structure, and BMD has a 6-8 octahedral structure. Moreover, COP and BMD are crystal defects in which specific crystal orientation planes including the (111) plane are exposed. Therefore, as in the eighth embodiment, the intensity of the light scattered by the COP or BMD crystal orientation plane has a rotation angle dependency.

  FIG. 44 is a cross-sectional view showing a semiconductor wafer for explaining the operating principle of the semiconductor wafer manufacturing apparatus according to the ninth embodiment. Inside the wafer 121, there are minute crystal defects 122 such as COP or BMD. Beam-shaped infrared light 123 is applied obliquely to the first main surface of the wafer 121. An infrared laser beam can be used as the beam-like infrared light 123. A part of the infrared light 123 enters the wafer 121 and is scattered by the crystal defects 122. At this time, the infrared light 123 is reflected by a specific crystal orientation plane of the crystal defect 122. The scattered infrared light 126 is detected by the scattered light detector 124 provided above the first main surface of the wafer 121.

  Further, the wafer 121 is disposed on a wafer stage 125 having a rotation mechanism. The infrared light 123 is applied to the center of rotation of the wafer 121. While rotating the wafer 121, the intensity of the light 126 scattered by the crystal defect 122 located at the rotation center is continuously detected. At this time, the intensity of the scattered light changes periodically. That is, the intensity of the scattered light to be detected has a rotation angle dependency. The crystal orientation of the wafer 121 can be determined from the profile of the scattered light intensity.

  When an infrared laser beam having a wavelength of 1000 nm is used, the depth in the wafer 121 that the infrared laser beam 123 can reach is about 50 μm from the first main surface. Therefore, the crystal defect to be measured is a crystal defect existing at a depth of about 50 μm from the first main surface.

  FIG. 45 is an external view showing a configuration of a semiconductor wafer manufacturing apparatus according to the ninth embodiment. The semiconductor wafer manufacturing apparatus includes an infrared laser light source 127, a wafer stage 125 having a rotation mechanism, a scattered light detector 124, a laser marker (mark engraver) 128 that forms a marking mechanism for numbering, and the entire apparatus. And a computer (PC) 129 that analyzes data relating to the rotation angle dependence of the scattered light intensity.

  Infrared laser light emitted from the infrared laser light source 127 is incident on the rotation center of the wafer stage 125 obliquely with respect to the first main surface of the wafer 121. The scattered light detector 124 is disposed above the first main surface of the wafer 121 and measures the intensity of infrared laser light scattered by crystal defects in the wafer 121.

  The chamber 130 has a function of covering and concealing the wafer stage 125, the infrared laser light source 127, the scattered light detector 124, the laser marker 128, and the wafer 121, and blocking infrared light entering from the outside. The computer 129 is installed with analysis software for analyzing data related to the rotation angle dependency of the scattered light intensity. The laser marker 128 irradiates the outer peripheral portion of the wafer 121 with laser light imaged on the wafer surface. As a result, in the process of melting and recrystallization of the wafer surface, for example, minute protrusions (dot marks) having a size of 5 μm and a step of 0.5 μm are formed. As the laser marker 128, for example, a He—Ne laser having a Gaussian-shaped energy density distribution can be used.

(A) First, the wafer 121 to be measured is placed on the wafer stage 125. The wafer 121 is a circular CZ wafer in which notches and orientation flats are not formed. The (100) plane is exposed on the first main surface of the CZ wafer 121. The low efficiency ρ is 10 to 20 Ω · cm, and the oxygen concentration [Oi] is 12 to 14 × 10 ₁₇ atoms / cm ₃ (old ASTM).

  (B) Next, as shown in FIG. 46, in step S40, while rotating the CZ wafer 121 using the rotating mechanism of the wafer stage 125, the infrared laser light source 127 is used to rotate the first main surface of the CZ wafer 121. On the other hand, infrared laser light is irradiated obliquely. At the same time, in step S41, the scattered light detector 124 is operated to continuously measure the intensity of the laser light scattered by the crystal defects inside the CZ wafer 121. Note that the steps S40 and S41 need to be performed in parallel and are sufficient. Therefore, the order of starting does not matter. That is, the scattered light detector 124 may be operated after the rotation mechanism is operated first, or vice versa.

  (C) Next, data indicating the rotation angle dependence of the laser light intensity scattered in step S42 is analyzed by the PC 129, and the crystal orientation of the CZ wafer 121 is determined in step S43. Specifically, a profile indicating the change in scattered light intensity with respect to the rotation angle of the CZ wafer 121 as shown in FIG. 47 is analyzed on the PC 129. The diamond-shaped points and connecting lines thereof indicate the COP profiles actually measured for the CZ wafer 121 by the method according to the ninth embodiment. As shown in FIG. 47, the rotation angle dependence of the scattered light intensity has a periodicity consisting of a sine wave. At the rotation angle of the CZ wafer 121 where the maximum value and the minimum value of the scattered light intensity are formed, the (111) plane of the COP faces the incident direction of the laser light.

  Although illustration is omitted, the COP profile is actually measured for the epitaxial wafer, and the same result as the CZ wafer 121 is obtained. The epitaxial wafer to be measured is a notchless p / p-wafer having an epilayer resistivity ρVG of 10 to 20 Ω · cm and an epilayer thickness tVG of 3 μm. The (100) plane is exposed on the first main surface of the wafer.

  Incidentally, when the CZ wafer 121 is rotated, the wafer stage 125 may vibrate and noise may be generated. In that case, the rotation of the CZ wafer 121 is stopped to reduce the number of measurement points. The measurement accuracy decreases due to the small number of measurement points. However, by installing software for approximating and analyzing the obtained curve as a sine wave on the PC 129, it is possible to determine the crystal orientation with high accuracy even if there are few measurement points.

  (D) Then, the rotation mechanism of the wafer stage 125 is operated again to align the [011] line of the CZ wafer 121 with the laser irradiation position of the laser marker 128. In step S44, the laser marker 128 is operated to imprint a reference ID mark indicating the crystal orientation of the CZ wafer 121 within a range of 3 mm × 8 mm at a position 2 mm from the outer peripheral edge of the CZ wafer 121.

(Experimental example 1 of 9th Embodiment)
An annealed wafer annealed in a reducing atmosphere was used as the measurement target wafer. The annealed wafer used has a low efficiency ρ of 10 to 30 Ω · cm and an oxygen concentration [Oi] of 10 to 12 × 10 ₁₇ atoms / cm ₃ . The (100) plane is exposed on the first main surface of the annealed wafer. In FIG. 47, the square points and the lines connecting them indicate the BMD profiles actually measured for the annealed wafer. At the rotation angle of the annealed wafer where the maximum value and the minimum value of the scattered light intensity are formed, the (111) plane of the BMD faces the incident direction of the laser light.

(Experiment 2 of 9th Embodiment)
Next, the above-described measurement of the crystal orientation of the wafer was performed when the pattern was exposed on the wafer, not when the reference ID mark was imprinted on the wafer. After determining the crystal orientation, a reference ID mark was imprinted on the wafer, and then the wafer was aligned based on the reference ID mark and then the pattern was exposed.

(Comparative example of the ninth embodiment)
A wafer similar to the CZ wafer 121 according to the ninth embodiment was prepared, and the crystal orientation was determined based on a Laue image formed by the same X-ray diffraction method as in the seventh embodiment. The (100) plane is exposed on the first main surface of the CZ wafer 121. The low efficiency ρ is 10 to 20 Ω · cm, and the oxygen concentration [Oi] is 12 to 14 × 10 ₁₇ atoms / cm ₃ (old ASTM).

  In the ninth embodiment described above, Experimental Examples 1 and 2, and Comparative Example, the crystal orientation of the wafer could be determined. In Experimental Example 2, after determining the crystal orientation, it was possible to align the crystal orientation of the wafer during pattern exposure.

  FIG. 48 is a graph showing the time required to determine the crystal orientation of the wafer. “Ninth Embodiment” shows the ninth embodiment and Experimental Examples 1 and 2, and “Comparative Example” shows a comparative example of the ninth embodiment. The “ninth embodiment” took about 1 to 2 minutes per wafer, whereas the “comparative example” took about 10 to 20 minutes, which is about 10 times as long. In order to accurately determine the crystal orientation of the wafer using X-rays, it is necessary to narrow the slit through which X-rays pass to reduce the measurement area, and X-rays with low intensity are measured for a long time. Because.

  As described above, according to the ninth embodiment and the experimental examples 1 and 2, even in the case of a circular wafer having no notch or orientation flat as in the eighth embodiment, And the crystal orientation can be determined in a short time.

  In the ninth embodiment, the experimental examples 1 and 2, and the comparative example, the case where the crystal orientation of the wafer is measured in the manufacturing process of the semiconductor device has been described. However, the crystal orientation of the wafer can be measured by a similar method even during the process of manufacturing the wafer.

  Moreover, although the case where the light irradiated to a wafer is infrared light was shown, visible light may be sufficient. In other words, a visible laser light source may be used instead of the infrared laser light source 127 shown in FIG. 45 to irradiate the first main surface of the wafer with visible laser light. In this case, the wavelength range measured by the scattered light detector 124 is of course the visible range.

  Furthermore, the case where the laser beam 123 is irradiated obliquely to the first main surface of the wafer and the scattered light detector 124 is disposed above the first main surface of the wafer has been described. However, the relationship between the incident direction of the laser beam and the detection direction of the scattered laser beam is not limited to this. Laser light may be irradiated from above the first main surface of the wafer, and the scattered light detector 124 may be held at an angle to detect the scattered laser light. Alternatively, the laser beam may be incident obliquely and the laser beam scattered obliquely may be detected.

(Tenth embodiment)
In the tenth embodiment, as in the eighth embodiment, a semiconductor that determines the crystal orientation of a semiconductor wafer using etch pits formed by performing an anisotropic etching process using an alkaline solution. A wafer manufacturing method will be described. In the tenth embodiment, a case where the crystal orientation is detected using etch pits formed on the first main surface of the semiconductor wafer will be described.

  First, an experimental example according to the tenth embodiment conducted by the inventors will be described. FIG. 49 is a flowchart showing a series of manufacturing steps of a semiconductor wafer. The pulled single crystal ingot (S50) is subjected to peripheral grinding (S51) to determine the diameter of the wafer, and then subjected to block cutting (S52) and slicing (S53) to obtain a disk-shaped wafer. Form. The (100) plane is exposed on the first main surface of the wafer. Note that since the measurement of crystal orientation and notch or orientation flat processing are not performed on the single crystal ingot, the shape of the outer periphery of the wafer is circular.

  A so-called chamfering process is performed to drop the corner of the outer peripheral edge of the wafer (S54). A bevel portion having a surface (bevel surface) inclined with respect to the first main surface of the wafer is formed on the outer peripheral portion of the wafer. Then, lapping is performed on the first main surface and the bevel portion of the wafer (S55). Then, an anisotropic etching process is performed with one of the main objectives being to remove large waviness on the first main surface of the wafer (S56). The anisotropic etching process refers to an etching process (alkali etching) using an alkaline solution having an etching rate that varies depending on the crystal orientation of the wafer. As the alkaline solution, KOH or NaOH can be used. By performing an anisotropic etching process, an etch pit in which a crystal orientation plane different from the (100) plane is exposed is formed on the first main surface of the wafer.

  After that, an etching process (acid etching) using an acid solution whose main purpose is to remove etch pits is performed (S57). Then, the wafer first main surface and the bevel portion are polished (S58), cleaned and inspected (S59), and then packed and shipped (S60).

  The inventors extracted the wafer after performing alkali etching (S56) and before performing acid etching (S57) from the production line, and used this as a sample wafer.

  FIG. 50 is an external view showing the configuration of the apparatus used in the experimental example. The sample wafer 140 is placed on the wafer stage 141. The first main surface of the sample wafer 140 has many etch pits in which a second crystal plane different from the (100) plane which is the first crystal plane is exposed. A light source 142 is disposed above the first main surface of the sample wafer 140, and white light is vertically incident on the etch pits 144 exposed on the first main surface. The light scattered by the etch pit 144 is detected by the scattered light detector 143. The sample wafer 140, the wafer stage 141, the light source 142, and the scattered light detector 143 are covered with a chamber 146. The chamber 146 blocks light entering from the outside.

  The change in scattered light intensity was measured when the light receiving surface 155 of the scattered light detector 143 was tilted from a state parallel to the (100) plane. FIG. 51 is a graph showing changes in scattered light intensity with respect to the inclination angle of the light receiving surface 155 of the scattered light detector 143. The horizontal axis indicates the tilt angle of the detector 143, and the vertical axis indicates the scattered light intensity as a relative value. A peak appeared when the light receiving surface 155 was parallel to the (100) plane, that is, when the inclination angle was 0 °. In addition, peaks also appeared in a state tilted by 35 ° and −35 °.

  FIG. 52 is a schematic diagram for explaining light scattering by the etch pits 144 formed on the first main surface of the sample wafer 140. Light (147a, 147b) emitted from the light source is incident perpendicular to the (100) plane. The detector 143a whose light-receiving surface 155a has an inclination angle of 0 ° detects the scattered light 148a that is directly reflected by the (100) surface. As a result, a peak at an inclination angle of 0 ° is formed.

  The detector 143b whose light receiving surface 155b has an inclination angle of 35 ° detects the scattered light 148b scattered by the etch pits 144. This forms a peak at an inclination angle of 35 °. As shown in FIG. 52, in the etch pit 144, a second crystal plane including a (111) plane and a crystal plane equivalent to the (111) plane is exposed. The light scattered by the etch pit 144 is reflected by the second crystal plane in the etch pit 144, and is detected by the detector 143b whose light receiving surface 155b is inclined by 35 °.

  Based on the experimental example described above, a semiconductor wafer manufacturing apparatus according to the tenth embodiment will be described. FIG. 53 is an external view showing a semiconductor wafer manufacturing apparatus according to the tenth embodiment. A semiconductor wafer manufacturing apparatus is an apparatus that measures the crystal orientation of a wafer by making white light incident on the wafer surface immediately after alkali etching and measures the scattered light, thereby marking the wafer.

  The semiconductor wafer manufacturing apparatus irradiates light onto the wafer stage 141 and the first main surface of the wafer 140 placed on the wafer stage 141, and is scattered by etch pits 144 formed on the first main surface of the wafer 140. A detection unit 149 for measuring the intensity of the scattered light, a computer 145 for analyzing data on the rotation angle dependence of the intensity of the scattered light, and a reference ID mark indicating the crystal orientation of the wafer 140 on the wafer 140. It has a laser marker (mark stamper) 150 and a chamber 146 that covers at least the wafer stage 141, the wafer 140, and the detection unit 149 and blocks light entering from the outside. The computer 145 is equipped with software that analyzes data related to the rotation angle dependency of the intensity of scattered light and corrects the tilt angle of the wafer 140.

  Here, the first crystal plane (here, (100) plane) is exposed on the first main surface of the wafer 140, and the second crystal plane is exposed by alkali etching, which is different from the (100) plane. A pit is formed. The second crystal plane includes a (111) plane and a crystal plane equivalent to the (111) plane. The detection unit 149 has a function of irradiating light to the first main surface of the wafer 140 and a function of measuring the intensity of light scattered by the etch pits 144 formed on the first main surface of the wafer 140. The laser marker 150 irradiates a laser on the outer peripheral portion of the second main surface of the wafer 140 to imprint a reference ID mark composed of a plurality of dot marks. The formation position of the reference ID mark is not limited to the outer peripheral portion of the second main surface of the wafer 140, but may be the outer peripheral portion or the side surface portion of the first main surface of the wafer 140.

  FIGS. 54A and 54B are diagrams showing the configuration of the detection unit 149. 54A is a cross-sectional view of the detection unit 149, and FIG. 54B is a bottom view of the detection unit 149 viewed from the wafer 140 side. The detection unit 149 measures the intensity of the light scattered by the light source 154 that irradiates the light 151 on the first main surface of the wafer placed on the wafer stage and the etch pit formed on the first main surface of the wafer. Light receiving element 149. As the light receiving element 149, a CCD camera having a diameter of 1.25 cm and 300,000 pixels can be used.

  The light receiving element 149 has a ring-shaped light receiving surface 155 that surrounds the outer periphery of the light 151 emission port and is inclined with respect to the irradiation direction of the light 151. Here, the light receiving surface 155 has a substantially circular shape. The inclination angle of the light receiving surface 155 is set to 35.3 ± 1 °. Thus, the detection unit 149 is a unit in which the light source 154 and the light receiving element 152 are integrated.

  The light 151 applied to the wafer is a parallel light beam composed of a bundle of parallel lights that do not diverge or converge. The light 151 may be white light or monochromatic light. In addition to visible light, infrared light may be used. Therefore, a monochromatic laser or an infrared laser can be used as the light source 154.

  The light source 154 is operated to irradiate the first main surface of the wafer with the parallel light beam 151. Of the irradiated parallel light beam 151, the light scattered by the etch pits formed on the first main surface is detected by the light receiving element 152 inclined by 35 °. Since the light receiving element 152 is arranged so as to surround the periphery of the light source 154, the light scattered in all directions by the etch pits can be simultaneously measured without rotating the wafer or the light receiving element 149. The computer 145 evaluates the intensity of light scattered in all directions by the etch pit for each rotation angle of the light receiving surface 155 with the incident light 151 as the center.

  FIG. 55 is a graph showing the rotation angle dependence of the scattered light evaluated by the computer 145. The horizontal axis indicates the light receiving portion specified by the rotation angle of the light receiving surface 155, and the vertical axis indicates the scattered light intensity as a relative value. Also, a ring-shaped light receiving surface 155 in FIG. 55 indicates the position of the light receiving portion 153 corresponding to the main rotation angle. Scattered light peaks having substantially the same intensity appear at four positions every 90 °. This is because there are (111) planes exposed to the etch pits and four crystal planes equivalent thereto. By arranging the light receiving elements in a circular shape, it is possible to detect scattered light from the (111) plane and an equivalent crystal plane at a time without capturing scattered light from the (100) plane.

  On the other hand, FIG. 56 is also a graph showing the rotation angle dependence of the scattered light evaluated by the computer 145. However, the scattered light peaks shown in FIG. 56 have irregular intervals and intensities. Peaks appear at rotation angles of 10 °, 50 °, 170 °, and 310 °, and the intensity of each peak is not uniform. This occurs when the crystal plane exposed on the first main surface of the wafer is shifted from the (100) plane, or when the detection unit is inclined with respect to the first main surface of the wafer. In this case, by correcting the angle of the first main surface of the wafer or the detection unit using a computer, four peaks having a uniform interval and strength are formed as shown in FIG.

  The distance between the wafer 140 and the light receiving element 152 in the detection unit 149 has an optimum value. Specifically, as shown in FIG. 57A, the distance between the center of the parallel light beam 151 irradiated to the wafer 140 and the center of the light receiving surface 155 is the center of the first main surface of the wafer 140 and the center of the light receiving surface 155. It is desirable that the distance is 0.7.

FIG. 57B fixes the distance (d _L ) between the center of the parallel light beam 151 irradiated to the wafer 140 and the center of the light receiving surface 155, and sets the distance between the first main surface of the wafer 140 and the center of the light receiving surface 155. distance (d _W) is changed to show the result of measuring the variations in intensity of the scattered light. The horizontal axis represents (d _L / d _W ), and the vertical axis represents scattered light intensity. As shown in FIG. 57 (b), the maximum value of the scattered light intensity is obtained when (d _L / d _W ) = 0.7 ± 0.1. This indicates that the scattered light 148b from the (111) plane shown in FIG. 52 and the equivalent crystal plane is detected most efficiently.

  As described above, the measurement accuracy is improved by correcting the distance between the detection unit 149 and the wafer and the inclination of the wafer 140 or the detection unit 149.

  FIG. 58 is a flowchart showing a method for manufacturing a semiconductor wafer according to the tenth embodiment. FIG. 58 is almost the same as the flowchart of FIG. In place of extracting the sample wafer in FIG. 49, in FIG. 58, the crystal orientation is measured and marked (S61) using the semiconductor wafer manufacturing apparatus shown in FIG.

  Specifically, the wafer after the alkali etching (S56) is irradiated with a parallel light beam on etch pits formed on the first main surface of the wafer by the etching process. The light scattered by the second crystal plane exposed in the etch pit is measured, and the rotation angle dependence of the scattered light intensity is evaluated. Then, a reference ID mark indicating the crystal orientation of the wafer is attached on the wafer. Thereafter, etch pits are removed by acid etching (S57).

(Comparative example of the tenth embodiment)
After alkali etching (S56) and before acid etching (S57), the wafer was irradiated with X-rays to measure crystal orientation. And it marked on the wafer using the marking apparatus based on the measurement result.

  FIG. 59 is a graph comparing the tenth embodiment and the comparative example with respect to the time required for wafer orientation measurement and marking. In the comparative example, it takes about 10 to 20 minutes per wafer, but in the tenth embodiment, it is about 1 to 2 minutes per wafer. In the tenth embodiment, visible light or infrared light is used, but in the comparative example, X-rays that adversely affect the human body are used, and thus a device for ensuring safety is required.

  Therefore, according to the tenth embodiment, the manufacturing cost can be reduced, and the crystal orientation measurement and marking of the wafer can be performed safely and accurately in a short time.

(Eleventh embodiment)
In recent years, the performance of semiconductor integrated circuits has been improved, and the adoption of SOI wafers having features of power saving and high-speed operation has become serious. However, when an SOI wafer is manufactured by the direct bonding method, two wafers are required for manufacturing one SOI wafer, which has a disadvantage that the wafer price is high. For example, the price of an 8-inch wafer is about 100,000 yen per sheet. Therefore, price reduction is one of the biggest concerns of SOI wafers.

  On the other hand, in order to further improve the characteristics of semiconductor products, various elements have recently been used in the manufacturing process. Along with this, a wafer cleaning process has become important in order to prevent contamination of the next process due to dust remaining in the notch portion (recessed portion) and contamination between the wafer and the wafer. However, the element (dust) deposited on the notch portion cannot be removed by using various cleaning methods. Therefore, the notch causes contamination of the wafer, and the manufacturing yield is lowered.

  In the eleventh embodiment, as in the fifth embodiment, the substrate wafer made of single crystal silicon, the insulating layer disposed on the main surface of the substrate wafer, and the insulating layer are disposed on the insulating layer. An SOI wafer having an SOI layer (single crystal silicon layer) will be described. In particular, an SOI wafer in which a notch and an orientation flat are not present on the base wafer and the outer periphery of the base wafer is circular and a manufacturing method thereof will be described.

  FIG. 60A is an external view showing the entire configuration of the SOI wafer according to the eleventh embodiment. The SOI wafer 173 includes a base wafer 160 having a circular outer periphery, a bevel formed on the outer periphery of the base wafer 160, an insulating layer disposed on the base wafer 160, and an insulating layer. And a reference position 169 formed on the outer periphery of the SOI layer, and a reference ID mark indicating the crystal orientation of the SOI layer.

  The reference position 169 is a notch or an orientation flat indicating the crystal orientation of the SOI layer. Here, the description of the case where the reference position is the notch 169 is continued.

  FIG. 60B is a partially enlarged view showing the notch 169 and the reference ID mark formed in the vicinity thereof. An insulating layer 172 is disposed on the main surface of the substrate wafer 160, and an SOI layer 171 is disposed on the insulating layer 172. The notch 169 is formed in the outer peripheral portion of the insulating layer 172 and the SOI layer 171. Note that the notch 169 may be formed only at least in the outer peripheral portion of the SOI layer 171. That is, it does not matter whether it is formed on the insulating layer 172 or not.

  The reference ID mark 165 is attached on the bevel portion of the base wafer 160 in alignment with the notch 169. Further, an ID mark 164 indicating information on the SOI wafer 173 is attached on the bevel portion of the base wafer 160 adjacent to the reference ID mark 165. Here, a mark “Δ” is used as the reference ID mark 165. However, it is not limited to this. As shown in other embodiments, the reference ID mark 165 may be a mark of any shape as long as it is a mark for recognizing the crystal orientation of the SOI layer. The ID mark 164 is a plurality of alphanumeric characters whose main purpose is to manage the quality of the SOI wafer 173. In the following description, the reference ID mark 165 and the ID mark 164 are collectively referred to as an ID mark 162.

  Next, a method for manufacturing the SOI wafer 173 shown in FIG. 60 will be described. The SOI wafer 173 according to the eleventh embodiment is an SOI wafer manufactured by a direct bonding method. FIG. 61 is a flowchart showing a method for manufacturing a substrate wafer 160 according to the eleventh embodiment. First, a peripheral grinding process (S72) is performed on the pulled single crystal ingot (S71) to specify the diameter of the wafer, and a slicing process (S75) is performed to form a disk-shaped wafer. Note that since the measurement of crystal orientation and notch or orientation flat processing are not performed on the single crystal ingot, the shape of the outer periphery of the wafer is circular.

  A so-called chamfering process is performed to drop the corner of the outer peripheral edge of the wafer (S76). A bevel portion having a surface (bevel surface) inclined with respect to the main surface of the wafer is formed on the outer peripheral portion of the wafer. Then, lapping is performed on the main surface and the bevel portion of the wafer (S76). Then, an etching process is performed with one of the main purposes being to remove large waviness on the main surface of the wafer (S78). The etching process includes an etching process using an alkaline solution (alkali etching) and an etching process using an acid solution (acid etching).

  Then, a mirror polishing process is performed on the wafer main surface and the bevel portion (S79), and cleaning and inspection are performed. Thereafter, an ID mark 162 for recognizing crystal orientation and quality control of the SOI wafer is drawn on the bevel portion of the wafer. The substrate wafer 160 according to the eleventh embodiment is completed through the above steps.

  FIG. 62A is an external view showing the overall configuration of the base wafer 160 manufactured according to the flowchart shown in FIG. The outer periphery of the substrate wafer 160 has a circular shape, and a reference position such as a notch or an orientation flat is not formed. A bevel portion 163 is formed on the outer peripheral portion of the base wafer 160. FIG. 62B is an enlarged view of a portion where the ID mark 162 is drawn. The ID mark 162 is drawn on the side close to the main surface 161 of the bevel portion 163.

  FIG. 63 is a flowchart showing a method of manufacturing the SOI layer wafer 166 according to the eleventh embodiment. First, a silicon (Si) wafer having a notch formed on the outer periphery of the wafer is manufactured by a method according to the manufacturing method of the base wafer 160 shown in FIG. However, after the peripheral polishing (S72) and before the slicing process (S75), the crystal orientation of the single crystal ingot is measured using X-rays, and the single crystal ingot is notched. In this manner, a silicon (Si) wafer 170 having a notch formed on the outer periphery of the wafer is manufactured.

Next, as shown in FIG. 63, heat treatment is applied to the first main surface of the Si wafer to form a thermal oxide film (S91). Alternatively, a silicon oxide film may be deposited on the first main surface of the Si wafer. These thermal oxide films or silicon oxide films (hereinafter simply referred to as “oxide films”) serve as buried oxide films 172 that function as BOX layers in the SOI wafer 173. Hydrogen ions are implanted into the first main surface of the Si wafer from above the oxide film using an ion implantation method (S92). As ion implantation conditions, for example, the acceleration energy of ions is set to about 50 keV and the implantation density is set to 10 ₁₇ / cm ₂ . A hydrogen ion implanted layer is formed inside the Si wafer 170 so as to be separated from the oxide film. Through the above steps, the SOI layer wafer 166 is completed.

  FIG. 64A is an external view showing the overall configuration of the SOI layer wafer 166 manufactured according to the flowchart shown in FIG. A notch 169 is formed in the bevel portion 170 of the SOI layer wafer 166. FIG. 64B is a diagram showing a cross-sectional configuration of the SOI layer wafer 166. An oxide film 172 is formed on the first main surface 167 of the SOI layer wafer 166. Further, a hydrogen ion implantation layer 168 is formed inside the wafer 170 so as to be separated from the oxide film 172. A layer disposed between the oxide film 172 and the hydrogen ion implantation layer 168 becomes an SOI layer (single crystal silicon layer) 171.

  FIG. 65 is a flowchart showing a method of manufacturing an SOI wafer 173 according to the eleventh embodiment using the base wafer 160 of FIG. 62 and the SOI layer wafer 166 of FIG. First, the main surface 161 of the base wafer 160 and the first main surface 167 of the SOI layer wafer 166 are bonded at room temperature (S95). At this time, the notch 169 formed on the outer peripheral portion of the SOI layer wafer 166 and the reference ID mark “Δ” formed on the bevel portion 163 of the base wafer 160 are aligned with each other for the base wafer 160 and the SOI layer. The wafer 166 is bonded together. For alignment between the notch 169 and the reference ID mark 165, an optical mark reading device using a CCD may be used. The orientation of both wafers (160, 166) is adjusted with reference to the “Δ” mark 165 formed on the bevel portion.

  Thereafter, the wall of the SOI layer wafer 166 is opened with the hydrogen ion implantation layer 168 of the SOI layer wafer 166 as a boundary while applying heat treatment (S96). As a result, the oxide film (buried oxide film) 172 and the SOI layer 171 are integrated on the main surface 161 of the base wafer 160. Lastly, the polished surface is subjected to mirror polishing (S97), and the SOI wafer 173 shown in FIG. 60 is completed.

  Here, the method of opening the SOI layer wafer 166 with the hydrogen ion implantation layer 168 as a boundary after the base wafer 160 and the SOI layer wafer 166 are bonded together has been described. However, the SOI wafer manufacturing method according to the eleventh embodiment is not limited to this. The base wafer 160 and the SOI layer wafer 166 may be bonded or bonded without forming the hydrogen ion implantation layer 168. In this case, after bonding both wafers (160, 166), the SOI layer 171 is formed by thinning the SOI layer wafer 166 from the second main surface facing the first main surface 167 to a desired thickness. That's fine. As a means for thinning, chemical mechanical polishing (CMP) or chemical or physical etching can be used.

  As described above, the notch and the orientation flat in the SOI wafer are necessary for knowing the in-plane orientation of the SOI layer in manufacturing the semiconductor integrated circuit. Therefore, the crystal orientation of the base wafer is the SOI layer wafer. There is no particular problem even if the crystal orientation is misaligned. Therefore, as long as the crystal orientation of the SOI layer can be known, the substrate wafer may have a simple disk shape without a notch or an orientation flat.

(Modification 1 of the eleventh embodiment)
In the eleventh embodiment, as shown in FIG. 62B, the case where the ID mark 162 drawn on the bevel portion of the base wafer 160 is composed of the alphanumeric code 164 and the “Δ” mark 165 has been described. In the first modification of the eleventh embodiment, a case where a bar code is used instead of the alphanumeric code and the “Δ” mark will be described.

  As shown in FIG. 66A, the SOI layer wafer 166 and the base wafer 160 are bonded together. A notch 169 is formed in the SOI layer wafer 166. On the other hand, a bar code 175 is attached to the bevel portion of the base wafer 160 according to the notch 169. As shown in FIG. 66B, the bar code 175 is provided adjacent to the notch 169 and on the side near the SOI layer wafer 166 in the bevel portion. The barcode 175 includes a two-dimensional barcode in addition to the one-dimensional barcode as shown in FIG. 66 (b).

(Modification 2 of the eleventh embodiment)
In general, a notch and an orientation flat in an SOI wafer are necessary for knowing the in-plane orientation of the SOI layer 171 when manufacturing a semiconductor integrated circuit. Accordingly, the crystal orientation of the base wafer 160 is not particularly problematic. The SOI layer wafer 166 has a notch 169 indicating the crystal orientation of the SOI layer 171. Therefore, if the crystal orientation of the SOI layer 171 can be recognized using the notch 169, it is not necessary to attach a reference ID mark such as the “Δ” mark 165 for indicating the crystal orientation of the SOI layer 171 to the base wafer 160.

  Therefore, in Modification 2 of the eleventh embodiment, a case will be described in which a reference ID mark for indicating the crystal orientation of the SOI layer 171 is not formed on the base wafer 160. As shown in FIG. 67 (a), an SOI wafer 176 according to the second modification of the eleventh embodiment includes an SOI layer wafer 166 in which a notch 169 is formed, and a substrate on which no reference ID mark is formed. The wafer 160 is manufactured by bonding. As shown in FIG. 67B, a notch 169 is formed in the buried oxide film and the SOI layer of the SOI layer wafer 166. On the other hand, the reference ID mark indicating the crystal orientation and the ID mark for managing the quality of the SOI wafer are not formed on the bevel portion of the base wafer 160.

  In the manufacturing process of a semiconductor integrated circuit that requires alignment of the crystal orientation of the wafer, an optical mark reading device using a CCD camera is used to recognize the notch 169 of the SOI layer 171 and align the crystal orientation. It can be carried out.

  As described above, even if the outer peripheral shape of the base wafer is a circle having no notch or orientation flat, if the notch or orientation flat is formed at least on the outer periphery of the SOI layer in the SOI layer wafer, the semiconductor In manufacturing the integrated circuit, the in-plane orientation of the SOI layer can be known. Furthermore, the reference ID mark is read on the bevel portion of the base wafer in accordance with the notch of the SOI layer wafer without directly detecting the notch on the outer periphery of the SOI layer. Thus, the crystal orientation of the SOI layer can be quickly obtained by a simple method.

  When manufacturing the base wafer, the processing cost of the notch or the orientation flat can be reduced, so that the cost of the SOI wafer can be reduced. In addition, since the outer peripheral shape is circular, the uniformity within the wafer surface in the manufacturing process of the semiconductor integrated circuit is improved. Further, dust such as a residual film generated during the production does not remain in the notch portion, and contamination (cross contamination) in the subsequent process can be prevented. Therefore, a high-quality semiconductor wafer can be supplied at low cost.

(Comparative example of the eleventh embodiment)
The SOI wafer according to the comparative example of the eleventh embodiment is manufactured by bonding a base wafer having a notch and an SOI layer wafer having a notch. That is, the base wafer has a notch instead of the reference ID mark. Below, the manufacturing method of the base wafer and SOI wafer which concern on a comparative example are demonstrated.

  FIG. 68 is a flowchart showing a method for manufacturing the base wafer 177 according to the comparative example of the eleventh embodiment. Similar to FIG. 61, the peripheral grinding process (S72) is performed on the pulled single crystal ingot (S71). Thereafter, the crystal orientation of the single crystal ingot is measured using X-rays (S73). Then, a notch or orientation flat indicating the in-plane crystal orientation of the wafer (usually indicating the [110] direction) is formed (S74). Thereafter, the processes of S75 to S79 are performed as in FIG. Then, a laser mark for quality control is attached to the back surface of the wafer (S81). This is because if the marking is made on the surface side, the unevenness of the mark becomes an obstacle at the time of wafer bonding.

  FIGS. 69A and 69B show the configuration of an SOI wafer 178 according to a comparative example. The SOI wafer 178 is manufactured by bonding the base wafer 177 manufactured according to the flowchart of FIG. 68 and the SOI layer wafer 166. Here, the SOI layer wafer 166 is manufactured according to the flowchart of FIG. 63, and has the same configuration as the SOI layer wafer shown in FIG. Further, the bonding of the base wafer 177 and the SOI layer wafer 166 is performed according to the flowchart shown in FIG. At this time, the notches 169 of the base wafer 177 are aligned with the notches 169 of the SOI layer wafer 166, and the two wafers (166, 177) are bonded together.

  Therefore, as shown in FIG. 69A, the positions of both notches (169, 179) coincide. That is, in the SOI wafer 178 according to the comparative example, a notch 179 is formed instead of attaching the reference ID mark to the base wafer 177 as compared with the SOI wafer 173 in FIG. 60 according to the eleventh embodiment. Bonding is performed based on the standard.

  As shown in FIG. 69 (b), a laser mark 164 for quality control is attached to the back surface of the wafer.

1 is a partial external view of a semiconductor wafer according to a first embodiment. FIGS. 2A to 2C are flowcharts showing a method for marking a semiconductor wafer according to the second embodiment. It is a partial external view of the semiconductor wafer which concerns on 3rd Embodiment. It is a figure which compares 3rd Embodiment and a comparative example about a throughput (required time). It is a figure explaining the method of calculating | requiring the shape of the bevel part of a wafer in the modification of 3rd Embodiment. It is a table | surface which shows the reading result of the ID mark which concerns on the modification 1 of 3rd Embodiment. It is sectional drawing which shows the structure of the bevel part formed in the outer peripheral part of a semiconductor wafer, and the ID mark formed on the bevel part. It is a partial external view of the semiconductor wafer which shows the case where it divides into right and left based on the edge part of a notch based on 4th Embodiment, and stamps an ID mark. It is a partial external view of the semiconductor wafer which shows the case where it arranges on the same right side on the basis of the edge part of a notch as a comparative example of 4th Embodiment, and marks an ID mark. 10 is a table showing the time required to imprint an ID mark on the semiconductor wafer shown in FIG. 9. It is a top view which shows the whole SOI wafer which concerns on 5th Embodiment. It is a fragmentary sectional view which shows the structure of the notch periphery of the SOI wafer shown in FIG. It is sectional drawing which shows a problem at the time of performing laser marking with respect to the SOI layer on a buried oxide film. It is a partial external view which shows the ID mark attached | subjected to the bevel part of the SOI wafer which concerns on the modification of 5th Embodiment. It is a top view which shows the whole 1st main surface of the semiconductor wafer which concerns on 6th Embodiment. FIG. 16 is a plan view in which a bevel portion in which a reference ID mark in FIG. 15 is formed is partially enlarged. FIG. 5 is an enlarged plan view showing a matrix type two-dimensional code including an L-shaped guide cell as an example of a reference ID mark. It is a top view of the whole semiconductor wafer concerning the modification 1 of 6th Embodiment. It is an external view of a semiconductor wafer when a reference ID mark is formed between crystal orientation lines perpendicular to each other according to Modification 1 of the sixth embodiment. It is a top view of the whole semiconductor wafer concerning the modification 2 of 6th Embodiment. It is the top view to which the outer peripheral part of the wafer in which the reference | standard ID mark was formed in FIG. 20 was expanded. It is a block diagram which shows the structure of the manufacturing apparatus of the semiconductor wafer which concerns on 7th Embodiment. It is a flowchart which shows the manufacturing method of the semiconductor wafer using the manufacturing apparatus of the semiconductor wafer shown in FIG. FIG. 24A is a plan view of a wafer showing the rotation angle of the wafer in the main manufacturing process (No. 1). FIG. 24B shows a Laue image displayed on a monitor in the main manufacturing process (No. 1). FIG. 25A is a plan view of a wafer showing the rotation angle of the wafer in the main manufacturing process (No. 2). FIG. 25B shows a Laue image displayed on the monitor in the main manufacturing process (No. 2). It is a top view of the wafer which shows the reference | standard ID mark attached | subjected on the wafer. It is a block diagram which shows the structure of the manufacturing apparatus of the semiconductor wafer which concerns on the modification 1 of 7th Embodiment. FIGS. 28A and 28B are block diagrams showing a marking system alignment function included in the semiconductor wafer manufacturing apparatus according to the seventh embodiment (No. 1). FIGS. 29A and 29B are block diagrams showing the alignment function of the marking system provided in the semiconductor wafer manufacturing apparatus according to the seventh embodiment (No. 2). It is a block diagram which shows the marking system which the manufacturing apparatus of the semiconductor wafer which concerns on the modification 3 of 7th Embodiment comprises. FIG. 31 is an external view showing a case where the reference ID mark formed on the side surface of the wafer by the marking system shown in FIG. 30 is a two-dimensional dot matrix. FIG. 31 is an external view showing a case where the reference ID mark formed on the side surface of the wafer by the marking system shown in FIG. 30 has a concave shape that has no particular meaning. It is a flowchart which shows the manufacturing method of the semiconductor wafer which concerns on 8th Embodiment. FIG. 34 is an external view of a wafer showing a method for processing an orientation determination region in the flowchart shown in FIG. 33. It is an external view which shows the recessed part (azimuth | direction determination area | region) after the direction determination area | region process in the flowchart shown in FIG. FIG. 36A shows a cross-sectional shape of the orientation determination region. FIG. 36B shows a planar shape of the orientation determination area. FIG. 37A is a perspective view showing the shape of the etch pit in which the (111) plane formed on the (100) plane and the equivalent crystal plane (second crystal plane) are exposed. FIG. 37B is a plan view of the etch pit. It is a fragmentary sectional view which shows the shape of the etch pit formed in the bottom face of the direction determination area. It is a block diagram which shows the apparatus which measures / evaluates the rotation angle dependence of the intensity | strength of the light reflected by the 2nd crystal plane in an etch pit, and provides orientation information to a wafer based on 8th Embodiment. It is a figure which shows the relationship between the position where the orientation determination area | region of a wafer is formed, the shape of an etch pit, and the shape of a scattered light intensity profile. It is the graph which compared 8th Embodiment and the case where a wafer orientation is detected by X-ray diffraction (comparative example) about the time required for the measurement of the crystal orientation of a wafer. It is a block diagram which shows the structure of the manufacturing apparatus of the semiconductor wafer which concerns on the modification 1 of 8th Embodiment. 43 are micrographs of crystal defects, FIG. 43 (a) shows crystal defects called crystal-originated particles (COP), and FIG. 43 (b) shows bulk micro-particles. It shows crystal defects called defects (Bulk Micro Defect: BMD). It is sectional drawing which shows the semiconductor wafer for demonstrating the operating principle of the manufacturing apparatus of the semiconductor wafer which concerns on 9th Embodiment. It is an external view which shows the structure of the manufacturing apparatus of the semiconductor wafer which concerns on 9th Embodiment. It is a flowchart which shows the manufacturing method of the semiconductor wafer using the manufacturing apparatus shown in FIG. It is a graph which shows the rotation angle dependence of a scattered light intensity | strength about a CZ wafer and an annealed wafer. It is a graph which compares "9th Embodiment" with a "comparative example" about the time required to determine the crystal orientation of a wafer. It is a flowchart for demonstrating the sample wafer which concerns on the experiment example of 10th Embodiment, and is extracted in the middle of the manufacturing process of a semiconductor wafer. It is an external view which shows the structure of the apparatus which concerns on the experiment example of 10th Embodiment. It is a graph which shows the relationship between the intensity | strength of the scattered light measured by the apparatus shown in FIG. 50, and the inclination-angle of a detector. It is a conceptual diagram which shows the relationship between the inclination-angle of a detector, and the light scattering by an etch pit. It is an external view which shows the manufacturing apparatus of the semiconductor wafer which concerns on 10th Embodiment. FIG. 54A is a cross-sectional view showing the configuration of the detection unit. FIG. 54B is a bottom view of the detection unit viewed from the wafer side. It is a graph which shows the rotation angle dependence of the scattered light evaluated by the computer (the 1). It is a graph which shows the rotation angle dependence of the scattered light evaluated by the computer (the 2). FIG. 57A is a schematic diagram showing the relationship between the parallel light flux and the distance between the light receiving elements (d _L ) and the distance between the wafer and the light receiving element (d _W ). FIG. 57B is a graph showing the optimum value of (d _L / d _W ) for improving the detection efficiency. It is a flowchart which shows the manufacturing method of the semiconductor wafer which concerns on 10th Embodiment. It is a graph which compares 10th Embodiment and its comparative example about the time which the crystal orientation measurement and marking of a wafer require. FIG. 60A is an external view showing the entire configuration of the SOI wafer according to the eleventh embodiment. FIG. 60B is a partially enlarged view showing the notch and the reference ID mark formed in the vicinity thereof. It is a flowchart which shows the manufacturing method of the base wafer which concerns on 11th Embodiment. FIG. 62A is an external view showing the entire configuration of the base wafer manufactured by the manufacturing method shown in FIG. FIG. 62B is a partially enlarged view showing the reference ID mark formed on the bevel portion of the base wafer. It is a flowchart which shows the manufacturing method of the wafer for SOI layers which has a buried oxide film and SOI layer based on 11th Embodiment. FIG. 64A is an external view showing the entire structure of the SOI layer wafer manufactured by the manufacturing method shown in FIG. FIG. 64B is a cross-sectional view of the SOI layer wafer. FIG. 67 is a flowchart showing a method for manufacturing an SOI wafer according to the tenth embodiment by bonding the base wafer shown in FIG. 62 (a) and the SOI layer wafer shown in FIG. 64 (a). FIG. 66A is an external view showing an overall configuration of an SOI wafer according to Modification 1 of the eleventh embodiment. FIG. 66B is a partially enlarged view showing a notch and a one-dimensional barcode formed in the vicinity thereof. FIG. 67A is an external view showing the entire configuration of the SOI wafer according to the second modification of the eleventh embodiment. FIG. 67B is a partially enlarged view showing the notch and the bevel portion of the base wafer in the vicinity thereof. It is a flowchart which shows the manufacturing method of the base wafer which has a notch based on the comparative example of 11th Embodiment. FIG. 69A is an external view showing the entire configuration of an SOI wafer according to a comparative example of the eleventh embodiment. FIG. 69B is a partially enlarged view showing marks formed on the outer periphery of the back surface of the SOI wafer.

Explanation of symbols

11, 16, 21, 26, 31, 34, 60, 71, 91, 121, 140 Wafer 12, 22, 27, 32, 35, 53a, 92, 163 Bevel part 13, 23, 36, 43, 169, 179 Notch 14, 24, 33a, 33b, 37-40, 44, 54, 162 ID mark 15, 25, 46 Product 17 Concavity and convexity 20 Dot mark 29, 95, 161, 167 First main surface (front surface)
30 Second main surface (back surface)
32a First bevel portion 32b Second bevel portions 41, 49, 171 Single crystal silicon layer (SOI layer)
42, 47, 160 Base wafer 45, 48, 172 Insulating layer (buried oxide film)
52, 173 SOI wafer 61, 63a-d, 64a-c, 65, 81, 83, 165, 175 Reference ID mark 62 L-shaped guide cell 72 Incident X-ray 74 Scattered X-ray 75, 82 X-ray detector 76 Monitor 77 , 105, 128, 150 Laser marker 79 Mirror 94, 94a-c Orientation determination area (recess)
96a-d Second crystal plane 97, 97a-c, 144 Etch pit 98, 127, 142, 154 Light source 101, 108, 143 Detector (detector)
102, 129, 145 Computer 103 First rotation driving unit 104 Second rotation driving unit 106 Database 122 Crystal defect 124 Scattered light detector 125, 141 Wafer stage 130, 146 Chamber 149 Detection unit 151 Parallel beam 152 Light receiving element 155 Light receiving surface 166 SOI layer wafer 168 Hydrogen ion implanted layer

Claims (12)

A wafer having a circular first main surface on which a semiconductor element is formed;
A bevel formed on the outer periphery of the wafer;
A reference ID mark indicating the crystal orientation of the wafer attached to the bevel portion;
The bevel portion includes a first bevel portion located on the first main surface side of the wafer, and a second bevel portion located on the second main surface side facing the first main surface,
The semiconductor wafer, wherein the reference ID mark is attached to each of the first bevel portion and the second bevel portion. A wafer having a circular first main surface on which a semiconductor element is formed;
A reference ID mark indicating the crystal orientation of the wafer attached on the wafer;
A recess formed on a part of the outer peripheral portion of the wafer and having a bottom surface inclined with respect to the first main surface;
Etch pits formed on the bottom surface of the recesses and remaining after the polishing of the wafer, wherein a second crystal plane different from the first crystal plane exposed on the first main surface is exposed. A semiconductor wafer characterized by Forming a concave portion on a part of the outer periphery of the wafer with a bottom surface inclined with respect to the first main surface of the wafer on which a semiconductor element is formed;
Etching in which an etching process having a different etching rate depending on crystal orientation is performed on the wafer, and a second crystal plane different from the first crystal plane exposed on the first main surface is exposed on the bottom surface of the recess. Form a pit,
Obtain the crystal orientation of the recess from the shape of the etch pit,
A method of manufacturing a semiconductor device, wherein a reference ID mark indicating a crystal orientation of the wafer is attached on the wafer. Obtaining the crystal orientation of the recess from the shape of the etch pit,
Irradiate the etch pit with light,
Evaluating the rotation angle dependence of the intensity of light reflected by the second crystal plane in the etch pit,
The method for manufacturing a semiconductor device according to claim 3, wherein the crystal orientation of the concave portion is determined from the rotation angle dependency. Determining the crystal orientation of the recess from the rotation angle dependency,
Registering in the database the data on the rotation angle dependence obtained for the etch pits formed over the entire circumference of the wafer,
The method of manufacturing a semiconductor device according to claim 4, wherein the crystal orientation of the recess is calculated by comparing with data in the database. A wafer stage;
A light source for irradiating light on the main surface of the wafer placed on the wafer stage;
The light scattered around by the etch pit formed on the main surface of the wafer, which has a ring-shaped light-receiving surface that surrounds the outer periphery of the light emission port and is inclined with respect to the light irradiation direction A light receiving element for measuring the intensity of
A computer for analyzing data relating to the rotation angle dependence of the intensity of the scattered light;
A mark stamper for attaching a reference ID mark indicating the crystal orientation of the wafer on the wafer;
An apparatus for manufacturing a semiconductor device, comprising: a chamber that covers at least the wafer stage, the wafer, the light source, and the light receiving element and blocks light entering from outside.   The semiconductor device manufacturing apparatus according to claim 6, wherein the light applied to the wafer is a parallel light flux. The semiconductor device manufacturing apparatus according to claim 6, wherein the light receiving surface of the light receiving element is inclined by 35 degrees with respect to an irradiation direction of the light.   8. The semiconductor device according to claim 7, wherein a distance between the center of the parallel light flux and the center of the light receiving surface is 0.7 with respect to a distance between the main surface of the wafer and the center of the light receiving surface. Manufacturing equipment. Slicing a single crystal ingot to form a wafer,
For the main surface of the wafer, in order to remove large waviness of the main surface, an etching process with different etching rates depending on the crystal orientation using an alkaline solution is performed,
Using etch pits formed on the main surface of the wafer by the etching process, measuring the crystal orientation of the wafer,
A reference ID mark indicating the crystal orientation of the wafer is attached on the wafer,
The method for producing a semiconductor wafer, wherein the etch pit is removed. Forming a bevel on the outer periphery of the base wafer having a circular outer periphery;
A reference ID mark for indicating the crystal orientation of the SOI layer wafer is attached to the bevel portion,
Forming a wafer for the SOI layer having a reference position indicating a crystal orientation;
Forming an insulating layer on the first main surface of the SOI layer wafer;
A method for manufacturing a semiconductor wafer, comprising: bonding the base wafer and the first main surface of the SOI layer wafer in a state where the reference ID mark and the reference position are aligned. Before bonding the base wafer and the first main surface of the SOI layer wafer, hydrogen ions are implanted into the first main surface of the SOI layer wafer, and the inside of the SOI layer wafer Forming a hydrogen ion implantation layer apart from the insulating layer;
12. The SOI layer wafer is wall-opened with the hydrogen ion implantation layer as a boundary after the base wafer and the first main surface of the SOI layer wafer are bonded together. Semiconductor wafer manufacturing method.