CN113176493A

CN113176493A - Chip test mainboard, test system and test method

Info

Publication number: CN113176493A
Application number: CN202110434677.6A
Authority: CN
Inventors: 陈辉
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-04-22
Filing date: 2021-04-22
Publication date: 2021-07-27
Anticipated expiration: 2041-04-22
Also published as: CN113176493B

Abstract

The disclosure provides a chip test mainboard, a test system and a test method. This chip test mainboard includes: a chip interface configured to connect a chip under test to a test motherboard; and a controller configured to interface with the chip, wherein the controller includes a network connection unit configured to perform network communication and a control unit configured to: receiving test data via a network connection unit; controlling to enable the tested chip to run test data; and acquiring test information generated by the operation test data of the tested chip, and sending the test information through the network connection unit.

Description

Chip test mainboard, test system and test method

Technical Field

The present disclosure relates to the field of processor technologies, and in particular, to a chip test motherboard, a test system, and a test method.

Background

As the size of transistors becomes smaller and smaller with the progress of manufacturing technology, the size of chips becomes larger and larger, and the energy efficiency and performance are also continuously improved. A System-on-a-Chip (SOC) is an integrated circuit with special functions, which includes complete circuitry and is embedded with software programs, and its design is usually very complex. This makes it necessary to go through a large number of bare machine tests before mass production of the SOC to ensure that the working conditions of each logic module inside the SOC are consistent with the original design. In order to test the functions of the SOC, a tester needs to prepare a large number of test cases corresponding to different test targets in advance, iteratively execute the test cases by controlling the tested SOC to obtain an execution result, and then perform an all-around test on the tested SOC based on the execution result.

Disclosure of Invention

Based on this, the present disclosure provides an automatic chip testing motherboard, a testing system and a testing method, which are used for performing an automatic test on a tested chip, thereby implementing a more convenient, concise and intelligent remote control automatic chip testing platform.

According to an aspect of the present disclosure, there is provided an automated chip testing motherboard, a chip interface configured to connect a chip under test to the testing motherboard; and a controller configured to interface with the chip, wherein the controller includes a network connection unit configured to perform network communication and a control unit configured to: receiving test data via a network connection unit; controlling to enable the tested chip to run the test data; and acquiring test information generated by the operation test data of the tested chip, and sending the test information through the network connection unit.

According to some embodiments of the disclosure, the controller further comprises a general purpose input output interface, the control unit further configured to: and outputting a reset signal to the tested chip through the universal input/output interface, wherein the reset signal is used for resetting the tested chip to start the tested chip, and the tested chip runs the test data after being started.

According to some embodiments of the disclosure, the controller further comprises an integrated circuit bus interface, the test motherboard further comprises a power management circuit interfaced with the controller and the chip, the control unit is further configured to: and outputting a power supply control signal to the tested chip through the integrated circuit bus interface and the power supply management circuit, wherein the power supply control signal is used for electrifying the tested chip to start the tested chip, and the tested chip runs the test data after being started. According to some embodiments of the present disclosure, an interface controller includes a transceiver transmitter through which the interface controller obtains test log information from a chip under test.

According to some embodiments of the present disclosure, the controller further includes a transceiver transmitter, through which the control unit acquires the test information from the chip under test.

According to some embodiments of the present disclosure, the testing main board further includes a first memory, wherein the first memory includes a serial peripheral interface, wherein the controlling unit controls the tested chip to run the test data includes: and writing the test data into the first memory through the serial peripheral interface so that the tested chip reads the test data from the first memory and runs the test data, wherein the first memory comprises a flash memory chip or a static random access memory.

According to some embodiments of the present disclosure, the test data includes at least one test case and test parameters corresponding to the at least one test case, and the test information includes operation information and result information generated by the test data when the tested chip operates.

According to another aspect of the present disclosure, there is also provided a chip testing system, including: at least one computing device; and one or more test motherboards, wherein each of the one or more test motherboards includes: the device comprises a chip interface configured to connect a chip to be tested to a test mainboard, and a controller connected with the chip interface, wherein the controller comprises a network connection unit and a control unit, and the control unit is configured to: connecting with at least one computing device via a network connection unit to receive test data from the computing device; controlling to enable the tested chip to run test data; and acquiring test information generated by the operation test data of the tested chip, and sending the test information to at least one computing device through the network connection unit.

According to some embodiments of the disclosure, at least one computing device is configured to: acquiring test data; transmitting the test data to a controller on one or more test mainboards, wherein the test data received by the one or more test mainboards can be the same or different; and receiving test information from the one or more test motherboards via the controller.

According to another aspect of the present disclosure, there is also provided a chip testing method, adapted to test a motherboard, the test motherboard including a chip interface for connecting a chip to be tested to the test motherboard, the method including: receiving test data via a network connection unit; controlling to enable the tested chip to run test data; and acquiring test information generated by the operation test data of the tested chip, and sending the test information through the network connection unit.

According to some embodiments of the disclosure, the method further comprises: and outputting a reset signal to the tested chip through the universal input/output interface, wherein the reset signal is used for resetting the tested chip to start the tested chip, and the tested chip runs the test data after being started.

According to some embodiments of the disclosure, the method further comprises: and outputting a power supply control signal to the chip to be tested through the integrated circuit bus interface and the power supply management circuit, wherein the power supply control signal is used for electrifying the chip to be tested to start the chip to be tested, and the chip to be tested runs the test data after being started.

According to some embodiments of the present disclosure, obtaining test information generated by running test data of a chip under test includes: and acquiring test information from the tested chip through the transceiver transmitter.

According to some embodiments of the present disclosure, the test motherboard further includes a first memory, wherein the controlling of the chip under test to run the test data includes: and writing the test data into the first memory through the serial peripheral interface so that the tested chip reads the test data from the first memory and runs the test data, wherein the first memory comprises a flash memory chip or a static random access memory.

According to still another aspect of the present disclosure, there is also provided a chip testing method, including: connecting with a test mainboard through a network; transmitting the test data to the test motherboard via a network; transmitting a chip starting signal to a test mainboard through a network, wherein the chip starting signal is used for starting a tested chip connected on the test mainboard, and the tested chip runs test data after being started; and receiving test information generated by the operation test data of the tested chip from the test mainboard through the network.

According to some embodiments of the present disclosure, connecting with a test motherboard via a network includes: the chip testing method is connected with a plurality of testing mainboards through a network, and further comprises the following steps: after first test data in the test data are transmitted to at least one test mainboard in the plurality of test mainboards through a network, recording the test state of the at least one test mainboard as a first state; and recording the test state of the at least one test mainboard as a second state after receiving first test information corresponding to the first test data from the at least one test mainboard via the network.

According to some embodiments of the present disclosure, transmitting test data to a test motherboard via a network includes: and transmitting second test data in the test data to the test mainboard recorded as the second state through the network.

According to some embodiments of the disclosure, the chip testing method further comprises: recording a time length that each of the plurality of test motherboards is in a first state within a predetermined time period, wherein transmitting the test data to the test motherboard via the network comprises: and determining the test mainboard with the shortest time length, and transmitting the third test data in the test data to the test mainboard with the shortest time length through the network.

In the automatic chip testing main board, the testing system and the testing method provided by the disclosure, the controller with the network connection function is arranged on the testing main board, so that the testing main board can be connected to the host computer through a network, and data transmission between the host computer and the testing main board is realized.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 shows a schematic block diagram of a test motherboard according to an embodiment of the present disclosure;

FIG. 2 shows another schematic block diagram of a test motherboard according to an embodiment of the present disclosure;

FIG. 3 shows a schematic block diagram of a test system according to an embodiment of the present disclosure;

FIG. 4 shows a schematic flow chart diagram of a chip testing method according to an embodiment of the present disclosure;

FIG. 5 shows a schematic flow chart diagram of another chip testing method according to an embodiment of the present disclosure;

FIG. 6A shows a flow chart of a host performing chip testing according to an embodiment of the present disclosure;

FIG. 6B shows a flow chart of chip testing by the interface controller according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without any inventive step, are intended to be within the scope of the present disclosure.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The chip test process typically includes the following steps: writing test data into a Read Only Memory (ROM) on a test motherboard, wherein the test data generally comprises test cases and test parameters; then, carrying out power-on starting or resetting restarting operation on the tested chip, so that the tested chip loads test data from the ROM and runs the test data; finally, test log information including the running process and results is collected through the debug port. The tester can evaluate the test condition of the chip based on the collected log information. For example, when the operation result of the tested chip for a certain test case is consistent with the expected result, it indicates that the tested chip can implement the function corresponding to the test case. In addition, in the case that the operation result does not meet the expected result, the tester can also analyze the tested chip based on log information such as the operation process, and design a new test case for further testing.

In the above-described test flow, writing test data into the ROM, resetting/restarting the chip, and the like, originally needs to be manually completed by a tester. In order to improve the testing efficiency and avoid manual operation as much as possible, a method for automatically testing a chip is provided. The core idea is to introduce a computer host into a test process, and control the whole test flow by using a program and a script on the host, thereby achieving the purpose of test automation.

In the related art test method, the host and the test motherboard may be connected through a Peripheral Component Interconnect (PCI) bus. For example, the PCI interface controller is connected to the host through a PCI bus, thereby converting the test motherboard into a PCI card that is inserted into a PCI slot of the host. However, although the closed-loop process of automatic testing can be realized based on the PCI interface controller, each test motherboard needs to be configured with a host to operate with the host, which results in waste of hardware resources. On the other hand, the test program and the script need to be logged in each host computer to run respectively, and the test data on each test mainboard needs to be collected respectively, which inevitably reduces the test efficiency.

Based on this, the present disclosure provides a chip testing motherboard, a testing system and a testing method, which are used for automatically testing a tested chip, thereby implementing a more convenient, concise and intelligent remote control automatic chip testing platform. On the test mainboard according to the embodiment of the present disclosure, a processor with a network function is arranged as a controller, for example, the controller may be implemented as a network interface controller, on one hand, the controller may implement communication with a computing device such as a host, and on the other hand, the controller may also control a memory and a chip under test on the test mainboard, and implement functions such as writing of a test case, starting of the chip under test, and collecting of test information. Therefore, in the test system composed of the host, the tested chip and the controller, the controller plays a role of a bridge, and the host, the controller and the tested chip form a component of the whole remote automatic test system together to form a closed loop of automatic test.

When the chip is required to be tested, the host can be connected to the controller arranged on the test mainboard through the network, so that the test progress of the test mainboard can be remotely controlled, and the host can simultaneously control a plurality of test mainboards through the network, namely, the automatic chip test platform for controlling the plurality of test mainboards by the host is realized, which is favorable for saving test hardware resources and improving test efficiency. In addition, the automatic chip testing platform also enables the host computer to more intelligently schedule a plurality of testing main boards, and further beneficial effects such as intelligent distribution of test cases, load balancing and the like are realized. In addition, it is understood that a plurality of hosts may be further included in the test system, which is not limited herein.

The test motherboard, the test system and the test method provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic block diagram of an automated chip testing motherboard according to an embodiment of the disclosure. As shown in FIG. 1, the test motherboard 110 may include a chip interface for connecting a chip under test to the test motherboard, shown in FIG. 1 as chip under test 112. The structure and type of the chip interface are matched with the chip to be tested, and various appropriate structures can be selected, which is not limited in this embodiment of the disclosure. For example, after a chip is manufactured, the chip may be connected to a test motherboard through a chip interface on the test motherboard to implement a series of test processes for the chip. After the test is completed, the connection between the chip and the chip interface may be broken. The test motherboard may then be connected to another chip, for example, via a chip interface, to implement a test procedure for the other chip. In the present disclosure, a chip under test may be understood as a chip that is currently connected to and tested on a test motherboard. In addition, the present disclosure does not limit the specific connection manner between the chip interface and the chip under test.

The test motherboard according to an embodiment of the present disclosure may further include a controller configured to interface with the chip. The controller may be implemented as the network interface controller 111 shown in fig. 1.

Next, as shown in fig. 1, the test main board 110 may further include a first memory 113, which may be, for example, a Read Only Memory (ROM) for storing test data used for performing a chip test. For example, the test data may include at least one test case and test parameters corresponding to the test case. Generally, the test data includes a large number of test cases and test parameters corresponding to the test cases, so as to achieve sufficient verification for the chip. The first memory 113 may be connected to the network interface controller 111 shown in fig. 1. It is understood that ROM herein represents a generalized read-only memory concept, for example, a commonly used Flash with Serial Peripheral Interface (SPI) can be said to be a kind of ROM, and the Flash can be subjected to data erasing and writing operations by commands. Thus, a read only memory ROM as referred to herein refers to a memory in which data cannot be written randomly, but can be written by a specific command. For example, test data may be written by a command.

In one aspect, the network interface controller 111 may include a network connection unit for making a network connection with the host to receive the test data and the control command from the host according to an embodiment of the present disclosure. The access means of the network may be wired or wireless. As an implementation, in case of a wired connection, the network interface controller 111 may be implemented as a Microcontroller Unit (MCU) having an ethernet function, wherein the MCU is a small system-on-chip integrating a central processing Unit, a memory and an input/output device on one chip. As another implementation, in case of wireless connection, the network interface controller 111 may also be implemented as an MCU having wireless network functions, such as some kind of WIFI controller. In this implementation, the MCU is connected to the host through a wireless network. Hereinafter, the network interface controller 111 may be described as a MCU as a specific example, and it is understood that the implementation manner of the interface controller 111 is not limited thereto, for example, the network interface controller 111 may also be implemented as various other processors that can implement control functions and network functions.

On the other hand, the network interface controller 111 further includes a control unit, which may be configured to control the first memory 113 and the chip under test 112 connected to the test motherboard 110. In particular, after receiving test data from the host, the control unit may be configured to: and controlling to enable the tested chip to run the test data. After the tested chip runs the test data, the control unit of the network interface controller 111 may be configured to obtain test information generated by the tested chip running the test data, and send the test information via the network, for example, transmit the test information to the host computer via the network. For example, the test information may also be test log information, which includes operation information and result information generated by the operation of the test data by the tested chip.

According to some embodiments of the present disclosure, the first memory 113 may include a serial peripheral interface, and thus the controlling unit controls the tested chip to run the test data includes: and writing the test data into the first memory through the serial peripheral interface so that the tested chip reads the test data from the first memory and runs the test data.

As shown in fig. 1, the test motherboard 110 may further include a second memory 114 configured to store data associated with the chip under test running the test data. For example, the second memory 114 is connected to the chip under test interface, and for example, the second memory 114 may also be connected to the chip under test. For example, the second Memory 114 may be a Random Access Memory (RAM), and a chip under test accessing the test motherboard may perform read and write operations on the RAM.

In the solution according to the disclosure, the above-described functions performed by the control unit can be implemented by program code, such as by a tester. As an example, the program code may be implemented in the form of Firmware (Firmware), so that the network interface controller 111 may implement the control functions involved in the above-described test procedure by loading and running the Firmware therein, thereby implementing an automated chip test procedure. Therefore, testers only need to write and debug the required firmware and load the firmware into the network interface controllers 111 of the test mainboards, the test process of one or more test mainboards can be realized, the labor cost can be saved, and the test efficiency is improved.

According to the automatic test mainboard provided by the disclosure, in terms of hardware design, a controller with a network connection function and a control function, for example, the MCU with an ethernet function is added, so that the test mainboard can be used as a network node controlled by a host as a whole, and after receiving test data, the test mainboard can automatically perform a test procedure (such as writing a test case and collecting a test log) without manual operation of a tester, thereby implementing an automatic chip test procedure.

Fig. 2 shows another schematic block diagram of a test motherboard according to an embodiment of the present disclosure, and in fig. 2, the MCU is implemented as a controller, and specifically shows various structural components required by the MCU to implement a test process.

According to some embodiments of the present disclosure, as shown in fig. 2, the test motherboard 210 is arranged with an MCU211, and specifically, the MCU211 includes a network connection unit 2111 for network connection with a host. As an example, the network connection unit 2111 may be a WIFI module to enable wireless communication with a host. The MCU211 may receive the test data via the network connection unit 2111, and after receiving the test data, the MCU211 may perform a subsequent test control step. Further, the network connection unit 2111 may also be used for receiving test related instructions. For example, after the MCU211 receives the test data, the test data may be written into the ROM 213, and then the MCU211 does not directly perform a subsequent operation, such as starting up the chip under test 212, but after receiving a start instruction from the host, the MCU211 performs a process of starting up the chip under test 212, whereby the host may control the test process in a manner of outputting the instruction.

According to the embodiments of the present disclosure, the first memory may select various suitable memories. For example, the memory may be a non-volatile storage device, for example, the memory may be Flash, and the MCU may directly perform data erasing and writing operations on the memory. Because the memory is nonvolatile, data cannot be lost after power failure. According to an embodiment of the present disclosure, the first memory may include a Serial Peripheral Interface (SPI). For example, as one implementation, the first memory may be a flash memory chip with SPI; as another implementation, the first Memory may also be a Static Random-Access Memory (SRAM). For example, when the data amount of the test data is small, the SRAM may be used instead of the ROM, and the data in the SRAM is updated much faster than the data in the ROM, so that the overall test speed can be greatly increased.

Accordingly, an SPI is also configured in the MCU211 for connection with the first memory. The SPI is a high-speed, full-duplex, synchronous communication bus commonly used in the MCU. Via the SPI, the MCU may write the received test data to the first memory.

According to some embodiments of the present disclosure, the controller may further include a General-Purpose Input/Output (GPIO) interface. For example, the MCU may be configured to output a Reset Signal (RST) to the chip under test 212 through the GPIO interface, the reset signal being used to reset the chip under test to enable the chip under test to boot, wherein the chip under test automatically reads the test data from the first memory and runs the test data after booting. For example, the GPIO interface may pull down or pull up the level of each pin of the chip under test 212 based on a reset signal to implement a chip reset, after which the chip under test will read the stored test data from the ROM 213.

According to further embodiments of the present disclosure, the controller may further include an Inter-Integrated Circuit bus (I2C) interface, the I2C interface for outputting the power control signal. In this embodiment, the test motherboard 310 also includes power management circuitry that interfaces with the controller and chip. As an implementation, the Power Management circuit may be implemented as a separate chip, for example, a Power Management chip (PMIC) that is used to provide Power to other chips (such as the chip under test 212). For example, the MCU outputs a power control signal through the I2C interface to control the PMIC to supply power to the chip under test. The chip under test will automatically read the test data from the first memory and run the test data after receiving power. As another implementation, the power management circuit may be implemented as a non-independent power management circuit, for example, as a power management unit designed to be included inside the MCU, which is not limited herein.

It is understood that the above I2C interface and GPIO interface may each separately implement the start-up control for the chip under test, so that the chip under test reads the test data stored in the first memory and runs the test data. As an example, the MCU may be designed to include only one of the above I2C interface or GPIO interface for controlling the implementation of the start-up operation of the chip under test. As other examples, the MCU may also be designed to include both interfaces. Based on the two interfaces, the MCU can realize power supply, reset and other key signals of the tested chip, and accordingly the testing process of the tested chip is controlled.

According to some embodiments of the disclosure, the controller may further comprise a transceiver transmitter. As an example, the transceiver Transmitter may be a Universal Asynchronous Receiver Transmitter/Transmitter (UART), wherein the UART may output the debug information as a debug port in the embedded device. For example, the MCU obtains test log information from the chip under test through the UART, where the test log information includes operation information and result information generated by the chip under test operating test data.

After receiving the test log information, the MCU may also be configured to send the test log information via the network connection unit 2111, e.g., to transmit the test log information to the host computer via the network for test analysis by the tester.

It will be appreciated that only a schematic block diagram of the MCU is shown in fig. 2, which may also be designed to include other required functional modules or components for the purpose of automated chip testing. For example, the MCU may further be connected to a memory for storing log information collected from the chip under test, and after detecting that all test cases are completed by the chip under test, the MCU sends the collected log information to the host.

The controller provided according to the embodiment of the disclosure is a core component for connecting a computer host and a test mainboard. For example, the controller is an MCU having a network connection function so that the host communicates with the test motherboard through a standard network protocol. The MCU according to the embodiment of the present disclosure has a control capability for the ROM and the chip under test in addition to a network function. For example, the MCU is connected with the ROM and the chip to be tested through the UART, I2C, GPIO and SPI interfaces as described above.

In the embodiment according to the disclosure, the test mainboard is networked and is directly connected with the host computer through the network, so that the consumption of intermediate hardware resources is reduced, and the efficiency and flexibility of chip test can be improved, thereby realizing more convenient, concise and intelligent automatic chip test mainboard.

According to another aspect of the present disclosure, there is also provided an automated chip testing system including at least one computing device and one or more test motherboards.

For a computing device, it will be understood by those skilled in the art that the computing device may be a host computer, or may be any device with processing capabilities, such as a notebook computer, a tablet computer, etc. Such a computer device may be a general purpose computer device or a special purpose computer device. Such a computer device may be implemented by hardware devices, software programs, firmware, and combinations thereof. For example, where the computing device is a host, it may be a single host or a group of hosts. The group of hosts may be centralized or distributed, such as a distributed system. Furthermore, the computing device may also be implemented as a virtual host, without limitation.

The computer device may include a processor for executing program instructions. The computer device may also include an internal communication bus, various forms of program storage units and data storage units, such as a hard disk, Read Only Memory (ROM), Random Access Memory (RAM), which can be used to store various data files for processing and/or communication by the computer, and possibly program instructions for execution by the processor. The computing device may also include an input/output component that supports input/output data flow between the computing device and other components. The computer device may also send and receive information and data via the communication port, for example to download the required test data from a network.

For each of the one or more test motherboards, it may include: the test system comprises a chip interface configured to connect a chip to be tested to the test mainboard, and a controller connected with the chip interface, wherein the controller can comprise a network connection unit and a control unit.

FIG. 3 shows a schematic block diagram of a test system according to an embodiment of the present disclosure. The structure of the test system provided in accordance with implementations of the present disclosure and its functions will be described in detail below in conjunction with fig. 3.

As shown in fig. 3, the automated chip testing system 300 may include one or more test motherboards (fig. 3 is schematically illustrated as including a plurality of

test motherboards

310, 330, 340, 350) and a host 320, wherein the host 320 is the above-mentioned computing device, which may be one or more, and only one host 320 is shown in fig. 3. The structure and connection manner of each of the at least one test motherboard are similar, for example, the test motherboard may specifically have the structure described above in conjunction with fig. 1 and 2 and can implement the above functions, and the description is not repeated here.

According to some embodiments of the present disclosure, the host 320 may be configured to perform the following steps: acquiring test data; transmitting the test data to a controller on one or more test motherboards; and receiving test information from the one or more test motherboards via the controller. In an aspect according to an embodiment of the present disclosure, the above functions and steps performed by the host 320 may be implemented as program code, for example, by a tester, and the host executes the program code to implement the above functions. For example, a control program, so that the host 320 implements the above-mentioned test control function by running the control program, thereby implementing an automated chip test process.

For example, the program code can be implemented in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional procedural programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may run entirely on the host computer, as a stand-alone software package, or partially on the host computer.

The control program on the host 320 may act as the actual controller in the chip test process. The control program can continuously and repeatedly execute tasks such as downloading of test cases, test running, collection and storage of test logs and the like according to the setting of a tester. And when all the test cases specified by the tester are executed, ending the control program and quitting.

Further, the host 320 may be connected to a plurality of test motherboards at the same time, and perform respective test control, where the plurality of test motherboards may serve as a resource pool of the host 320. Through corresponding algorithms and programs, the host can more intelligently schedule and utilize the test mainboard resources, and realize functions such as intelligent case distribution, load balancing and the like. For example, the test data received by one or more test motherboards may be the same or different. For example, the host 320, as a controller, can simultaneously control a plurality of chips under test to run different test cases, thereby improving the test efficiency of the chips under test. In addition, based on the testing time required by different test cases, the host 320 may also allocate a new test case to the tested chip with shorter time, so as to achieve the effect of intelligently allocating the test cases.

By using the automatic test system provided by the embodiment of the disclosure, a large number of test cases can be automatically, remotely and uninterruptedly executed on a plurality of test motherboards only by presetting a control program on the host, so that the efficiency and flexibility of chip testing are improved, and in addition, the host can network the test motherboards which are in network connection with the host, so that the consumption of intermediate hardware resources is reduced. In the test system, a plurality of test mainboards can be abstracted into a resource pool on the whole for the host to perform operations such as flexible scheduling, case distribution, load balancing and the like, so as to improve the intelligent and automatic degree of the whole test system.

According to another aspect of the disclosure, an automatic chip testing method is also provided, which is suitable for a controller for controlling chip testing. The controller may be arranged on the test motherboard as shown in fig. 1 and embodied as an MCU as shown in fig. 2.

Fig. 4 shows a schematic flowchart of a chip testing method according to an embodiment of the present disclosure, and as shown in fig. 4, the chip testing method executed by the controller may include steps S1101-S1103. Specifically, in step S1101, test data is received via the network connection unit. For example, a connection may be made with the host via the network connection unit to receive test data from the host. According to the embodiment of the disclosure, the test data comprises at least one test case and test parameters corresponding to the at least one test case.

In step S1102, control causes the chip under test to run test data. As an example, the test motherboard may include the first memory described above, wherein step S1102 may include writing the test data into the first memory through the serial peripheral interface, so that the chip under test reads the test data from the first memory and runs the test data. For example, the first memory may be a ROM 213 as shown in fig. 2, and the controller may implement a write operation of test data. According to some embodiments of the present disclosure, the controller may write the test data to the first memory through the above-mentioned Serial Peripheral Interface (SPI), wherein the first memory may be a flash memory chip having the SPI or a static random access memory.

Writing the test data to the first memory may cause the chip under test to read the test data from the first memory and run the test data. During the process of running test data by the tested chip, the generated corresponding running information and the final result information are recorded as test log information, and based on the test log information, a tester can analyze whether the tested chip meets design expectations or not.

As an example, chip testing may include functional performance testing and reliability testing. For example, for a functional performance test, the test data may include an excitation signal to be applied to an input pin of the chip under test, while monitoring an output pin of the chip under test, and collecting an output signal thereof as a test result, and a tester may determine, based on the output signal, whether the output signal is in accordance with an expectation, and if so, it indicates that the chip under test may implement a function corresponding to the excitation signal. For another example, for reliability testing, the chip under test may be stressed to enhance or accelerate potential failure mechanisms, and the applied stress may include, for example, temperature, humidity, voltage, current, and the like, such as subjecting components of the chip under test to transitions between extremely high and low temperatures, and testing whether the test chip after temperature cycling can still perform the intended function.

According to some embodiments of the present disclosure, for example, the chip under test may be caused to read the test data from the first memory by activating the chip under test. As an example, starting the chip under test may include: and outputting a reset signal to the tested chip through the universal input/output interface of the controller, wherein the reset signal is used for resetting the tested chip to start the tested chip, and the tested chip automatically reads the test data from the first memory and runs the test data after starting. As another example, activating the chip under test may include: outputting, by an integrated circuit bus interface of the controller, a power control signal to the chip under test via a power management circuit (such as the PMIC shown in fig. 2), the power control signal being used to power up the chip under test to start up the chip under test, wherein the chip under test automatically reads test data from the first memory and runs the test data after start-up.

In step S1103, test information generated by running the test data on the chip under test is obtained, and the test information is sent via the network connection unit, for example, the test information is transmitted to the host. According to some embodiments of the present disclosure, the controller may obtain the test log information from the chip under test through the transceiver transmitter. For example, the test log information includes operation information and result information generated by the operation of the test data by the tested chip.

According to another aspect of the disclosure, an automated chip testing method is also provided, which is suitable for a host computer performing chip testing control. The host can be connected with the controller on the test mainboard through a network as shown in fig. 3, so as to realize the self-adaptive control of the chip test.

Fig. 5 shows a schematic flowchart of another chip testing method according to an embodiment of the present disclosure, and the flowchart shown in fig. 5 corresponds to the steps executed by the host 320 in fig. 3, and specifically includes steps S1201-S1204.

First, in step S1201, a test motherboard is connected via a network. For example, the tester may download and transmit test data required for the test to the host computer. The test data includes at least one test case and test parameters corresponding to the test case. According to some embodiments of the present disclosure, a host may be connected with a plurality of test motherboards via a network to implement test control for the plurality of test motherboards.

Next, in step S1202, the test data is transmitted to a controller on the test motherboard via a network, for example, the controller may be the MCU211 shown in fig. 2. After receiving the test data, the MCU211 may store the test data to a first memory on the test motherboard, such as the ROM 213 in fig. 2.

In step S1203, a chip start signal is transmitted to the controller via the network, where the chip start signal is used for enabling the controller to start the tested chip connected on the test motherboard. For example, after receiving the chip start signal, the MCU211 may reset the chip under test via the GPIO interface or power up the chip under test via the I2C interface, thereby starting the chip under test. According to the embodiment of the disclosure, the chip under test can automatically read the test data from the first memory and run the test data after being started.

Finally, in step S1204, test information generated by running test data on the chip under test is received from the controller.

In the chip testing method according to the present disclosure, a plurality of test motherboards connected to a host may serve as a resource pool of the host. Through corresponding algorithms and programs, the host can more intelligently schedule and utilize the test mainboard resources, and realize functions such as intelligent case distribution, load balancing and the like.

According to some embodiments of the present disclosure, the chip testing method may further include: after first test data in the test data are transmitted to at least one test mainboard in the plurality of test mainboards through a network, recording the test state of the at least one test mainboard as a first state; and recording the test state of the at least one test mainboard as a second state after receiving first test information corresponding to the first test data from the at least one test mainboard via the network.

For example, the first state indicates that the chip under test connected to the test motherboard is currently in a "busy" state, i.e., running test data, and the second state indicates that the chip under test connected to the test motherboard is currently in an "idle" state, i.e., not running test data.

Accordingly, the transmitting the test data to the test motherboard via the network may include: and transmitting second test data in the test data to the test mainboard recorded as the second state through the network. For example, the second test data represents a current test routine that currently needs to be transferred to the test motherboard, and the first test data represents a previous test routine that has been transferred to the test motherboard before the second test data. For the current test routine, the host computer may first determine a test motherboard in an "idle" state among the plurality of test motherboards, and transmit the current test routine to the test motherboard in the "idle" state, thereby improving the test resource utilization rate and the test efficiency, and avoiding the waste of resources caused by sending the current test routine to the test motherboard currently running the previous test routine. Further, in a case where it is determined that there is no test motherboard in the "idle" state among the plurality of test motherboards, that is, each test motherboard is in the "busy" state, the host stops sending the current test routine to the test motherboard.

According to some embodiments of the present disclosure, the chip testing method may further include: recording a time length that each of the plurality of test motherboards is in a first state within a predetermined time period, wherein transmitting the test data to the test motherboard via the network comprises: and determining the test mainboard with the shortest time length, and transmitting the third test data in the test data to the test mainboard with the shortest time length through the network.

As an example, the predetermined time period may be a time period such as 5 hours or 1 day. For example, the host computer may record the accumulated length of time that each test motherboard is in the "busy" state within 5 hours, and before transmitting test data to the test motherboard, the host computer may first determine the test motherboard with the shortest busy length and transmit the current test routine to the test motherboard with the shortest busy length via the network. As another implementation manner, the host may also record a time length that each of the plurality of test motherboards is in the second state within a predetermined time period, and transmit the third test data to the test motherboard with the longest time length via the network. Namely, the current test routine is transmitted to the test mainboard with the longest idle time length. Therefore, the host can control the resource consumption of each test mainboard to be relatively balanced.

By utilizing the chip testing method provided by the embodiment of the disclosure, a large number of testing routines can be automatically, remotely and uninterruptedly executed on a plurality of testing main boards through the control program on the host, so that the efficiency and the flexibility of chip testing are improved, in addition, the host can network the testing main boards which are in network connection with the host, the consumption of intermediate hardware resources is reduced, the plurality of testing main boards can be abstracted into a resource pool on the whole, and the host can perform operations such as flexible scheduling, case allocation, load balancing and the like, so that the intelligent and automatic degrees of the whole testing system are improved.

As an example, fig. 6A shows a flowchart of a host performing chip testing according to an embodiment of the present disclosure, as shown in fig. 6A, for example, the host 320 may first determine whether a test motherboard is connected, in case of determining connection, may load a user script, and determine whether a last test case is currently completed, if the test case is a case that is not tested, the host may download the test case and test parameters to, for example, an MCU via a network, and send, for example, a start signal to the MCU, so that the MCU controls execution of a start chip, and after the start, the chip under test will read test data stored in a ROM and execute a corresponding processing procedure. The host may then receive the collected test logs from the test motherboard. As an example, the flow shown in fig. 6A may be implemented by a control program loaded into a host, and the control program on the host may be an actual controller of the chip test flow. The control program can be set according to the requirements of users so as to continuously and repeatedly execute tasks of downloading of test cases, initializing parameters, starting test operation, collecting and storing test logs and the like. After all test cases, such as specified by the tester, have been executed, the control routine ends and exits.

As an example, fig. 6B shows a flowchart of a chip test performed by a controller according to an embodiment of the present disclosure, and as shown in fig. 6B, such as the MCU211, may first perform steps of hardware self-test and initialization, running a network protocol stack, and communicating with a host. Under the condition that the MCU is determined to be connected with the host, the MCU can analyze the command received from the host, and for the effective command, the MCU can sequentially execute the steps of writing the test case into the ROM, writing the test parameter into the ROM, starting the chip, collecting the test log and the like. In addition, the MCU also sends the test log to the host via the network. As an example, the flow shown in fig. 6B may be implemented by a firmware program loaded into the MCU, where the firmware program is an executor of the whole chip test process, and its core task is to receive a command from the host and execute a corresponding operation according to the command.

The automated chip testing process provided in accordance with the present disclosure may be implemented through the steps shown in fig. 6A and 6B, respectively.

According to the chip testing method provided by the embodiment of the disclosure, the tested chip is automatically tested, so that a more convenient, concise and intelligent remote control automatic chip testing process is realized.

Those skilled in the art will appreciate that the disclosure of the present disclosure is susceptible to numerous variations and modifications. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.

Further, while the present disclosure makes various references to certain elements of a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.

Flow charts are used in this disclosure to illustrate steps of methods according to embodiments of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Also, other operations may be added to the processes.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing relevant hardware, and the program may be stored in a computer readable storage medium, such as a read only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A chip test motherboard comprising:

a chip interface configured to connect a chip under test to the test motherboard; and

a controller configured to interface with the chip, wherein the controller includes a network connection unit configured to perform network communication and a control unit configured to:

receiving test data via the network connection unit;

controlling the tested chip to run the test data; and

and acquiring test information generated by the tested chip running the test data, and sending the test information through the network connection unit.

2. The test motherboard of claim 1 wherein the controller further comprises a general purpose input output interface, the control unit further configured to:

outputting a reset signal to the tested chip through the universal input/output interface, wherein the reset signal is used for resetting the tested chip to start the tested chip, and the tested chip runs the test data after being started.

3. The test motherboard of claim 1 wherein the controller further comprises an integrated circuit bus interface, the test motherboard further comprising power management circuitry interfaced with the controller and the chip, the control unit further configured to:

and outputting a power supply control signal to the tested chip through the integrated circuit bus interface via the power supply management circuit, wherein the power supply control signal is used for electrifying the tested chip to start the tested chip, and the tested chip runs the test data after being started.

4. The test motherboard of claim 1 wherein said controller further comprises a transceiver transmitter,

and the control unit acquires the test information from the chip to be tested through the transceiver transmitter.

5. The test motherboard of claim 1, further comprising a first memory, wherein the first memory comprises a serial peripheral interface, wherein the control unit to control the chip under test to run the test data comprises:

and writing the test data into the first memory through the serial peripheral interface so that the tested chip reads the test data from the first memory and runs the test data, wherein the first memory comprises a flash memory chip or a static random access memory.

6. The test motherboard of claim 1 wherein the test data comprises at least one test case and test parameters corresponding to the at least one test case,

the test information comprises operation information and result information generated by the tested chip operating the test data.

7. A chip test system, comprising:

at least one computing device; and

one or more test motherboards, wherein each of the one or more test motherboards includes: a chip interface configured to connect a chip under test to the test motherboard, a controller connected to the chip interface, wherein the controller includes a network connection unit and a control unit, the control unit configured to:

connecting with the at least one computing device via the network connection unit to receive test data from the computing device;

controlling the tested chip to run the test data; and

and acquiring test information generated by the tested chip running the test data, and sending the test information to the at least one computing device through the network connection unit.

8. The test system of claim 7, wherein the at least one computing device is configured to:

acquiring the test data;

transmitting the test data to the controller on the one or more test motherboards, wherein the test data received by the one or more test motherboards may be the same or different; and

receiving, via the controller, the test information from the one or more test motherboards.

9. A chip testing method is suitable for testing a mainboard, wherein the testing mainboard comprises a chip interface for connecting a chip to be tested to the testing mainboard, and the method comprises the following steps:

receiving test data via a network connection unit;

controlling the tested chip to run the test data; and

10. The method of claim 9, further comprising:

outputting a reset signal to the tested chip through a general input/output interface, wherein the reset signal is used for resetting the tested chip to start the tested chip, and the tested chip runs the test data after being started.

11. The method of claim 9, further comprising:

and outputting a power supply control signal to the tested chip through a power supply management circuit through an integrated circuit bus interface, wherein the power supply control signal is used for electrifying the tested chip to start the tested chip, and the tested chip runs the test data after being started.

12. The method of claim 9, wherein the obtaining test information generated by the chip under test running the test data comprises:

and acquiring the test information from the tested chip through a transceiver transmitter.

13. The method of claim 9, wherein the test motherboard further comprises a first memory, wherein the controlling causing the chip under test to run the test data comprises:

and writing the test data into the first memory through a serial peripheral interface so that the tested chip reads the test data from the first memory and runs the test data, wherein the first memory comprises a flash memory chip or a static random access memory.

14. The method of claim 9, wherein the test data includes at least one test case and test parameters corresponding to the at least one test case,

15. A method of chip testing, comprising:

connecting with a test mainboard through a network;

transmitting test data to the test motherboard via the network;

transmitting a chip starting signal to the test mainboard through the network, wherein the chip starting signal is used for starting a tested chip connected on the test mainboard, and the tested chip runs the test data after being started; and

and receiving test information generated by the tested chip running the test data from the test mainboard through the network.

16. The chip testing method according to claim 15, wherein the connecting with the test motherboard via the network comprises: connecting with a plurality of test motherboards via a network, the method further comprising:

after first test data in the test data are transmitted to at least one test mainboard in the plurality of test mainboards through the network, recording the test state of the at least one test mainboard as a first state;

and recording the test state of the at least one test mainboard as a second state after receiving first test information corresponding to the first test data from the at least one test mainboard via the network.

17. The chip testing method according to claim 16, wherein the transmitting test data to the test motherboard via the network comprises:

and transmitting second test data in the test data to the test mainboard recorded as the second state through the network.

18. The chip testing method according to claim 16, further comprising:

recording a length of time that each of the plurality of test motherboards is in the first state within a predetermined period of time, wherein the transmitting test data to the test motherboard via the network comprises:

and determining the test mainboard with the shortest time length, and transmitting the third test data in the test data to the test mainboard with the shortest time length through the network.