CN113097080A - Fan-out packaging method for wafer-level chip - Google Patents
Fan-out packaging method for wafer-level chip Download PDFInfo
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- CN113097080A CN113097080A CN202110310266.6A CN202110310266A CN113097080A CN 113097080 A CN113097080 A CN 113097080A CN 202110310266 A CN202110310266 A CN 202110310266A CN 113097080 A CN113097080 A CN 113097080A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70383—Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
Abstract
The invention discloses a wafer-level chip fan-out packaging method, which comprises the following steps: providing a chip unit, wherein the chip unit comprises a bare chip and a rewiring layer; the laser direct writing photoetching equipment acquires the actual position information of the bare chip; the laser direct-writing photoetching equipment adjusts the original wiring pattern of the digital mask plate according to the actual position information; the laser direct-writing photoetching equipment carries out exposure treatment on the rewiring layer according to the adjusted wiring pattern; and injecting metal into the exposed wiring pattern to form a rewiring line, wherein the rewiring line is used for connecting the bare chip with an external bonding pad, and/or the rewiring line is used for interconnecting the bare chip. According to the wafer level chip fan-out packaging method, accurate butt joint with a rewiring circuit can be realized after the position of a bare chip is deviated, and the chip packaging yield is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip fan-out packaging method.
Background
In the related art, the wafer level fan-out packaging technology includes a system level packaging technology, a board level packaging technology, a module packaging of a power device, and the like. The chip packaging structure integrates chips with different substrates and different functions, achieves stacking and interconnection of the chips in a small area, greatly reduces the packaging size of the chips, increases the reliability of the chips, and has wide application prospect and development space.
In the fan-out packaging process of the wafer level chip, the placement position of the chip is predetermined, and in order to connect the chip with another chip or an external bonding pad, a connecting line between the chip and the other chip or between the chip and the external bonding pad needs to be designed. Conventionally, a chip is transferred to a predetermined position and then exposed by a mask to form a connection circuit pattern, so that the connection circuit accurately connects the chip to another chip or accurately connects the chip to an external pad. The pattern or shape of the mask is customized according to the designed connecting circuit, namely the pattern of the mask is fixed. However, in actual operation, due to the possibility of deviation, expansion and contraction and the like during the chip transfer process, the actual placement position of the chip after the chip transfer often has a certain degree of deviation relative to the predetermined placement position, so that the connection circuit pattern obtained by exposure according to the pattern of the mask cannot be accurately butted with the chip, and the chip cannot be accurately connected with another chip or the chip and the external bonding pad.
Moreover, the above-mentioned problems are difficult to solve using the conventional step-and-repeat projection exposure machine.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, one object of the present invention is to provide a wafer level chip fan-out packaging method, which can realize accurate butt joint with a rewiring line after the position of a bare chip is shifted, thereby improving the chip packaging yield.
The wafer level chip fan-out packaging method provided by the embodiment of the invention comprises the following steps: providing a chip unit, wherein the chip unit comprises a bare chip and a rewiring layer; the laser direct writing photoetching equipment acquires the actual position information of the bare chip; the laser direct-writing photoetching equipment adjusts the original wiring pattern of the digital mask plate according to the actual position information; the laser direct-writing photoetching equipment carries out exposure treatment on the rewiring layer according to the adjusted wiring pattern; and injecting metal into the exposed wiring pattern to form a rewiring line, wherein the rewiring line is used for connecting the bare chip with an external bonding pad, and/or the rewiring line is used for interconnecting the bare chip.
According to the wafer level chip fan-out packaging method provided by the embodiment of the invention, the actual position information of the bare chip is acquired through the laser direct writing photoetching equipment, and adjusting the original wiring pattern of the digital mask plate according to the actual position information of the bare chip, and exposing the rewiring layer according to the adjusted wiring pattern, even if the position of the bare chip is transferred, the final rewiring circuit obtained by adjusting the wiring pattern of the digital mask according to the position of the transferred bare chip can still be accurately butted with the bare chip, thereby realizing accurate connection between the bare chip and another bare chip or an external bonding pad, reducing the dependence of chip mounting precision of the bare chip, reducing the difficulty of chip interconnection, reducing the problems of open circuit and short circuit, improving the packaging yield of the chip, compared with the mode of adopting the entity mask, the method does not need to customize a new entity mask, and saves the cost.
According to some embodiments of the invention, the laser direct write lithography apparatus includes an autofocus system, and the laser direct write lithography apparatus performs exposure processing on the rewiring layer according to the adjusted wiring pattern, including: the laser direct writing photoetching equipment acquires warping information of the chip unit; the automatic focusing system adjusts the focusing surface of the exposure area according to the warping information; and the laser direct-writing photoetching equipment exposes the rewiring layer at the focusing surface according to the adjusted wiring pattern.
According to some embodiments of the invention, the providing the chip unit comprises: providing a temporary substrate base plate; attaching a bare chip to the temporary substrate, wherein a plurality of salient points are arranged on one side of the bare chip; carrying out plastic package treatment on the bare chip and the plurality of salient points of the bare chip to form a plastic package layer; exposing the plurality of salient points of the bare chip out of the plastic packaging layer; and forming the rewiring layer on the surface of the plastic package layer on one side of the plurality of bumps.
According to some embodiments of the present invention, the exposing the plurality of bumps of the bare chip to the plastic package layer with the front surface of the bare chip facing the temporary substrate includes: and stripping the temporary substrate, the bare chip and the bumps.
According to some embodiments of the invention, the number of the die is multiple, and the heights of the die in a direction perpendicular to a plane in which the die is located are different.
According to some embodiments of the invention, the front side of the bare chip is far away from the temporary substrate, and exposing the plurality of bumps of the bare chip to the plastic package layer comprises: and grinding the plastic packaging layer to expose the salient points.
According to some embodiments of the invention, the die is a plurality of die, and the height of the plurality of die is equal along a direction perpendicular to a plane in which the die is located.
According to some embodiments of the invention, prior to attaching the bare chip on the temporary substrate base plate, the method further comprises: and coating temporary bonding glue on the temporary substrate base plate.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram of a wafer level chip fan-out packaging method according to an embodiment of the invention.
Fig. 2 is a sub-step of step S1 shown in fig. 1.
Fig. 3 is a sub-step of step S4 shown in fig. 1.
Fig. 4 is a flowchart of a wafer level chip packaging method according to another embodiment of the invention.
Fig. 5 is a schematic diagram illustrating an accurate docking of a bare chip with an adjusted rewiring line according to a wafer-level chip fan-out packaging method in an embodiment of the present invention.
FIG. 6 shows a schematic diagram of an original design layout of a wafer level chip fan-out packaging method according to an embodiment of the invention.
Fig. 7 is a schematic diagram illustrating the inability of a bare chip to interface with rewiring lines of an original design after transfer during a chip packaging process in the prior art.
Reference numerals:
a bare chip 1; a bump 11; an outer pad 2; rewiring the wiring 3; layout 200 is originally designed.
Detailed Description
Embodiments of the present invention will be described in detail below, the embodiments described with reference to the drawings being illustrative, and the embodiments of the present invention will be described in detail below.
The deficiencies of the prior art wafer level chip fan-out package technique are briefly described first with reference to fig. 6-7.
Fig. 6 is an original layout diagram 200, in which the positions of the bare chip 1 (the positions of the bumps 11 on the bare chip 1) and the external pads 2 are predetermined, and the rewiring lines 3 are designed to achieve accurate interfacing with the bumps 11 of the bare chip 1.
Fig. 7 is a circuit diagram of an actual patch operation. Since the position of the bare chip 1 is often shifted when the bare chip 1 is mounted, the shifted bare chip 1 cannot be accurately butted with the rewired circuit 3 that is originally designed, which may cause a problem of disconnection or short circuit.
In order to solve the above problem, an embodiment of the present invention provides a wafer level chip fan-out packaging method. A wafer level chip fan out packaging method according to an embodiment of the invention is described below with reference to fig. 1-5.
Fig. 1 is a flowchart of a wafer level chip fan-out packaging method according to an embodiment of the present invention, and as shown in fig. 1, the wafer level chip fan-out packaging method according to an embodiment of the present invention may include the following steps:
s1: a chip unit is provided.
Referring to fig. 5, the chip unit includes a bare chip 1 and a rewiring layer. The rewiring layer is located on the bare chip 1 and covers the bare chip 1, and the role of the rewiring layer is to obtain a final rewiring line 3 after exposure to achieve inter-chip interconnection of the bare chip 1 or electrical connection of the bare chip 1 to other elements or structures.
S2: the laser direct-write lithography apparatus obtains actual position information of the bare chip.
As shown in fig. 5, the bare chip 1 is first placed at a predetermined position. However, in actual operation, the bare chip 1 is liable to shift at the time of transfer. Since the pre-designed pattern of the rewiring line 3 is designed for the predetermined position of the bare chip 1, the pre-designed rewiring line 3 cannot be accurately butted against the bare chip 1 after the placement position of the bare chip 1 is shifted. For this reason, it is necessary to obtain actual position information after the bare chip 1 is transferred. The actual position information includes angle information and position information after the bare chip 1 is transferred, and deviations between the angle information and the position information after the bare chip 1 is transferred, respectively, and predetermined angle information and position information of the bare chip 1. Of course, the present invention is not limited thereto, and the above-described actual position information of the bare chip 1 may also be obtained by an Automated Optical Inspection (AOI) apparatus, for example.
S3: and adjusting the original wiring pattern of the digital mask plate by the laser direct-writing photoetching equipment according to the actual position information of the bare chip.
The laser direct-writing photoetching equipment adopts a digital mask, and the wiring pattern of the digital mask can be changed according to an input instruction. The laser direct-write lithography apparatus performs exposure processing on the rewiring layer based on the wiring pattern of the digital mask, and can obtain the rewiring line 3.
Specifically, the original wiring pattern of the digital reticle is designed according to a predetermined position of the bare chip 1. When the position of the bare chip 1 changes, in order to ensure that the rewiring line 3 to be finally formed is accurately butted with the bare chip 1, the original wiring pattern of the digital mask needs to be adjusted, so as to obtain the adjusted wiring pattern of the digital mask according to the actual position information of the bare chip 1. The laser direct-write lithography equipment can automatically calculate according to the actual position of the bare chip 1 after being transferred and modify the original wiring pattern to obtain the adjusted wiring pattern.
S4: and the laser direct-writing photoetching equipment carries out exposure treatment on the heavy wiring layer according to the adjusted wiring pattern.
Because the adjusted wiring pattern of the digital mask is adjusted according to the transferred actual position information of the bare chip 1, after the exposure treatment is carried out on the rewiring layer according to the adjusted wiring pattern, the adjusted wiring pattern of the digital mask can be transferred onto the rewiring layer of the chip unit, thereby ensuring that the finally formed rewiring line 3 is accurately butted with the bare chip 1, and further ensuring that the rewiring line 3 accurately connects the bare chip 1 with a bonding pad outside the bare chip 1 or the bare chip 1 with other bare chips 1.
S5: and injecting metal into the exposed wiring pattern to form a rewiring line, wherein the rewiring line is used for connecting the bare chip with an external bonding pad, and/or the rewiring line is used for interconnecting the bare chip.
Specifically, after the rewiring layer is exposed to light in accordance with the adjusted wiring pattern of the digital reticle, the adjusted rewiring line pattern can be obtained. Then, a metal may be implanted at the wiring pattern on the rewiring layer to form a rewiring line. Referring to fig. 5, in the case where the rewiring line pattern is designed to extend the I/O connection point of the bare chip 1, it is necessary to electrically connect the bumps 11 on the bare chip 1 to the external pads 2, so that other electronic components can be electrically connected to the bumps 11 on the bare chip 1 through the external pads 2. In the case where the rewiring line pattern is designed to interconnect a plurality of bare chips 1, taking two bare chips 1 (but not limited thereto) as an example, it is necessary to connect the bumps 11 on one of the bare chips 1 to the bumps 11 on the other bare chip 1 through the rewiring line 3 to realize the interconnection between the two bare chips 1.
Therefore, according to the wafer level chip fan-out packaging method provided by the embodiment of the invention, rewiring exposure processing is carried out based on laser direct writing lithography equipment, the laser direct writing lithography equipment acquires the actual position information of the bare chip 1, adjusts the original wiring pattern of the digital mask plate according to the actual position information, and carries out exposure processing on the rewiring layer according to the adjusted wiring pattern, after the position of the bare chip 1 is transferred, the final rewiring line 3 obtained through the wiring pattern of the adjusted digital mask plate can still be accurately butted with the bare chip 1, so that accurate connection between the bare chip 1 and another bare chip 1 or an external bonding pad 2 can be realized, the dependence of the chip mounting precision of the bare chip 1 is reduced, the difficulty of chip interconnection is reduced, the problems of open circuit and short circuit are reduced, the chip packaging yield is improved, and compared with the mode adopting a solid mask plate, and a new entity mask is not required to be customized, so that the cost is saved.
In addition, with reference to fig. 6 and 7, another drawback of the wafer level chip fan-out package technology in the prior art is that exposure processing is required in the process of forming the rewiring circuit pattern, and the exposure area of the chip may warp, which results in poor exposure, affects the accuracy of the rewiring circuit pattern, and finally affects the accuracy of the butting between the rewiring circuit and the chip.
To solve this problem, in an embodiment of the present invention, the laser direct write lithography apparatus may include an autofocus system. The autofocus system can obtain the distance between it and the subject. For example, the autofocus system may obtain the distance between it and the respective location of the redistribution layer. Since the rewiring layer of the chip unit is likely to warp to some extent, the rewiring layer is poorly exposed to light, and the accuracy of the rewiring line 3 to be formed is eventually reduced. The automatic focusing system can adjust the focusing surface of the exposure area of the rewiring layer in real time in the vertical direction so as to improve the exposure accuracy and improve the accuracy of the rewiring line pattern.
Specifically, referring to fig. 2, the step S4 of the laser direct write lithography apparatus performing the exposure process on the heavy wiring layer according to the adjusted wiring pattern may include:
s41: and the laser direct-writing photoetching equipment acquires the warping information of the chip unit. For example, the warp information may include differences in distances measured by the autofocus system from various locations of the redistribution layer. Of course, the present invention is not limited thereto, and for example, warpage information of a chip unit may also be obtained by an AOI apparatus.
S42: and the automatic focusing system adjusts the focusing surface of the exposure area according to the warping information. The autofocus system can obtain its distances to the respective positions of the chip unit, particularly the rewiring layer, which may be different when the chip unit, particularly the rewiring layer, is warped. When the automatic focusing system measures that the distance changes, the automatic focusing system adjusts the focusing surface in real time according to the measured distance, so that accurate exposure of the rewiring layer is realized, and the exposure position is prevented from deviating.
S43: and exposing the heavy wiring layer at the focusing surface by the laser direct-writing photoetching equipment according to the adjusted wiring pattern.
Through the steps S41-S42, automatic focusing can be carried out on the rewiring layer of the chip unit, accurate exposure of the rewiring layer can be realized, the problem of poor exposure caused by warping of the chip unit is solved, an accurate rewiring circuit graph can be finally obtained, and accurate butt joint of the rewiring circuit 3 and the bare chip 1 is realized.
Optionally, as shown in fig. 3, the step S1 of providing a chip unit may specifically include:
and S11, providing a temporary substrate base plate.
The temporary substrate may be, for example, a glass substrate, but is not limited thereto.
And S12, attaching the bare chip to the temporary substrate, wherein one side of the bare chip is provided with a plurality of bumps.
As shown in fig. 5, a plurality of bumps 11 on the die 1 are electrical connection points on the die 1 for connecting to external pads 2 or other die 1. Therefore, it is necessary to design a circuit on the side of the bare chip 1 where the plurality of bumps 11 are provided. The temporary substrate provides temporary support and protection for the bare chip 1 in the subsequent steps of providing the chip unit.
And S13, carrying out plastic package treatment on the bare chip and the plurality of bumps of the bare chip to form a plastic package layer.
In this step, a layer of molding compound may be applied on the bare chip 1 to cover the bare chip 1 and the bumps 11 on the bare chip 1, thereby forming a molding layer of the bare chip 1 and the bumps 11 on the bare chip 1. The molding compound may not only cover the bare chip 1 but also extend a rewiring area of the bare chip 1, for example, the area of the molding compound may be determined according to an area of the rewiring line 3. The molding compound layer may be located on one side surface of the bare chip 1 on which the plurality of bumps 11 are provided, or may be located on the other side surface of the bare chip 1 opposite to the one side surface.
And S14, exposing the plurality of bumps of the bare chip to the plastic packaging layer. Referring to fig. 5 to 7, since the bumps 11 are electrical connection points on the die 1, it is necessary to extend the bumps 11 to the outside of the die 1 to extend I/O (Input/Output) connection points of the die 1, or to electrically connect the bumps 11 with other die 1, which requires a connection line to be formed between the bumps 11 of the die 1 and the I/O connection points or between the bumps 11 of the die 1 and the bumps 11 of other die 1. For this reason, the bumps 11 of the bare chip 1 need to be exposed, for example, at least the surface of the bumps 11 of the bare chip 1 is exposed.
And S15, forming a rewiring layer on the surface of the plastic package layer on one side of the bumps.
A rewiring layer needs to be formed on the surface of the plastic package layer on the side where the bumps 11 are exposed. Thus, the rewiring layer can be exposed to light using the wiring pattern adjusted by the digital mask to obtain a rewiring line pattern, and the rewiring line 3 formed from the obtained rewiring line pattern can be directly abutted to the bump 11.
Through steps S11-S15, Circuit design can be performed on the molding layer, a Printed Circuit Board (PCB) is not required, and the thickness of the entire chip package after packaging can be reduced. When the chip package is used in an electronic device such as a mobile phone, the thickness of the whole electronic device can be reduced, power consumption can be reduced, and portability and aesthetic property of the electronic device can be improved.
In the embodiment, the rewiring process includes a chip-up process and a chip-down process, which will be described below.
According to some alternative embodiments of the invention, the front side of the bare chip 1 faces the temporary substrate base plate, which is the case with the chip facing downwards. In the description of the present invention, the expression "the front surface of the die 1" refers to a side surface of the die 1 on which the plurality of bumps 11 are provided, and the other side surface opposite to the side surface of the die 1 is the back surface of the die 1. At this time, the temporary substrate covers the front surface of the bare chip 1, and the plastic package layer covers the back surface of the bare chip 1. Thus, the step S14 of exposing the plurality of bumps 11 of the bare chip 1 to the molding layer may include:
and S141, stripping the temporary substrate, the bare chip and the plurality of bumps. Since the temporary substrate covers the bare chip 1 and the plurality of bumps 11 on the bare chip 1, the plurality of bumps 11 can be exposed only by peeling off the temporary substrate in order to expose the plurality of bumps 11 out of the plastic package layer. The step is simple to operate, and the chip packaging process is simplified.
In the case where the front surface of the bare chip 1 faces the temporary substrate, the front surface of the bare chip 1 faces downward at this time. Therefore, after the temporary substrate is peeled off and before the redistribution layer is formed on the surface of the molding layer, the bare chip 1 needs to be turned over so that the front side of the bare chip 1 faces upward, thereby facilitating the formation of the redistribution layer on the surface of the molding layer.
Further, the bare chip 1 is plural. In the description of the present invention, "a plurality" means two or more. Alternatively, a plurality of bare chips 1 may be formed by dicing and separating qualified chips. In the case where the front surfaces of the die 1 face the temporary substrate base, the heights of the plurality of die 1 in a direction perpendicular to the plane in which the die 1 is located may not be equal. For example, the plurality of die 1 can be the same or different types of die, e.g., capacitive die, processor die, etc. Since the bumps 11 of the respective bare chips 1 are in contact with the temporary substrate in the case where the bare chips 1 are all faced toward the temporary substrate, it is possible to ensure that the bumps 11 of the bare chips 1 are maintained on the same plane. This not only facilitates the fabrication of the rewiring lines 3 between the plurality of bare chips 1, but also ensures the thickness uniformity of the entire package.
Of course, the present invention is not limited thereto. In the case where the front surfaces of the plurality of die 1 face the temporary substrate, the heights of the plurality of die 1 in the direction perpendicular to the plane of the die 1 may be equal. At this time, the bumps 11 of the plurality of bare chips 1 remain on the same plane.
According to further alternative embodiments of the present invention, the front side of the bare chip 1 is remote from the temporary substrate base, which is the case when the chip is facing upwards. At this time, the back surface of the bare chip 1 is covered with the temporary substrate, and the front surface of the bare chip 1 (i.e., the surface on which the bumps 11 are provided) is covered with the molding layer. Thus, the step S14 of exposing the plurality of bumps 11 of the bare chip 1 to the molding layer may include:
and S142, grinding the plastic packaging layer to expose the bumps.
Specifically, the entire surface of the molding layer may be ground until the plurality of bumps 11 of the bare chip 1 are sufficiently exposed. Optionally, the whole surface of the ground plastic package layer is a flat surface, so that the redistribution layer formed on the plastic package layer has a uniform thickness and a flat surface.
Further, in the case where the front surface of the die 1 is far from the temporary substrate, the die 1 is plural, and the heights of the die 1 in the direction perpendicular to the plane of the die 1 are equal. For example, the plurality of die 1 may be highly identical dies of the same type or different types. Under the condition that the front surfaces of the bare chips 1 are far away from the temporary substrate, the bumps 11 of the bare chips 1 are upward and are in contact with the plastic package layer, and the back surfaces of the bare chips 1 are in contact with the temporary deposition substrate, so that the back surfaces of the bare chips 1 are on the same plane. In order to ensure that the bumps 11 of the plurality of bare chips 1 remain on the same plane, the heights of the plurality of bare chips 1 must be equal.
Alternatively, the bumps 11 of the plurality of bare chips 1 are equal in height.
Optionally, referring to fig. 4, before attaching the bare chip on the temporary substrate base plate, the wafer level chip fan-out packaging method further includes the following steps:
and S0, coating the temporary bonding glue on the temporary substrate base plate.
Specifically, first, a temporary bonding paste is coated on one side surface of the temporary substrate base plate on which the bare chip 1 is to be placed, and then the bare chip 1 is placed on the one side surface of the temporary substrate base plate. The temporary bonding glue is applied to ensure that the bare chip 1 is temporarily and firmly attached to the temporary substrate. The temporary bonding paste may be separated from the temporary substrate base plate.
In the description of the present invention, it is to be understood that the terms "thickness", "upper", "lower", and the like, which indicate orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description herein, references to the description of "some embodiments" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (8)
1. A wafer level chip fan-out packaging method is characterized by comprising the following steps:
providing a chip unit, wherein the chip unit comprises a bare chip and a rewiring layer;
the laser direct writing photoetching equipment acquires the actual position information of the bare chip;
the laser direct-writing photoetching equipment adjusts the original wiring pattern of the digital mask plate according to the actual position information;
the laser direct-writing photoetching equipment carries out exposure treatment on the rewiring layer according to the adjusted wiring pattern;
and injecting metal into the exposed wiring pattern to form a rewiring line, wherein the rewiring line is used for connecting the bare chip with an external bonding pad, and/or the rewiring line is used for interconnecting the bare chip.
2. The wafer level chip fan-out packaging method of claim 1, wherein the laser direct write lithography apparatus includes an auto focus system, and the laser direct write lithography apparatus performs exposure processing on the rewiring layer according to the adjusted wiring pattern, including:
the laser direct writing photoetching equipment acquires warping information of the chip unit;
the automatic focusing system adjusts the focusing surface of the exposure area according to the warping information;
and the laser direct-writing photoetching equipment exposes the rewiring layer at the focusing surface according to the adjusted wiring pattern.
3. The wafer level chip fan out packaging method of claim 1 or 2, wherein the providing a chip unit comprises:
providing a temporary substrate base plate;
attaching a bare chip to the temporary substrate, wherein a plurality of salient points are arranged on one side of the bare chip;
carrying out plastic package treatment on the bare chip and the plurality of salient points of the bare chip to form a plastic package layer;
exposing the plurality of salient points of the bare chip out of the plastic packaging layer;
and forming the rewiring layer on the surface of the plastic package layer on one side of the plurality of bumps.
4. The wafer level chip fan-out packaging method of claim 2, wherein the front side of the bare chip faces the temporary substrate base plate, and the exposing the plurality of bumps of the bare chip to the molding layer comprises: and stripping the temporary substrate, the bare chip and the bumps.
5. The wafer-level chip fan-out packaging method of claim 4, wherein the number of the die is multiple, and the heights of the die are different along a direction perpendicular to a plane in which the die is located.
6. The wafer level chip fan-out packaging method of claim 2, wherein the front side of the bare chip is away from the temporary substrate base plate, and the plurality of bumps of the bare chip are exposed out of the plastic encapsulation layer, comprising:
and grinding the plastic packaging layer to expose the salient points.
7. The wafer-level chip fan-out packaging method of claim 6, wherein the number of the die is multiple, and the height of the die is equal along a direction perpendicular to a plane of the die.
8. The wafer level chip fan out packaging method of claim 2, in which prior to attaching the bare chip on the temporary substrate base plate, the method further comprises:
and coating temporary bonding glue on the temporary substrate base plate.
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