CN113066727A - Chip assembly manufacturing method, chip assembly and electronic equipment - Google Patents
Chip assembly manufacturing method, chip assembly and electronic equipment Download PDFInfo
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- CN113066727A CN113066727A CN202110296741.9A CN202110296741A CN113066727A CN 113066727 A CN113066727 A CN 113066727A CN 202110296741 A CN202110296741 A CN 202110296741A CN 113066727 A CN113066727 A CN 113066727A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 149
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- 239000000853 adhesive Substances 0.000 claims abstract description 99
- 230000001070 adhesive effect Effects 0.000 claims abstract description 99
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 48
- 229910000831 Steel Inorganic materials 0.000 claims abstract description 34
- 239000010959 steel Substances 0.000 claims abstract description 34
- 238000009713 electroplating Methods 0.000 claims abstract description 20
- 238000003825 pressing Methods 0.000 claims abstract description 16
- 238000007650 screen-printing Methods 0.000 claims abstract description 15
- 239000003292 glue Substances 0.000 claims abstract description 13
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 47
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- 239000004332 silver Substances 0.000 claims description 40
- 229910000679 solder Inorganic materials 0.000 claims description 32
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- 230000001681 protective effect Effects 0.000 claims description 26
- 238000007639 printing Methods 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 238000005245 sintering Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
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- 239000010931 gold Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
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- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 230000002787 reinforcement Effects 0.000 claims 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 19
- 238000007772 electroless plating Methods 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The embodiment of the application provides a manufacturing method of a chip assembly, the chip assembly and electronic equipment, relates to the technical field of chip assembly, and can reduce the size of the chip assembly. The manufacturing method of the chip assembly is used for electrically connecting a chip with a Flexible Printed Circuit (FPC), the FPC comprises a base material layer and a reinforcing layer which are arranged in a stacked mode, the base material layer is provided with a hollowed-out opening, an FPC terminal is arranged on the FPC, and a chip terminal is arranged on the surface of the chip, and the method comprises the following steps: bonding the chip to the surface of the reinforcing layer close to one side of the base material layer through adhesive glue to form a component to be connected; in the assembly to be connected, the chip is positioned in the opening of the substrate layer, and a gap is formed between the chip and the substrate layer; filling the excessive adhesive in the gap between the chip and the substrate layer; and forming an interconnection line between the chip terminal and the FPC terminal; the interconnection circuit is formed by an electroplating process, a steel screen printing process or an ACF pressing process and is used for electrically connecting the chip terminal and the FPC terminal.
Description
Technical Field
The present disclosure relates to the field of chip assembly technologies, and in particular, to a method for manufacturing a chip assembly, and an electronic device.
Background
At present, the chip is usually assembled by electrically connecting the chip and a Flexible Printed Circuit (FPC). The conventional manner of electrical connection between the Chip and the FPC includes a Chip Scale Package (CSP) process, in which conductive balls are required to be used, but the space occupied by the conductive balls is large.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of a chip assembly, the chip assembly and electronic equipment, which can reduce the size of the chip assembly.
In a first aspect, a method for manufacturing a chip assembly is used for electrically connecting a chip and a Flexible Printed Circuit (FPC), the FPC comprises a substrate layer and a reinforcing layer which are arranged in a stacked manner, the substrate layer is provided with a hollowed-out opening, an FPC terminal is arranged on the FPC, and a chip terminal is arranged on the surface of the chip, and the method comprises the following steps:
bonding the chip to the surface of the reinforcing layer close to one side of the base material layer through an adhesive to form a component to be connected; in the component to be connected, the chip is positioned in the opening of the substrate layer, and a gap exists between the chip and the substrate layer;
filling the excessive adhesive in the gap between the chip and the substrate layer; and
forming an interconnection line between the chip terminal and the FPC terminal; the interconnection line is formed through an electroplating process, a steel screen printing process or an ACF pressing process and is used for electrically connecting the chip terminal and the FPC terminal.
In a possible embodiment, when the FPC terminal is disposed on a surface of the substrate layer on a side away from the reinforcing layer, the forming of the interconnection line further includes:
forming a conductive metal layer by an electroplating process, and connecting the surface of the chip terminal with the surface of the FPC terminal; and
and etching the conductive metal layer by utilizing a laser direct writing process to enable the conductive metal layer to form the interconnection circuit.
In one possible embodiment, the material of the conductive metal layer is copper.
In a possible embodiment, when the FPC terminal is disposed on a surface of the substrate layer on a side away from the reinforcing layer, the forming of the interconnection line further includes:
the steel mesh printing solder paste or the conductive silver adhesive is used for connecting the surface of the chip terminal and the surface of the FPC terminal; and
and heating to solidify the solder paste or the conductive silver adhesive to form the interconnection circuit.
In a possible embodiment, when the FPC terminal is disposed on a surface of the substrate layer on a side away from the reinforcing layer, the forming of the interconnection line further includes:
the steel mesh printing silver paste is used for connecting the surface of the chip terminal and the surface of the FPC terminal; and
and sintering the silver paste to solidify the silver paste to form the interconnection circuit.
In a possible embodiment, after the sintering the silver paste, the method further comprises:
and printing solder paste on the surface of the interconnection line, which is far away from one side of the reinforcing layer, and at the positions corresponding to the chip terminal and the FPC terminal by using a steel mesh.
In one possible embodiment, the FPC further includes a connection layer located on a side of the chip terminal away from the stiffening layer;
when the FPC terminal set up in the surface of connecting layer near strengthening layer one side, form the interconnect circuit, further include:
and connecting the chip terminal and the FPC terminal by utilizing anisotropic conductive Adhesive (ACF) in a pressing mode.
In one possible implementation, after the forming the interconnection line, the method further includes:
and dispensing a protective adhesive around the chip terminal or the FPC terminal.
In one possible implementation, after the forming the interconnection line, the method further includes:
and dispensing a protective adhesive on the surface of the interconnection line far away from one side of the reinforcing layer.
In a possible implementation, before the forming the interconnection line, the method further includes:
and plating nickel and gold on the surface of the chip terminal or the surface of the FPC terminal.
In a possible implementation, before the forming the interconnection line, the method further includes:
and filling insulating ink between the chip terminal and the FPC terminal, wherein the insulating ink is positioned between the interconnection line and the adhesive glue.
In one possible embodiment, the chip terminals and the FPC terminals are at the same level.
In one possible embodiment, the area between the chip terminals and the FPC terminals is filled with an insulating ink.
In one possible embodiment, the substrate layer is attached to the stiffening layer by a conductive adhesive.
In a possible embodiment, the chip terminals are arranged on a surface of the chip on a side remote from the stiffening layer.
In a second aspect, a chip assembly comprises a chip and a Flexible Printed Circuit (FPC), wherein the FPC comprises a substrate layer and a reinforcing layer which are arranged in a stacked mode, the substrate layer is provided with a hollowed-out opening, an FPC terminal is arranged on the FPC, and a chip terminal is arranged on the surface of the chip;
the chip is adhered to the surface of the reinforcing layer close to one side of the base material layer through an adhesive, and is positioned in the opening of the base material layer;
a gap exists between the chip and the substrate layer, and the adhesive glue is filled in the gap between the chip and the substrate layer;
the chip terminal is electrically connected with the FPC terminal through an interconnection line; the interconnection line is formed through an electroplating process, a steel screen printing process or an ACF pressing process.
In one possible embodiment, the FPC terminal is provided on a surface of the substrate layer on a side away from the reinforcing layer;
the interconnection circuit is formed by etching the conductive metal layer formed by the electroplating process by utilizing a laser direct writing process and is used for connecting the surface of the chip terminal and the surface of the FPC terminal.
In one possible embodiment, the conductive metal layer is copper.
In one possible embodiment, the FPC terminal is provided on a surface of the substrate layer on a side away from the reinforcing layer;
the interconnection circuit is made by printing solder paste or conductive silver adhesive through a steel mesh and heating the solder paste or the conductive silver adhesive to solidify the solder paste or the conductive silver adhesive and is used for connecting the surface of the chip terminal and the surface of the FPC terminal.
In one possible embodiment, the FPC terminal is provided on a surface of the substrate layer on a side away from the reinforcing layer;
printing silver paste on the interconnection circuit through a steel mesh and sintering the silver paste to enable the silver paste to be solidified and made, wherein the silver paste is used for connecting the surface of the chip terminal and the surface of the FPC terminal;
a first connecting solder paste layer is arranged at the joint of the FPC terminal and the interconnection circuit and contacts the FPC terminal and the interconnection circuit;
and a second connecting solder paste layer is arranged at the joint of the chip terminal and the interconnection circuit and contacts the chip terminal and the interconnection circuit.
In a possible implementation manner, the FPC further includes a connection layer, the connection layer is located on one side of the chip terminal far away from the reinforcing layer, and the FPC terminal is arranged on the surface of the connection layer close to one side of the reinforcing layer;
the interconnection line is made of anisotropic conductive Adhesive (ACF) and is used for connecting the chip terminal and the FPC terminal in a pressing mode.
In one possible embodiment, the chip terminals and the FPC terminals are provided with a protective adhesive on their side surfaces.
In a possible embodiment, a surface of the interconnection line on a side away from the stiffening layer is provided with a protective paste.
In one possible embodiment, the surface of the chip terminal or the surface of the FPC terminal is plated with nickel gold.
In one possible embodiment, the chip terminals and the FPC terminals are filled with insulating ink, and the insulating ink is located between the interconnection lines and the adhesive.
In one possible embodiment, the chip terminals and the FPC terminals are at the same level.
In one possible embodiment, the area between the chip terminals and the FPC terminals is filled with an insulating ink.
In one possible embodiment, the substrate layer is attached to the stiffening layer by a conductive adhesive.
In a possible embodiment, the chip terminals are arranged on a surface of the chip on a side remote from the stiffening layer.
In a third aspect, an electronic device comprises a chip assembly as described in the second aspect or any one of the possible embodiments of the second aspect.
According to the chip assembly, the manufacturing method thereof and the electronic device, on one hand, the hollowed-out opening is formed in the substrate layer, the chip is bonded on the reinforcing layer through the adhesive, and the chip is located in the opening of the substrate layer, so that the chip assembly is light and thin; on the other hand, because the connection between the chip terminal and the FPC terminal is realized by using an electroplating process, a steel screen printing process or an ACF pressing process, the CSP process or a wire bonding process in the prior art is not needed, wherein the expensive gold wires are needed by using the wire bonding process, the cost is higher, the CSP process is not beneficial to the miniaturization of the chip, the process cost adopted in the embodiment of the application is lower, and the size of the chip assembly can be obviously reduced; on the other hand, the chip terminal and the FPC terminal are connected through the electroplating process, the steel screen printing process or the ACF pressing process in the embodiment of the application, the whole process can be performed in the process, and the manufacturing efficiency is high.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a chip assembly according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of an FPC according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view along AA' of FIG. 2;
FIG. 4 is a schematic view of the FPC and the chip of FIG. 2 after they are assembled;
FIG. 5 is another schematic structural view of the FPC and the chip of FIG. 2 after being assembled;
FIG. 6 is a schematic cross-sectional view along AA' of FIG. 5;
FIG. 7 is a schematic view of a partial structure of another FPC according to an embodiment of the present disclosure;
FIG. 8 is a schematic view of a cross-sectional view along AA' of FIG. 7;
FIG. 9 is a schematic view of the FPC and the chip of FIG. 7 after they are assembled;
FIG. 10 is a schematic view of the FPC, the chip and the connecting layer of FIG. 7 after being assembled;
FIG. 11 is a schematic cross-sectional view along direction BB' of FIG. 10;
fig. 12 is a schematic flow chart illustrating a method for manufacturing a chip assembly according to an embodiment of the present disclosure;
fig. 13 is a schematic cross-sectional structure view of a chip assembly obtained by the manufacturing method of fig. 12;
FIG. 14 is a schematic flow chart illustrating another method for fabricating a chip assembly according to an embodiment of the present application;
fig. 15 is a schematic cross-sectional structure view of a chip assembly obtained by the manufacturing method of fig. 14;
FIG. 16 is a schematic flow chart illustrating another method for fabricating a chip assembly according to an embodiment of the present application;
fig. 17 is a schematic cross-sectional structure view of a chip assembly obtained by the manufacturing method of fig. 16;
FIG. 18 is a schematic flow chart illustrating another method for fabricating a chip assembly according to an embodiment of the present application;
FIG. 19 is a schematic cross-sectional view of a chip assembly obtained by the fabrication method of FIG. 18;
FIG. 20 is a schematic flow chart illustrating another method for fabricating a chip assembly according to an embodiment of the present application;
FIG. 21 is another schematic view of the FPC and the chip of FIG. 2 after they are combined;
FIG. 22 is a schematic cross-sectional view along direction AA' of FIG. 21.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As shown in fig. 1 to 11, an embodiment of the present application provides a method for manufacturing a chip assembly, which is used to electrically connect a chip 2 to a flexible printed circuit FPC, where the FPC includes a substrate layer 12 and a reinforcing layer 11 that are stacked, the substrate layer 12 has a hollow opening 120, an FPC terminal 121 is provided on the FPC, and a chip terminal 21 is provided on a surface of the chip 2, and the method includes:
101, attaching a chip 2 to the surface of one side, close to a base material layer 12, of a reinforcing layer 11 through an adhesive 3 to form a component to be connected; in the component to be connected, the chip 2 is located in the opening 120 of the substrate layer 12, and a gap exists between the chip 2 and the substrate layer 12; the adhesive 3 overflows and is filled in the gap between the chip 2 and the substrate layer 12;
102, forming an interconnection line 4 between the chip terminal 21 and the FPC terminal 121; the interconnection lines 4 are formed through a plating process, a steel screen printing process, or an ACF press-fitting process, and electrically connect the chip terminals 21 with the FPC terminals 121.
Specifically, in the chip assembly, the FPC includes a reinforcing layer 11 and a substrate layer 12 which are stacked, and the substrate layer 12 has a hollow opening 120; the chip 2 is attached to the surface of one side, close to the base material layer 12, of the reinforcing layer 11 through the adhesive 3, the chip 2 is located in the opening 120 of the base material layer 12, and the surface of one side, far away from the reinforcing layer 11, of the chip 2 is provided with a chip terminal 21; FPC terminals 121 are provided on the FPC, and the FPC terminals 121 are electrically connected to the chip terminals 21 through the interconnection lines 4. The chip 2 is provided with a plurality of chip terminals 21, the FPC is provided with a plurality of FPC terminals 121, the plurality of chip terminals 21 and the plurality of FPC terminals 121 are electrically connected correspondingly, the terminals are also called pads or pins, the chip terminals 21 are used for leading out an internal circuit of the chip 2 and connecting with a peripheral circuit to realize electrical connection, and all the pins form an interface of the chip. The adhesive 3 may be Die Bonding (DB) glue; the DB paste is lower in cost than a Die Attach Film (DAF). The stiffening layer 11 may be, for example, a stiffening steel sheet for increasing the mechanical strength and reliability of the chip assembly, and in other possible implementations, the stiffening layer 11 may also be composed of a Printed Circuit Board (PCB). In the structure shown in fig. 2 to 6, the FPC terminal 121 is provided on the surface of the base material layer 12 on the side away from the reinforcing layer 11, and by providing the opening 120 in the base material layer 12, the chip 2 is fixed in the opening 120, and the FPC terminal 121 on the surface of the base material layer 12 and the chip terminal 21 on the surface of the chip 2 are electrically connected to realize Bonding connection between the chip 2 and the FPC; in the structure shown in fig. 7 to 11, the FPC further includes a connection layer 13, the FPC terminal 121 is disposed on a surface of the connection layer 13 on a side close to the reinforcing layer 11, and the chip 2 is fixed in the opening 120 by providing the opening 120 on the base material layer 12, so that the chip 2 is fixed, and the chip terminal 21 on the surface of the chip 2 and the FPC terminal 121 on the surface of the connection layer 13 are electrically connected, so that Bonding connection between the chip 2 and the FPC is achieved.
In the chip assembly in the embodiment of the application, on one hand, the hollowed-out opening is formed in the substrate layer, the chip is adhered to the reinforcing layer through the adhesive, and the chip is located in the opening of the substrate layer, so that the space utilization rate of the chip and the supporting part is improved by the fixing mode of the chip, and the chip assembly is thinned; on the other hand, because the connection between the chip terminal and the FPC terminal is realized by using an electroplating process, a steel screen printing process or an ACF pressing process, the CSP process or a wire bonding process in the prior art is not needed, wherein the wire bonding process needs to use an expensive gold wire, the cost is higher, the CSP process is not beneficial to the miniaturization of a chip assembly, while the process cost used in the embodiment of the application is lower, and the size of the chip can be obviously reduced; on the other hand, the terminal connection is realized through the electroplating process, the steel screen printing process or the ACF pressing process in the embodiment of the application, the whole-page operation can be performed in the process, and the manufacturing efficiency is high.
In one possible embodiment, as shown in fig. 12 and 13, the FPC terminal 121 is provided on the surface of the base material layer 12 on the side away from the reinforcing layer 11;
the forming an interconnection line in step 102 further includes:
step 1021, forming a conductive metal layer by an electroplating process, and connecting the surface of the chip terminal 21 and the surface of the FPC terminal 121;
and 1022, etching the conductive metal layer by using a laser direct writing process, so that the conductive metal layer forms an interconnection line 4, and the formed interconnection line 4 can realize the electrical connection between the chip terminal 21 and the corresponding FPC terminal 121.
In one possible embodiment, as shown in fig. 12 and 13, the material of the conductive metal layer is copper Cu.
In one possible embodiment, as shown in fig. 14, 15, 16, and 17, the FPC terminal 121 is provided on the surface of the base material layer 12 on the side away from the reinforcing layer 11;
the forming an interconnection line in step 102 further includes:
step 1023, printing solder paste or conductive silver adhesive on a steel mesh, and connecting the surface of the chip terminal 21 and the surface of the FPC terminal 121;
and step 1024, heating to solidify the solder paste or the conductive silver adhesive to form the interconnection circuit 4.
In one possible embodiment, as shown in fig. 18 and 19, the FPC terminal 121 is provided on the surface of the base material layer 12 on the side away from the reinforcing layer 11;
the forming an interconnection line in step 102 further includes:
step 1025, printing silver paste on a steel mesh, and connecting the surface of the chip terminal 21 and the surface of the FPC terminal 121;
and step 1026, sintering the silver paste to solidify the silver paste to form the interconnection circuit 4.
In one possible embodiment, as shown in fig. 18 and 19, after the step 1026 of sintering the silver paste, the method further includes:
step 104, performing steel mesh printing on the surface of the interconnection line 4 far from the reinforcing layer 11 and corresponding to the positions of the chip terminals 21 and the FPC terminals 121 with solder paste, wherein the solder paste can stabilize the electrical connection between the interconnection line 4 and the chip terminals 21 and the electrical connection between the interconnection line 4 and the FPC terminals 121, thereby improving the reliability of the overall structure.
In one possible embodiment, as shown in fig. 20 and fig. 7 to 11, the FPC further includes a connection layer 13, the connection layer 13 is located on a side of the chip terminal 21 away from the reinforcing layer 11, and the FPC terminal 121 is disposed on a surface of the connection layer 13 close to the reinforcing layer 11;
the forming an interconnection line in step 102 further includes:
step 1027, connecting the chip terminals 21 and the FPC terminals 121 by using anisotropic conductive adhesive ACF in a press-fit manner to form the interconnection lines 4.
Step 1027 may specifically include:
step 10271, forming anisotropic conductive film ACF (interconnection line 4) on the surface of the chip terminal 21;
step 10272, the component to be connected and the connection layer 13 are pressed together by anisotropic conductive film ACF (interconnection line 4), so that the chip terminal 21 and the FPC terminal 121 are electrically connected by the interconnection line 4.
Specifically, as shown in fig. 7 to 11 and 20, Anisotropic Conductive Film (ACF) is synthesized from high-quality resin and Conductive particles, and is mainly used for connecting two different substrates/lines, wherein the two different substrates/lines need to be connected to each other, and the ACF has the characteristics of vertical (Z-axis) electrical conduction and horizontal (X, Y-axis) insulation, has excellent moisture-proof, adhesion, conduction and insulation functions, and is a good choice for connecting two different substrates/lines. The Z-axis direction is the thickness direction of the chip 2, the ACF can be used to make independent signal lines without corresponding to different terminals, and only the positional relationship between the chip terminals 21 and the FPC terminals 121 needs to be preset to make the chip terminals 21 and the FPC terminals 121 face each other, and then the chip 2 and the FPC are pressed together by the ACF, so that the chip terminals 21 and the FPC terminals 121 can be electrically connected, that is, the interconnection circuit 4 is realized by the ACF.
In one possible embodiment, as shown in fig. 20 and fig. 7 to 11, after the step 10272 of forming the interconnection line 4, the method further includes:
step 200, dispensing a protective adhesive 8 around the chip terminal 21 or the FPC terminal 121, wherein the protective adhesive 8 is used for protecting the terminal connection position.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, after the forming of the interconnection line, the method further includes:
step 103, dispensing a protective paste 6 on the surface of the interconnection line 4 away from the stiffening layer 11.
In one possible embodiment, in addition to the above embodiments, before the step 101 of bonding the chip 2 to the surface of the reinforcing layer 11 close to the base material layer 12 by the adhesive 3, the method further includes: nickel gold (not shown) is plated on the surface of the chip terminal 21 or the surface of the FPC terminal 121. So that the chip terminals 21 are electrically connected to the interconnection lines 4 through nickel gold on the surface and the FPC terminals 121 are electrically connected to the interconnection lines 4 through nickel gold on the surface after the interconnection lines 4 are subsequently formed. The chip terminal 21 and the FPC terminal 121 may be made of aluminum, and the aluminum is easily oxidized to form a nonconductive aluminum oxide film, so that a layer of nickel gold is plated on the surfaces of the chip terminal 21 and the FPC terminal 121, so that the electrical connection performance between the chip terminal 21 and the FPC terminal 121 can be improved.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, before forming the interconnection line, the method further includes:
step 300, filling insulating ink 5 between the chip terminals 21 and the FPC terminals 121, wherein the insulating ink 5 is located between the interconnection lines 4 and the adhesive 3, and the insulating ink 5 is used for preventing short circuit caused by metal residues on the chip terminals 21.
Specifically, an insulating ink 5 is provided between the adhesive paste 3 and the interconnection lines 4, and the insulating ink 5 is located between the FPC terminals 121 and the chip terminals 21. In the manufacturing process of the chip 2, during the process of cutting the chip 2 into the single independent chips 2 from the whole wafer, metal residues may exist at the edge of the chip 2, and the metal residues may contact the interconnection lines 4 to cause short circuit between the interconnection lines 4, so that, in order to improve the problem of short circuit of the interconnection lines 4 caused by the metal residues at the edge of the chip 2, before the manufacturing process of the interconnection lines 4, a layer of insulating ink 5 may be manufactured between the chip terminals 21 and the FPC terminals 121 through a pad printing process, and meanwhile, the insulating ink 5 may also be used for filling the grooves between the chip 2 and the FPC, so that even if the edge of the chip 2 has the metal residues, the metal residues and the interconnection lines 4 are insulated to reduce the probability of short circuit of the interconnection lines 4. The thickness of the insulating ink 5 may be 20 μm.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the chip terminal 21 and the FPC terminal 121 are at the same level, and the terminals at the same level can be connected by the more flat and stable interconnection line 4, so as to ensure the stability of the electrical connection.
Specifically, the height h1 of the surface of the chip 2 away from the reinforcing layer 11 may be the same as the height h2 of the surface of the FPC away from the reinforcing layer 11, so that the chip terminals 21 and the FPC terminals 121 are at the same level, the height h1 of the surface of the chip 2 away from the reinforcing layer 11 is the distance between the surface of the chip 2 away from the reinforcing layer 11 and the reinforcing layer 11, and the height h2 of the surface of the FPC away from the reinforcing layer 11 is the distance between the surface of the FPC away from the reinforcing layer 11 and the reinforcing layer 11. The height h1 of the surface of the chip 2 away from the reinforcing layer 11 can be adjusted by the pressure of the bonding glue 3 and the glue amount of the bonding glue 3 when the chip 2 is bonded with the reinforcing layer 11, and when h1 is equal to h2, the chip terminal 21 and the FPC terminal 121 can be positioned at the same horizontal height, which is more beneficial to the flatness and stability of the interconnection line 4, so as to reduce the probability of disconnection of the interconnection line 4.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the chip terminals 21 and the FPC terminals 121 are filled with the insulating ink 5, and after the filling with the insulating ink 5, the interconnection lines 4 are more stably formed between the chip terminals 21 and the FPC terminals 121, so that the problem that the interconnection lines 4 are easily broken due to the difference in height is reduced, and the stability of the electrical connection between the terminals is improved.
In one possible embodiment, as shown in fig. 4 and 9, the side surface of the chip 2 and the side surface of the substrate layer 12 are spaced apart from each other, and the distance between the side surface of the chip 2 and the side surface of the substrate layer 12 is d, where d is greater than or equal to 0.15mm and less than or equal to 0.3mm, for example, d is greater than or equal to 0.17mm, and the distance can ensure that the chip 2 can still enter the opening 120 of the substrate layer 12 during the process of attaching to the surface of the reinforcing layer 11 in the case of extreme tolerance. In addition, the size of the chip terminals 21 may be 70 μm × 70 μm, the pitch between adjacent chip terminals 21 may be 110 μm, the size of the FPC terminals 121 may be 80 μm × 150 μm, and the pitch between adjacent FPC terminals 121 may be 160 μm in the embodiment of the present application.
In a possible embodiment, the side surface of the chip 2 and the side surface of the substrate layer 12 are spaced apart from each other, and the adhesive 3 is further filled between the side surface of the chip 2 and the side surface of the substrate layer 12, specifically, the adhesive 3 between the chip 2 and the reinforcing layer 11 may overflow to the side surface of the chip 2, even if a part of the adhesive 3 is filled in the gap between the chip 2 and the substrate layer 12, so as to improve the fixing effect of the chip 2.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the FPC terminals 121 are located near the edge of the substrate layer 12, and the chip terminals 21 are located near the edge of the chip 2, and since the chip 2 and the substrate layer 12 are spaced apart from each other, the interconnection lines 4 need to span the gap region between the two to electrically connect the chip terminals 21 and the corresponding FPC terminals 121. In this way, the FPC terminal 121 and the chip terminal 21 can have better electrical connection performance, and do not need to be connected by a CSP process or by gold wires, on one hand, the volume is reduced because larger-sized conductive balls in the CSP process are not needed, and on the other hand, the cost is lower because gold wires are not needed and a connection wire with lower cost can be used. In addition, because the adhesive 3 is filled between the side surface of the chip 2 and the side surface of the substrate layer 12, the adhesive 3 can make the groove between the chip terminal 21 and the FPC terminal 121 smoother and even eliminate the groove, so that the probability of wire breakage of the interconnection line 4 caused by uneven substrate can be reduced in the subsequent process of manufacturing the interconnection line 4.
In one possible embodiment, the interconnect lines 4 are copper, tin or silver material, as shown in fig. 2-6, 12-19, 21 and 22. Based on the structure, the chip terminal 21 and the FPC terminal 121 can be made of copper, tin or silver materials to form the interconnection line 4, so that the chip terminal 21 and the FPC terminal 121 are electrically connected, the interconnection line 4 made of the materials can realize good electrical connection performance, and a gold wire connection mode is not needed, so that expensive equipment and materials are not needed, the cost is reduced, and meanwhile, the whole structure of the chip assembly can be miniaturized and thinned. The manufacturing process of the interconnection line 4 can be specifically realized by an electroplating and laser direct writing process or a steel screen printing process.
In one possible embodiment, as shown in fig. 2 to 6, 12 to 19, 21 and 22, the surface of the interconnect line 4 on the side away from the stiffening layer 11 is provided with a protective paste 6 to improve the reliability of the interconnect line 4.
In addition, the substrate layer 12 is provided with the alignment mark M around the substrate layer in the embodiment of the present application, and the alignment mark M is used for aligning in the process of attaching the chip 2 to the opening 120 of the substrate layer 12, so as to ensure the accuracy of the placement position of the chip 2.
The following is illustrated by the 5 examples in more detail:
as shown in fig. 12 and 13, the method of manufacturing the chip assembly of example 1 includes:
forming a layer of nickel gold with the thickness of about 2 μm on the surface of the chip terminal 21 and the surface of the FPC terminal 121 by an electroless plating process, and then proceeding to step 100;
step 100, forming adhesive 3 at the position of the reinforcing layer 11 in the FPC, which is located in the opening 120, through a dispensing process, and then entering step 101;
101, attaching a chip 2 to the surface of one side, close to a substrate layer 12, of a reinforcing layer 11 through an adhesive 3 to form a to-be-connected assembly, wherein in the to-be-connected assembly, the chip 2 is located in an opening 120 of the substrate layer 12, a chip terminal 21 is located on the surface of one side, far away from the reinforcing layer 11, of the chip 2, the side surface of the chip 2 and the side surface of an FPC are arranged at intervals, and the adhesive 3 overflows to a gap between the chip 2 and the FPC, so that the adhesive 3 is filled between the side surface of the chip 2 and the side surface of the FPC, and then entering step 300;
step 300, filling insulating ink 5 between the chip terminal 21 and the FPC terminal 121, wherein the insulating ink 5 is located between the interconnection line 4 and the adhesive 3, and then entering step 1021;
step 1021, forming a conductive metal layer (for example, metal copper Cu) by an electroplating process, connecting the surface of the chip terminal 21 with the surface of the FPC terminal 121, and then proceeding to step 1022;
and 1022, etching the conductive metal layer by using a laser direct writing process to form an interconnection line 4 on the conductive metal layer, removing redundant copper Cu in the process, and then entering 103.
103, dotting a protective adhesive 6 on the surface of the interconnection line 4 far from the reinforcing layer 11, wherein the protective adhesive 6, nickel gold, and the insulating ink 5 have good bondability, and the protective adhesive 6 is made of epoxy resin, for example, and is used for maintaining the stability of the whole structure, improving the reliability of the product, and preventing the circuit from being incapable of working normally due to accidental touch, extreme temperature (for example, extreme cold), and the like. A schematic cross-sectional view of a chip assembly fabricated by the process steps shown in fig. 12 is shown in fig. 13.
As shown in fig. 14 and 15, the method of manufacturing the chip assembly of example 2 includes:
forming a layer of nickel gold with the thickness of about 2 μm on the surface of the chip terminal 21 and the surface of the FPC terminal 121 by an electroless plating process, and then proceeding to step 100;
step 100, forming adhesive 3 at the position of the reinforcing layer 11 in the FPC, which is located in the opening 120, through a dispensing process, and then entering step 101;
101, attaching a chip 2 to the surface of one side, close to a base material layer 12, of a reinforcing layer 11 through an adhesive 3 to form a component to be connected, wherein in the component to be connected, the chip 2 is located in an opening 120 of the base material layer 12, and a gap exists between the chip 2 and the base material layer 12; filling the adhesive 3 in the gap between the chip 2 and the substrate layer 12 by glue overflow, and then entering step 300;
step 300, filling insulating ink 5 between the chip terminal 21 and the FPC terminal 121, and the insulating ink 5 is located between the interconnection line 4 and the adhesive 3, and then proceeding to step 1023;
1023, manufacturing the interconnection line 4 of the solder paste on the insulating ink 5 by using a steel mesh printing process, wherein the steel mesh printing process has the advantages of high precision, full-page printing and improvement of printing efficiency, and then entering a step 1024;
step 1024, curing the interconnection lines 4 of solder paste by a vacuum reflow process at a high temperature of 180 ℃ to 260 ℃, which may be, for example, 200 ℃, and then proceeding to step 103.
And 103, forming a protective adhesive 6 on the surface of the interconnection line 4 far away from the reinforcing layer 11, wherein the protective adhesive 6, the solder paste, the nickel gold and the insulating ink 5 have good bonding property. A cross-sectional view of the chip assembly fabricated by the process steps shown in fig. 14 is shown in fig. 15.
As shown in fig. 16 and 17, the method of manufacturing the chip assembly of example 3 includes:
forming a layer of nickel gold with the thickness of about 2 μm on the surface of the chip terminal 21 and the surface of the FPC terminal 121 by an electroless plating process, and then proceeding to step 100;
step 100, forming adhesive 3 at the position of the reinforcing layer 11 in the FPC, which is located in the opening 120, through a dispensing process, and then entering step 101;
101, attaching a chip 2 to the surface of one side, close to a substrate layer 12, of a reinforcing layer 11 through an adhesive 3 to form a to-be-connected assembly, wherein in the to-be-connected assembly, the chip 2 is located in an opening 120 of the substrate layer 12, a chip terminal 21 is located on the surface of one side, far away from the reinforcing layer 11, of the chip 2, the side surface of the chip 2 and the side surface of an FPC are arranged at intervals, and the adhesive 3 overflows to a gap between the chip 2 and the FPC, so that the adhesive 3 is filled between the side surface of the chip 2 and the side surface of the FPC, and then entering step 300;
step 300, filling insulating ink 5 between the chip terminal 21 and the FPC terminal 121, wherein the insulating ink 5 is located between the interconnection line 4 and the adhesive 3, and then entering step 1025;
1023, manufacturing the interconnection circuit 4 of the conductive silver adhesive on the insulating ink 5 by using a steel mesh printing process, and then entering a step 1024;
1024, curing the interconnection line 4 of the conductive silver adhesive at a high temperature of 150-200 ℃ through a high-temperature process, and then entering 103;
step 103, forming a protective adhesive 6 on the surface of the interconnection line 4 far from the reinforcing layer 11, wherein the protective adhesive 6, the conductive silver adhesive, the nickel gold and the insulating ink 5 have good bondability. A cross-sectional view of the chip assembly fabricated by the process steps shown in fig. 16 is shown in fig. 17.
As shown in fig. 18 and 19, the method of manufacturing the chip assembly of example 4 includes:
forming a layer of nickel gold with the thickness of about 2 μm on the surface of the chip terminal 21 and the surface of the FPC terminal 121 by an electroless plating process, and then proceeding to step 100;
step 100, forming adhesive 3 at the position of the reinforcing layer 11 in the FPC, which is located in the opening 120, through a dispensing process, and then entering step 101;
101, attaching a chip 2 to the surface of one side, close to a base material layer 12, of a reinforcing layer 11 through an adhesive 3 to form a component to be connected, wherein in the component to be connected, the chip 2 is located in an opening 120 of the base material layer 12, and a gap exists between the chip 2 and the base material layer 12; filling the adhesive 3 in the gap between the chip 2 and the substrate layer 12 by glue overflow, and then entering step 300;
step 300, filling insulating ink 5 between the chip terminal 21 and the FPC terminal 121, wherein the insulating ink 5 is located between the interconnection line 4 and the adhesive 3, and then entering step 1025;
step 1025, manufacturing an interconnection circuit 4 of the conductive silver paste on the insulating ink 5 by using a steel mesh printing process, and then entering step 1026;
1026, solidifying the interconnection line 4 of the conductive silver paste by a sintering process at a high temperature of 150-220 ℃, and then entering step 104;
104, forming solder paste on the FPC terminal 121 and the chip terminal 21 by using a steel mesh printing process, wherein the solder paste can further enhance the electrical connection performance of the interconnection lines 4 and the FPC terminal 121 and the interconnection lines 4 and the chip terminal 21, and then entering step 103;
and 103, forming a protective adhesive 6 on the surface of the interconnection line 4 far away from the reinforcing layer 11, wherein the protective adhesive 6, the conductive silver paste, the nickel gold and the insulating ink 5 have good bonding property. A cross-sectional view of the chip assembly fabricated by the process steps shown in fig. 18 is shown in fig. 19.
As shown in fig. 20 and fig. 6 to 11, the method of manufacturing the chip assembly of embodiment 5 includes:
forming a layer of nickel gold with the thickness of about 2 μm on the surface of the chip terminal 21 and the surface of the FPC terminal 121 by an electroless plating process, and then proceeding to step 100;
step 100, forming adhesive 3 at the position of the reinforcing layer 11 in the FPC, which is located in the opening 120, through a dispensing process, and then entering step 101;
101, attaching a chip 2 to the surface of the reinforcing layer 11 close to the side of the substrate layer 12 through an adhesive 3 to form a to-be-connected assembly, wherein in the to-be-connected assembly, the chip 2 is located in the opening 120 of the substrate layer 12, the chip terminal 21 is located on the surface of the chip 2 far away from the reinforcing layer 11, the side surface of the chip 2 and the side surface of the substrate layer 12 are arranged at intervals, the adhesive 3 overflows to a gap between the chip 2 and the FPC, so that the adhesive 3 is filled between the side surface of the chip 2 and the side surface of the substrate layer 12, and then entering step 10271;
step 10271, forming anisotropic conductive film ACF (interconnection line 4) on the surface of the chip terminal 21, and then proceeding to step 10272;
step 10272, pressing the component to be connected and the connection layer 13 by anisotropic conductive adhesive ACF (interconnection line 4), so that the chip terminal 21 and the FPC terminal 121 are electrically connected by the interconnection line 4, the chip terminal 21 is located on one side of the chip 2 close to the connection layer 13, the FPC terminal 121 is located on one side of the connection layer 13 close to the chip 2, the chip terminal 21 is connected to the FPC terminal 121 by the anisotropic conductive adhesive ACF, and then the process proceeds to step 200.
Step 200, a protective adhesive 8 is dispensed around the chip terminals 21 or the FPC terminals 121. A cross-sectional view of the chip assembly fabricated by the process steps shown in fig. 20 is shown in fig. 11. As shown in fig. 20 and fig. 7 to 11, the chip assembly and the method for manufacturing the same can prevent the FPC from forming a tail-like structure on the outer shape, and the AFC lamination process is simple and low in cost.
In addition, in the above embodiments, as in fig. 2 to 11, the base material layer 12 may be connected to the reinforcing layer 11 through the conductive paste 9 so as to ground the FPC through the reinforcing layer 11. In addition, the surface of the base material layer 12 on the side far away from the reinforcing layer 11 is provided with green oil 10, and the green oil 10 can be used for preventing the circuit on the FPC from being broken; the deterioration and corrosion of the circuit insulation caused by external environmental factors such as dust, moisture and the like are prevented; the green oil 10 has high insulation, and is advantageous for achieving high density of a circuit.
As shown in fig. 2 to 11, an embodiment of the present application provides a chip assembly, which includes a chip 2 and a flexible printed circuit FPC, where the FPC includes a substrate layer 12 and a reinforcing layer 11 that are stacked, the substrate layer 12 has a hollow opening 120, the FPC is provided with an FPC terminal 121, and the surface of the chip 2 is provided with a chip terminal 21; the chip 2 is attached to the surface of the reinforcing layer 11 close to one side of the base material layer 12 through the adhesive 3, and the chip 2 is positioned in the opening 120 of the base material layer 12; a gap exists between the chip 2 and the base material layer 12, and the adhesive 3 is filled in the gap between the chip 2 and the base material layer 12; the chip terminals 21 and the FPC terminals 121 are electrically connected through the interconnection lines 4; the interconnection 4 is formed by an electroplating process, a steel screen printing process, or an ACF press-fitting process.
The specific structure and manufacturing method of the chip assembly are the same as those of the above embodiments, and are not described herein again.
In one possible embodiment, as shown in fig. 12 and 13, the FPC terminal 121 is provided on the surface of the base material layer 12 on the side away from the reinforcing layer 11; the interconnection lines 4 are formed by etching a conductive metal layer formed by an electroplating process using a laser direct writing process, and are used to connect the surfaces of the chip terminals 21 and the surfaces of the FPC terminals 121.
In one possible embodiment, as shown in fig. 12 and 13, the material of the conductive metal layer is copper Cu.
In one possible embodiment, as shown in fig. 14, 15, 16, and 17, the surface of the base material layer 12 on the side away from the reinforcing layer 11 is provided with an FPC terminal 121; the interconnection lines 4 are formed by printing solder paste or conductive silver paste on a steel mesh and heating the solder paste or conductive silver paste to cure the solder paste or conductive silver paste, and are used for connecting the surfaces of the chip terminals 21 and the surfaces of the FPC terminals 121.
In one possible embodiment, as shown in fig. 18 and 19, the interconnection lines 4 are made by screen printing a silver paste and sintering the silver paste to cure the silver paste for connecting the surfaces of the chip terminals 21 and the surfaces of the FPC terminals 121; a first connecting solder paste is arranged at the joint of the FPC terminal 121 and the interconnection line 4, and the first connecting solder paste contacts the FPC terminal 121 and the interconnection line 4; the joint of the chip terminal 21 and the interconnection line 4 is provided with a second connection solder paste, which contacts the chip terminal 21 and the interconnection line 4. In order to ensure the electrical connection performance between the interconnection line 4 formed by curing the conductive silver paste and the terminal, solder paste is additionally arranged at the joint of the terminal and the interconnection line 4, so that the electrical connection performance can be further ensured.
In one possible embodiment, as shown in fig. 20 and fig. 7 to 11, the FPC further includes a connection layer 13, the connection layer 13 is located on a side of the chip terminal 21 away from the reinforcing layer 11, and the FPC terminal 121 is located on a surface of the connection layer 13 close to the reinforcing layer 11; the interconnection lines 4 are made of anisotropic conductive paste ACF, and are used for press-fitting the chip terminals 21 and the FPC terminals 121.
In one possible embodiment, as shown in fig. 20 and 7 to 11, the side surfaces of the chip terminals 21 and the FPC terminals 121 are provided with a protective paste 8.
In one possible embodiment, as shown in fig. 21 and 22, the surface of the interconnection line 4 on the side away from the stiffening layer 11 is provided with a protective paste 6.
In one possible embodiment, as shown in fig. 21 and 22, the surfaces of the chip terminals 21 and the surfaces of the FPC terminals 121 are plated with nickel gold; specifically, the surface of the chip terminal 21 is connected to the interconnection line 4 through nickel gold, and the nickel gold is located between the protective adhesive 6 and the chip terminal 21; alternatively, the surface of the FPC terminal 121 is connected to the interconnection line 4 by nickel gold, and the nickel gold is located between the protective paste 6 and the FPC terminal 121.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the insulating ink 5 is filled between the chip terminals 21 and the FPC terminals 121, and the insulating ink 5 is located between the interconnection lines 4 and the adhesive paste 3.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the chip terminals 21 and the FPC terminals 121 are at the same level.
In one possible embodiment, as shown in fig. 2 to 6 and 12 to 19, the chip terminals 21 and the FPC terminals 121 are filled with the insulating ink 5.
In one possible embodiment, as shown in fig. 2 to 11, the substrate layer 12 may be connected to the reinforcing layer 11 through the conductive paste 9 so as to ground the FPC through the reinforcing layer 11.
In the chip assembly and the manufacturing method thereof in the above embodiments, on one hand, the hollowed-out opening is formed in the substrate layer, the chip is bonded on the reinforcing layer through the adhesive, and the chip is located in the opening, so that the space utilization rate of the chip and the supporting portion is improved by the fixing mode of the chip, and the size of the chip assembly is reduced; on the other hand, because the connection between the chip terminal and the FPC terminal is realized by using an electroplating process, a steel screen printing process or an ACF pressing process, the CSP process or a wire bonding process in the prior art is not needed, the wire bonding process needs to use an expensive gold wire, the cost is higher, the CSP process is not beneficial to the miniaturization of the chip assembly, the process cost used by the process in the embodiment of the application is lower, and the size of the chip assembly can be obviously reduced; on the other hand, the chip terminal and the FPC terminal are connected through the electroplating process, the steel screen printing process or the ACF pressing process in the embodiment of the application, the whole process can be performed in the process, and the manufacturing efficiency is high.
In addition, it should be noted that the chip in the embodiment of the present application may be, for example, a camera chip or a fingerprint identification chip, but the embodiment of the present application does not limit the specific function of the chip, as long as the technical solution of the present application can be applied to reduce the occupied space.
An embodiment of the present application further provides an electronic device, including the chip assembly in any of the above embodiments. The electronic device may be, for example, a mobile phone, a tablet computer, a notebook computer, a smart wearable device, a vehicle-mounted device, or a television.
In the electronic equipment, the FPC in the chip assembly is electrically connected with devices in the electronic equipment so as to realize the electrical connection between the chip and other devices in the electronic equipment, and taking a camera chip in a mobile phone as an example, the camera chip is electrically connected with the FPC to form the chip assembly in the embodiment of the application.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (30)
1. The manufacturing method of the chip assembly is characterized by being used for electrically connecting a chip with a Flexible Printed Circuit (FPC), wherein the FPC comprises a base material layer and a reinforcing layer which are arranged in a stacked mode, the base material layer is provided with a hollowed-out opening, an FPC terminal is arranged on the FPC, and a chip terminal is arranged on the surface of the chip, and the method comprises the following steps of:
bonding the chip to the surface of the reinforcing layer close to one side of the base material layer through an adhesive to form a component to be connected; in the component to be connected, the chip is positioned in the opening of the substrate layer, and a gap exists between the chip and the substrate layer;
filling the excessive adhesive in the gap between the chip and the substrate layer; and
forming an interconnection line between the chip terminal and the FPC terminal; the interconnection line is formed through an electroplating process, a steel screen printing process or an ACF pressing process and is used for electrically connecting the chip terminal and the FPC terminal.
2. The method of claim 1,
when the FPC terminal set up in keeping away from of substrate layer when the surface of strengthening layer one side, form the interconnect circuit, further include:
forming a conductive metal layer by an electroplating process, and connecting the surface of the chip terminal with the surface of the FPC terminal; and
and etching the conductive metal layer by utilizing a laser direct writing process to enable the conductive metal layer to form the interconnection circuit.
3. The method of claim 2, wherein the conductive metal layer is copper.
4. The method of claim 1,
when the FPC terminal set up in keeping away from of substrate layer when the surface of strengthening layer one side, form the interconnect circuit, further include:
the steel mesh printing solder paste or the conductive silver adhesive is used for connecting the surface of the chip terminal and the surface of the FPC terminal; and
and heating to solidify the solder paste or the conductive silver adhesive to form the interconnection circuit.
5. The method of claim 1,
when the FPC terminal set up in keeping away from of substrate layer when the surface of strengthening layer one side, form the interconnect circuit, further include:
the steel mesh printing silver paste is used for connecting the surface of the chip terminal and the surface of the FPC terminal; and
and sintering the silver paste to solidify the silver paste to form the interconnection circuit.
6. The method of claim 5, further comprising, after the sintering the silver paste:
and printing solder paste on the surface of the interconnection line, which is far away from one side of the reinforcing layer, and at the positions corresponding to the chip terminal and the FPC terminal by using a steel mesh.
7. The method of claim 1, wherein the FPC further comprises a connection layer located on a side of the chip terminals remote from the stiffening layer;
when the FPC terminal set up in the surface of connecting layer near strengthening layer one side, form the interconnect circuit, further include:
and connecting the chip terminal and the FPC terminal by utilizing anisotropic conductive Adhesive (ACF) in a pressing mode.
8. The method of claim 7, further comprising, after said forming interconnect lines:
and dispensing a protective adhesive around the chip terminal or the FPC terminal.
9. The method of claim 1, further comprising, after said forming interconnect lines:
and dispensing a protective adhesive on the surface of the interconnection line far away from one side of the reinforcing layer.
10. The method of claim 1, further comprising, prior to said forming interconnect lines:
and plating nickel and gold on the surface of the chip terminal or the surface of the FPC terminal.
11. The method of claim 1, further comprising, prior to said forming interconnect lines:
and filling insulating ink between the chip terminal and the FPC terminal, wherein the insulating ink is positioned between the interconnection line and the adhesive glue.
12. The method of any one of claims 2 to 6, wherein the chip terminals and the FPC terminals are at the same level.
13. The method of claim 12, wherein the area between the chip terminals and the FPC terminals is filled with an insulating ink.
14. The method according to any one of claims 1 to 11, wherein the substrate layer is attached to the reinforcement layer by a conductive adhesive.
15. The method according to any one of claims 1 to 11, wherein the chip terminals are provided on a surface of the chip on a side remote from the stiffening layer.
16. A chip assembly is characterized by comprising a chip and a Flexible Printed Circuit (FPC), wherein the FPC comprises a base material layer and a reinforcing layer which are arranged in a stacked mode, the base material layer is provided with a hollowed-out opening, an FPC terminal is arranged on the FPC, and a chip terminal is arranged on the surface of the chip;
the chip is adhered to the surface of the reinforcing layer close to one side of the base material layer through an adhesive, and is positioned in the opening of the base material layer;
a gap exists between the chip and the substrate layer, and the adhesive glue is filled in the gap between the chip and the substrate layer;
the chip terminal is electrically connected with the FPC terminal through an interconnection line; the interconnection line is formed through an electroplating process, a steel screen printing process or an ACF pressing process.
17. The chip assembly according to claim 16,
the FPC terminal is arranged on the surface of one side of the base material layer far away from the reinforcing layer;
the interconnection circuit is formed by etching the conductive metal layer formed by the electroplating process by utilizing a laser direct writing process and is used for connecting the surface of the chip terminal and the surface of the FPC terminal.
18. The chip assembly according to claim 17,
the conductive metal layer is copper.
19. The chip assembly according to claim 16,
the FPC terminal is arranged on the surface of one side of the base material layer far away from the reinforcing layer;
the interconnection circuit is made by printing solder paste or conductive silver adhesive through a steel mesh and heating the solder paste or the conductive silver adhesive to solidify the solder paste or the conductive silver adhesive and is used for connecting the surface of the chip terminal and the surface of the FPC terminal.
20. The chip assembly according to claim 16,
the FPC terminal is arranged on the surface of one side of the base material layer far away from the reinforcing layer;
printing silver paste on the interconnection circuit through a steel mesh and sintering the silver paste to enable the silver paste to be solidified and made, wherein the silver paste is used for connecting the surface of the chip terminal and the surface of the FPC terminal;
a first connecting solder paste layer is arranged at the joint of the FPC terminal and the interconnection circuit and contacts the FPC terminal and the interconnection circuit;
and a second connecting solder paste layer is arranged at the joint of the chip terminal and the interconnection circuit and contacts the chip terminal and the interconnection circuit.
21. The chip assembly according to claim 16,
the FPC further comprises a connecting layer, the connecting layer is positioned on one side, far away from the reinforcing layer, of the chip terminal, and the FPC terminal is arranged on the surface, close to the reinforcing layer, of the connecting layer;
the interconnection line is made of anisotropic conductive Adhesive (ACF) and is used for connecting the chip terminal and the FPC terminal in a pressing mode.
22. The chip assembly according to claim 21,
and the side surfaces of the chip terminal and the FPC terminal are provided with protective glue.
23. The chip assembly according to claim 16,
and a protective adhesive is arranged on the surface of the interconnection line, which is far away from one side of the reinforcing layer.
24. The chip assembly according to claim 16,
and the surface of the chip terminal or the surface of the FPC terminal is plated with nickel and gold.
25. The chip assembly according to claim 16,
and insulating ink is filled between the chip terminal and the FPC terminal and is positioned between the interconnection line and the adhesive glue.
26. The chip assembly according to any of claims 17 to 20,
the chip terminal and the FPC terminal are at the same horizontal height.
27. The chip assembly according to claim 26,
the area between the chip terminals and the FPC terminals is filled and leveled by insulating ink.
28. The chip assembly according to any of claims 16 to 25,
the substrate layer is attached to the reinforcing layer through conductive adhesive.
29. The chip assembly according to any of claims 16 to 25,
the chip terminal is arranged on the surface of the chip far away from one side of the reinforcing layer.
30. An electronic device, comprising a chip assembly according to any one of claims 16 to 29.
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| CN202110296741.9A CN113066727A (en) | 2021-03-19 | 2021-03-19 | Chip assembly manufacturing method, chip assembly and electronic equipment |
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| CN202110296741.9A CN113066727A (en) | 2021-03-19 | 2021-03-19 | Chip assembly manufacturing method, chip assembly and electronic equipment |
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Cited By (1)
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|---|---|---|---|---|
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