CN113066448A

CN113066448A - Source driver and display device

Info

Publication number: CN113066448A
Application number: CN202011437748.XA
Authority: CN
Inventors: 谷口直树; 土弘; 大野崇
Original assignee: Lapis Semiconductor Co Ltd
Current assignee: Lapis Semiconductor Co Ltd
Priority date: 2019-12-13
Filing date: 2020-12-11
Publication date: 2021-07-02
Anticipated expiration: 2040-12-11
Also published as: JP2021096451A; JP6952819B2; CN113066448B; JP2022008587A

Abstract

The invention relates to a source driver and a display device. Provided is a source driver capable of suppressing occurrence of luminance unevenness. The video display device includes a data latch unit for sequentially inputting groups of pixel data pieces from a video data signal at predetermined intervals and sequentially outputting the m pieces of pixel data pieces from m output terminals, a gradation voltage conversion unit for sequentially inputting the pieces of pixel data output from the data latch unit and converting the pieces of pixel data into gradation voltages, an output unit for amplifying the gradation voltages and outputting the amplified gradation voltages to source lines, and a timing control unit for controlling output timings of the pieces of pixel data of the data latch unit. Each of the n pixel data piece groups is a pixel data piece group corresponding to a gradation voltage signal to which a pixel column along each of the n gate lines is supplied. The timing control section controls the timing difference between the introduction of the group of pixel data pieces by the data latch section and the output of the pixel data pieces to be smaller as the length from the source driver to the source line of the pixel column becomes longer.

Description

Source driver and display device

Technical Field

The invention relates to a source driver and a display device.

Background

As a driving method of a display device including a display device such as a liquid crystal display (lcd) or an organic EL (Electro Luminescence), an active matrix driving method is adopted. In the active matrix driving type display device, a display panel is formed of a semiconductor substrate in which pixel portions and pixel switches (switches) are arranged in a matrix. On/off of the pixel switches is controlled by the gate signals, and when the pixel switches are turned on, the gray scale voltage signals corresponding to the video data signals are supplied to the pixel portions, and the luminance of each pixel portion is controlled, thereby performing display. The gate signal is supplied to the pixel switch by a gate driver via a scanning line (also referred to as a gate line). The supply of the gradation voltage signal to the pixel portion is performed by the source driver via the source line. The gate driver supplies at least a binary gate signal, and the source driver supplies a multi-level gradation voltage signal corresponding to the gradation voltage.

In a display device in which a gate driver and a source driver are arranged on one side of a display panel, there are cases in which: the image quality of the display image is deteriorated due to a bias of a wiring load caused by a wiring resistance or a capacitance of the wiring between the gate driver (i.e., the scan driver) and each scan line. In view of the above, a display device has been proposed in which a display panel is divided into a plurality of regions according to a wiring load of a wiring between a scan driver and each scan line, and a gate signal having a different pulse width is applied to the scan line for each region (for example, patent document 1).

Documents of the prior art

Patent document

Patent document 1: japanese patent No. 5380765.

Disclosure of Invention

Problems to be solved by the invention

In recent years, as a display device used for a TV or a monitor, there has been an increasing demand for a display device having a display panel with high resolution and a large screen such as a 4K panel (pixel row: 3840 × RGB, pixel row: 2160) or an 8K panel (pixel row and pixel row 2 times as large as the 4K panel). In such a display device having a display panel with a large screen, driving of the display panel by high-resolution and high-speed display is required. This increases the wiring resistance (load capacitance) of the source line and the scan line, and increases the parasitic resistance and capacitance of the display panel.

For example, when the load capacitance of the source line becomes large, there is almost no slowness of rising and falling at a position on the source line where the distance from the source driver is relatively short with respect to the signal waveform of the gradation voltage signal supplied from the source driver, whereas the slowness of rising and falling increases as the distance from the source driver becomes relatively long. As a result, an output delay occurs, and the charging rate of the pixel electrode is lowered at a position on the source line relatively distant from the source driver. Therefore, there is a problem that: the writing voltage cannot be made constant in the display panel, and image quality deterioration due to luminance unevenness or the like occurs. Further, there is a problem that: when the wiring resistance (spread wiring width) of the scan line or the source line is reduced in order to reduce the luminance unevenness, the transmittance of the panel is lowered.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of suppressing occurrence of luminance unevenness due to a decrease in writing voltage in a pixel electrode.

Means for solving the problems

A source driver according to the present invention is a source driver connected to a display panel having m × n pixel portions provided in a matrix at each of intersections of m source lines and n gate lines (m and n are integers equal to or greater than 2), the source driver receiving video data signals of 1 frame each formed by n pixel data piece groups of m pixel data pieces in succession and generating, based on the video data signals, grayscale voltage signals to be supplied to each of the m × n pixel portions, the source driver including: a data latch unit that sequentially introduces the n pixel data piece groups at a predetermined cycle from the video data signal, and sequentially outputs the m pixel data pieces included in the introduced pixel data piece group from m output terminals corresponding to the m source lines; a gradation voltage converting section for sequentially inputting the m pieces of pixel data outputted from the data latch section and converting the m pieces of pixel data into m gradation voltages; an output unit which amplifies the m gray voltages and outputs the amplified m gray voltages to the m source lines; and a timing control unit that controls a timing of output of the m pieces of pixel data from the data latch unit, each of the n pieces of pixel data being a piece of pixel data corresponding to a gradation voltage signal to be supplied to each of n pixel columns including pixel units arranged along each of the n gate lines, wherein the timing control unit controls the timing of output of the data latch unit such that a timing difference between a piece of pixel data corresponding to a gradation voltage signal to be supplied to the pixel column, which is introduced by the data latch unit, and a timing of output of the data latch unit of the m pieces of pixel data constituting the piece of pixel data becomes smaller as a length of a source line from the source driver to the pixel column becomes longer.

Further, a display device according to the present invention is a display device including: a display panel having m source lines and n gate lines (m and n are integers of 2 or more), and m × n pixel units provided in a matrix at each of intersections of the m source lines and the n gate lines; a display controller outputting a video data signal formed by a plurality of pixel data pieces being continuous; a gate driver configured to supply gate signals to the m × n pixel units via the n gate lines; and a plurality of source drivers provided for every predetermined number of source lines among the m source lines, receiving supply of the video data signal from the display controller, and outputting a gradation voltage signal based on the video data signal to each of the predetermined number of source lines in accordance with a timing at which the gate signal is supplied from the gate driver, each of the plurality of source drivers including: a data latch unit that sequentially introduces pieces of pixel data included in the video data signal at a predetermined cycle for each of the predetermined number of pieces of pixel data and outputs the pieces of pixel data from output terminals corresponding to the predetermined number of source lines; a gradation voltage conversion unit that sequentially introduces the predetermined number of pieces of pixel data output from the data latch unit and converts the pieces of pixel data into the predetermined number of gradation voltage signals; an output unit which amplifies the predetermined number of gradation voltage signals and outputs the amplified signals to the predetermined number of source lines; and a timing control section that controls a timing of output of the pixel data pieces from the data latch section, the timing control section including: a first output delay setting section that sets a first delay time such that a time interval from introduction to output of the data latch section of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel sections becomes larger as a length of the gate line from the gate driver to each of a predetermined number of pixel sections becomes longer; and a second output delay setting unit that sets a second delay time such that a time interval from the introduction to the output of the data latch unit of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel units becomes smaller as a distance from the source driver to each gate line to which each of the predetermined number of pixel units is assigned becomes longer, and controls a timing of the output of the pixel data piece from the data latch unit based on an output delay time determined by the first delay time and the second delay time.

Effects of the invention

According to the source driver of the present invention, it is possible to suppress the occurrence of luminance unevenness due to a decrease in write voltage.

Drawings

Fig. 1 is a block diagram showing the structure of a display device of the present invention.

Fig. 2 is a block diagram showing an internal structure of the source driver of the present invention.

Fig. 3 is a block diagram showing the internal structure of the timing control section of embodiment 1 together with the source control core and the data latch section.

Fig. 4 is a timing chart showing output timings of respective signals in the operation of the source driver of embodiment 1.

Fig. 5 is a diagram schematically illustrating a pixel region on a display panel corresponding to a distance from a gate driver and a source driver.

Fig. 6 is a diagram showing signal waveforms of the gate signal and the gradation voltage signal of example 1 in each pixel region of fig. 5.

Fig. 7 is a block diagram showing the internal structure of the timing control section of embodiment 2 together with the source control core and the data latch section.

Fig. 8 is a conceptual diagram of an image showing the setting of the output delay and the delay time of each source driver IC of embodiment 2.

Fig. 9 is a timing chart showing output timings when source output is performed from the near end of the source driver toward the far end in embodiment 2.

Fig. 10 is a timing chart showing output timings in a case where source output is performed from the far end toward the near end of the source driver in embodiment 2.

Fig. 11 is a diagram showing signal waveforms of a gate signal and a gradation voltage signal in each pixel region in embodiment 2.

Fig. 12 is a diagram showing signal waveforms of gate signals and gradation voltage signals in each pixel region of a comparative example in which adjustment of output delay is performed in consideration of only the gate line direction.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to substantially the same or equivalent parts.

[ example 1]

Fig. 1 is a block diagram showing the structure of a display device 100 of the present invention. The display device 100 is a liquid crystal display device of an active matrix driving method. The display device 100 includes a display panel 11, a display controller 12,

gate drivers

13A and 13B, and source drivers 14-1 to 14-p.

The display panel 11 has a plurality of pixel portions P arranged in a matrix₁₁～P_nmAnd a pixel switch M₁₁～M_nmA semiconductor substrate (n, m: a natural number of 2 or more). The display panel 11 includes n gate lines GL1 to GLn and m source lines SL1 to SLm arranged to intersect the gate lines GL1 to GLn. In the following description, any 1 gate line among the n gate lines GL1 to GLn may be referred to as a gate line GLk, and any 1 source line among the m source lines SL1 to SLm may be referred to as a source line SLx. Pixel part P₁₁～P_nmAnd a pixel switch M₁₁～M_nmProvided at intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm.

Pixel switch M₁₁～M_nmAre controlled to be on or off in accordance with the gate signals Vg1 to Vgn supplied from the gate driver 13.

Pixel part P₁₁～P_nmThe source drivers 14-1 to 14-p receive the grayscale voltage signals Vd1 to Vdm corresponding to the video data. At the pixel switch M₁₁～M_nmWhen turned on, the grayscale voltage signals Vd 1-Vdm are supplied to the pixel portion P₁₁～P_nmEach pixel electrode of (2) charges each pixel electrode. According to the pixel part P₁₁～P_nmControls the pixel portion P by the gray scale voltage signals Vd 1-Vdm of each pixel electrode₁₁～P_nmThereby performing display. In the following description, Vdx may denote any 1 of the grayscale voltage signals Vd1 to Vdm.

In the case where the display device 100 is a liquid crystal display device, the pixel portion P₁₁～P_nmEach including a transparent electrode, not shown, and a liquid crystal sealed between the liquid crystal and a counter substrateThe substrate and the semiconductor substrate were disposed to face each other, and 1 transparent electrode was formed on the entire surface. For the backlight inside the display device, according to the supply to the pixel part P₁₁～P_nmThe potential difference between the gray scale voltage signals Vd1 to Vdm and the counter substrate voltage changes the transmittance of the liquid crystal, thereby performing display.

The display controller 12 generates a video data signal VDs comprising a sequence of pixel data slices PD (also referred to as video data slices PD) representing the luminance levels of the respective pixels with a luminance grayscale of 256 phases of, for example, 8 bits, based on the video data VD. The video data signal VDS is a video data signal formed by serializing the video data signal according to the number of transmission lines for each predetermined number of source lines.

In the present embodiment, the video data signal VDS of 1 frame amount is constituted by sequentially continuing n pixel data slice groups each constituted by m pixel data slices PD. Each of the n pixel data piece groups is a pixel data piece group in which n pixel columns each including a pixel portion arranged along each of the gate lines GL1 to GLn are each a pixel data piece corresponding to a gradation voltage signal to be supplied. Then, by the operation of the source drivers 14-1 to 14-P, n × m pixel sections (i.e., pixel sections P) are generated based on the m × n pieces of pixel data PD₁₁～P_nm) The gradation voltage signals Vd1 to Vdm to be supplied.

The display controller 12 generates a clock signal CLK of an embedded clock system in which the period of a clock pulse (hereinafter, referred to as a clock period) is constant. Then, the display controller 12 supplies the sequence signal in which the clock signal CLK is integrated with the video data signal VDS to each of the source drivers 14-1 to 14-p, and performs display control of the video data.

Further, the display controller 12 supplies a gate timing signal GS to the

gate drivers

13A and 13B provided at both ends of the display panel 11.

The

gate drivers

13A and 13B supply the gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the gate timing signal GS supplied from the display controller 12. By the supply of the gate signals Vg 1-Vgn, every timePixel portion P is selected by pixel row₁₁～P_nm. Then, the gray scale voltage signals Vd1 to Vdm are supplied from the source drivers 14-1 to 14-p to the selected pixel section, whereby the gray scale voltage signals Vd1 to Vdm are written to the pixel electrode.

The source drivers 14-1 to 14-p are provided for every predetermined number of source lines obtained by dividing the source lines SL1 to SLm. The number of source lines driven by each source driver corresponds to the number of outputs ch of the source driver. For example, when a display panel has 960 ch outputs per 1 source driver and 1 source line per 1 pixel column, a 4K panel drives the source lines by 12 source drivers, and an 8K panel drives the source lines by 24 source drivers. In the present embodiment, the following description will be given, taking as an example a case where each of the source drivers 14-1 to 14-p drives k (k is an integer not less than 2 and not more than m) source lines (that is, a case where the number of output ch is k). Each of the source drivers 14-1 to 14-p is formed on a semiconductor IC (Integrated Circuit) chip.

The source drivers 14-1 to 14-p receive a sequence signal in which the clock signal CLK and the video data signal VDS are integrated from the display controller 12, and supply the sequence signal from the display controller 12 through different transmission paths. A differential signal in which k ch-numbered video data signals VDS and clock signals CLK are sequentially outputted is supplied to the source drivers 14-1 to 14-p for 1 data period.

Fig. 2 is a block diagram showing the internal structure of the source driver 14-1. The other source drivers 14-2 to 14-p have the same structure. The source driver 14-1 includes a source control core 20, a data latch section 21, a gradation voltage conversion section 22, an output section 23, and a timing control section 24.

The source control core 20 supplies the LOAD signal LOAD to the data latch section 21, and performs control of importing video data (i.e., importing from a sequence of pixel data pieces PD in the video data signal VDS) by the data latch section 21. The source control core 20 controls a timing control section 24, and the timing control section 24 is a circuit block that controls the timing of data output from the data latch section 21.

The data latch section 21 sequentially imports a sequence of pixel data pieces PD included in the video data signal VDS supplied from the display controller 12. At this time, the data latch section 21 imports the pixel data piece PD according to the control by the source control core 20.

The data latch section 21 outputs the pixel data pieces PD, which are introduced, to the gradation voltage converting section 22 as pixel data Q1 to Qk in accordance with the introduction of the pixel data pieces PD of the number of output ch of the source driver 14-1 (that is, k ch). The data latch unit 21 has k output terminals corresponding to the source lines SL1 to SLk driven by the source driver 14-1, and outputs pixel data Q1 to Qk from the k output terminals. At this time, the data latch unit 21 outputs the pixel data Q1 to Qk at a timing corresponding to the control of the timing control unit 24.

The gradation voltage converting section 22 converts each of the pixel data Q1 to Qk supplied from the data latch section 21 into the gradation voltages a1 to Ak having voltage values corresponding to the luminance gradation represented by the pixel data, and supplies the converted voltage to the output section 23.

The output unit 23 generates signals for amplifying the grayscale voltages a1 to Ak into grayscale voltage signals Vd1 to Vdk, and supplies the grayscale voltage signals to the source lines SL1 to SLk, respectively.

The timing control unit 24 controls the output timing of the pixel data Q1 to Qk by the data latch unit 21.

Fig. 3 is a block diagram showing the internal structure of the timing control section 24 together with the source control core 20 and the data latch section 21. The timing control section 24 includes a gate line counter 31, a register 32, and an output timing control circuit 33.

The source control core 20 controls the timing control section 24 based on the video data signal VDS supplied from the display controller 12 and the common setting information CS read out from the register 32. For example, the source control core 20 detects the timing of each 1 horizontal scanning line (i.e., gate line) of the sequence of pixel data pieces PD included in the video data signal VDS, and supplies a signal showing the timing to the gate line counter 31 as the line signal LS. Further, the source control core 20 detects the timing of every 1 frame (i.e., 1 screen of the display panel 11) of the sequence of the pixel data pieces PD included in the video data signal VDS, and supplies a signal showing the timing to the gate line counter 31 as a frame signal FS.

Further, the source control core 20 generates a LOAD signal LOAD based on the timing of each 1 horizontal scanning line of the pixel data pieces PD included in the video data signal VDS, and supplies to the output timing control circuit 33 and the data latch section 21.

The gate line counter 31 counts based on the frame signal FS and the line signal LS supplied from the source control core 20, and outputs a count value as a counter output COUT. The line signal LS is a signal indicating the timing of each 1 horizontal scanning line (i.e., gate line) of the sequence of pixel data pieces PD included in the video data signal VDS, and therefore, the counter output COUT of the gate line counter 31 is a value showing the result of counting the pixel data pieces PD included in the video data signal VDS by each gate line.

The gate line counter 31 supplies the counter output COUT to the output timing control circuit 33. Thereby, the output timing control circuit 33 is notified of which gate line each of the pixel data pieces PD included in the video data signal VDS is display data of which output object.

The register 32 stores various setting information related to the source output from the source driver 14-1. For example, the register 32 stores, as the common setting information CS, information on the driving order of the source lines by the source driver 14-1 (i.e., the order of supplying the gradation voltage signals Vd in the horizontal direction of the display panel 11) and in what order the gradation voltage signals Vd are supplied to the intersections of the source lines and the gate lines on 1 source line (i.e., the driving order of the gradation voltage signals Vd in the vertical direction of the display panel 11).

For example, in the present embodiment, the source driver 14-1 drives the source lines SL1 to SLk in order from the source line close to the gate driver 13A (i.e., in order from SL1 to SLk). The source driver 14-1 of the present embodiment supplies the grayscale voltage signals Vd1 to Vdk in the order from the pixel portion on the gate line GL1, which is closer to the source driver 14-1, to the pixel portion on the gate line GLn, which is farther from the source driver 14-1, among the pixel portions located at the intersections of the source lines and the gate lines GL1 to GLn (that is, in the order from GL1 to GLn). These pieces of information are stored as general setting information CS in the register 32.

Further, the register 32 stores timing adjustment setting information TA. The timing adjustment setting information TA is setting information for adjusting the timing of the source output (i.e., the supply of the grayscale voltage signals Vd1 to Vdk to the pixel portions on the source lines SL1 to SLk) of the source driver 14-1 in accordance with the intersection positions with the gate lines GL1 to GLn.

In the present embodiment, for example, regarding the supply of the grayscale voltage signal Vd1 to the pixel portion disposed along the source line SL1 (i.e., the pixel portion at the intersection with each of the gate lines GL1 to GLn), the timing is adjusted so that the time interval of the supply of the grayscale voltage signal Vd1 becomes shorter from the pixel portion on the gate line GL1 closer to the source driver 14-1 toward the pixel portion on the gate line GLn farther from the source driver 14-1.

More specifically, in the present embodiment, the timing of the output of the pixel data Q1 to Qk from the data latch unit 21 to the gradation voltage conversion unit 22 is controlled to supply the gradation voltage signal to the pixel unit P₁₁～P_nkAdjustment of output timing of (1). The k pixel data pieces PD of 1 line introduced by the data latch section 21 correspond to the gradation voltage signals to be supplied to the k pixel sections (hereinafter, referred to as pixel columns) of 1 line arranged along the gate lines. The data latch section 21 imports the pixel data pieces PD at regular time intervals. Therefore, in the present embodiment, the timing is adjusted so that the timing difference between the timing of introducing the pixel data piece PD by the data latch section 21 and the timing of outputting the pixel data Q1 to Qk becomes smaller as the length from the source driver to the source line of the pixel column becomes longer. The setting information to be used for such timing adjustment is stored in the register 32 as timing adjustment setting information TA.

Further, the register 32 stores extension (spread) adjustment setting information SA. The extension adjustment setting information SA is setting information for adjusting a difference in output timing from the source output to the source output of the front head ch to the final head ch of the source driver 14-1 (i.e., a timing difference in supply of the grayscale voltage signal Vdk to the pixel portion on the source line SL1 from among the pixels at the intersections of each of the gate lines GL1 to GLn and each of the source lines SL1 to SLk to the grayscale voltage signal Vd1 to the pixel portion on the source line SLk).

For example, in the present embodiment, the timing is adjusted so that the time interval between the supply of the grayscale voltage signals Vd1 to Vdk from the head ch to the final ch becomes longer from the pixel portion on the source line SL1 closer to the gate driver 13A toward the pixel portion on the source line SLk farther from the gate driver 13A, that is, the time interval between the supply of the grayscale voltage signals between adjacent ch increases in accordance with the distance from the gate driver 13A.

More specifically, in the present embodiment, the output timing of the data latch section 21 is adjusted so that the timing difference between the output timing of pixel data to be supplied to 1 pixel section constituting a pixel column and the output timing of pixel data to be supplied to another pixel section adjacent to the 1 pixel section becomes larger as the length of the gate line from the gate driver to each pixel section of the pixel column becomes longer. Accordingly, the time difference in the output timing of the pixel data corresponding to the adjacent pixel units constituting the pixel column increases in accordance with the distance from the gate driver, and as a result, the time interval between the supply of the gradation voltage signals between adjacent ch increases in accordance with the distance from the gate driver 13A. The setting information to which such timing adjustment is to be performed is stored in the register 32 as the extended adjustment setting information SA.

In addition, the register 32 stores setting information for adjusting the timing of the source output in the adjoining portion of each of the source drivers 14-1 and 14-2. That is, in the present embodiment, the source drivers 14-1 to 14-p are divided to supply the gray scale voltage signals Vd1 to Vdm to the source lines SL1 to SLm. Therefore, it is necessary to perform timing adjustment so that the output of the final ch of the adjacent 1 source driver and the output of the head ch of the other source driver are smoothly and continuously performed. Information on control of the timing of output of the pixel data Q1 to Qk from the data latch section 21 for performing such timing adjustment is stored in the register 32 as setting information.

The output timing control circuit 33 generates a source output start signal SS based on the LOAD signal LOAD supplied from the source control core 20 and the timing adjustment setting information TA read from the register 32, and supplies the source output start signal SS to the data latch section 21. The source output start signal SS is a signal showing the timing of the start of the source output in the front header ch of the source driver 14-1. Actually, the timing control section 24 is a circuit section that controls the data latch section 21, and therefore, the output of the pixel data Q1 to Qk from the data latch section 21 to the gradation voltage conversion section 22 is started based on the source output start signal SS. In response to this, the gray-scale voltages a1 to Ak are output from the gray-scale voltage conversion unit 22 to the output unit 23, and the gray-scale voltage signals Vd1 to Vdk are output from the output unit 23.

The output timing control circuit 33 generates an extended setting signal SP based on the timing adjustment setting information TA and the extended adjustment setting information SA read from the register 32, and supplies the extended setting signal SP to the data latch unit 21. The extension setting signal SP is a setting signal for setting the timing of output of the pixel data Q1 to Qk from the data latch section 21 for each line (i.e., for each gate line).

The data latch section 21 imports a sequence of pieces of pixel data PD from the video data signal VDS based on the clock signal CLK, and determines importation of pieces of pixel data PD of 1 line amount (i.e., k pieces of pixel data PD) based on the LOAD signal LOAD supplied from the source control core 20. Then, the data latch section 21 starts the output of the pixel data Q1 in accordance with the source output start SS from the output timing control circuit 33, and outputs the pixel data Q2 to Qk at the timing set by the extended setting signal SP.

Next, the operation of the source driver 14-1 of the present embodiment will be described with reference to the timing chart of fig. 4.

The source control core 20 receives the supply of the video data signal VDS from the display controller 10, detects the head position of 1 frame of the sequence of the pixel data pieces PD included in the video data signal VDS, and supplies the frame signal FS showing the start of the 1 frame of the pixel data pieces PD to the gate line counter 31. As shown in fig. 4, the frame signal FS is a binary signal showing the leading position of the pixel data piece PD by 1 frame amount with, for example, 1 pulse.

Further, the source control core 20 detects the leading position of the pixel data piece PD for every 1 line (i.e., every gate line) included in the video data signal VDS, and supplies a line signal LS showing the leading position to the gate line counter 31. As shown in fig. 4, the line signal LS is a binary signal showing the leading position of the pixel data pieces PD for every 1 line with 1 pulse.

Further, the source control core 20 generates a LOAD signal LOAD based on the video data signal VDS, and supplies to the output timing control circuit 33 and the data latch section 21. As shown in fig. 4, the LOAD signal LOAD is a binary signal showing a lead-in period corresponding to the pixel data piece PD for 1 line at a certain interval by 1 pulse.

The gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT indicating a count value. For example, when the number of the gate lines GL1 to GLn is 4320 (i.e., n = 4320), the value of the counter output COUT rises from 0 to 4319 for every 1 pulse of the line signal LS as shown in fig. 4.

The output timing control circuit 33 supplies the extended setting signal SP to the data latch section 21 based on the timing adjustment setting information TA and the extended adjustment setting information SA read from the register 32. Thereby, the setting of the output timing of the pixel data Q1 to Qk by the data latch unit 21 is switched. For example, as shown in fig. 4, switching of setting is performed every 2 lines (i.e., every 2 gate lines) in the sequence of the pixel data pieces PD.

The output timing control circuit 33 supplies the source output start signal SS to the data latch section 21 based on the LOAD signal LOAD and the timing adjustment setting information TA read from the register 32. The source output start signal SS is a binary signal showing the start of source output for every 1 line with, for example, 1 pulse.

The signal level of the source output start signal SS changes with delay from the change of the signal level of the LOAD signal LOAD. Then, the time difference between the signal changes of the source output start signal SS and the LOAD signal LOAD (hereinafter, referred to as the delay time of the source output start signal SS) changes according to the distance between the line to which the source output start signal SS is applied and the source driver 14-1.

For example, in the present embodiment, as described above, the timing difference between the timing of introduction of the pixel data piece PD by the data latch section 21 and the timing of output of the pixel data Q1 to Qk is set so as to become smaller as the length from the source driver 14-1 to the source line of the pixel column (i.e., 1 line worth of pixel sections arranged along the gate line) becomes longer. Therefore, the time difference between the supply of the gradation voltage signals Vd1 to Vdk, which are the final source outputs, and the LOAD signal LOAD also becomes shorter as the length from the source driver 14-1 to the source line of the pixel portion becomes longer. Therefore, as shown in fig. 4, the delay time of the source output start signal SS is longer in the first line (gate line GL1, count 0), and the delay time of the source output start signal SS becomes smaller toward the final line (gate line GLn, count 4319).

The data latch section 21 outputs the pixel data Q1 corresponding to the leading head ch of the source driver 14-1 (i.e., the source line SL 1) at a timing corresponding to a change in the signal level of the source output start signal SS. In fig. 4, a binary signal indicating the output timing of the pixel data Q1 is shown as "source output SOUT (chip front header)".

The data latch section 21 sequentially outputs pixel data Q1 to Qk from pixel data Q1 corresponding to the head ch of the source driver 14-1 to pixel data Qk corresponding to the final ch (i.e., the source line SLk). At this time, the data latch section 21 changes the pixel data Q1 to Qk for every 2 lines (that is, the pixel data Q1 to Qk for every 2 gate lines) in accordance with the setting of the extension setting signal SP.

For example, in the present embodiment, as described above, the timing difference of the output of the pixel data from the data latch section 21 corresponding to the gradation voltage signal to be supplied to the adjacent pixels is set to be larger as the length from the source driver 14-1 to the source line of the pixel column (i.e., 1 line of pixel sections arranged along the gate line) becomes longer. Therefore, the time difference in the supply timing between adjacent ch becomes larger as the length from the source driver 14-1 to the source line of the pixel portion becomes longer, with respect to the supply of the gradation voltage signals Vd1 to Vdk which are the final source outputs. Therefore, the time interval from the output of the head ch to the output of the final ch also increases in accordance with the distance from the source driver 14-1. As a result, as shown as "source output SOUT (chip final ch)" in fig. 4, in the first line (gate line GL1, count 0), the time difference between the output of the pixel data Q1 corresponding to the head ch and the output of the pixel data Qk corresponding to the final ch is small, and the time difference increases as going to the final line (gate line GLn, count 4319).

As described above, in the source driver 14-1 of the present embodiment, the timing of the output of the pixel data Q1 to Qk from the data latch section 21 is adjusted, and as a result, the timing of the supply of the gradation voltage signals Vd1 to Vdk from the source driver 14-1 to the pixel section is adjusted. In addition, the same timing adjustment is performed in each of the source drivers 14-2 to 14-p. By such timing adjustment, the pixel portion P can be made₁₁～P_nmThe pixel charging rate in (1) becomes uniform. This is explained with reference to fig. 5 and 6.

FIG. 5 is a diagram schematically showing pixel positions on the display panel corresponding to distances from the

gate drivers

13A, 13B and the source drivers 14-1 to 14-p.

The region of the pixel section closer to the

gate driver

13A or 13B and closer to the source drivers 14-1 to 14-p is shown as "GnSn". In addition, the region of the pixel section which is farther from the

gate driver

13A or 13B and closer to the source drivers 14-1 to 14-p is shown as "GfSn". The region of the pixel section which is closer to the

gate driver

13A or 13B and is at an intermediate distance from the source drivers 14-1 to 14-p (i.e., near the center of the display panel 11) is shown as "GnSc". The region of the pixel section that is far from the

gate driver

13A or 13B and is at an intermediate distance from the source drivers 14-1 to 14-p (i.e., near the center of the display panel 11) is shown as "GfSc". In addition, the region of the pixel section closer to the

gate driver

13A or 13B and farther from the source drivers 14-1 ~ 14-p is shown as "GnSf". The region of the pixel section distant from the

gate driver

13A or 13B and distant from the source drivers 14-1 to 14-p is shown as "GfSf".

Fig. 6 is a diagram showing signal waveforms of gate signals and gray voltage signals in each pixel region of fig. 5. In the figure, "1H" shows a period in which the signal level of the gradation voltage signal becomes H level, and "0E" shows an offset period for writing. The gate signal shows an example of a signal waveform in which a gate selection period (high-level period) during which preliminary charging (so-called gate precharge) is performed on a pixel portion to be selected is long, and a rising portion of the gate signal is omitted.

In GnSn, since the influence of the impedance of the Gate line is small as the distance from the

Gate driver

13A or 13B is short, the slowness of the drop of the signal waveform (shown as Gate in the figure) of the Gate signal is small (or almost zero). Further, since the source line impedance has a small influence when the source line is close to the source drivers 14-1 to 14-p, the rising and falling of the signal waveform (Data in the figure) of the gradation voltage signal are less sluggish (or almost no).

In contrast, GnSc is closer to the

gate driver

13A or 13B, and therefore the fall of the signal waveform of the gate signal is less sluggish (or almost no), but is farther from the source drivers 14-1 to 14-p than GnSn, and therefore, the rise and fall of the signal waveform of the gradation voltage signal are sluggish due to the influence of the impedance of the source line.

Similarly, in GnSf, the slowness of the fall of the signal waveform of the gate signal is small (or almost zero), but the distance from the source drivers 14-1 to 14-p is longer than GnSc, and therefore, the influence of the impedance of the source line is large, and the slowness of the rise and fall of the signal waveform of the gradation voltage signal becomes large.

In the present embodiment, as shown in fig. 4, it is set such that the delay time of the source output SOUT (i.e., the time difference from the LOAD signal LOAD) becomes larger as the value of the counter output COUT becomes larger, that is, becomes smaller as the distance from the source driver to the gate line becomes longer. Therefore, as shown in fig. 6, the gradation voltage signal in GnSc has a signal waveform that changes at a timing earlier than the gradation voltage signal in GnSn with reference to the timing of the fall of the gate signal. Further, the gradation voltage signal in GnSf is a signal waveform that changes at an earlier timing with reference to the timing of the fall of the gate signal.

It is assumed that, without performing timing adjustment of source output as in this embodiment, the signal waveform of the gradation voltage signal in GnSf becomes a signal waveform as shown by one-dot broken lines in GnSc and GnSf of fig. 6. Therefore, in GnSf, the gate signal falls before the gray scale voltage signal sufficiently rises, and the pixel electrode cannot be sufficiently charged by the supply of the gray scale voltage signal.

In contrast, by adjusting the timing of the source output as in the present embodiment so that the timing of the gradation voltage signal based on the gate signal is relatively advanced, the pixel electrode can be charged at the time point when the signal waveform of the gradation voltage signal sufficiently rises in GnSf.

Further, in the present embodiment, the time difference between the respective ch of the source outputs SOUT is set so as to become larger as the value of the counter output COUT becomes larger, that is, as the distance from the source driver to the gate line becomes longer (that is, the time difference between the leading ch and the final ch becomes larger). This is because, as shown by GfSn, GfSc, and GfSf in fig. 6, in a pixel region which is distant from the

gate driver

13A or 13B, the drop of the signal waveform of the gate signal is largely retarded by the influence of the impedance of the gate line.

That is, in the pixel region distant from the

gate driver

13A or 13B, the rising and falling dullness of the signal waveform of the gradation voltage signal is large in accordance with the distance from the source driver, but the falling dullness of the signal waveform of the gate signal is also large. Therefore, the dullness of the rise and fall of the signal waveform of the gradation voltage signal does not affect the charging to the pixel electrode in the pixel region closer to the

gate driver

13A or 13B.

That is, in the pixel regions GfSn, GfSc, and GfSf which are distant from the

gate drivers

13A and 13B, unlike the pixel regions which are close to the

gate drivers

13A and 13B, it is not necessary to advance the timing of the gradation voltage signal even if the distance from the source driver to the gate line becomes distant. Therefore, as shown in fig. 4, the timing of the gray-scale voltage signals in the pixel regions distant from the

gate drivers

13A and 13B is adjusted so that the time difference between the respective ch periods of the source outputs SOUT is controlled to be larger as the distance from the source driver to the gate line becomes longer.

As described above, in the source drivers 14-1 to 14-p of the present embodiment, in the pixel region closer to the

gate driver

13A or 13B, the relative timing of the gradation voltage signal with respect to the gate signal is adjusted so as to become earlier as the distance from the source driver becomes farther. Thus, even when dullness occurs in the signal waveform of the gradation voltage signal due to the influence of the impedance of the source line, the pixel electrode can be sufficiently charged.

On the other hand, in the pixel region distant from the

gate driver

13A or 13B, when the pixel region is distant from the source driver, although the signal waveform of the gradation voltage signal is blunted due to the influence of the impedance of the source line, the signal waveform of the gate signal is also blunted due to the influence of the impedance of the gate line. Therefore, in the source drivers 14-1 to 14-p of the present embodiment, the timing adjustment is performed so that the gradation voltage signals rise at the same timing regardless of whether the distance from the source driver is close or far. Thus, in the pixel region which is distant from the

gate driver

13A or 13B, the pixel electrode can be sufficiently charged regardless of the distance from the source driver. As a result, the occurrence of luminance unevenness due to a decrease in the writing voltage is suppressed.

[ example 2]

Next, example 2 of the present invention will be explained. The display device of embodiment 2 is different from the display device 100 of embodiment 1 in the internal structure and operation of the timing control section 24 of the source driver IC. In the following description, the IC constituting the source driver 14-1 is referred to as IC1, and the IC constituting the centrally located source driver 14-y among the source drivers 14-1 to 14-p is referred to as ICy.

Fig. 7 is a block diagram showing the internal configuration of the timing control section 24 of the display device of embodiment 2 together with the source control core 20 and the data latch section 21. The timing control unit 24 includes a gate line counter 31, a register 32, a gate line direction output delay timing generation unit 41, a source line direction output delay timing generation unit 42, and a setting signal addition unit 43.

The register 32 stores general-purpose setting information CS supplied from the source control core 20, timing adjustment setting information TA that is setting information on adjustment of output timing (delay amount) corresponding to source signal delay, spread adjustment setting information SA that adjusts output timing (delay amount) between source lines corresponding to gate signal delay, and setting information SI that shows timing (delay amount) of start of source output for the head ch (or final ch) of each source driver IC.

The extension adjustment setting information SA includes setting information of the delay amount OE between the source outputs of each source driver IC. The timing adjustment setting information TA includes setting information of the delay amount Ds corresponding to the distance from the source driver.

The register 32 of the present embodiment stores the division number setting information DA for the timing adjustment setting information TA. The division number setting information DA is setting information on the number of steps by which the delay amount Ds corresponding to the distance from the source driver is set for each driver, in other words, information showing the stage to which the setting of the output timing with respect to the extension direction of the source line (hereinafter referred to as the source line direction) is switched. For example, in the present embodiment, information indicating that the setting is changed to the Y stage (settings 1 to Y) is stored in the register 32 as the division number setting information DA for each output of the video data pieces corresponding to 2 gate lines.

The gate-line-direction output delay timing generating unit 41 generates an output timing setting signal TS for setting a delay time of a source output corresponding to a distance in an extending direction of the gate line (hereinafter, referred to as a gate line direction) based on the expansion adjustment setting information SA and the setting information SI read from the register 32. For example, in the present embodiment, the output timing setting signal TS is generated as follows: the signals set the source output timing such that the output delay is small for the output of a source driver IC (e.g., IC 1) that is closer to the

gate driver

13A or 13B, and the output delay is large in a source driver IC (e.g., ICy) that is farther from the

gate driver

13A or 13B.

The source line direction output delay timing generating section 42 generates an output timing setting signal TD for setting a delay time of a source output corresponding to the distance in the source line direction based on the timing adjustment setting information TA and the division number setting information DA read from the register 32. For example, in the present embodiment, the output timing setting signal TD is generated as follows: the signal sets the delay time such that the output delay is relatively large for the source output to which the pixel on the gate line closer to each source driver IC is supplied, and the output delay is relatively small for the source output to which the pixel on the gate line farther from each source driver IC is supplied. In the present embodiment, the output timing setting signal TD is generated as the output timing setting signal TD by changing the output timing for 2 gate lines based on the division number setting information DA to change the setting for 2 gate lines.

The setting signal adder 43 adds the output timing setting signal TS and the output timing setting signal TD to generate an output timing signal LOAD-Gr. The output timing signal LOAD-Gr is an output timing signal group including data output timing in 1 frame of each ch from the latch unit and data output timing between the ch.

The data latch section 21 receives the LOAD signal LOAD from the source control core 20. The LOAD signal LOAD is a timing signal of 1H period based on the line signal LS, and is an introduction timing signal of the video data piece PD into the data latch section 21. The LOAD signal LOAD is a signal linked to the gate-off timing, which is the timing of falling of the gate signals Vg1 to Vgn.

The data latch section 21 imports the piece of video data PD based on the timing of the LOAD signal LOAD. Then, the pixel data Q1 to Qk are output based on the output timing signal LOAD-Gr.

Fig. 8 is a conceptual diagram of an image showing the setting of the output delay and the delay time of each source driver IC of the present embodiment.

The horizontal axis shows the source output of each ch of the respective source driver ICs. The vertical axis shows the delay time of the source output with reference to the LOAD signal LOAD. Further, ts1, ts2, ts3, and ts4 show the start timing of the source output of the front header ch of each source driver IC (here, IC1, IC2, IC3, and IC 4) set based on the setting information SI.

For example, in IC1 (source driver 14-1) which is the source driver IC closest to the gate driver 13A, the delay time of the output delay in the gate line direction is set to the delay amount OE1 based on the output timing setting signal TS. Then, the delay amount OE1 and the delay amount Ds1 corresponding to the distance from the source driver are added to each other, thereby obtaining the delay time of the source output of the IC 1.

In the source driver IC ICy (source driver 14-y) farthest from the

gate drivers

13A and 13B, the delay time of the output delay based on the gate line direction is set to the delay amount OEf based on the output timing setting signal TS. Then, the delay amount OEf is added to the delay amount Dsf corresponding to the distance from the source driver, thereby obtaining a delay time of ICy for the source output.

The gate line direction delay amount OE (OE 1 to OE OEf) is set to change in stages for each predetermined ch even between the leading ch and the final ch of each IC based on the output timing signal LOAD-Gr.

Although fig. 8 shows an example in which each IC is set to 3 stages with respect to the delay amount Ds (Ds 1 to Dsf) of each IC corresponding to the distance from the source driver, the delay amount Ds may be set to any stage (number of steps) for each IC.

Next, the operation of the ICs 1 (source driver 14-1) and ICy (source driver 14-y) of the present embodiment will be described with reference to the timing chart of fig. 9. The timing chart of fig. 9 shows a case where the supply of the gradation voltage signal (i.e., the source output) is performed in a direction from the pixel portion near the source line closer to the source driver toward the pixel portion far from the source line farther from the source driver.

The source control core 20 supplies a frame signal FS showing the start of the video data piece PD of 1 frame amount included in the video data signal VDS to the gate line counter 31. Further, the source control core 20 supplies a line signal LS showing the leading position of the video data piece PD for each 1H period to the gate line counter 31. Further, the source control core 20 generates a LOAD signal LOAD based on the video data signal VDS, and supplies the LOAD signal LOAD to the gate line direction output delay timing generation section 41, the source line direction output delay timing generation section 42, and the data latch section 21.

The gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT indicating a count value. When the number of gate lines n =4320, the value of the counter output COUT rises from 0 to 4319 every 1 pulse of the line signal LS as shown in fig. 9.

The gate line to be supplied with the source output is selected in accordance with the counter output COUT of the gate line counter 31. That is, when the grayscale voltage signals Vd1 to Vdk are supplied from a position on the gate line close to the source driver (i.e., the source line near end) toward a position on the gate line far from the source driver (i.e., the source line far end), the gate lines to which the source outputs are supplied are selected in the order of the gate lines GL1, GL2, GL3, GL4, … GL4318, GL4319, and GL 4320.

The source line direction output delay timing generation unit 42 changes the setting of the delay amount Ds corresponding to the distance from the source driver based on the counter output COUT, the division number setting information DA, and the timing adjustment setting information TA. In this embodiment, the setting of the delay amount Ds is changed every 2 steps of the gate line. The source line direction output delay timing generating section 42 generates an output timing setting signal TD including a setting of the delay amount Ds.

The gate-line-direction output delay timing generating section 41 generates the output timing setting signal TS in which the delay amounts OE1 to OEy are set so that the delay time increases as the distance from the gate driver 13A increases. For example, the delay amount of the source driver 14-1 (IC 1) which is a source driver closer to the gate driver 13A is set to the delay amount OE1, and the delay amount of the source driver 14-y (icy) which is a source driver farther from the gate driver 13A is set to the delay amount OEy. The relationship between the retardation OE 1-OEy is OE1 < OE2 … < OEy.

The setting signal adder 43 adds the output timing setting signal TS generated by the gate line direction output delay timing generator 41 and the output timing setting signal TD generated by the source line direction output delay timing generator 42, and supplies the output timing signal LOAD-Gr, which is the addition result, to the data latch unit 21.

For example, as for the source output of the source driver 14-1, as shown as "TS + TD (IC 1)" in fig. 9, the delay amount by which the delay amount OE1 is added to the delay amount Ds1_1 is set as the delay time for the outputs of the pixel section on the gate line GL1 and the pixel section on GL 2. Further, the delay amount of the delay amount OE1 added to the delay amount Ds1_2 is set as a delay time for the outputs of the pixel section on the gate line GL3 and the pixel section on GL 4. Hereinafter, the delay time is similarly set, and the delay amount obtained by adding the delay amount OE1 to the delay amount Ds1_ Y is set as the delay time for the outputs of the pixel portion on the gate line GL4319 and the pixel portion on GL 4320.

Similarly, regarding the source output of the source driver 14-y, as shown as "TS + td (icy)" in fig. 9, the delay amount of the addition of the delay amount OEy and the delay amount Dsy _1 is set as the delay time for the outputs of the pixel section on the gate line GL1 and the pixel section on GL 2. Further, the delay amount of the delay OEy added to the delay Dsy _2 is set as a delay time for the outputs of the pixel section on the gate line GL3 and the pixel section on GL 4. Hereinafter, the delay time is similarly set, and the delay amount obtained by adding the delay amount OEy to the delay amount Dsy _ Y is set as the delay time for the outputs of the pixel portion on the gate line GL4319 and the pixel portion on the GL 4320.

Further, the retardation Ds is set so that the longer the distance from the source driver to each gate line, the smaller the retardation, and hence Ds1_1 > Ds1_2 > … > Ds1_ Y. Furthermore, Dsy _1 > Dsy _2 > … > Dsy _ Y. In the present embodiment, the setting of the delay amount Ds is changed every 2 gate lines.

The data latch section 21 outputs the pixel data Q1 to Qk with a delay amount (OE + Ds) set based on the output timing signal LOAD-Gr. For example, the data latch section 21 of the source driver 14-1 outputs pixel data Q1 to Qk corresponding to the gradation voltage signals to be supplied to the pixel sections on the gate lines GL1, GL2, GL3, GL4, …, GL4317, GL4318, GL4319, and GL4320 at timings of V1, V2, V3, V4, …, V4317, V4318, V4319, and V4320 as shown as "latch output (IC 1)" in fig. 9. Similarly, the data latch section 21 of the source driver 14-y outputs pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel section of each gate line at the timing shown as "latch output (ICy)" in fig. 9.

Fig. 10 shows a case where supply of a gradation voltage signal (i.e., a source output) is performed in a direction from a pixel portion at a far end of a source line far from a source driver toward a pixel portion at a near end of the source line near the source driver, unlike fig. 9.

As in the timing chart of fig. 9, the gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT indicating a count value. The gate line to be supplied with the source output is selected in accordance with the counter output COUT of the gate line counter 31.

When the grayscale voltage signals Vd1 to Vdk are supplied from a position on a gate line distant from the source driver (i.e., a source line distal end) to a position on the gate line close to the source driver (i.e., a source line proximal end), gate lines to which source outputs are supplied are selected in the order of the gate lines GL4320, GL4319, GL4318, GL4317, … GL3, GL2, and GL 1.

The setting of the delay amounts OE1 to OEy by the gate line direction output delay timing generating section 41, the setting of the delay amount Ds by the source line direction output delay timing generating section 42, and the setting of the added delay amounts to the data latch section 21 are the same as those in the timing chart of fig. 9.

The data latch section 21 outputs the pixel data Q1 to Qk with a delay amount (OE + Ds) set based on the output timing signal LOAD-Gr. For example, the data latch section 21 of the source driver 14-1 outputs pixel data Q1 to Qk corresponding to the gradation voltage signals to be supplied to the pixel sections on the gate lines GL4320, GL4319, GL4318, GL4317, …, GL4, GL3, GL2, and GL1 at timings of V4320, V4319, V4318, V4317, …, V4, V3, V2, and V1 as shown as "latch output (IC 1)" in fig. 10. Similarly, the data latch section 21 of the source driver 14-y outputs pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel section of each gate line at the timing shown as "latch output (ICy)" in fig. 10.

In this way, the output timing can be controlled in the same manner for both the case where the source output is performed from the source line near end toward the far end (fig. 9) and the case where the source output is performed from the source line far end toward the near end (fig. 10).

As described above, in the display device of the present embodiment, the gate line direction output delay timing generation section 41 as the first output delay setting section sets the first delay time (delay amount OE) of the source output so that the delay amount becomes larger as the distance in the gate line direction (i.e., the distance from the gate driver) becomes longer. Further, the source line direction output delay timing generation section 42 as the second output delay setting section sets the second delay time (delay amount Ds) of the source output so that the delay amount becomes smaller as the distance in the source line direction (i.e., the distance from the source driver) becomes longer. Then, the timing control section 24 sets a delay time of adding the first delay time (OE) and the second delay time (Ds) as a delay time of the output of the pixel data Q1 to Qk from the data latch section 21.

By adjusting the timing of the output of the pixel data Q1 to Qk from the data latch section 21 in this manner, the timing of supply of the gradation voltage signals from the source drivers to the pixel section is adjusted. By such timing adjustment, the pixel charging rates of the pixel portions P11 to Pnm can be made uniform for the entire display panel 11.

Fig. 11 is a diagram showing signal waveforms and timings of gate signals and gray voltage signals in each pixel region on the display panel. (1) Each of the regions (1) to (4) corresponds to the regions (GnSn), (GnSf), (GfSn), and (GfSf) of the pixel section shown in fig. 5. The gate signal in fig. 11 also shows an example of a signal waveform in which the gate selection period (high-level period) for preliminarily charging the pixel portion to be selected (so-called gate precharge) is long, as in fig. 6, and the rising portion of the gate signal is omitted.

When GnSn (1) and GfSn (3) are compared, GnSn is closer to the

Gate driver

13A or 13B, and the influence of the impedance of the Gate line is smaller, so that the slowness of the drop of the signal waveform (shown as Gate in the figure) of the Gate signal is smaller. In contrast, in GfSn, the distance from the

gate driver

13A or 13B is long, and the influence of the impedance of the gate line is large, so that the fall of the signal waveform of the gate signal is large. Therefore, the delay amount OE1 is set to be small in GnSn and the delay amount OEf is set to be large in GfSn in accordance with the timing of fall of the gate signal (i.e., the gate-off timing). The same applies to the comparison of GnSf (2) and GfSf (4).

Next, when GnSn (1) and GnSf (2) are compared, GnSn is closer to the source driver, and the influence of the impedance of the source line is small, so that the rising and falling of the signal waveform (shown as Data in the figure) of the gradation voltage signal are less sluggish. On the other hand, GnSf is far from the source driver and has a large influence of the impedance of the source line, so that the rising and falling of the signal waveform of the gradation voltage signal are slow. Therefore, the delay amount Ds (= Ds 1) is set to be large in GnSn and small in GnSf in accordance with the timing of the rise of the source signal and the fall of the gate signal (Ds 1=0 in fig. 11). The same applies to the comparison between GfSn (3) and GfSf (4).

In (1) to (4) of fig. 11, the black-painted portions schematically show the pixel charging rates in the pixel portions of the respective pixel regions. That is, the area of the blackened portion corresponds to the result of integrating the gray scale voltage signal (Data) during a period from the rise of the gray scale voltage signal to the fall of the gate signal below the gray scale voltage.

In the display device of the present embodiment, in the pixel regions (GfSn, GfSf) in which the fall (dullness) of the gate signal is slow, the output of the gradation voltage signal is delayed as compared with the pixel regions in which the fall (sensitivity) of the gate signal is fast, and in the pixel regions (GnSn, GfSn) in which the rise (sensitivity) of the gradation voltage signal is fast, the output of the gradation voltage signal is delayed as compared with the pixel regions (GnSf, GfSf) in which the rise (dullness) of the gradation voltage signal is slow, whereby the timing of the source output is adjusted so that the areas of the blackened portions become the same. This equalizes the charging rates of the pixels in the respective pixel portions within the plane of the display panel.

Fig. 12 is a diagram showing signal waveforms of a gate signal and a gray-scale voltage signal in each pixel region in a comparative example in which adjustment of an output delay is performed in consideration of only the influence of the impedance of a gate line, unlike the display device of the present embodiment.

In comparison between GnSn (1) and GfSn (3), in the pixel region distant from the

gate driver

13A or 13B, the delay amount OE is set to be larger (OEf > OE 1) than in the pixel region close to the

gate driver

13A or 13B, and therefore, the pixel charging rate in GfSn decreases and the difference from the pixel charging rate in GnSn increases. The same applies to the comparison of GnSf (2) and GfSf (4).

In comparison between GnSn (1) and GnSf (2), since the delay time corresponding to the distance from the source driver is not adjusted, the pixel charging rate is lower in a pixel region that is farther from the source driver than in a pixel region that is closer to the source driver.

Therefore, the state is such that the pixel charging rate of the pixel region of GnSn (1) is the highest and the pixel charging rate of the pixel region of GfSf is the lowest, and the difference in pixel charging rate, that is, the difference in luminance in the display panel surface is large.

In contrast, in the display device of the present embodiment, as described above, the delay time of the source output is adjusted in consideration of both the influence of the impedance of the gate line and the influence of the impedance of the source line, and therefore, the difference in the pixel charging rate, that is, the luminance difference can be made uniform within the display panel surface.

The present invention is not limited to the above embodiments. For example, although the display device 100 is a liquid crystal display device in the above embodiment, it may be an organic el (electro luminescence) display device different from the above embodiment. In the case where the display device 100 is an organic EL display device, the pixel portion P₁₁～P_nmEach of which includes an organic EL element and a thin film transistor for controlling a current flowing through the organic EL element. The thin film transistor is supplied to the pixel part P₁₁～P_nmThe gray scale voltage signals Vd1 to Vdm control the current flowing through the organic EL element, and display is performed by changing the emission luminance of the organic EL element in accordance with the current. The present invention can be applied to an organic EL display device as well to suppress the occurrence of luminance unevenness due to a decrease in writing voltage.

In the above-described embodiment, the case where the supply of the gradation voltage signals is performed in the order from the pixel portion on the gate line closer to the source driver to the pixel portion on the gate line farther from the source driver has been described as an example. In contrast, the gray scale voltage signals may be supplied in order from the pixel portion on the gate line distant from the source driver to the pixel portion on the gate line close to the source driver. In this case, the pixel electrode can be charged at a time point when the signal waveform of the gradation voltage signal sufficiently rises as in the above-described embodiment by relatively advancing the timing of supplying the gradation voltage signal to the pixel portion which is distant from the source driver.

In the above-described embodiment, the case where the

gate drivers

13A and 13B are provided on both sides of the display panel 11 and the gate signals are supplied from both sides has been described as an example. However, unlike this, a gate driver may be provided only on one side of the display panel 11, and the gate signal may be supplied from one direction.

In the above embodiment, the case where the gray scale voltage signals are supplied by using the source drivers 14-1 to 14-p as the plurality of source driver ICs has been described as an example. However, a single source driver may be used to supply all the gradation voltage signals. In short, the source driver constituted by a single source driver IC or a plurality of source driver ICs may have the following configuration as a whole.

That is, the source driver is connected to the Source Line (SL) having m source lines₁～SL_m) And n Gate Lines (GL)₁～GL_n) (m and n are integers of 2 or more), and m × n pixel units (P) arranged in a matrix at each of intersections of the m source lines and the n gate lines₁₁～P_nm) The display panel (11) receives a Video Data Signal (VDS) of 1 frame formed by n pixel data slice groups composed of m pixel data slices (PD) and continuously, and generates gray scale voltage signals (Vd 1-Vdm) which are supplied to each of m x n pixel parts based on the video data signal. The source driver has: a data latch unit (21) for sequentially introducing n pixel data piece groups from a video data signal at a predetermined cycle, and sequentially outputting m pixel data pieces included in the introduced pixel data piece groups from m output terminals corresponding to the m source lines(ii) a A gray scale voltage conversion unit (22) for sequentially inputting the m pixel data pieces outputted from the data latch unit and converting the m pixel data pieces into m gray scale voltages; an output unit (23) which amplifies the m gray scale voltages and outputs the amplified m gray scale voltages to the m source lines; and a timing control unit (24) for controlling the timing of the output of the m pieces of pixel data from the data latch unit. Each of the n pixel data piece groups corresponds to a gradation voltage signal to be supplied to each of n pixel columns each including a pixel portion arranged along each of the n gate lines. The timing control section controls the timing of the output of the data latch section so that a timing difference between the timing of the introduction of the data latch section into the pixel data piece group corresponding to the gradation voltage signal to be supplied to the pixel column and the timing of the output of the data latch section from the m pixel data pieces constituting the pixel data piece group becomes smaller as the length from the source driver to the source line of the pixel column becomes longer.

The timing control unit controls the timing of the output of the data latch unit so that a difference between the timing of the output of 1 pixel data piece corresponding to a gradation voltage signal to be supplied to 1 pixel unit constituting the pixel column and the timing of the output of another pixel data piece corresponding to a gradation voltage signal to be supplied to another pixel unit adjacent to the 1 pixel unit constituting the pixel column becomes larger as the length of the gate line from the gate driver to each pixel unit of the pixel column becomes longer.

With such a source driver structure, it is possible to suppress the occurrence of luminance unevenness due to a decrease in the write voltage.

Description of reference numerals

100 display device

11 display panel

12 display controller

13A, 13B gate driver

14-1 to 14-p source driver

20 source control core

21 data latch part

22 gray scale voltage conversion unit

23 output part

24 timing control part

31 gate line counter

32 register

33 output timing control circuit.

Claims

1. A source driver connected to a display panel having m × n pixel portions each having m source lines and n gate lines and arranged in a matrix at each of intersections of the m source lines and the n gate lines, for receiving a video data signal of 1 frame formed by n pixel data piece groups each formed by m pixel data pieces in succession and generating a gradation voltage signal to be supplied to each of the m × n pixel portions based on the video data signal, wherein m and n are integers of 2 or more, the source driver comprising:

a data latch unit that sequentially introduces the n pixel data piece groups at a predetermined cycle from the video data signal, and sequentially outputs the m pixel data pieces included in the introduced pixel data piece group from m output terminals corresponding to the m source lines;

a gradation voltage converting section for sequentially inputting the m pieces of pixel data outputted from the data latch section and converting the m pieces of pixel data into m gradation voltages;

an output unit which amplifies the m gray voltages and outputs the amplified m gray voltages to the m source lines; and

a timing control section that controls a timing of output of the m pieces of pixel data from the data latch section,

each of the n pixel data piece groups is a pixel data piece group corresponding to a gradation voltage signal to which n pixel columns each including a pixel portion arranged along each of the n gate lines are supplied,

the timing control unit controls the timing of the output of the data latch unit such that a timing difference between the timing of the introduction of the data latch unit into a pixel data piece group corresponding to a gradation voltage signal to be supplied to the pixel column and the timing of the output of the data latch unit from m pixel data pieces constituting the pixel data piece group becomes smaller as the length from the source driver to the source line of the pixel column becomes longer.

2. The source driver of claim 1, wherein the timing control section controls the timing of the output of the data latch section such that a difference between the timing of the output of 1 pixel data piece corresponding to a gradation voltage signal to be supplied to 1 pixel section constituting the pixel column and the timing of the output of another pixel data piece corresponding to a gradation voltage signal to be supplied to another pixel section constituting the pixel column and adjacent to the 1 pixel section becomes larger as a length of the gate line from the gate driver to each pixel section of the pixel column becomes longer.

3. The source driver of claim 1 or 2,

a gate driver supplying a gate signal to each of the m × n pixel sections via the n gate lines is connected to the display panel,

the timing control unit controls the timing of the output of the data latch unit such that a timing difference between the timing of the introduction of the data latch unit into the pixel data piece corresponding to the gradation voltage signal to be supplied to the pixel unit and the timing of the output of the data latch unit from the m pixel data pieces constituting the pixel data piece group becomes larger as the length of the gate line from the gate driver to each of the m pixel units constituting the pixel column becomes longer.

4. The source driver according to any of claims 1 to 3,

the timing control section has a counter that counts the n groups of pixel data pieces corresponding to each of the n gate lines every 1 group of pixel data pieces and controls the timing of output of the m pieces of pixel data by the data latch section based on a counter value of the counter.

5. A display device is characterized by comprising:

a display panel having m source lines and n gate lines, and m × n pixel units arranged in a matrix at each of intersections of the m source lines and the n gate lines, wherein m and n are integers of 2 or more;

a display controller outputting a video data signal formed by a plurality of pixel data pieces being continuous;

a gate driver configured to supply gate signals to the m × n pixel units via the n gate lines; and

a plurality of source drivers provided for every predetermined number of source lines among the m source lines, receiving the supply of the video data signal from the display controller, and outputting a gradation voltage signal based on the video data signal to each of the predetermined number of source lines in accordance with a timing of the supply of the gate signal from the gate driver,

each of the plurality of source drivers has:

a data latch unit that sequentially introduces pieces of pixel data included in the video data signal at a predetermined cycle for each of the predetermined number of pieces of pixel data and outputs the pieces of pixel data from output terminals corresponding to the predetermined number of source lines;

a gradation voltage conversion unit that sequentially introduces the predetermined number of pieces of pixel data output from the data latch unit and converts the pieces of pixel data into the predetermined number of gradation voltage signals;

an output unit which amplifies the predetermined number of gradation voltage signals and outputs the amplified signals to the predetermined number of source lines; and

a timing control section that controls a timing of output of the pixel data piece from the data latch section,

the timing control unit includes:

a first output delay setting section that sets a first delay time such that a time interval from introduction to output of the data latch section of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel sections becomes larger as a length of the gate line from the gate driver to each of a predetermined number of pixel sections becomes longer; and

a second output delay setting section that sets a second delay time such that a time interval from input to output of the data latch section of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel sections becomes smaller as a distance from the source driver to each gate line to which each of the predetermined number of pixel sections is assigned becomes longer,

controlling timing of output of the pixel data piece from the data latch section based on an output delay time determined by the first delay time and the second delay time.

6. The display device according to claim 5, wherein the second output delay setting section sets the second delay time such that the second delay time changes in a stepwise manner for each of a plurality of gate lines with respect to the gate signal of the gate line selected in sequence.

7. The display device according to claim 5 or 6, wherein the first output delay setting section of each of the plurality of source drivers sets the first delay time such that the first delay time includes a delay time of at least a leading head ch and a delay time which changes stepwise between the ch for each source driver.

8. The display device according to any one of claims 5 to 7,

the timing control unit further includes a setting storage unit that stores setting information supplied from the display controller to each of the plurality of source drivers at a predetermined timing,

the setting information includes setting information of a delay time with respect to a predetermined timing corresponding to supply of the gate signal,

the delay time setting information includes at least setting information of delay time of the head ch of each source driver, setting information of delay time between the source drivers corresponding to the gate signal delay, delay time of each predetermined gate line corresponding to the source signal delay, and setting information showing the number of steps to which the delay time is changed,

the first output delay setting section sets the first delay time based on the delay time of the preceding header ch and the setting information of the delay time between the respective ch from the setting storage section,

the second output delay setting section sets the second delay time based on the delay time per the predetermined gate line and the setting information of the number of steps from the setting storage section.

9. The display device according to claim 8, wherein the setting information of the delay time further includes setting information adjusted so that output timings of a final ch of a source driver adjacent to the source driver and a leading ch of the source driver are smoothly continuous.

10. A source driver connected to a display panel having m × n pixel portions each having m source lines and n gate lines and arranged in a matrix at each of intersections of the m source lines and the n gate lines, for receiving a video data signal formed by connecting a plurality of pieces of pixel data, generating a gradation voltage signal to be supplied to a plurality of pixel portions on a predetermined number of the m source lines based on the video data signal, and outputting the gradation voltage signal to the predetermined number of the source lines in accordance with a timing of supply of a gate signal from a gate driver connected to the n gate lines to the plurality of pixel portions, wherein m and n are integers of 2 or more, the source driver comprising:

the timing control unit includes:

a first output delay setting section that sets a first delay time such that a time interval from introduction to output of the data latch section of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel sections becomes larger as a length of the gate line from the gate driver to each of a predetermined number of pixel sections becomes longer;

a second output delay setting section that sets a second delay time such that a time interval from input to output of the data latch section of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel sections becomes smaller as a distance from the source driver to the gate line to which each of the predetermined number of pixel sections is assigned becomes longer,

11. The source driver of claim 10, wherein the second output delay setting section sets the second delay time such that the second delay time changes in a stepwise manner for each of a plurality of gate lines with respect to the gate signal of the sequentially selected gate line.

12. The source driver of claim 10 or 11,

the timing control section further includes a setting storage section that stores setting information supplied from outside the source driver,

the delay time setting information includes at least setting information of delay time of the head ch of the source driver, setting information of delay time between the source driver and the head ch corresponding to the gate signal delay, delay time of each predetermined gate line corresponding to the source signal delay, and setting information of the number of steps to change the delay time,

13. The source driver of claim 12, wherein the setting information of the delay time further includes setting information adjusted so that output timings of a final ch and a leading ch of the source driver adjacent to the source driver are smoothly continuous.