CN114187869A

CN114187869A - Display panel, control method, control device, and storage medium

Info

Publication number: CN114187869A
Application number: CN202111467363.2A
Authority: CN
Inventors: 南帐镇; 李东明
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-03-15

Abstract

A display panel, a control method, a control apparatus, and a storage medium. The display panel includes a pixel array including a plurality of pixel rows, a plurality of source drivers configured to supply a row scan signal to an ith pixel row from a signal application side of the pixel array, and a gate driver configured to output a plurality of data signals to different portions of the ith pixel row, the plurality of source drivers including a first source driver and a second source driver, a distance from a signal application side of a first portion of the ith pixel row corresponding to the first source driver being smaller than a distance from a signal application side of a second portion of the ith pixel row corresponding to the second source driver. During the period when the gate driver applies the row scan signal to the ith pixel row, the time when the second source driver starts outputting the data signal is later than the time when the first source driver starts outputting the data signal.

Description

Display panel, control method, control device, and storage medium

Technical Field

Embodiments of the present disclosure relate to a display panel, a control method, a control apparatus, and a non-transitory computer-readable storage medium.

Background

Currently, the requirements for high resolution (high-resolution), high frame rate (high-frame rate), and large size display (large size display) of the display panel are increasing, and as the resolution is increased and the frame rate is increased, the charging time of one row of pixels is continuously reduced. The delay time of the gate signal becomes long due to the increase in resolution and the increase in panel size, further resulting in insufficient charging time of the pixel to cause deterioration of display performance.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display panel including a pixel array including a plurality of pixel rows, a plurality of source drivers configured to provide a row scan signal from a signal application side to an ith pixel row among the plurality of pixel rows, and a gate driver configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers including a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, wherein, i is a positive integer, and a time when the second source driver starts outputting the data signal is later than a time when the first source driver starts outputting the data signal while the gate driver applies the row scan signal to the ith pixel row.

For example, in a display panel provided in at least one embodiment of the present disclosure, a time when the first source driver starts outputting a data signal is determined based on a time when the row scan signal is applied to the first portion of the ith pixel row; the timing at which the second source driver starts outputting the data signal is determined based on the timing at which the row scan signal is applied to the second portion of the ith pixel row.

For example, in a display panel provided in at least one embodiment of the present disclosure, an output data time difference between a time when the second source driver starts outputting a data signal and a time when the first source driver starts outputting a data signal is equal to a scan signal time difference between a time when the row scan signal is applied to the second portion of the ith pixel row and a time when the row scan signal is applied to the first portion of the ith pixel row.

For example, in a display panel provided in at least one embodiment of the present disclosure, the scan signal time difference is determined based on a panel size and a resolution of the display panel.

For example, at least one embodiment of the present disclosure provides the display panel further comprising a timing control board configured to output a plurality of image input signals to the plurality of source drivers, respectively, the plurality of source drivers are configured to generate and output the plurality of data signals to different portions of the ith pixel row based on the plurality of image input signals, the timing control board outputs the image input signal to the second source driver later than the timing control board outputs the image input signal to the first source driver during a period in which the gate driver applies the row scan signal to the ith pixel row, so that during the period when the gate driver applies the row scan signal to the ith pixel row, the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal.

For example, the display panel provided by at least one embodiment of the present disclosure further includes a timing control board, each source driver includes a digital-to-analog conversion circuit, a data buffer module, and an output buffer amplifier, the timing control board is configured to output a plurality of image input signals to the plurality of source drivers, respectively, the digital-to-analog conversion circuit in the plurality of source drivers is configured to perform conversion processing on the plurality of image input signals to generate and output a plurality of first pixel data signals, the data buffer module in the plurality of source drivers is configured to generate and output a plurality of second pixel data signals based on the plurality of first pixel data signals, the output buffer amplifier in the plurality of source drivers is configured to process the plurality of second pixel data signals to generate and output the plurality of data signals, the data buffer module in the second source driver outputs the second pixel data signal later than the data buffer module in the first source driver during a period in which the gate driver applies the row scan signal to the ith pixel row, so that the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal during the period in which the gate driver applies the row scan signal to the ith pixel row.

For example, in a display panel provided in at least one embodiment of the present disclosure, the timing control board is configured to simultaneously output the plurality of image input signals to the plurality of source drivers, respectively.

For example, in a display panel provided in at least one embodiment of the present disclosure, the data signal output by the first source driver continuously changes with time during a period in which the row scan signal is applied to the first portion of the ith pixel row, and the data signal output by the second source driver continuously changes with time during a period in which the row scan signal is applied to the second portion of the ith pixel row.

For example, in a display panel provided in at least one embodiment of the present disclosure, each pixel row includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and a difference between an actual charge level and a predetermined charge level of each sub-pixel in a first portion and a second portion of an ith pixel row is equal to or less than a preset difference during a period in which the gate driver applies a row scan signal to the ith pixel row, wherein the actual charge level and the predetermined charge level of each sub-pixel are determined by a data signal corresponding to the each sub-pixel.

For example, in a display panel provided in at least one embodiment of the present disclosure, the preset difference value is 0.

At least one embodiment of the present disclosure provides a control method applied to a display panel, wherein the display panel includes a pixel array including a plurality of pixel rows, a plurality of source drivers configured to provide a row scan signal from a signal application side to an ith pixel row among the plurality of pixel rows, and a gate driver configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers including a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, wherein i is a positive integer, the control method comprises: and controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal while the gate driver applies the row scanning signal to the ith pixel row.

For example, in a control method provided in at least one embodiment of the present disclosure, controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal includes: determining a scan signal time difference between a time when the line scan signal is applied to the second portion of the ith pixel row and a time when the line scan signal is applied to the first portion of the ith pixel row; and controlling the time when the second source driver starts to output the data signal and the time when the first source driver starts to output the data signal on the basis of the scanning signal time difference, so that the time when the second source driver starts to output the data signal is later than the time when the first source driver starts to output the data signal.

For example, in a control method provided in at least one embodiment of the present disclosure, an output data time difference between a time when the second source driver starts outputting a data signal and a time when the first source driver starts outputting a data signal is equal to the scan signal time difference.

For example, in a control method provided in at least one embodiment of the present disclosure, determining a scan signal time difference between a time when the line scan signal is applied to the second portion of the ith pixel row and a time when the line scan signal is applied to the first portion of the ith pixel row includes: determining a panel size and a resolution of the display panel; determining the scan signal time difference based on the panel size and the resolution.

For example, in a control method provided in at least one embodiment of the present disclosure, the display panel further includes a timing control board configured to output a plurality of image input signals to the plurality of source drivers, respectively, the plurality of source drivers are configured to generate and output the plurality of data signals to different portions of the ith pixel row based on the plurality of image input signals, and the second source driver is controlled to start outputting data signals later than the first source driver during a period in which the gate driver applies a row scan signal to the ith pixel row, including: the timing control board is controlled to output the image input signal to the second source driver later than the timing control board outputs the image input signal to the first source driver, so that the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal during a period in which the gate driver applies the row scan signal to the ith pixel row.

For example, in a control method provided in at least one embodiment of the present disclosure, the display panel further includes a timing control board, each source driver includes a digital-to-analog conversion circuit, a data buffer module, and an output buffer amplifier, the timing control board is configured to output a plurality of image input signals to the plurality of source drivers, respectively, the digital-to-analog conversion circuit of the plurality of source drivers is configured to perform conversion processing on the plurality of image input signals to generate a plurality of first pixel data signals, the data buffer module of the plurality of source drivers is configured to generate a plurality of second pixel data signals based on the plurality of first pixel data signals, the output buffer amplifier of the plurality of source drivers is configured to process the plurality of second pixel data signals to generate the plurality of data signals, during a period in which the gate driver applies a row scan signal to the ith pixel row, controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal, comprising: and controlling the time for outputting the second pixel data signal by the data buffer module in the second source driver to be later than the time for outputting the second pixel data signal by the data buffer module in the first source driver, so that the time for outputting the data signal by the second source driver is later than the time for outputting the data signal by the first source driver during the period that the row scanning signal is applied to the ith pixel row by the gate driver.

For example, in a control method provided in at least one embodiment of the present disclosure, the timing control board is configured to simultaneously output the plurality of image input signals to the plurality of source drivers, respectively.

For example, in a control method provided in at least one embodiment of the present disclosure, the data signal output by the first source driver continuously changes with time during a period in which the row scan signal is applied to the first portion of the ith pixel row, and the data signal output by the second source driver continuously changes with time during a period in which the row scan signal is applied to the second portion of the ith pixel row.

For example, in a control method provided in at least one embodiment of the present disclosure, each pixel row includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and the control method further includes: and controlling the second source driver to start outputting the data signal later than the first source driver so that the difference between the actual charge level and the preset charge level of each sub-pixel in the first part and the second part of the ith pixel row is less than or equal to a preset difference, wherein the actual charge level and the preset charge level of each sub-pixel are determined by the data signal corresponding to each sub-pixel.

For example, in a control method provided in at least one embodiment of the present disclosure, the preset difference is 0.

At least one embodiment of the present disclosure provides a control apparatus applied to a display panel, wherein the display panel includes a pixel array including a plurality of pixel rows, a plurality of source drivers configured to provide a row scan signal from a signal application side to an ith pixel row among the plurality of pixel rows, and a gate driver configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers including a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, wherein i is a positive integer, the control device comprising: an output control circuit configured to control a time when the second source driver starts outputting the data signal to be later than a time when the first source driver starts outputting the data signal, during a period when the gate driver applies the row scan signal to the ith pixel row.

At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, implement a control method according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a timing diagram of a signal according to an embodiment of the disclosure;

FIG. 1B is a timing diagram of another signal provided by an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;

FIG. 3 is a timing diagram of a signal provided by some embodiments of the present disclosure;

FIG. 4 is a schematic diagram illustrating adjusting the timing of a plurality of data signals according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of another embodiment of the present disclosure for adjusting the timing of a plurality of data signals;

FIG. 6 is a schematic flow chart diagram of a control method provided by an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a control device provided in at least one embodiment of the present disclosure;

fig. 8 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.

Currently, if a Source Driver IC (SDIC) with 960 channels (one channel connecting a column of sub-pixels) is used, 24 SDICs are needed to support a display panel with 8K (7680 (columns) × 4320 (rows) pixels) resolution. As the resolution and panel size of the display panel become larger, the maximum propagation delay difference of the row scan signal (e.g., gate signal) for one row of sub-pixels increases, resulting in a difference in charging time between different sub-pixels, which is a cause of generating a dark block (block dim). It should be noted that "the maximum transfer delay difference of the row scan signal" may represent a time difference between the transfer of the row scan signal to the sub-pixel closest to the gate driver and the sub-pixel farthest from the gate driver in one row of the sub-pixels, or a time difference between the transfer of the row scan signal to the sub-pixel portion closest to the gate driver and the sub-pixel portion farthest from the gate driver in a plurality of sub-pixel portions (each sub-pixel portion includes a plurality of sub-pixels) in one row of the sub-pixels.

Fig. 1A is a timing diagram of a signal provided in an embodiment of the disclosure, and fig. 1B is a timing diagram of another signal provided in an embodiment of the disclosure.

DIN as shown in FIGS. 1A-1B₁/DIN₂₄A plurality of image input signals representing a plurality of source drivers generated by a timing control board of the display panel and transmitted to the display panel.

For example, a pixel array of a display panel includes a plurality of pixel rows, each pixel row of the pixel array including 24 sections, each section including a plurality of sub-pixels. As shown in FIGS. 1A-1B, the data signal SOUT₁[1]Representing the signal output to the first sub-pixel of the first portion of the first pixel row, the data signal SOUT₂₄[1]Indicating the signal output to the first sub-pixel of the 24 th part of the first pixel row. TP₁[1]～TP₂₄[1]Representing control data signal SOUT₁[1]～SOUT₂₄[1]Output signal, signal TP₁[1]～TP₂₄[1]For implementing the data signal SOUT₁[1]～SOUT₂₄[1]Update, signal TP₁[1]～TP₂₄[1]And data signal SOUT₁[1]～SOUT₂₄[1]Respectively in one-to-one correspondence. For example, at TP₁[1]～TP₂₄[1]A rising edge of the signal, the image input signal being input to the source driver; at TP₁[1]～TP₂₄[1]Falling edge of signal, data signal SOUT₁[1]～SOUT₂₄[1]Update, i.e. at TP₁[1]～TP₂₄[1]Falling edge of signal, data signal SOUT₁[1]～SOUT₂₄[1]Is transmitted to the pixel array of the display panel.

In fig. 1A and 1B, the data signal SOUT₁[1]And a data signal SOUT₂₄[1]Same, therefore, in order to clearly show the data signal SOUT₁[1]And a data signal SOUT₂₄[1]For representing the data signal SOUT₁[1]And for representing the data signal SOUT₂₄[1]Are separated from each other, but it should be understood thatFor representing the data signal SOUT₁[1]And for representing the data signal SOUT₂₄[1]May completely overlap each other, i.e. the data signal SOUT₁[1]And a data signal SOUT₂₄[1]There is no delay difference between them.

For example, as shown in FIGS. 1A to 1B, the image input signal DIN₁And an image input signal DIN₂₄Similarly, as shown in FIGS. 1A and 1B, signal TP₁[1]～TP₂₄[1]As well as all the same. For example, the charging time (1H-line time) of a line of pixels may include a Horizontal Blanking Period (HBP) and a data transmission period, and the charging time is different according to a load condition of the display panel. For a high-resolution large-size display panel, the charging time is long because the load is large. The data transfer stage being intended for transferring the image input signal DIN₁/DIN₂₄For example, IP2 denotes a data transfer phase of transferring an image input signal corresponding to a first pixel row of a pixel array, IP3 denotes a data transfer phase of transferring an image input signal corresponding to a second pixel row of a pixel array, and so on. It should be noted that the IP1 shown in fig. 1A to 1B may represent a data transfer stage for transferring an image input signal corresponding to the last pixel row for displaying the image of the previous frame.

For example, as shown in FIGS. 1A to 1B, the line scanning signal G1₁A row scanning signal G1 representing the first sub-pixel output by the gate driver of the display panel to the first portion of the first pixel row of the pixel array₂₄A row scanning signal G2 indicating the output of the gate driver of the display panel to the first sub-pixel of the 24 th part of the first pixel row of the pixel array₁A row scanning signal G2 representing the first sub-pixel output by the gate driver of the display panel to the first part of the second pixel row of the pixel array₂₄A gate driver representing the display panel outputs a row scan signal to the first subpixel of the 24 th portion of the second pixel row of the pixel array. Due to the transmission delay, the line scanning signal G1₁And a line scanning signal G1₂₄Is prolonged betweenRetardation is denoted as T_GD1，T_GD1A line scanning signal G2 representing the maximum propagation delay difference of the line scanning signal corresponding to the first pixel row₁And a line scanning signal G2₂₄The delay difference between them is denoted as T_GD2，T_GD2Which represents the maximum propagation delay difference of the line scanning signal corresponding to the second pixel row.

For example, as shown in FIGS. 1A-1B, the actual charge level of the first subpixel in the first portion of the first pixel row is CL1₁The actual charge level of the first sub-pixel of the 24 th part of the first pixel row is CL1₂₄Similarly, the actual charge level of the first sub-pixel of the first portion of the second row of pixels is CL2₁The actual charge level of the first sub-pixel of the 24 th part of the second pixel row is CL2₂₄。

As shown in fig. 1A, when the resolution of the display panel is low and the panel size is not large, the difference between the actual charge levels of the sub-pixels (CL 1 shown in fig. 1A) is small due to the small delay of the line scan signal even if the line scan signal delay compensation (GDC) is not performed (GDC)₁And CL1₂₄Difference between, CL2₁And CL2₂₄The difference therebetween) is also small.

However, as shown in fig. 1B, in the case where the resolution of the display panel is high and the size is large, the difference between the actual charge levels between the sub-pixels (CL 1 shown in fig. 1B)₁And CL1₂₄Difference between, CL2₁And CL2₂₄The difference therebetween), that is, the actual charge levels of the sub-pixels are different due to the difference in the transmission delay of the line scanning signals, thereby affecting the display performance, affecting the display effect, and causing display non-uniformity.

At least one embodiment of the present disclosure provides a display panel. The display panel includes a pixel array including a plurality of pixel rows, a plurality of source drivers and a gate driver, the gate driver is configured to provide a row scan signal to an ith pixel row from a signal application side of the pixel array, the plurality of source drivers are configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers include a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, where i is a positive integer. During the period when the gate driver applies the row scan signal to the ith pixel row, the time when the second source driver starts outputting the data signal is later than the time when the first source driver starts outputting the data signal.

In the display panel provided by the embodiment of the disclosure, by controlling the time for outputting the data signal by different source drivers, the transmission delay difference of the line scanning signal output by the gate driver can be effectively compensated, the display uniformity of the display panel is improved, the display performance is improved, and the display effect of the display panel is effectively improved. Meanwhile, the compensation range of the transmission delay difference of the line scanning signals can be not limited, so that the display panel is suitable for more application scenes.

At least one embodiment of the present disclosure also provides a control method, a control apparatus, and a non-transitory computer-readable storage medium.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments. It should be noted that, in the embodiments of the present disclosure, "a plurality" means two or more, that is, at least two.

Fig. 2 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.

For example, as shown in fig. 2, in some embodiments, the display panel 100 may include a pixel array 110, a plurality of source drivers 120, and a gate driver 130.

For example, the pixel array 110 may include a plurality of pixel rows, the gate driver 130 is configured to provide a row scan signal to an ith pixel row from a signal application side SS of the pixel array 110 for the ith pixel row among the plurality of pixel rows, the plurality of source drivers 120 are configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers 120 include a first source driver and a second source driver, and a distance from the signal application side SS of a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side SS of a second portion of the ith pixel row corresponding to the second source driver, that is, the first source driver is closer to the signal application side SS of the pixel array 110 than the second source driver, where i is a positive integer. For example, the gate driver 130 is located at a side of the pixel array 110 where the signal application side SS is located.

For example, in the ith pixel row, the timing at which the second source driver starts outputting the data signal is later than the timing at which the first source driver starts outputting the data signal while the gate driver applies the row scan signal to the ith pixel row.

In the present disclosure, the time when each source driver starts outputting the data signal is related to the distance between the portion of the pixel row corresponding to the source driver and the signal application side, and the time when the source driver starts outputting the data signal is later as the distance between the portion of the pixel row corresponding to the source driver and the signal application side is larger.

In the display panel provided by the embodiment of the disclosure, by controlling the time when different source drivers start to output data signals, the transmission delay difference of the line scanning signals output by the gate driver can be effectively compensated, the display uniformity of the display panel is improved, the display performance is improved, and the display effect of the display panel is effectively improved. Meanwhile, the compensation range of the transmission delay difference of the line scanning signals can be not limited, so that the display panel is suitable for more application scenes.

In the display panel provided by the embodiment of the present disclosure, the propagation delay difference of the line scan signals is compensated by adjusting the time when the source driver outputs the data signal, because the adjustment range of the time when the source driver outputs the data signal is larger than the propagation delay difference of the line scan signals, so that the delay compensation can be free from the limitation of the horizontal blanking stage. Due to the signal TP₁[1]～TP₂₄[1]Output time difference T_GDCThe method is not limited by a horizontal blanking stage, so that the horizontal blanking stage can be minimized, the speed of an interface (interface) is reduced, and the operating speed of an interface circuit with the same resolution is minimized.

For example, the ith pixel row may be any one of a plurality of pixel rows, that is, the timing at which the second source driver starts outputting the data signal is made later than the timing at which the first source driver starts outputting the data signal during the period in which the gate driver applies the row scan signal to each pixel row, so that the difference in the transmission delay of the row scan signal output to each pixel row can be effectively compensated.

The following describes a specific structure of the display panel 100 provided in some embodiments of the present disclosure with reference to fig. 2.

For example, the display panel 100 may be an Active-matrix organic light emitting diode (AMOLED) display panel, a quantum dot light emitting diode (QLED) display panel, a liquid crystal display panel, or the like.

For example, as shown in fig. 2, the display panel 100 may have 8K resolution, i.e., the display panel 100 may include 7680 (columns) × 4320 (rows) pixel array. It should be noted that the resolution of the display panel 100 can be set according to actual situations, and fig. 2 is only an example. The following description will be given taking the display panel 100 shown in fig. 2 as an example, that is, taking the display panel 100 having 8K resolution as an example.

For example, the display panel 100 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like. In addition, the display panel 100 may be not only a flat panel, but also a curved panel, or even a spherical panel.

For example, the display panel 100 may be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

For example, as shown in fig. 2, the pixel array 110 may include a plurality of pixel rows, e.g., 4096 pixel rows, of which only three are shown in fig. 2, a first pixel row R1, a second pixel row R2, and a 4096 th pixel row R4096, respectively.

For example, each pixel row includes a plurality of pixels, each pixel including a plurality of sub-pixels. For example, in some embodiments, each pixel includes three subpixels, a red subpixel, a blue subpixel, and a green subpixel; in other embodiments, each pixel includes four sub-pixels, a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white sub-pixel. It should be noted that, the embodiments of the present disclosure do not specifically limit the number and colors of the sub-pixels in each pixel, as long as the pixels in the display panel 100 can realize the colors to be displayed.

For example, in some embodiments, each sub-pixel may include a light emitting element and a driving circuit (not shown). The light emitting element may be a light emitting diode or the like. The light emitting diode may be an Organic Light Emitting Diode (OLED), a quantum dot light emitting diode (QLED), or the like. The light emitting element is configured to receive a light emitting signal (which may be a current signal, for example) and emit light of an intensity corresponding to the light emitting signal when in operation. The driving circuit is configured to drive the light emitting element to emit light, and the driving circuit may have a 7T1C (seven transistors and one capacitor) structure or the like. As shown in fig. 2, each driving circuit may include a capacitor Ct connected to the power supply terminal VSS, and the specific structure of the driving circuit is not limited by this disclosure.

For example, each pixel row may include a plurality of portions each including at least one sub-pixel, and as shown in fig. 2, each pixel row includes 24 portions, the 24 portions being respectively a portion shown by a rectangular dashed box PG1, a portion shown by a rectangular dashed box PG2, …, and a portion shown by a rectangular dashed box PG 24. The respective parts of each pixel row will be indicated below directly with the references PG1, PG2, PG24, etc.

It should be noted that the number of sub-pixels included in each portion of each pixel row may be set according to actual conditions, and the portions of the pixel row are divided for illustration and do not represent that the pixel row actually has the structure. In the example shown in fig. 2, the number of sub-pixels included in each portion of each pixel row is a fixed value, for example, 960. For example, a rectangular dashed box PG1 shown in fig. 2 shows a portion PG1 of all pixel rows, a rectangular dashed box PG2 shown in fig. 2 shows a portion PG2 of all pixel rows, and a rectangular dashed box PG24 shown in fig. 2 shows a portion PG24 of all pixel rows. The rectangular dashed box PG1 may comprise 320 x 4096 pixels, i.e. the rectangular dashed box PG1 shows a portion PG1 of 4096 pixel rows, the portion PG1 of each pixel row comprises 320 pixels, and if each pixel comprises 3 sub-pixels, the portion PG1 of each pixel row comprises 960 sub-pixels, e.g. the rectangular dashed box PG2 also comprises 320 x 4096 pixels, and the rectangular dashed box PG24 also comprises 320 x 4096 pixels. However, the embodiments of the present disclosure are not limited thereto, and each different portion of each pixel row may include a different number of sub-pixels, for example, the number of sub-pixels included in the portion PG1 of the first pixel row R1 and the number of sub-pixels included in the portion PG2 of the first pixel row R1 may be different, and the dividing manner of the different portions of each pixel row may be set according to actual situations, and the embodiments of the present disclosure do not specifically limit this.

For example, as shown in fig. 2, the row direction of the pixel array 110 is the X direction, and the column direction of the pixel array 110 is the Y direction. The X-direction and the Y-direction are perpendicular to each other, for example, in some examples, the X-direction may represent a horizontal direction and the Y-direction may represent a vertical direction.

For example, the distance of the first portion of the ith pixel row from the signal application side may represent a minimum distance between the first portion of the ith pixel row and the signal application side, and the minimum distance may be a distance between the first subpixel of the first portion of the ith pixel row and the signal application side. Similarly, the distance from the signal application side to the second portion of the ith pixel row corresponding to the second source driver may represent a minimum distance between the second portion of the ith pixel row corresponding to the second source driver and the signal application side. However, embodiments of the present disclosure are not limited thereto, and the distance of the first portion of the ith pixel row from the signal application side may represent a maximum distance or a mean distance between the first portion of the ith pixel row and the signal application side, etc., and accordingly, the distance of the second portion of the ith pixel row corresponding to the second source driver from the signal application side may represent a maximum distance or a mean distance between the second portion of the ith pixel row corresponding to the second source driver and the signal application side, etc. Note that the "intermediate distance" may mean a distance between the center of one part of the pixel row and the signal application side in the X direction.

Note that, in the present disclosure, the first subpixel in each portion denotes a subpixel closest to the signal application side SS in each portion in the X direction.

For example, as shown in fig. 2, with respect to the first pixel row R1, the distance from the signal application side to the portion PG1 of the first pixel row R1 is smallest, and the distance from the signal application side to the portion PG24 of the first pixel row R1 is largest.

For example, the gate driver 130 is disposed at the signal application side SS of the pixel array 110 and is connected to the pixel array 110 through a plurality of gate lines, and the gate driver 130 is configured to supply a plurality of row scan signals from the signal application side SS of the pixel array 110 to a plurality of pixel rows, for example, the row scan signals may be applied to driving circuits in the subpixels to control the driving circuits in the subpixels. As shown in fig. 2, the number of the plurality of line scan signals may be 4096, and the plurality of line scan signals may include a line scan signal G1, line scan signals G2, …, and a line scan signal G4096, each line scan signal corresponding to one pixel line. Each row scanning signal is transmitted to all the sub-pixels in one pixel row through one gate line, as shown in fig. 2, the gate line has a line group R, so that the row scanning signal received by each sub-pixel is not the same, and there is a transmission time delay in the transmission of the row scanning signal for all the sub-pixels in one pixel row.

For example, the gate line may be a metal line to realize signal transmission.

For example, as shown in fig. 2, the transmission direction of the row scan signals G1-G4096 may be the X direction, i.e., the row direction of the pixel array 110. Different portions of each pixel row are arranged in order in the transmission direction of the row scanning signal (i.e., the X direction), for example, the respective portions PG1 to PG24 of the first pixel row R1 are arranged in order in the X direction, and at this time, the distance of the portion PG1 from the signal application side SS is smaller than the distance of the portion PG2 from the signal application side SS, and the distance of the portion PG2 from the signal application side SS is smaller than the distance of the portion PG24 from the signal application side SS.

For example, as shown in fig. 2, the row scan signal G1 is transmitted to the first pixel row R1 of the display panel 100, and due to the transmission delay, the row scan signal transmitted to the first sub-pixel in the portion PG1 of the first pixel row R1 is denoted as G1₁The row scanning signal transmitted to the first sub-pixel in the section PG2 of the first pixel row R1 is represented as G1₂The row scanning signal transmitted to the first sub-pixel in the section PG24 of the first pixel row R1 is represented as G1₂₄. The row scan signal G2 is transmitted to the second pixel row of the display panel 100, and due to the transmission delay, the row scan signal transmitted to the first sub-pixel in the portion PG1 of the second pixel row R2 is denoted as G2₁The row scanning signal transmitted to the first sub-pixel in the section PG2 of the second pixel row R2 is denoted as G2₂The row scanning signal transmitted to the first sub-pixel in the section PG24 of the second pixel row R2 is denoted as G2₂₄(ii) a Similarly, the row scan signal G4096 is transmitted to the 4096 th pixel row of the display panel 100, and due to the transmission delay, the row scan signal transmitted to the first sub-pixel in the portion PG1 of the 4096 th pixel row is denoted as G4096₁The line scanning signal transmitted to the first sub-pixel in section PG2 of the 4096 th pixel row is denoted as G4096₂The line scanning signal transmitted to the first sub-pixel in section PG24 of the 4096 th pixel row is denoted as G4096₂₄。

For example, the gate driver 130 may be integrated on the display panel 100, so as to effectively reduce the production cost and power consumption, omit the bonding process, improve the yield and capacity of the product, and realize the narrow frame of the display panel. The gate driver 130 may also be disposed on a printed circuit board of the display panel 100. The gate driver 130 may be provided on one side of the display panel 100, or the gate driver 130 may be provided on both sides of the display panel 100.

For example, the plurality of source drivers 120 are configured to output a plurality of data signals to different portions of each pixel row, respectively, each data signal may include at least one sub-signal corresponding to at least one sub-pixel in a portion of the pixel row corresponding to the data signal, respectively, that is, one sub-signal is transmitted to one sub-pixel.

For example, each of the source drivers 120 corresponds to a portion of a pixel row, i.e., a data signal output from one of the source drivers 120 is transmitted to a portion of a pixel row. As shown in fig. 2, the plurality of source drivers 120 includes 24 source drivers, the 24 source drivers respectively corresponding to 24 sections of one pixel row, the 24 source drivers respectively being a source driver SDIC1, source drivers SDIC2, …, and a source driver SDIC 24. For example, the source driver SDIC1 generates and provides the data signal SOUT₁[1:960]To the portion PG1 of the pixel row, the source driver SDIC2 generates and supplies the data signal SOUT₂[1:960]To the portion PG2 of the pixel row and so on, the source driver SDIC24 generates and supplies the data signal SOUT₂₄[1:960]To portion PG24 of the pixel row.

With data signal SOUT₁[1:960]Is provided to the first pixel row R1 for illustration, for example, the data signal SOUT₁[1:960]Comprises 960 sub-signals SOUT₁[1]～SOUT₁[960]The 960 sub-signals are respectively transmitted to 960 sub-pixels in the portion PG1 of the first pixel row R1, for example, the sub-signals SOUT₁[1]The first sub-pixel, sub-signal SOUT, in the portion PG1 transmitted to the first pixel row R1₁[960]To the last sub-pixel in section PG1 of the first pixel row R1.

Note that, in the present disclosure, the last subpixel in each section denotes a subpixel farthest from the signal application side SS in each section in the X direction.

For example, the plurality of source drivers 120 are connected to the pixel array 110 through a plurality of data lines, and each source driver is configured to output a data signal to one portion of a pixel row corresponding to each source driver through the data lines. For example, the data line may be a metal line to implement signal transmission.

For example, the time when the first source driver starts to output the data signal may represent the time when the first source driver outputs a sub-signal corresponding to the first sub-pixel in the first portion of the ith pixel row. The time when the second source driver starts to output the data signal may represent a time when the second source driver outputs a sub-signal corresponding to the first sub-pixel in the second portion of the ith pixel row. In some embodiments, i is 1, that is, the ith pixel row is the first pixel row R1, the first portion of the ith pixel row may be the portion PG1 of the first pixel row R1, the second portion of the ith pixel row may be the portion PG2 of the first pixel row R1, at this time, the first source driver may be the source driver SDIC1, the second source driver may be the source driver SDIC2, and a time when the first source driver SDIC1 starts outputting the data signal may indicate that the first source driver SDIC1 outputs the sub signal SOUT₁[1]A time when the second source driver SDIC2 starts to output the data signal may represent that the second source driver SDIC2 outputs the sub-signal SOUT₂[1]Time of (d). Sub-signal SOUT₂[1]Representing the signal transmitted to the first subpixel in section PG2 of the first pixel row R1.

It should be noted that the first portion and the second portion of the ith pixel row are not limited to the above description, and may be determined according to specific situations, where the first portion and the second portion of the ith pixel row may be two portions adjacent in the X direction, or may be two portions not adjacent, that is, at least one portion of the ith pixel row is further included between the first portion and the second portion of the ith pixel row. For example, when the ith pixel row is the first pixel row R1, the first portion of the ith pixel row may be the portion PG1 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG24 of the first pixel row R1; alternatively, the first portion of the ith pixel row may be the portion PG2 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG24 of the first pixel row R1; alternatively, the first portion of the ith pixel row may be the portion PG2 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG3 of the first pixel row R1 (the portion PG3 represents a portion of the first pixel row R1 adjacent to the portion PG2 and located on a side of the portion PG2 away from the portion PG 1).

For example, while the gate driver 130 applies the row scan signal to each pixel row, the timings at which the plurality of source drivers start outputting the data signals are sequentially delayed. For example, as shown in fig. 2, the plurality of source drivers SDIC1 to SDIC24 are arranged in sequence in the X direction, and while the gate driver 130 applies the row scan signal to each pixel row, the source driver SDIC1 starts outputting the data signal earlier than the source driver SDIC2 starts outputting the data signal, and so on, and in the X direction, the source driver adjacent to the source driver SDIC24 starts outputting the data signal earlier than the source driver SDIC24 starts outputting the data signal, wherein a distance from a signal application side to a portion of a pixel row corresponding to the source driver adjacent to the source driver SDIC24 is smaller than a distance from a signal application side to a second portion of the pixel row corresponding to the source driver SDIC 24.

For example, in some embodiments, a timing at which the first source driver starts outputting the data signal is determined based on a timing at which the row scan signal is applied to the first portion of the ith pixel row, and a timing at which the second source driver starts outputting the data signal is determined based on a timing at which the row scan signal is applied to the second portion of the ith pixel row.

For example, the time when the first source driver starts to output the data signal is positively correlated with the time when the row scan signal is applied to the first portion of the ith pixel row, and similarly, the time when the second source driver starts to output the data signal is positively correlated with the time when the row scan signal is applied to the second portion of the ith pixel row.

For example, in some embodiments, an output data time difference between a time when the second source driver starts to output the data signal and a time when the first source driver starts to output the data signal is equal to a scan signal between a time when the row scan signal is applied to the second portion of the ith pixel row and a time when the row scan signal is applied to the first portion of the ith pixel rowNumber time difference. For example, as shown in fig. 2, the plurality of source drivers SDIC1 to SDIC24 are sequentially arranged in the X direction, and the data signal SOUT₁[1:960]To data signal SOUT₂₄[1:960]Sequentially output in turn, the output data time difference between the times at which the two source drivers start outputting the data signals may be determined according to the scan signal time difference (i.e., the delay difference due to the transmission delay) of the line scan signals between the two portions respectively corresponding to the two source drivers. For example, as shown in fig. 2, the data signal SOUT output by the source driver SDIC1₁[1:960]And a data signal SOUT output from the source driver SDIC2₂[1:960]Time difference of output data therebetween (i.e., the sub-signal SOUT output by the source driver SDIC1₁[1]And a sub signal SOUT output from the source driver SDIC2₂[1]Time difference therebetween) may be the line scan signal G1₁And a line scanning signal G1₂The scanning signal time difference between.

For example, in some embodiments, the first portion of the ith pixel row may be a portion of the ith pixel row closest to the signal application side SS, and the second portion of the ith pixel row may be a portion of the ith pixel row farthest from the signal application side SS, as shown in fig. 2, when the ith pixel row is the first pixel row R1, the first portion of the ith pixel row may be the portion PG1 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG24 of the first pixel row R1.

For example, in some embodiments, the scan signal time difference is determined based on the panel size and resolution of the display panel.

Fig. 3 is a timing diagram of a signal according to some embodiments of the present disclosure. The schematic diagram shown in fig. 3 is for example the case that a plurality of data signals are the same. It should be noted that all reference numerals in fig. 3 have the same meaning as fig. 1A to 1B, and repeated description is omitted.

For example, in some embodiments, the scan signal time difference may represent a time difference between a time when the line scan signal starts to be applied to the second portion of the ith pixel row and a time when the line scan signal starts to be applied to the first portion of the ith pixel row. Example (b)As shown in fig. 2, in some embodiments, the ith pixel row includes portions PG1 through PG24 arranged in this order along the transmission direction (i.e., the X direction) of the row scan signal. For example, when the ith pixel row is the first pixel row R1, the first portion of the ith pixel row may be the portion PG1 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG24 of the first pixel row R1, and at this time, the scan signal time difference represents a difference between a time when the line scan signal starts to be applied to the portion PG1 of the first pixel row R1 and a time when the line scan signal starts to be applied to the portion PG24 of the first pixel row R1, as shown in fig. 2, the scan signal time difference represents the line scan signal G1 24₁And a line scanning signal G1₂₄The difference in transmission delay between them, for example, as shown in FIG. 3, the scanning signal time difference may be a line scanning signal G1₁Rising edge of and line scanning signal G1₂₄Time difference T between rising edges of_GD1. The larger the panel size of the display panel 100, the higher the resolution of the display panel 100, and the time difference T_GD1The larger.

For example, in other embodiments, the scan signal time difference represents a difference between a time at which the row scan signal is transmitted to a first subpixel in the first portion of the ith pixel row and a time at which the row scan signal is transmitted to a last subpixel in the second portion of the ith pixel row. As shown in fig. 2, the scan signal time difference may represent a time difference between a rising edge of a row scan signal received by a first subpixel in a first portion (e.g., portion PG1) of an ith pixel row and a rising edge of a row scan signal received by a last subpixel in a second portion (e.g., portion PG24) of the ith pixel row.

For example, in some embodiments, during the period in which the gate driver applies the row scan signal to the ith pixel row, a difference between an actual charge level and a predetermined charge level of each sub-pixel in the first and second portions of the ith pixel row is less than or equal to a preset difference, and the actual charge level and the predetermined charge level of each sub-pixel are both determined by the data signal corresponding to each sub-pixel.

In the embodiments of the present disclosure, the time when the second source driver starts outputting the data signal and the time when the first source driver starts outputting the data signal are controlled so that the difference between the actual charge level of the sub-pixel and the predetermined charge level is less than or equal to the preset difference. For example, the timing at which the plurality of source drivers start outputting the data signals is controlled such that the difference between the actual charge level and the predetermined charge level of each sub-pixel in the display panel 100 is equal to or less than a preset difference.

When the difference between the actual charging level and the predetermined charging level of the sub-pixel is less than or equal to the preset difference, the problem that the actual charging level is inconsistent with the predetermined charging level due to the transmission delay of the line scanning signal can be avoided, so that the actual display brightness (the brightness corresponding to the actual charging level) sent by the sub-pixel reaches the predetermined display brightness (the brightness corresponding to the predetermined charging level), the actual display requirement is met, and the display effect is improved.

It should be noted that, in the embodiment of the present disclosure, the data signal is stored in the driving circuit of the sub-pixel at the time of the falling edge of the row scanning signal, and the actual charge level indicates the level of the data signal at the time of the falling edge of the row scanning signal. Further, the "predetermined charge level" of one sub-pixel may represent a charge level corresponding to the sub-pixel without considering a transmission delay of a line scanning signal. The predetermined charge level is determined by the data signal and the row scan signal corresponding to the sub-pixel.

For example, in some embodiments, the preset difference value may be 0. The preset difference may be set according to actual conditions, and the embodiment of the disclosure is not limited thereto.

For example, as shown in fig. 3, when the ith pixel row is the first pixel row R1, CL1₁May represent the actual charge level of the first sub-pixel of the portion PG1 in the first pixel row R1, CL1₂₄May represent the actual charge level of the first sub-pixel of the portion PG24 in the first pixel row R1, e.g., CL1₂₄＝CL1₁The actual charge level of each sub-pixel is the same, thereby compensating for the transmission delay due to the line scanning signalAnd display difference is caused, the display uniformity is prompted, and the display effect is improved.

For example, in some embodiments, as shown in FIG. 2, if a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]The time when the second source driver starts to output the data signal is later than the time when the first source driver starts to output the data signal, so that the difference between the actual charge levels of any two sub-pixels in the first part and the second part of the ith pixel row is smaller than or equal to the preset difference. When the plurality of data signals are the same, the predetermined charging levels corresponding to all the sub-pixels in the same pixel row are the same, and at this time, the difference between the actual charging levels of any two sub-pixels in the same pixel row needs to be less than or equal to the preset difference, so that the display uniformity is ensured.

For example, as shown in fig. 2, the display panel 100 further includes a timing control board TCON configured to output the plurality of image input signals to the plurality of source drivers 120(SDIC1, SDIC2, and SDIC24), respectively, the plurality of source drivers 120 configured to generate and output the plurality of data signals to different portions of the ith pixel row based on the plurality of image input signals.

For example, as shown in FIG. 2, in some embodiments, the timing control board TCON is used to input a plurality of image input signals DIN₁～DIN₂₄Respectively output to a plurality of source drivers 120, e.g., image input signals DIN₁Sent to the source driver SDIC1 for an image input signal DIN₂Sent to the source driver SDIC2, and so on, and the image input signal DIN₂₄Sent to the source driver SDIC 24.

For example, each source driver is used to process an image input signal to generate a data signal and transmit the data signal to the pixel array 110. For example, as shown in fig. 2, the source driver SDIC1 applies an image input signal DIN₁Is processed to generate a data signal SOUT₁[1:960]The source driver SDIC2 applies an image input signal DIN₂Is processed to generate a data signal SOUT₂[1:960]The source driver SDIC24 applies an image input signal DIN₂₄Is processed to generate a data signal SOUT₂₄[1:960]。

Fig. 4 is a schematic diagram of adjusting the timing of a plurality of data signals according to some embodiments of the present disclosure, and fig. 5 is a schematic diagram of adjusting the timing of a plurality of data signals according to some embodiments of the present disclosure.

For example, in some embodiments, the timing control board TCON may adjust a timing at which the plurality of source drivers start to output the plurality of data signals, at which time the timing control board TCON outputs the image input signal to the second source driver later than the timing control board TCON outputs the image input signal to the first source driver during the period in which the gate driver 130 applies the row scan signal to the ith pixel row, so that the timing at which the second source driver starts to output the data signal is later than the timing at which the first source driver starts to output the data signal during the period in which the gate driver applies the row scan signal to the ith pixel row.

For example, in some embodiments, the timing control board may determine the time to output the image input signal to the first and second source drivers based on a scan signal time difference between a time when the row scan signal is applied to the second portion of the ith pixel row and a time when the row scan signal is applied to the first portion of the ith pixel row, such that the time at which the timing control board outputs the image input signal to the second source driver is later than the time at which the timing control board outputs the image input signal to the first source driver.

For example, the time when the source driver 120 starts to output the data signal is positively correlated with the time when the source driver 120 receives the image input signal transmitted from the timing control board TCON, that is, if the time when the timing control board TCON outputs the image input signal to the second source driver is later than the time when the timing control board TCON outputs the image input signal to the first source driver, the time when the second source driver starts to output the data signal is also later than the time when the first source driver starts to output the data signal.

For example, a time difference between a time when the timing control board TCON outputs the image input signal to the second source driver and a time when the timing control board TCON outputs the image input signal to the first source driver may be equal to a time difference between a time when the second source driver starts to output the data signal and a time when the first source driver starts to output the data signal.

For example, as shown in fig. 4, VBP indicates a Vertical blanking period, and VBP refers to a section that is not displayed on the actual picture. Image input signal DIN in fig. 4₁Corresponding VBP length and image input signal DIN₂₄The corresponding VBP has different lengths in order to show that the starting point of the respective data transfer phase IP1 is different, in fact DIN₁Corresponding VBP ratio DIN₂₄The corresponding VBP starts earlier. In fact, VBP is the same for each image input signal.

For example, as shown in fig. 4, the image input signal DIN output to the plurality of source drivers 120 may be directly adjusted by the timing control board TCON₁～DIN₂₄Thereby realizing adjustment of a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]The timing of (c). As shown in fig. 3, the signal DIN is input due to an image₁～DIN₂₄Are not the same, i.e. the image input signal DIN₁～DIN₂₄Is time-shared and transmitted to a plurality of source drivers 120, signal TP₁[1]～TP₂₄[1]Can be respectively connected with image input signal DIN₁～DIN₂₄Corresponding, e.g. to signal TP₁[1]Is located in the image input signal DIN₁HBP period of (1), signal TP₂₄[1]Is located in the image input signal DIN₂₄HBP period of (1), signal TP₁[1]Rising edge of (d) and signal TP₂₄[1]Has a time difference of T_GDC. The time difference T_GDCCan be matched with a line scanning signal G1₁And a line scanning signal G1₂₄Time difference T of scanning signals between_GD1Equal, i.e. T_GDC＝T_GD1At this time, the actual charge level CL1 may be made₂₄And an actual charge level CL1₁The same, thus compensate because of the transmission delay of the line scanning signal causes the display difference, the suggestion shows the homogeneity, promotes the display effect. E.g. T_GDCCan represent the image input signal DIN₁Time and image input signal DIN transmitted to source driver SDIC1₂₄A time difference between times of being transmitted to the source driver SDIC 24.

For example, as shown in fig. 4, in some embodiments, each source driver 120 includes a digital-to-analog conversion circuit RGB format and an output buffer amplifier sa (source amplifier). The digital-to-analog conversion circuits RGB format in the plurality of source drivers 120 are configured to perform conversion processing on a plurality of image input signals to generate and output a plurality of first pixel data signals, i.e., the digital-to-analog conversion circuits RGB format have a function of selectively restoring the image input signals DIN received from the timing control board TCON₁～DIN₂₄Thereby generating first pixel data signals RGB for driving the sub-pixels₁～RGB₂₄(e.g., red pixel data signal, blue pixel data signal, and green pixel data signal), i.e., for converting a digital image input signal DIN₁～DIN₂₄Convert into corresponding analog first pixel data signal RGB₁～RGB₂₄. The output buffer amplifiers in the source drivers 120 are used for processing the first pixel data signals to generate and output data signals, e.g., the output buffer amplifier SA is used for further amplifying the analog first pixel data signals RGB₁～RGB₂₄To obtain a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]Thereby driving a large capacitive load connected to the data line. The output buffer amplifier SA may include a two-stage operational amplifier structure, the first stage operational amplifier structure may be a differential amplifier, and the second stage operational amplifier structure may be an output operational amplifier. As shown in FIG. 4, the data signal SOUT₁[1:960]May include a sub-signal SOUT₁[1]Sub-signal SOUT₁[960]Similarly, the data signal SOUT₂₄[1:960]May include a sub-signal SOUT₂₄[1]Sub-signal SOUT₂₄[960]。

In fig. 4, the first pixel data signal RGB₁The corresponding time period RGBP1 represents outputting the first pixel data signal R corresponding to the part PG1 of the first pixel rowGB₁First pixel data signal RGB₂₄The corresponding time period RGBP1 represents outputting the first pixel data signal RGB corresponding to the part PG24 of the first pixel row₂₄And (3) a stage of (a). In fig. 4, the direction indicated by the arrow is the direction of time, and time corresponding to tm1 is earlier than time corresponding to tm 2. As can be seen from fig. 4, the first pixel data signal RGB corresponding to the portion PG1 of the first pixel row starts to be output₁Earlier than the start of outputting the first pixel data signal RGB corresponding to the portion PG24 of the first pixel row₂₄And (3) a stage of (a).

For example, in the example shown in fig. 4, a plurality of image input signals DIN₁～DIN₂₄Are different in timing, a plurality of image input signals DIN₁～DIN₂₄Is time-shared to the plurality of source drivers SDIC 1-SDIC 24, the plurality of source drivers SDIC 1-SDIC 24 do not need to process a plurality of image input signals DIN₁～DIN₂₄Is adjusted based on the plurality of image input signals DIN₁～DIN₂₄Resulting plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]And a plurality of image input signals DIN₁～DIN₂₄Are the same, i.e. the data signal SOUT₁[1:960]～SOUT₂₄[1:960]The timing of the data signals outputted from the source drivers is different, and at this time, the timing of the data signals outputted from the source drivers is different, for example, the timing of the data signals outputted from the second source driver is later than the timing of the data signals outputted from the first source driver, so that the difference in the transmission delay of the row scanning signals outputted from the gate drivers can be effectively compensated.

For example, in other embodiments, as shown in fig. 5, each of the source drivers includes a digital-to-analog conversion circuit RGB format, a data buffer module DB (data buffer), and an output buffer amplifier SA, the digital-to-analog conversion circuit RGB format of the plurality of source drivers is configured to perform a conversion process on a plurality of image input signals to generate and output a plurality of first pixel data signals, the data buffer module DB of the plurality of source drivers is configured to generate and output a plurality of second pixel data signals based on the plurality of first pixel data signals, and the output buffer amplifier SA of the plurality of source drivers is configured to process the plurality of second pixel data signals to generate and output a plurality of data signals.

For example, in some embodiments, the timing of the plurality of first pixel data signals may be adjusted by using the data buffer module DB of the source driver, so that the timing of the plurality of data signals is adjusted to compensate for the delay difference of the row scan signal. For example, during a period in which the gate driver applies the row scan signal to the ith pixel row, the data buffer module in the second source driver outputs the second pixel data signal later than the data buffer module in the first source driver outputs the second pixel data signal, so that during the period in which the gate driver applies the row scan signal to the ith pixel row, the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal.

For example, as shown in fig. 5, when the source driver includes the data buffer module DB, the data buffer DB has a function of adjusting the first pixel data signal RGB₁～RGB₂₄Thereby controlling the timing of the output data signals of the respective source drivers 120, for example, the data buffer module DB can adjust the plurality of first pixel data signals RGB₁～RGB₂₄To obtain a plurality of second pixel data signals RGB_d1～RGB_d24. Then, the output buffer amplifiers SA in the plurality of source drivers are applied to the plurality of second pixel data signals RGB_d1～RGB_d24Is processed to generate a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]。

In fig. 5, the second pixel data signal RGBd₁The corresponding period RGBBP1 represents outputting the second pixel data signal RGBd corresponding to the portion PG1 of the first pixel row₁Second pixel data signal RGBd₂₄The corresponding period RGBBP1 represents outputting the second pixel data signal RGBd corresponding to the portion PG24 of the first pixel row₂₄And (3) a stage of (a). In FIG. 5, the direction indicated by the arrow is the direction of time, and tm1 corresponds to the timeEarlier than the time corresponding to tm 2. As can be seen from fig. 5, the first pixel data signal RGB corresponding to the portion PG1 of the first pixel row is output₁And outputs the first pixel data signal RGB corresponding to the portion PG24 of the first pixel row₂₄Starts outputting the second pixel data signal RGBd corresponding to the portion PG1 of the first pixel row in the same phase₁Earlier than the start of outputting the second pixel data signal RGBd corresponding to the portion PG24 of the first pixel row₂₄And (3) a stage of (a).

For example, the time when the source driver 120 starts to output the data signal is positively correlated to the time when the data buffer module in the source driver 120 outputs the second pixel data signal, that is, if the time when the data buffer module in the second source driver outputs the second pixel data signal is later than the time when the data buffer module in the first source driver outputs the second pixel data signal, the time when the second source driver starts to output the data signal is also later than the time when the first source driver starts to output the data signal.

For example, in the example shown in fig. 5, a plurality of image input signals DIN₁～DIN₂₄The timing of the timing control board TCON can simultaneously input a plurality of image input signals DIN₁～DIN₂₄And transmitting the second pixel data signals to the plurality of source drivers SDIC1 to SDIC24, and adjusting the timing of the second pixel data signals through the data buffer module DB in the source drivers, thereby controlling the timing of the output data signals of the source drivers. For example, as shown in fig. 5, a plurality of first pixel data signals RGB₁～RGB₂₄The timing of the first pixel data signals RGB is the same for the data buffer modules DB of the source drivers SDIC1 to SDIC24₁～RGB₂₄Is adjusted to obtain a plurality of second pixel data signals RGB_d1～RGB_d24A plurality of second pixel data signals RGB_d1～RGB_d24Then, the output buffer amplifiers SA of the plurality of source drivers SDIC1 to SDIC24 are aligned with the plurality of second pixel data signals RGB_d1～RGB_d24Converted and amplified to obtain a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]. Multiple second pixel data signals RGB_d1～RGB_d24And the timing of a plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]The same is true.

For example, each source driver SDIC itself has a certain delay adjustment range, and each source driver SDIC can adjust a time difference at which a plurality of sub-pixels connected thereto receive a row scan signal. As shown in fig. 2, the row scanning signal corresponding to each sub-pixel in the portion PG1 of the first pixel row R1 is G1₁However, in practice, the times at which the respective sub-pixels in the section PG1 of the first pixel row R1 receive the row scan signals are not the same, with a slight time difference, and the source driver SDIC1 may compensate for the time difference at which the respective sub-pixels in the section PG1 of the first pixel row R1 receive the row scan signals.

The timing control board TCON may adjust the timing of the data signal, so that the delay difference adjustment range of the data signal output from each channel (channel) of the source driver SDIC may be reduced.

For example, the data signal output by the first source driver continuously changes with time during a period in which the row scan signal is applied to the first portion of the ith pixel row, and the data signal output by the second source driver continuously changes with time during a period in which the row scan signal is applied to the second portion of the ith pixel row. It should be noted that the time-varying manner of the data signal output by each source driver during the period when the row scanning signal is applied to the portion of the pixel row corresponding to the source driver may be set according to actual conditions, and the present disclosure is not limited thereto.

For example, as shown in fig. 3, the ith pixel row may be the first pixel row R1, the first portion of the ith pixel row may be the portion PG1 of the first pixel row R1, and the second portion of the ith pixel row may be the portion PG24 of the first pixel row R1, in response to the plurality of data signals SOUT₁[1:960]～SOUT₂₄[1:960]And a plurality of image input signals DIN₁～DIN₂₄In the case where the timings of (1) are the same, the period T1 represents the line scanning signal G1₁A period of time T24 applied to the portion PG1 of the first pixel row R1 represents the row scan signal G1₂₄The period of time applied to the portion PG24 of the first pixel row R1 is, in the period T1, the data signal SOUT transferred to the portion PG1 of the first pixel row R1₁[1]Gradually increasing with time, during the period T24, the data signal SOUT of the partial PG24 transmitted to the first pixel row R1₂₄[1]Gradually increasing with time.

In the present disclosure, for convenience of understanding, in the examples shown in fig. 1A to 1B and fig. 3, each signal is described by taking a display image (display pattern) in which each pixel row is inverted (toggle) between a high level (high level) and a low level (low level) as an example.

Note that, in the embodiment of the present disclosure, the "time difference" indicates an absolute value.

At least one embodiment of the present disclosure also provides a control method. Fig. 6 is a schematic flow chart of a control method provided by an embodiment of the disclosure.

For example, in some embodiments of the present disclosure, the control method may be applied to a display panel, the display panel may be the display panel 100 shown in fig. 2, and for the related description of the display panel 100, reference may be made to the description in the embodiments of the display panel described above, and details are not repeated here.

For example, as shown in fig. 6, the control method includes the following step S10 for the ith pixel row.

Step S10: and controlling the time when the second source driver starts outputting the data signal to be later than the time when the first source driver starts outputting the data signal during the period when the gate driver applies the row scanning signal to the ith pixel row.

In the control method provided by the embodiment of the disclosure, by controlling the time for outputting the data signal by the different source drivers, the transmission delay difference of the line scanning signal output by the gate driver can be effectively compensated, the display uniformity of the display panel is improved, the display performance is improved, and the display effect of the display panel is effectively improved. Meanwhile, the compensation range of the transmission delay difference of the line scanning signals can be not limited, so that the display panel is suitable for more application scenes.

For example, the ith pixel row may be any one of a plurality of pixel rows, that is, the control method provided by the embodiments of the present disclosure may be performed for each of the plurality of pixel rows, so that the difference in the transmission delay of the row scan signal output to each pixel row may be effectively compensated.

For example, the data signal output by the first source driver continuously changes, e.g., gradually increases, with time during the period in which the row scan signal is applied to the first portion of the ith pixel row, and the data signal output by the second source driver continuously changes, e.g., gradually increases, with time during the period in which the row scan signal is applied to the second portion of the ith pixel row.

For example, in some embodiments, controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal in step S10 includes: determining a scan signal time difference between a time when the line scan signal is applied to the second portion of the ith pixel row and a time when the line scan signal is applied to the first portion of the ith pixel row; and controlling the time when the second source driver starts to output the data signal and the time when the first source driver starts to output the data signal based on the scanning signal time difference, so that the time when the second source driver starts to output the data signal is later than the time when the first source driver starts to output the data signal.

For example, an output data time difference between a time when the second source driver starts outputting the data signal and a time when the first source driver starts outputting the data signal is equal to the scan signal time difference.

For example, as shown in fig. 2, the first source driver may be the source driver SDIC1 and the second source driver may be the source driver SDIC2, at which time the second source driver starts to output the data signal and the first source driverThe output data time difference between the times when the driver starts to output the data signals indicates that the source driver SDIC1 outputs the sub-signal SOUT₁[1]Time and source driver SDIC2 outputs sub-signal SOUT₂[1]The time difference between the times of (a) and (b).

For example, in some embodiments, determining a scan signal time difference between a time when the row scan signal is applied to the second portion of the ith pixel row and a time when the row scan signal is applied to the first portion of the ith pixel row includes: determining the panel size and the resolution of the display panel; based on the panel size and resolution, the scan signal time difference is determined.

For example, in some embodiments, the control method further comprises: the second source driver is controlled to start outputting the data signal later than the first source driver so that a difference between an actual charge level and a predetermined charge level of each sub-pixel in the first and second portions of the ith pixel row is equal to or less than a preset difference. The actual charge level and the predetermined charge level of each sub-pixel are determined by the data signal corresponding to each sub-pixel.

For example, the preset difference is 0, so that the actual charge level of each sub-pixel is equal to the predetermined charge level.

For example, in some embodiments, as shown in fig. 2, the display panel 100 further includes a timing control board TCON, and in step S10, controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal includes: the timing control board is controlled to output the image input signal to the second source driver later than the timing control board outputs the image input signal to the first source driver, so that the second source driver starts to output the data signal later than the first source driver starts to output the data signal during a period in which the gate driver applies the row scan signal to the ith pixel row.

For example, in some embodiments, controlling the timing control board to output the image input signal to the second source driver later than the timing control board outputs the image input signal to the first source driver in step S10 may include: determining a scan signal time difference between a time when the line scan signal is applied to the second portion of the ith pixel row and a time when the line scan signal is applied to the first portion of the ith pixel row; and controlling the timing control board to output the image input signals to the first source driver and the second source driver based on the scanning signal time difference so that the timing control board outputs the image input signals to the second source driver later than the timing control board outputs the image input signals to the first source driver.

For example, in some embodiments, each source driver includes a digital-to-analog conversion circuit, a data buffering module, and an output buffer amplifier. The timing of the plurality of first pixel data signals may be adjusted using the data buffer module DB of the source driver, thereby adjusting the timing of the plurality of data signals and compensating for a delay difference of the row scan signal. For example, step S10 may include: and controlling the time for outputting the second pixel data signal by the data buffering module in the second source driver to be later than the time for outputting the second pixel data signal by the data buffering module in the first source driver, so that the time for outputting the data signal by the second source driver is later than the time for outputting the data signal by the first source driver during the period that the row scanning signal is applied to the ith pixel row by the gate driver. At this time, the timing control board may simultaneously output a plurality of image input signals to a plurality of source drivers, respectively.

At least one embodiment of the present disclosure also provides a control apparatus. Fig. 7 is a schematic diagram of a control device according to at least one embodiment of the present disclosure.

For example, in some embodiments of the present disclosure, the control device may be applied to a display panel, which may be the display panel shown in fig. 2. As shown in fig. 2, the display panel 100 includes a pixel array 110, a plurality of source drivers 120, and a gate driver 130, the pixel array 110 includes a plurality of pixel rows, for an ith pixel row of the plurality of pixel rows, the gate driver 130 is configured to provide a row scan signal to the ith pixel row from a signal application side of the pixel array, the plurality of source drivers 120 is configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the plurality of source drivers 120 includes a first source driver and a second source driver, and a distance from the signal application side of a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side of a second portion of the ith pixel row corresponding to the second source driver, where i is a positive integer.

For example, the control device 700 may be integrated in the display panel 100.

For example, as shown in fig. 7, the control device 700 may include an output control circuit 710. It should be noted that the components of the control device 700 shown in fig. 7 are only exemplary and not limiting, and the control device 700 may have other components according to the actual application.

The output control circuit 710 is configured to control a time at which the second source driver starts outputting the data signal to be later than a time at which the first source driver starts outputting the data signal, while the gate driver applies the row scan signal to the ith pixel row, for the ith pixel row.

The output control circuit 710 may be configured to implement step S10 in the control method shown in fig. 6, and for specific descriptions of functions that the output control circuit 710 may implement, reference may be made to the description of step S10 in the above embodiment of the control method, and repeated descriptions are omitted.

For example, the output control circuit 710 may be implemented in hardware, software, firmware, or any feasible combination thereof.

For example, for a detailed description of a process of the control device 700 executing the control method, reference may be made to the related description in the embodiment of the control method, and repeated descriptions are omitted.

The control device 700 provided by the embodiment of the present disclosure can achieve the same technical effects as the control method provided by the embodiment of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory computer readable storage medium, and fig. 8 is a schematic diagram of a non-transitory computer readable storage medium provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 8, a non-transitory computer-readable storage medium 800 may store, non-temporarily, one or more computer-executable instructions 801. For example, the computer-executable instructions 801, when executed by a computer, may perform one or more steps in accordance with the control method described above.

For example, the non-transitory computer-readable storage medium 800 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DRRAM). The non-volatile memory may include, for example, read-only memory (ROM), programmable read-only memory (PROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. It should be noted that the memory described in this disclosure is intended to comprise, without being limited to, these and any other suitable types of memory.

For example, various applications, various data, and the like may also be stored in the non-transitory computer-readable storage medium 800.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A display panel includes a pixel array, a plurality of source drivers and gate drivers,

wherein the pixel array includes a plurality of pixel rows, the gate driver is configured to provide a row scan signal to an ith pixel row from a signal application side of the pixel array for the ith pixel row, the source drivers are configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the source drivers include a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, where i is a positive integer,

the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal while the gate driver applies the row scan signal to the ith pixel row.

2. The display panel of claim 1,

a time when the first source driver starts outputting the data signal is determined based on a time when the row scan signal is applied to the first portion of the ith pixel row;

the timing at which the second source driver starts outputting the data signal is determined based on the timing at which the row scan signal is applied to the second portion of the ith pixel row.

3. The display panel of claim 2, wherein an output data time difference between a time when the second source driver starts outputting the data signal and a time when the first source driver starts outputting the data signal is equal to a scan signal time difference between a time when the row scan signal is applied to the second portion of the ith pixel row and a time when the row scan signal is applied to the first portion of the ith pixel row.

4. The display panel of claim 3, wherein the scan signal time difference is determined based on a panel size and a resolution of the display panel.

5. The display panel of claim 1, further comprising a timing control board,

wherein the timing control board is configured to output a plurality of image input signals to the plurality of source drivers, respectively, the plurality of source drivers being configured to generate and output the plurality of data signals to different portions of the ith pixel row based on the plurality of image input signals,

the timing control board outputs the image input signal to the second source driver later than the timing control board outputs the image input signal to the first source driver during a period in which the gate driver applies the row scan signal to the ith pixel row, so that the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal during the period in which the gate driver applies the row scan signal to the ith pixel row.

6. The display panel of claim 1, further comprising a timing control board,

wherein the timing control board is configured to output a plurality of image input signals to the plurality of source drivers, respectively,

each source driver includes a digital-to-analog conversion circuit, a data buffer module, and an output buffer amplifier, the digital-to-analog conversion circuit of the plurality of source drivers is configured to perform conversion processing on the plurality of image input signals to generate and output a plurality of first pixel data signals,

the data buffering modules in the plurality of source drivers are configured to generate and output a plurality of second pixel data signals based on the plurality of first pixel data signals,

the output buffer amplifiers in the plurality of source drivers are configured to process the plurality of second pixel data signals to generate and output the plurality of data signals,

the data buffer module in the second source driver outputs the second pixel data signal later than the data buffer module in the first source driver during a period in which the gate driver applies the row scan signal to the ith pixel row, so that the second source driver starts outputting the data signal later than the first source driver starts outputting the data signal during the period in which the gate driver applies the row scan signal to the ith pixel row.

7. The display panel according to claim 6, wherein the timing control board is configured to simultaneously output the plurality of image input signals to the plurality of source drivers, respectively.

8. The display panel according to any one of claims 1 to 7, wherein the data signal output by the first source driver continuously changes with time during a period in which the row scan signal is applied to a first portion of the ith pixel row, and the data signal output by the second source driver continuously changes with time during a period in which the row scan signal is applied to a second portion of the ith pixel row.

9. The display panel of any of claims 1-7, wherein each pixel row comprises a plurality of pixels, each pixel comprising a plurality of sub-pixels,

a difference between an actual charge level and a predetermined charge level of each sub-pixel in first and second portions of the ith pixel row is less than or equal to a preset difference during a period in which the gate driver applies a row scan signal to the ith pixel row,

wherein the actual charge level and the predetermined charge level of each sub-pixel are determined by the data signal corresponding to said each sub-pixel.

10. The display panel according to claim 9, wherein the preset difference value is 0.

11. A control device is applied to a display panel, wherein the display panel comprises a pixel array, a plurality of source drivers and a gate driver,

the pixel array includes a plurality of pixel rows, the gate driver is configured to provide a row scan signal to an ith pixel row from a signal application side of the pixel array for the ith pixel row, the source drivers are configured to output a plurality of data signals to different portions of the ith pixel row, respectively, the source drivers include a first source driver and a second source driver, and a distance from the signal application side to a first portion of the ith pixel row corresponding to the first source driver is smaller than a distance from the signal application side to a second portion of the ith pixel row corresponding to the second source driver, where i is a positive integer,

the control device includes:

an output control circuit configured to control a time when the second source driver starts outputting the data signal to be later than a time when the first source driver starts outputting the data signal, during a period when the gate driver applies the row scan signal to the ith pixel row.

12. A control method is applied to a display panel, wherein the display panel comprises a pixel array, a plurality of source drivers and a gate driver,

the control method comprises the following steps:

and controlling the second source driver to start outputting the data signal later than the first source driver to start outputting the data signal while the gate driver applies the row scanning signal to the ith pixel row.

13. A non-transitory computer-readable storage medium storing computer-executable instructions,

wherein the computer-executable instructions, when executed by a computer, implement the control method of claim 12.