CN113066448B

CN113066448B - Source driver and display device

Info

Publication number: CN113066448B
Application number: CN202011437748.XA
Authority: CN
Inventors: 谷口直树; 土弘; 大野崇
Original assignee: Lapis Semiconductor Co Ltd
Current assignee: Lapis Semiconductor Co Ltd
Priority date: 2019-12-13
Filing date: 2020-12-11
Publication date: 2023-10-27
Anticipated expiration: 2040-12-11
Also published as: JP2021096451A; CN113066448A; JP6952819B2; JP2022008587A

Abstract

The invention relates to a source driver and a display device. Provided is a source driver capable of suppressing occurrence of luminance unevenness. The display device includes a data latch unit for sequentially inputting pixel data pieces from a video data signal at predetermined periods and sequentially outputting the input m pixel data pieces from m output terminals, a gradation voltage conversion unit for sequentially inputting the pixel data pieces output from the data latch unit and converting the pixel data pieces into gradation voltages, an output unit for amplifying the gradation voltages and outputting the amplified gradation voltages to a source line, and a timing control unit for controlling output timings of the pixel data pieces of the data latch unit. Each of the n pixel data pieces is a pixel data piece corresponding to a gradation voltage signal to be supplied, the gradation voltage signal being a pixel column along each of the n gate lines. The timing control unit controls the timing difference between the input of the pixel data piece group and the output of the pixel data piece by the data latch unit so as to decrease as the length of the source line from the source driver to the pixel column increases.

Description

Source driver and display device

Technical Field

The invention relates to a source driver and a display device.

Background

An active matrix driving method is used as a driving method of a display device including a display device such as a liquid crystal or an organic EL (Electro Luminescence ). In an active matrix drive type display device, a display panel is formed of a semiconductor substrate on which pixel portions and pixel switches (switches) are arranged in a matrix. The pixel switch is turned on and off by a gate signal, and when the pixel switch is turned on, a gradation voltage signal corresponding to a video data signal is supplied to the pixel portion, and the luminance of each pixel portion is controlled, whereby display is performed. The supply of the gate signal to the pixel switch is performed by a gate driver via a scanning line (also referred to as a gate line). The supply of the gradation voltage signal to the pixel portion is performed by the source driver via the source line. The source driver supplies a gradation voltage signal of a multilevel level corresponding to the gradation voltage to the gate driver.

In a display device in which a gate driver and a source driver are arranged on one side of a display panel, there are cases where: the image quality of the display image is degraded due to bias in wiring load caused by wiring resistance or capacitance of the wiring between the gate driver (i.e., the scan driver) and each scan line. Then, a display device has been proposed in which a display panel is divided into a plurality of regions according to a wiring load of a wiring between a scan driver and each scan line, and gate signals having different pulse widths are applied to the scan lines for each region (for example, patent document 1).

Prior art literature

Patent literature

Patent document 1: japanese patent No. 5380765.

Disclosure of Invention

Problems to be solved by the invention

In recent years, as a display device used in a TV or a monitor, a display device having a display panel with high resolution and a large screen, such as a 4K panel (pixel column: 3840×rgb, pixel row: 2160) or an 8K panel (pixel column and pixel row 2 times that of the 4K panel), has been demanded. In such a display device having a large-screen display panel, driving of the display panel using high-resolution and high-speed display is required. With this, wiring resistances (load capacitances) of the source lines and the scanning lines are increased, and parasitic resistances or capacitances of the display panel are increased.

For example, when the load capacitance of the source line becomes large, there is little dullness in rising and falling at a position on the source line where the distance from the source driver is relatively short with respect to the signal waveform of the gradation voltage signal supplied from the source driver, whereas the dullness in rising and falling increases as the distance from the source driver becomes relatively long. As a result, an output delay occurs, and the charging rate of the pixel electrode is reduced at a position on the source line relatively distant from the source driver. Therefore, there is a problem that: the writing voltage cannot be made constant in the display panel, and deterioration of image quality due to uneven brightness or the like occurs. Further, there is a problem as follows: when the wiring resistance of the scanning line or the source line is reduced (the wiring width is expanded) in order to reduce the luminance unevenness, the transmittance of the panel is reduced.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a display device capable of suppressing occurrence of luminance unevenness due to a decrease in a writing voltage in a pixel electrode.

Means for solving the problems

A source driver according to the present invention is a source driver connected to a display panel having m source lines and n gate lines (m and n are integers equal to or greater than 2), and m×n pixel units provided in a matrix at intersections of the m source lines and the n gate lines, and configured to receive video data signals of 1 frame size formed by sequentially forming n pixel data pieces each of m pixel data pieces, and generate gradation voltage signals to be supplied to the m×n pixel units based on the video data signals, the source driver comprising: a data latch unit that sequentially inputs the n pixel data pieces from the video data signal at a predetermined cycle, and sequentially outputs the m pixel data pieces included in the input pixel data pieces from m output terminals corresponding to the m source lines; a gradation voltage conversion unit that sequentially introduces the m pieces of pixel data outputted from the data latch unit and converts the m pieces of pixel data into m gradation voltages; an output unit that amplifies the m gradation voltages and outputs the amplified m gradation voltages to the m source lines; and a timing control unit configured to control a timing of an input of the data latch unit of the m pixel data pieces, each of the n pixel data piece groups being a pixel data piece group corresponding to a gradation voltage signal to be supplied to each of n pixel columns each including a pixel unit arranged along each of the n gate lines, the timing control unit controlling a timing of an output of the data latch unit so that a timing difference between a timing of an input of the data latch unit of the pixel data piece group corresponding to the gradation voltage signal to be supplied to the pixel column and a timing of an output of the data latch unit of the m pixel data pieces constituting the pixel data piece group becomes smaller as a length of a source line from the source driver to the pixel column becomes longer.

The display device according to the present invention is a display device, comprising: a display panel having m source lines and n gate lines (m and n are integers of 2 or more), and m×n pixel portions provided in a matrix at each of intersections of the m source lines and the n gate lines; a display controller outputting a video data signal formed by a plurality of continuous pixel data pieces; a gate driver for supplying gate signals to the m×n pixel units via the n gate lines; and a plurality of source drivers provided for each predetermined number of the m source lines, each of the source drivers receiving the video data signal from the display controller, and outputting a gradation voltage signal based on the video data signal to the predetermined number of source lines in accordance with a timing of the supply of the gate signal from the gate driver, the source drivers each having: a data latch unit that sequentially inputs, for each predetermined number of pieces of pixel data, pieces of pixel data included in the video data signal at a predetermined period, and outputs the pieces of pixel data from output terminals corresponding to the predetermined number of source lines; a gradation voltage conversion unit that sequentially introduces the predetermined number of pieces of pixel data outputted from the data latch unit and converts the predetermined number of pieces of pixel data into the predetermined number of gradation voltage signals; an output unit that amplifies the predetermined number of gradation voltage signals and outputs the amplified predetermined number of gradation voltage signals to the predetermined number of source lines; and a timing control section that controls timing of output of the pixel data piece from the data latch section, the timing control section having: a first output delay setting unit that sets a first delay time such that a time interval from the input to the output of the data latch unit of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel units becomes longer as a length of the gate line from the gate driver to each of a predetermined number of pixel units becomes longer; and a second output delay setting unit that sets a second delay time so that a time interval from the input to the output of the data latch unit of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel units becomes smaller as a distance from the source driver to each of the gate lines to which each of the predetermined number of pixel units is assigned becomes longer, and controls timing of the output of the pixel data piece from the data latch unit based on an output delay time determined by the first delay time and the second delay time.

Effects of the invention

According to the source driver of the present invention, the occurrence of luminance unevenness due to a decrease in the write voltage can be suppressed.

Drawings

Fig. 1 is a block diagram showing the structure of a display device of the present invention.

Fig. 2 is a block diagram showing an internal structure of the source driver of the present invention.

Fig. 3 is a block diagram showing the internal structure of the timing control section of embodiment 1 together with a source control core and a data latch section.

Fig. 4 is a timing chart showing output timings of signals for the operation of the source driver of embodiment 1.

Fig. 5 is a diagram schematically showing a pixel region on a display panel corresponding to a distance from a gate driver and a source driver.

Fig. 6 is a diagram showing signal waveforms of the gate signal and the gradation voltage signal of embodiment 1 in each pixel region of fig. 5.

Fig. 7 is a block diagram showing the internal structure of the timing control section of embodiment 2 together with a source control core and a data latch section.

Fig. 8 is a conceptual diagram showing an image of setting of output delay and delay time of each source driver IC of embodiment 2.

Fig. 9 is a timing chart showing output timing in the case where source output is performed from the near end toward the far end of the source driver in embodiment 2.

Fig. 10 is a timing chart showing output timing in the case where source output is performed from the far end toward the near end of the source driver in embodiment 2.

Fig. 11 is a diagram showing signal waveforms of the gate signal and the gradation voltage signal in each pixel region in embodiment 2.

Fig. 12 is a diagram showing signal waveforms of the gate signal and the gradation voltage signal in each pixel region of the comparative example in which the adjustment of the output delay is performed in consideration of only the gate line direction.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

Example 1

Fig. 1 is a block diagram showing the structure of a display device 100 of the present invention. The display device 100 is a liquid crystal display device of an active matrix driving system. The display device 100 includes a display panel 11, a display controller 12, gate drivers 13A and 13B, and source drivers 14-1 to 14-p.

The display panel 11 has a plurality of pixel portions P arranged in a matrix ₁₁ ～P _nm And pixel switch M ₁₁ ～M _nm (n, m: a natural number of 2 or more). The display panel 11 includes n gate lines GL1 to GLn and m source lines SL1 to SLm disposed so as to intersect the n gate lines GL1 to GLn. In the following description, any 1 gate line among the n gate lines GL1 to GLn is referred to as a gate line GLk, where 1 source line among the m source lines SL1 to SLm is referred to as a source line SLx. Pixel portion P ₁₁ ～P _nm And pixel switch M ₁₁ ～M _nm Are provided at intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm.

Pixel switch M ₁₁ ～M _nm Is controlled to be turned on or off according to the gate signals Vg1 to Vgn supplied from the gate driver 13.

Pixel portion P ₁₁ ～P _nm The source drivers 14-1 to 14-p receive the supply of the gradation voltage signals Vd1 to Vdm corresponding to the video data. In pixel switch M ₁₁ ～M _nm When turned on, the gradation voltage signals Vd1 to Vdm are supplied to the pixel portion P ₁₁ ～P _nm Each of the pixel electrodes is charged. According to the pixel part P ₁₁ ～P _nm The pixel portion P is controlled by the gradation voltage signals Vd1 to Vdm in each pixel electrode ₁₁ ～P _nm To perform display. In the following description, any 1 of the gradation voltage signals Vd1 to Vdm may be denoted as Vdx.

In the case where the display device 100 is a liquid crystal display device, the pixel portion P ₁₁ ～P _nm Each of the substrates includes a transparent electrode, not shown, and a liquid crystal sealed between the substrate and a counter substrate, which is provided opposite to the semiconductor substrate and has 1 transparent electrode formed on the entire surface. The backlight inside the display device is supplied to the pixel portion P ₁₁ ～P _nm The transmittance of the liquid crystal is changed by a potential difference between the gradation voltage signals Vd1 to Vdm and the counter substrate voltage, thereby performing display.

The display controller 12 generates a video data signal VDs including a sequence of pixel data slices PD (also referred to as video data slices PD) representing the luminance levels of the respective pixels with luminance gradation of 256 stages of, for example, 8 bits, based on the video data VD. The video data signal VDS is configured as a video data signal in which source lines are serialized according to the number of transmission lines for each predetermined number of source lines.

In the present embodiment, the video data signal VDS of 1 frame amount is constituted by sequentially continuing n pieces of pixel data pieces each constituted of m pieces of pixel data PD. Each of the n pixel data piece groups is a pixel data piece group including n pixel columns each including a pixel portion arranged along each of the gate lines GL1 to GLn as a pixel data piece corresponding to a gradation voltage signal to be supplied. Then, by the operation of the source drivers 14-1 to 14-P, n×m pixel sections (i.e., pixel sections P) are generated based on the m×n pixel data pieces PD ₁₁ ～P _nm ) The supplied gradation voltage signals Vd1 to Vdm.

The display controller 12 generates a clock signal CLK of an embedded clock system having a constant clock pulse period (hereinafter referred to as a clock period). Then, the display controller 12 supplies a sequence signal in which the clock signal CLK and the video data signal VDS are integrated together to the source drivers 14-1 to 14-p, and performs display control of video data.

Further, the display controller 12 supplies a gate timing signal GS to gate drivers 13A and 13B provided at both ends of the display panel 11.

The gate drivers 13A and 13B supply gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the gate timing signal GS supplied from the display controller 12. The pixel portion P is selected for each pixel row by supply of the gate signals Vg1 to Vgn ₁₁ ～P _nm . Then, the gradation voltage signals Vd1 to Vdm are supplied from the source drivers 14-1 to 14-p to the selected pixel portion, and thereby writing of the gradation voltage signals Vd1 to Vdm to the pixel electrode is performed.

The source drivers 14-1 to 14-p are provided for every predetermined number of source lines that divide the source lines SL1 to SLm. The number of source lines driven by each source driver corresponds to the number of outputs ch of the source driver. For example, when the display panel has 960 ch outputs for every 1 source driver and 1 source line for every 1 pixel column, the 4K panel drives the source lines by 12 source drivers, and the 8K panel drives the source lines by 24 source drivers. In this embodiment, the following description will be made taking as an example a case where each of the source drivers 14-1 to 14-p drives k (k is an integer where m is not less than 2) source lines (i.e., a case where the number of outputs ch is k). Each of the source drivers 14-1 to 14-p is formed in a semiconductor IC (Integrated Circuit ) chip.

The source drivers 14-1 to 14-p receive the integrated serial signal of the clock signal CLK and the video data signal VDS from the display controller 12 and supply the serial signal from the display controller 12 through different transmission paths. The source drivers 14-1 to 14-p are supplied with the video data signals VDS of the number of ch, that is, k, and the differential signal in which the clock signal CLK is serialized, for each output ch in 1 data period.

Fig. 2 is a block diagram showing an internal structure of the source driver 14-1. The other source drivers 14-2 to 14-p have the same structure. The source driver 14-1 has a source control core 20, a data latch section 21, a gradation voltage converting section 22, an output section 23, and a timing control section 24.

The source control core 20 supplies the LOAD signal LOAD to the data latch section 21, and performs control to introduce video data (i.e., introduce a sequence of pixel data pieces PD from the video data signal VDS) by the data latch section 21. The source control core 20 controls a timing control unit 24, and the timing control unit 24 is a circuit block for controlling the timing of data output from the data latch unit 21.

The data latch section 21 sequentially introduces a sequence of pixel data pieces PD included in the video data signal VDS supplied from the display controller 12. At this time, the data latch section 21 performs the import of the pixel data piece PD in accordance with the control by the source control core 20.

The data latch unit 21 outputs the pixel data pieces PD to the gradation voltage converting unit 22 as the pixel data Q1 to Qk in correspondence with the input of the pixel data pieces PD of the number of outputs ch (i.e., the number of k ch) of the source driver 14-1. The data latch unit 21 has k output terminals corresponding to the source lines SL1 to SLk driven by the source driver 14-1, and outputs the pixel data Q1 to Qk from the k output terminals. At this time, the data latch unit 21 outputs the pixel data Q1 to Qk at a timing corresponding to the control of the timing control unit 24.

The gradation voltage converting section 22 converts each of the pixel data Q1 to Qk supplied from the data latch section 21 into gradation voltages A1 to Ak having voltage values corresponding to the luminance gradation indicated by the pixel data, and supplies the converted voltages to the output section 23.

The output unit 23 generates the signals for amplifying the gradation voltages A1 to Ak into gradation voltage signals Vd1 to Vdk, and supplies the gradation voltage signals to the source lines SL1 to SLk, respectively.

The timing control unit 24 controls the output timing of the pixel data Q1 to Qk by the data latch unit 21.

Fig. 3 is a block diagram showing the internal structure of the timing control section 24 together with the source control core 20 and the data latch section 21. The timing control section 24 includes a gate line counter 31, a register 32, and an output timing control circuit 33.

The source control core 20 performs control of the timing control section 24 based on the video data signal VDS supplied from the display controller 12 and the common setting information CS read out from the register 32. For example, the source control core 20 detects the timing of every 1 horizontal scanning line (i.e., gate line) of the sequence of the pixel data pieces PD included in the video data signal VDS, and supplies a signal showing the timing as a line signal LS to the gate line counter 31. Further, the source control core 20 detects timing of every 1 frame (i.e., 1 screen of the display panel 11) of the sequence of the pixel data pieces PD included in the video data signal VDS, and supplies a signal showing the timing as a frame signal FS to the gate line counter 31.

Further, the source control core 20 generates a LOAD signal LOAD based on the timing of each 1 horizontal scanning line of the pixel data piece PD included in the video data signal VDS, and supplies it to the output timing control circuit 33 and the data latch section 21.

The gate line counter 31 counts based on the frame signal FS and the line signal LS supplied from the source control core 20, and outputs the counted value as a counter output COUT. The line signal LS is a signal indicating the timing of every 1 horizontal scanning line (i.e., gate line) of the sequence of the pieces of pixel data PD included in the video data signal VDS, and therefore, the counter output COUT of the gate line counter 31 is a value showing the result of counting the pieces of pixel data PD included in the video data signal VDS for each gate line.

The gate line counter 31 supplies a counter output COUT to the output timing control circuit 33. Thereby, the output timing control circuit 33 is notified of which gate line is the display data of the output target for each of the pixel data pieces PD included in the video data signal VDS.

The register 32 stores various setting information related to the source output from the source driver 14-1. For example, the register 32 stores, as the general setting information CS, information on the driving order of the source lines (that is, the supply order of the gradation voltage signals Vd in the lateral direction of the display panel 11) by the source driver 14-1, and in what order the gradation voltage signals Vd are supplied to intersections of the source lines and the gate lines on 1 source line (that is, the driving order of the gradation voltage signals Vd in the longitudinal direction of the display panel 11).

For example, in the present embodiment, the source driver 14-1 drives the source lines SL1 to SLk in order from the source line close to the gate driver 13A (i.e., in order from SL1 toward SLk). The source driver 14-1 of the present embodiment supplies the gradation voltage signals Vd1 to Vdk in the order from the pixel portion on the gate line GL1 located closer to the source driver 14-1 among the pixel portions located at the intersections of the source lines and the gate lines GL1 to GLn toward the pixel portion on the gate line GLn located farther from the source driver 14-1 (that is, in the order from GL1 to GLn). These pieces of information are stored in the register 32 as general setting information CS.

Further, the register 32 stores timing adjustment setting information TA. The timing adjustment setting information TA is setting information for adjusting the timing of the source outputs of the source driver 14-1 (i.e., the supply of the gradation voltage signals Vd1 to Vdk to the pixel sections on the source lines SL1 to SLk) according to the crossing positions with the gate lines GL1 to GLn.

In the present embodiment, for example, with respect to the supply of the gradation voltage signal Vd1 to the pixel portion arranged along the source line SL1 (i.e., the pixel portion at the crossing position with each of the gate lines GL1 to GLn), the timing is adjusted such that the time interval of the supply of the gradation voltage signal Vd1 becomes shorter from the pixel portion on the gate line GL1 closer to the source driver 14-1 toward the pixel portion on the gate line GLn farther from the source driver 14-1.

More specifically, in the present embodiment, the timing of the output of the pixel data Q1 to Qk from the data latch section 21 to the gradation voltage converting section 22 is controlled, whereby the gradation voltage signal is supplied to the pixel section P ₁₁ ～P _nk Is provided. The k pieces of pixel data PD of 1 line quantity introduced by the data latch section 21 correspond to gradation voltage signals to be supplied to k pixel sections (hereinafter, referred to as pixel columns) of 1 line quantity arranged along the gate line. The data latch unit 21 performs the transfer of the pixel data pieces PD at regular time intervals. Therefore, in the present embodiment, the timing is adjusted so that the timing difference between the timing of introducing the pixel data piece PD by the data latch section 21 and the timing of outputting the pixel data Q1 to Qk becomes smaller as the length of the source line from the source driver to the pixel column becomes longer. Setting information to the effect of such timing adjustment is stored in the register 32 as timing adjustment setting information TA.

Further, the register 32 stores extension (spread) adjustment setting information SA. The expansion adjustment setting information SA is setting information for adjusting a difference in output timing from the source output to the front ch of the source driver 14-1 to the source output to the final ch (i.e., a timing difference in supply of the gradation voltage signal Vd1 to the pixel section on the source line SL1 from among pixels at the intersections of each of the pair of gate lines GL1 to GLn and each of the source lines SL1 to SLk to the gradation voltage signal Vdk to the pixel section on the source line SLk).

For example, in the present embodiment, the timing is adjusted such that the time interval of supply of the gradation voltage signals Vd1 to Vdk from the front ch to the final ch increases as the pixel portion on the source line SL1 closer to the gate driver 13A goes toward the pixel portion on the source line SLk farther from the gate driver 13A, that is, the time interval of supply of the gradation voltage signals between adjacent ch increases in accordance with the distance from the gate driver 13A.

More specifically, in the present embodiment, the output timing of the data latch section 21 is adjusted so that the timing difference between the output timing of the pixel data to be supplied to 1 pixel section constituting the pixel column and the output timing of the pixel data to be supplied to the other pixel section adjacent to the 1 pixel section becomes larger as the length of the gate line from the gate driver to each pixel section of the pixel column becomes longer. As a result, the time difference in output timing of the pixel data corresponding to the adjacent pixel units constituting the pixel column increases according to the distance from the gate driver, and as a result, the time interval for supplying the gradation voltage signal between the adjacent channels increases according to the distance from the gate driver 13A. Setting information to the effect of such timing adjustment is stored in the register 32 as extension adjustment setting information SA.

Further, the register 32 stores setting information for adjusting the timing of source outputs in adjacent portions of the source drivers 14-1 and 14-2. That is, in the present embodiment, the source drivers 14-1 to 14-p are divided to supply the gradation voltage signals Vd1 to Vdm to the source lines SL1 to SLm. Therefore, it is necessary to perform timing adjustment so that the final ch output of 1 source driver and the front ch output of the other source driver are smoothly and continuously performed. Information on control of the timing of the output of the pixel data Q1 to Qk from the data latch section 21 for performing such timing adjustment is stored in the register 32 as setting information.

The output timing control circuit 33 generates a source output start signal SS based on the LOAD signal LOAD supplied from the source control core 20 and the timing adjustment setting information TA read out from the register 32, and supplies the source output start signal SS to the data latch section 21. The source output start signal SS is a signal showing the timing of the start of source output in the front ch of the source driver 14-1. In practice, since the timing control section 24 is a circuit section that controls the data latch section 21, the output of the pixel data Q1 to Qk from the data latch section 21 to the gradation voltage converting section 22 is started based on the source output start signal SS. Then, the gradation voltages A1 to Ak are sequentially outputted from the gradation voltage converting section 22 to the output section 23 and the gradation voltage signals Vd1 to Vdk are outputted from the output section 23 in accordance with the output.

The output timing control circuit 33 generates an expansion setting signal SP based on the timing adjustment setting information TA and the expansion adjustment setting information SA read from the register 32, and supplies the expansion setting signal SP to the data latch unit 21. The extension setting signal SP is a setting signal for setting the timing of the output of the pixel data Q1 to Qk from the data latch section 21 for each line (i.e., each gate line).

The data latch section 21 determines the import of 1 line of pixel data pieces PD (i.e., k pixel data pieces PD) based on the LOAD signal LOAD supplied from the source control core 20 based on the sequence in which the pixel data pieces PD are imported from the video data signal VDS based on the clock signal CLK. Then, the data latch section 21 starts outputting the pixel data Q1 in correspondence with the start SS of the source output from the output timing control circuit 33, and outputs the pixel data Q2 to Qk at the timing set by the extension setting signal SP.

Next, the operation of the source driver 14-1 of the present embodiment will be described with reference to the timing chart of fig. 4.

The source control core 20 receives the supply of the video data signal VDS from the display controller 10, detects the front position of 1 frame amount of the sequence of the pixel data pieces PD included in the video data signal VDS, and supplies the frame signal FS showing the start of the pixel data piece PD of 1 frame amount to the gate line counter 31. As shown in fig. 4, the frame signal FS is a binary signal showing the front position of the pixel data piece PD of 1 frame amount with, for example, 1 pulse.

Further, the source control core 20 detects the front head position of the pixel data piece PD for every 1 line (i.e., every gate line) included in the video data signal VDS, and supplies a line signal LS showing the front head position to the gate line counter 31. As shown in fig. 4, the line signal LS is a binary signal showing the front position of the pixel data piece PD for every 1 line with 1 pulse.

Further, the source control core 20 generates a LOAD signal LOAD based on the video data signal VDS, and supplies it to the output timing control circuit 33 and the data latch section 21. As shown in fig. 4, the LOAD signal LOAD is a binary signal showing the lead-in period at a certain interval corresponding to the pixel data pieces PD of every 1 line with 1 pulse.

The gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT showing the count value. For example, when the number of gate lines GL1 to GLn is 4320 (i.e., n=4320), the counter output COUT increases from 0 to 4319 for every 1 pulse of the line signal LS as shown in fig. 4.

The output timing control circuit 33 supplies the expansion setting signal SP to the data latch section 21 based on the timing adjustment setting information TA and the expansion adjustment setting information SA read out from the register 32. Thereby, the setting of the output timing of the pixel data Q1 to Qk by the data latch section 21 is switched. For example, as shown in fig. 4, switching of setting is performed for every 2 line amounts (i.e., every 2 gate lines) of the sequence of the pixel data pieces PD.

The output timing control circuit 33 supplies the source output start signal SS to the data latch section 21 based on the LOAD signal LOAD and the timing adjustment setting information TA read out from the register 32. The source output start signal SS is a binary signal showing the start of source output every 1 line with, for example, 1 pulse.

The signal level of the source output start signal SS varies with a delay from the variation of the signal level of the LOAD signal LOAD. Then, the time difference between the signal changes of the source output start signal SS and the LOAD signal LOAD (hereinafter, referred to as the delay time of the source output start signal SS) changes according to the distance between the line to which the source output start signal SS is targeted and the source driver 14-1.

For example, in the present embodiment, as described above, the timing difference between the timing of introducing the pixel data piece PD by the data latch section 21 and the timing of outputting the pixel data Q1 to Qk is set so as to become smaller as the length of the source line from the source driver 14-1 to the pixel column (i.e., the pixel section of 1 line quantity arranged along the gate line) becomes longer. Accordingly, the time difference between the supply of the gradation voltage signals Vd1 to Vdk as the final source output and the LOAD signal LOAD becomes shorter as the length of the source line from the source driver 14-1 to the pixel portion becomes longer. Therefore, as shown in fig. 4, the delay time of the source output start signal SS is longer in the first line (gate line GL1, count 0), and the delay time of the source output start signal SS is shorter toward the final line (gate line GLn, count 4319).

The data latch section 21 outputs the pixel data Q1 corresponding to the front ch (i.e., the source line SL 1) of the source driver 14-1 at a timing corresponding to the change in the signal level of the source output start signal SS. In fig. 4, a binary signal representing the output timing of the pixel data Q1 is shown as "source output SOUT (chip front ch)".

The data latch unit 21 sequentially outputs the pixel data Q1 to Qk from the pixel data Q1 corresponding to the leading ch of the source driver 14-1 to the pixel data Qk corresponding to the final ch (i.e., the source line SLk). At this time, the data latch section 21 changes the time interval between the outputs of the respective channels from the leading channel to the final channel by the pixel data Q1 to Qk of each 2 line amounts (that is, the pixel data Q1 to Qk of each 2 gate lines amount) in accordance with the setting by the extension setting signal SP.

For example, in the present embodiment, as described above, the timing difference of the output of the pixel data corresponding to the gradation voltage signal to be supplied to the adjacent pixel from the data latch section 21 is set to be larger as the length of the source line from the source driver 14-1 to the pixel column (i.e., the pixel section of 1 line number arranged along the gate line) becomes longer. Accordingly, the time difference in supply timing between adjacent ch with respect to the supply of the gradation voltage signals Vd1 to Vdk as the final source output also increases as the length of the source line from the source driver 14-1 to the pixel portion increases. Therefore, the time interval from the output of the front ch to the output of the final ch also becomes larger in accordance with the distance from the source driver 14-1. As a result, as shown in fig. 4 as "source output SOUT (chip final ch)", in the first line (gate line GL1, count 0), the time difference between the output of the pixel data Q1 corresponding to the leading ch and the output of the pixel data Qk corresponding to the final ch is small, and the time difference becomes large as going to the final line (gate line GLn, count 4319).

As described above, in the source driver 14-1 of the present embodiment, the timing of the output of the pixel data Q1 to Qk from the data latch section 21 is adjusted, and as a result, the timing of the supply of the gradation voltage signals Vd1 to Vdk from the source driver 14-1 to the pixel section is adjusted. The same timing adjustment is performed in each of the source drivers 14-2 to 14-p. By such timing adjustment, the pixel portion P can be made ₁₁ ～P _nm The pixel charging rate in (a) becomes uniform. In this regard, description will be made with reference to fig. 5 and 6.

Fig. 5 is a diagram schematically showing pixel positions on the display panel corresponding to distances from the gate drivers 13A, 13B and the source drivers 14-1 to 14-p.

The region of the pixel portion that is closer to the gate driver 13A or 13B and closer to the source drivers 14-1 to 14-p is shown as "GnSn". The region of the pixel portion which is farther from the gate driver 13A or 13B and nearer to the source drivers 14-1 to 14-p is shown as "GfSn". The region of the pixel portion that is closer to the gate driver 13A or 13B and is intermediate in distance from the source drivers 14-1 to 14-p (i.e., near the central portion of the display panel 11) is shown as "GnSc". The region of the pixel portion that is farther from the gate driver 13A or 13B and is at a medium level (i.e., near the central portion of the display panel 11) from the source drivers 14-1 to 14-p is shown as "GfSc". In addition, a region of the pixel portion which is closer to the gate driver 13A or 13B and farther from the source drivers 14-1 to 14-p is shown as "GnSf". The region of the pixel portion that is farther from the gate driver 13A or 13B and farther from the source drivers 14-1 to 14-p is shown as "GfSf".

Fig. 6 is a diagram showing signal waveforms of the gate signal and the gray voltage signal in each pixel region of fig. 5. In the figure, "1H" shows a period in which the signal level of the gradation voltage signal changes to the H level, and "0E" shows an offset period for writing. The gate signal shows an example of a signal waveform in which a gate selection period (high level period) for precharging a pixel portion to be selected (so-called gate precharge) is long, and a rising portion of the gate signal is omitted.

In GnSn, since the influence of the impedance of the Gate line is small due to the close distance from the Gate driver 13A or 13B, the signal waveform (Gate in the figure) of the Gate signal is less (or almost no) dullness in the fall. Further, since the distances from the source drivers 14-1 to 14-p are closer, the influence of the impedance of the source line is smaller, so that the dullness of the rising and falling of the signal waveform (shown as Data in the figure) of the gradation voltage signal is smaller (or almost no).

In contrast, in GnSc, since the distance from the gate driver 13A or 13B is short, the signal waveform of the gate signal is less (or hardly) retarded, but since the distance from the source drivers 14-1 to 14-p is long compared to GnSn, the signal waveform of the gradation voltage signal is retarded in rising and falling due to the influence of the impedance of the source line.

In GnSf, too, the signal waveform of the gate signal is less (or hardly) retarded, but the distance from the source drivers 14-1 to 14-p is further than GnSc, and thus the signal waveform of the gradation voltage signal is greatly retarded by the impedance of the source line.

In the present embodiment, as shown in fig. 4, the delay time of the source output SOUT (i.e., the time difference from the LOAD signal LOAD) is set so as to become smaller as the value of the counter output COUT becomes larger, i.e., as the distance from the source driver to the gate line becomes longer. Therefore, as shown in fig. 6, the gradation voltage signal in GnSc is a signal waveform that changes at a timing earlier than the gradation voltage signal in GnSn with reference to the timing of the fall of the gate signal. Further, the gradation voltage signal in GnSf is a signal waveform that changes at an earlier timing with reference to the timing of the fall of the gate signal.

It is assumed that, without performing timing adjustment of the source output as in the present embodiment, the signal waveform of the gradation voltage signal in GnSf becomes a signal waveform shown with a one-dot dashed line in GnSc and GnSf of fig. 6. Therefore, in GnSf, the gate signal is lowered before the gradation voltage signal is sufficiently raised, and the pixel electrode to which the gradation voltage signal is supplied cannot be sufficiently charged.

In contrast, by performing timing adjustment of the source output as in the present embodiment and relatively advancing the timing of the gradation voltage signal with respect to the gate signal, it is possible to charge the pixel electrode at a point in time when the signal waveform of the gradation voltage signal sufficiently rises in GnSf.

Further, in the present embodiment, it is set such that the time difference between the respective chs of the source output SOUT becomes larger as the value of the counter output COUT becomes larger, that is, as the distance from the source driver to the gate line becomes longer (that is, such that the time difference of the leading ch and the final ch becomes larger). This is because, as shown in GfSn, gfSc, and GfSf of fig. 6, in the pixel region at a large distance from the gate driver 13A or 13B, the drop in the signal waveform of the gate signal is considerably retarded due to the influence of the impedance of the gate line.

That is, in the pixel region distant from the gate driver 13A or 13B, the dullness of the rising and falling of the signal waveform of the gradation voltage signal is large in accordance with the distance from the source driver, but the dullness of the falling of the signal waveform of the gate signal is also large. Therefore, the more in the pixel region closer to the gate driver 13A or 13B, the less delay in rising and falling of the signal waveform of the gradation voltage signal does not affect the charging to the pixel electrode.

That is, in the pixel regions GfSn, gfSc, and GfSf distant from the gate drivers 13A and 13B, unlike the pixel regions close to the gate drivers 13A and 13B, it is not necessary to advance the timing of the gradation voltage signal even if the distance from the source driver to the gate line becomes distant. Accordingly, as shown in fig. 4, control is performed such that the time difference between the respective chs of the source output SOUT becomes larger as the distance from the source driver to the gate line becomes longer, thereby adjusting such that the timings of the gradation voltage signals in the pixel regions farther from the gate drivers 13A and 13B are uniform.

As described above, in the source drivers 14-1 to 14-p of the present embodiment, in the pixel region closer to the gate driver 13A or 13B, the relative timing of the gradation voltage signal with respect to the gate signal is adjusted so as to become earlier as the distance from the source driver becomes longer. Thus, even when a dullness occurs in the signal waveform of the gradation voltage signal due to the influence of the impedance of the source line, the pixel electrode can be sufficiently charged.

On the other hand, in the pixel region distant from the gate driver 13A or 13B, in the case where the distance from the source driver is large, dullness occurs in the signal waveform of the gradation voltage signal due to the influence of the impedance of the source line, but dullness also occurs in the signal waveform of the gate signal due to the influence of the impedance of the gate line. Therefore, in the source drivers 14-1 to 14-p of the present embodiment, timing adjustment is performed in such a manner that the gradation voltage signal rises at the same timing regardless of whether the distance from the source driver is near or far. In this way, in the pixel region distant from the gate driver 13A or 13B, the pixel electrode can be sufficiently charged regardless of the distance from the source driver. As a result, the occurrence of brightness unevenness due to the decrease in the write voltage is suppressed.

Example 2

Next, example 2 of the present invention will be described. The display device of embodiment 2 is different from the display device 100 of embodiment 1 in the internal structure and operation of the timing control section 24 of the source driver IC. In the following description, the IC constituting the source driver 14-1 is referred to as IC1, and the IC constituting the centrally located source driver 14-y among the source drivers 14-1 to 14-p is referred to as ICy.

Fig. 7 is a block diagram showing the internal structure of the timing control section 24 of the display device of embodiment 2 together with the source control core 20 and the data latch section 21. The timing control section 24 has a gate line counter 31, a register 32, a gate line direction output delay timing generation section 41, a source line direction output delay timing generation section 42, and a setting signal addition section 43.

The register 32 stores common setting information CS supplied from the source control core 20, timing adjustment setting information TA which is setting information on adjustment of output timing (delay amount) corresponding to source signal delay, extension adjustment setting information SA which adjusts output timing (delay amount) between source lines corresponding to gate signal delay, and setting information SI which shows timing (delay amount) at which source output for the front ch (or the final ch) of each source driver IC starts.

The expansion adjustment setting information SA includes setting information of a delay amount OE between source outputs of each source driver IC. The timing adjustment setting information TA includes setting information of the delay amount Ds corresponding to the distance from the source driver.

Further, the register 32 of the present embodiment stores the division number setting information DA for the timing adjustment setting information TA. The division number setting information DA is setting information on how many steps the delay amount Ds corresponding to the distance from the source driver is set for each driver, in other words, information showing what stage the setting of the output timing with respect to the extending direction of the source line (hereinafter, referred to as the source line direction) is switched to. For example, in the present embodiment, information indicating that the setting is changed to the Y stage (setting 1 to Y) is stored in the register 32 as the division number setting information DA for each output of the video data pieces corresponding to the 2 gate lines.

The gate line direction output delay timing generation unit 41 generates an output timing setting signal TS for setting a delay time of the source output corresponding to a distance in the extending direction of the gate line (hereinafter referred to as a gate line direction) based on the extension adjustment setting information SA and the setting information SI read out from the register 32. For example, in the present embodiment, the following signals are generated as the output timing setting signal TS, that is: the signal sets the source output timing such that the output delay is small for the output of the source driver IC (e.g., IC 1) closer to the gate driver 13A or 13B, and in the source driver IC (e.g., ICy) farther from the gate driver 13A or 13B, the output delay is large.

The source line direction output delay timing generation unit 42 generates an output timing setting signal TD for setting a delay time of the source output corresponding to the distance in the source line direction, based on the timing adjustment setting information TA and the division number setting information DA read out from the register 32. For example, in the present embodiment, the following signals are generated as the output timing setting signal TD, that is: the signal sets the delay time such that the output delay is relatively large for the source output that is the supply target for the pixel on the gate line that is closer to each source driver IC, and the output delay is relatively small for the source output that is the supply target for the pixel on the gate line that is farther from each source driver IC. In the present embodiment, regarding the output timing setting signal TD, a signal for changing the output timing for each 2 gate lines is generated as the output timing setting signal TD based on the division number setting information DA in the sense that the setting is changed for each 2 gate lines.

The setting signal adder 43 adds the output timing setting signal TS and the output timing setting signal TD to generate an output timing signal LOAD-Gr. The output timing signal LOAD-Gr is an output timing signal group including the data output timing within 1 frame of each ch and the data output timing between ch from the latch section.

The data latch unit 21 receives a supply of a LOAD signal LOAD from the source control core 20. The LOAD signal LOAD is a timing signal of 1H period based on the line signal LS, and is a timing signal for introducing the video data slice PD into the data latch section 21. The LOAD signal LOAD is a signal that is linked to the gate off timing, which is the timing at which the gate signals Vg1 to Vgn fall.

The data latch section 21 imports the video data slice PD based on the timing of the LOAD signal LOAD. Then, the pixel data Q1 to Qk are output based on the output timing signal LOAD-Gr.

Fig. 8 is a conceptual diagram showing an image of setting of output delay and delay time of each source driver IC of the present embodiment.

The horizontal axis shows the source output of each ch of each source driver IC. The vertical axis shows the delay time of the source output with reference to the LOAD signal LOAD. Further, ts1, ts2, ts3, and ts4 show the start timing of the source output of the front ch of each source driver IC (here, IC1, IC2, IC3, and IC 4) set based on the setting information SI.

For example, in the IC1 (source driver 14-1) which is the source driver IC closest to the gate driver 13A, the delay time of the output delay in the gate line direction is set to the delay amount OE1 based on the output timing setting signal TS. Then, the delay amount OE1 and the delay amount Ds1 corresponding to the distance from the source driver are added to form a delay time of the source output of the IC 1.

In ICy (source driver 14-y), which is the source driver IC farthest from the gate drivers 13A and 13B, the delay time of the output delay based on the gate line direction is set as a delay amount OEf based on the output timing setting signal TS. Then, this delay amount OEf is added to the delay amount Dsf corresponding to the distance from the source driver, and the delay time of the source output of ICy is obtained.

The gate line direction delay amount OE (OE 1 to OEf) is set so as to vary stepwise for each predetermined ch based on the output timing signal LOAD-Gr even between the front ch and the final ch of each IC.

Note that, although fig. 8 shows an example in which each IC is set to 3 stages with respect to the delay amount Ds (Ds 1 to Dsf) of each IC corresponding to the distance from the source driver, each IC may be individually set to any stage (step number).

Next, operations of the IC1 (source driver 14-1) and ICy (source driver 14-y) of the present embodiment are described with reference to the timing chart of fig. 9. Fig. 9 is a timing chart showing a case where the gradation voltage signal (i.e., the source output) is supplied in a direction from the pixel portion near the source line, which is closer to the source driver, toward the pixel portion far the source line, which is farther from the source driver.

The source control core 20 supplies a frame signal FS showing the start of the video data piece PD of 1 frame amount included in the video data signal VDS to the gate line counter 31. Further, the source control core 20 supplies a line signal LS showing the front position of the video data piece PD during each 1H period to the gate line counter 31. The source control core 20 generates a LOAD signal LOAD based on the video data signal VDS, and supplies the LOAD signal LOAD to the gate line direction output delay timing generation section 41, the source line direction output delay timing generation section 42, and the data latch section 21.

The gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT showing the count value. When the number of gate lines n=4320, as shown in fig. 9, the value of the counter output COUT rises from 0 to 4319 for every 1 pulse of the line signal LS.

The gate line to be supplied as the source output is selected in accordance with the counter output COUT of the gate line counter 31. That is, when the gradation voltage signals Vd1 to Vdk are supplied from a position on the gate line close to the source driver (i.e., a source line near end) toward a position on the gate line far from the source driver (i.e., a source line far end), the gate lines to be supplied for the source output are selected in the order of the gate lines GL1, GL2, GL3, GL4, … GL4318, GL4319, GL 4320.

The source line direction output delay timing generation unit 42 changes the setting of the delay amount Ds corresponding to the distance from the source driver based on the counter output COUT, the division number setting information DA, and the timing adjustment setting information TA. In the present embodiment, the setting of the delay amount Ds is changed every 2 steps of the gate line. The source line direction output delay timing generation section 42 generates an output timing setting signal TD including the setting of the delay amount Ds.

The gate line direction output delay timing generation section 41 generates an output timing setting signal TS for setting the delay amounts OE1 to OEy so that the delay time becomes longer as the distance from the gate driver 13A becomes longer. For example, the delay amount of the source driver 14-1 (IC 1) which is the source driver closer to the gate driver 13A is set as the delay amount OE1, and the delay amount of the source driver 14-y (ICy) which is the source driver farther from the gate driver 13A is set as the delay amount OEy. The relation between the retardation amounts OE 1-OEy is OE1 < OE2 … < OEy.

The setting signal adder 43 adds the output timing setting signal TS generated by the gate line direction output delay timing generator 41 and the output timing setting signal TD generated by the source line direction output delay timing generator 42, and supplies the output timing signal LOAD-Gr as the addition result to the data latch unit 21.

For example, as for the source output of the source driver 14-1, as shown as "ts+td (IC 1)" in fig. 9, the delay amount by which the delay amount OE1 is added to the delay amount Ds1_1 is set as a delay time for the output of the pixel portion on the gate line GL1 and the pixel portion on GL 2. Further, the delay amount by which the delay amount OE1 and the delay amount ds1_2 are added is set as a delay time for the output of the pixel portion on the gate line GL3 and the pixel portion on GL 4. In the following, the delay time is set similarly, and the delay amount obtained by adding the delay amount OE1 to the delay amount ds1_y is set as the delay time for the output of the pixel portion on the gate line GL4319 and the pixel portion on GL 4320.

Similarly, regarding the source output of the source driver 14-y, as shown as "ts+td (ICy)" in fig. 9, the delay amount of the delay amount OEy added to the delay amount dsy_1 is set as a delay time for the output of the pixel portion on the gate line GL1 and the pixel portion on GL 2. Further, the delay amount of the delay amount OEy added to the delay amount dsy_2 is set as a delay time for the output of the pixel portion on the gate line GL3 and the pixel portion on GL 4. In the following, the delay time is set similarly, and the delay amount obtained by adding the delay amount OEy to the delay amount Dsy is set as the delay time for the output of the pixel portion on the gate line GL4319 and the pixel portion on GL 4320.

The delay amount Ds is set such that the longer the distance from the source driver to each gate line is, the smaller the delay amount is, and thus, ds1_1 > Ds1_2 > … > Ds1_y is. Furthermore, dsy_1 > dsy_2 > … > dsy_y. In the present embodiment, the setting of the delay amount Ds is changed for every 2 gate lines.

The data latch section 21 outputs the pixel data Q1 to Qk with a delay amount (oe+ds) set based on the output timing signal LOAD-Gr. For example, as shown in fig. 9 as "latch output (IC 1)", the data latch unit 21 of the source driver 14-1 outputs the pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel unit on the gate lines GL1, GL2, GL3, GL4, …, GL4317, GL4318, GL4319, and GL4320 at the timings of V1, V2, V3, V4, …, V4317, V4318, V4319, and V4320. Similarly, the data latch section 21 of the source driver 14-y outputs pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel section of each gate line at the timing shown as "latch output (ICy)" in fig. 9.

Fig. 10 is a view showing a case where the gradation voltage signal (i.e., the source output) is supplied in a direction from the pixel portion at the far end of the source line distant from the source driver toward the pixel portion at the near end of the source line distant from the source driver, unlike fig. 9.

Like the time chart of fig. 9, the gate line counter 31 counts based on the line signal LS, and outputs a counter output COUT showing the count value. The gate line to be supplied as the source output is selected in accordance with the counter output COUT of the gate line counter 31.

When the gradation voltage signals Vd1 to Vdk are supplied from a position on the gate line far from the source driver (i.e., a source line far end) toward a position on the gate line near the source driver (i.e., a source line near end), the gate lines to be supplied for source output are selected in the order of the gate lines GL4320, GL4319, GL4318, GL4317, … GL3, GL2, and GL 1.

The setting of the delay amounts OE1 to OEy by the gate line direction output delay timing generation unit 41, the setting of the delay amount Ds by the source line direction output delay timing generation unit 42, and the setting of the delay amount added thereto to the data latch unit 21 are the same as those of the time chart of fig. 9.

The data latch section 21 outputs the pixel data Q1 to Qk with a delay amount (oe+ds) set based on the output timing signal LOAD-Gr. For example, as shown in fig. 10, the data latch section 21 of the source driver 14-1 outputs pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel section on the gate lines GL4320, GL4319, GL4318, GL4317, …, GL4, GL3, GL2, and GL1 at timings of V4320, V4319, V4318, …, V4, V3, V2, and V1. Similarly, the data latch section 21 of the source driver 14-y outputs pixel data Q1 to Qk corresponding to the gradation voltage signal to be supplied to the pixel section of each gate line at the timing shown as "latch output (ICy)" in fig. 10.

As described above, the control of the output timing can be similarly performed for either the case where the source output is performed from the near end to the far end of the source line (fig. 9) or the case where the source output is performed from the far end to the near end of the source line (fig. 10).

As described above, in the display device of the present embodiment, the gate line direction output delay timing generation section 41 as the first output delay setting section sets the first delay time (delay amount OE) of the source output so that the delay amount becomes larger as the distance in the gate line direction (i.e., the distance from the gate driver) becomes longer. Further, the source line direction output delay timing generation section 42 as the second output delay setting section sets the second delay time (delay amount Ds) of the source output such that the delay amount becomes smaller as the distance in the source line direction (i.e., the distance from the source driver) becomes longer. Then, the timing control section 24 sets the delay time of adding the first delay time (OE) and the second delay time (Ds) as the delay time of the output of the pixel data Q1 to Qk from the data latch section 21.

By adjusting the timings of the outputs of the pixel data Q1 to Qk from the data latch section 21 in this way, the timings of the supply of the gradation voltage signals from the source drivers to the pixel sections are adjusted. By such timing adjustment, the pixel charging rates of the pixel portions P11 to Pnm can be made uniform for the entire display panel 11.

Fig. 11 is a diagram showing signal waveforms and timings of gate signals and gradation voltage signals in each pixel region on the display panel. (1) Each of (4) to (4) corresponds to the regions "GnSn", "GnSf", "GfSn", and "GfSf" of the pixel portion shown in fig. 5, respectively. Note that, the gate signal of fig. 11 also shows an example of a signal waveform in which a gate selection period (high level period) for precharging a pixel portion to be selected (so-called gate precharge) is long, like in fig. 6, and a rising portion of the gate signal is omitted.

When comparing GnSn (1) and GfSn (3), in GnSn, the distance from the Gate driver 13A or 13B is short, the influence of the impedance of the Gate line is small, and therefore, the dullness of the drop in the signal waveform (Gate in the figure) of the Gate signal is small. In contrast, in GfSn, since the distance from the gate driver 13A or 13B is large and the influence of the impedance of the gate line is large, the delay of the drop of the signal waveform of the gate signal is large. Accordingly, in accordance with the timing of the fall of the gate signal (i.e., gate off timing), the delay amount OE1 is set to be small in GnSn, and the delay amount OEf is set to be large in GfSn. The same applies to the comparison between GnSf (2) and GfSf (4).

Next, when comparing GnSn (1) and GnSf (2), in GnSn, the distance from the source driver is short, the influence of the impedance of the source line is small, and thus, the dullness of the rising and falling of the signal waveform (shown as Data in the figure) of the gradation voltage signal is small. In contrast, since GnSf is distant from the source driver, the influence of the impedance of the source line is large, and thus the rising and falling of the signal waveform of the gradation voltage signal is large. Therefore, in accordance with the timing of the rising of the source signal and the falling of the gate signal, the delay amount Ds (=ds 1) is set large in GnSn, and the delay amount Ds is set small in GnSf (in fig. 11, ds 1=0). The same applies to the comparison between GfSn (3) and GfSf (4).

In (1) to (4) of fig. 11, the black-painted portions schematically show the pixel charging rates in the pixel portions of the respective pixel regions. That is, the area of the black-out portion corresponds to the result of integrating the gradation voltage signal in a period from when the gradation voltage signal (Data) starts to rise to when the gate signal falls below the gradation voltage.

In the display device of the present embodiment, in the pixel regions (GfSn, gfSf) where the fall of the gate signal is slow (insensitive), the output of the gradation voltage signal is delayed as compared with the pixel regions where the fall of the gate signal is fast (sensitive), and in the pixel regions (GnSn, gfSn) where the rise of the gradation voltage signal is fast (sensitive), the output of the gradation voltage signal is delayed as compared with the pixel regions (GnSf, gfSf) where the rise of the gradation voltage signal is slow (insensitive), whereby the timing of the source output is adjusted so that the area of the black part becomes the same. Thus, the pixel charging rate in each pixel portion is equalized in the plane of the display panel.

Fig. 12 is a diagram showing signal waveforms of the gate signal and the gradation voltage signal in each pixel region in the comparative example in which the adjustment of the output delay is performed in consideration of only the influence of the impedance of the gate line unlike the display device of the present embodiment.

In comparison between GnSn (1) and GfSn (3), in the pixel region farther from the gate driver 13A or 13B, the delay amount OE is set larger (OEf > OE 1) than in the pixel region nearer to the gate driver 13A or 13B, and therefore, the pixel charging rate in GfSn is reduced and the difference between the pixel charging rate from GnSn is enlarged. The same applies to the comparison between GnSf (2) and GfSf (4).

In the comparison between GnSn (1) and GnSf (2), since the delay time is not adjusted according to the distance from the source driver, the pixel charging rate is lower in the pixel region farther from the source driver than in the pixel region nearer to the source driver.

Therefore, the pixel region of GnSn (1) has the highest pixel charging rate and the pixel region of GfSf has the lowest pixel charging rate, and the difference in pixel charging rate in the display panel surface, that is, the luminance difference is large.

In contrast, in the display device of the present embodiment, since the delay time of the source output is adjusted in consideration of both the influence of the impedance of the gate line and the influence of the impedance of the source line as described above, the difference in pixel charging rate, that is, the luminance difference in the display panel surface can be made uniform.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the display device 100 is a liquid crystal display device has been described, but may be an organic EL (Electro Luminescence) display device, unlike this. In the case where the display device 100 is an organic EL display device, the pixel portion P ₁₁ ～P _nm Each of which has an organic EL element and a thin film transistor controlling a current flowing in the organic EL element. The thin film transistor is supplied to the pixel portion P ₁₁ ～P _nm The gradation voltage signals Vd1 to Vdm of (a) control the current flowing through the organic EL element, and display is performed by changing the light emission luminance of the organic EL element in accordance with the current. In the organic EL display device, the occurrence of luminance unevenness due to the decrease in the writing voltage can be suppressed by applying the present invention.

In the above-described embodiment, the case where the gradation voltage signals are supplied in order from the pixel portion on the gate line closer to the source driver to the pixel portion on the gate line farther from the source driver was described as an example. However, the gradation voltage signals may be supplied in the order from the pixel portion on the gate line farther from the source driver to the pixel portion on the gate line nearer to the source driver. In this case, the pixel electrode can be charged at a point in time when the signal waveform of the gradation voltage signal sufficiently rises as in the above embodiment by making the timing of supply of the gradation voltage signal to the pixel portion distant from the source driver relatively earlier.

In the above embodiment, the case where the gate drivers 13A and 13B are provided on both sides of the display panel 11 and the gate signals are supplied from both sides is described as an example. However, unlike this, the gate driver may be provided only on one side of the display panel 11, and the gate signal may be supplied from one direction.

In the above embodiment, the case where the source driver ICs, that is, the source drivers 14-1 to 14-p are used to supply the gradation voltage signal is described as an example. However, a single source driver may be used to supply all the gradation voltage signals. In short, the source driver including a single source driver IC or a plurality of source driver ICs may have the following configuration as a whole.

That is, the source driver is connected to a transistor having m source lines (SL ₁ ～SL _m ) And n gate lines (GL ₁ ～GL _n ) (m and n are integers of 2 or more), and m×n pixel portions (P) disposed in matrix at each of intersections of the m source lines and the n gate lines ₁₁ ～P _nm ) Receiving Video Data Signals (VDS) of 1 frame size formed by successively forming n pixel data Pieces (PD) for each of m pixel data pieces, and generating gradation voltage signals (Vd 1 to Vdm) to be supplied to each of m x n pixel units based on the video data signals. The source driver includes: a data latch unit (21) that sequentially inputs n pixel data pieces from a video data signal at a predetermined cycle, and sequentially outputs m pixel data pieces included in the input pixel data pieces from m output terminals corresponding to the m source lines; a gradation voltage conversion unit (22) that sequentially introduces the m pieces of pixel data outputted from the data latch unit and converts the m pieces of pixel data into m gradation voltages; an output unit (23) that amplifies and outputs m gradation voltages to m source lines; and a timing control unit (24) that controls the timing of the output of the m pieces of pixel data from the data latch unit. Each of the n pixel data pieces is a pixel data piece corresponding to a gradation voltage signal to be supplied, the gradation voltage signal being a pixel row including n pixel columns each of which is arranged along each of the n gate lines. A timing control unit for controlling the timing of the introduction of the data latch unit of the pixel data slice group corresponding to the gradation voltage signal to be supplied to the pixel column and the introduction of the m pixel data slices constituting the pixel data slice group The timing difference in the timing of the output of the data latch section is controlled so that the timing difference becomes smaller as the length of the source line from the source driver to the pixel column becomes longer.

The timing control unit controls the timing of the output of the data latch unit so that a difference between the timing of the output of 1 pixel data piece corresponding to the gradation voltage signal to be supplied to 1 pixel unit constituting the pixel column and the timing of the output of another pixel data piece corresponding to the gradation voltage signal to be supplied to another pixel unit adjacent to the 1 pixel unit constituting the pixel column increases as the length of the gate line from the gate driver to each pixel unit of the pixel column increases.

According to the structure of the source driver, the occurrence of luminance unevenness due to the decrease of the writing voltage can be suppressed.

Description of the reference numerals

100 display device

11 display panel

12 display controller

13A, 13B gate driver

14-1 to 14-p source driver

20 Source control core

21 data latch section

22 gray scale voltage converting part

23 output part

24 timing control part

31 grid line counter

32 registers

33 output timing control circuit.

Claims

1. A source driver connected to a display panel having m source lines and n gate lines, and m×n pixel portions provided in a matrix at each of intersections of the m source lines and the n gate lines, the source driver receiving video data signals of 1 frame amount formed by successive n pixel data pieces each composed of m pixel data pieces, and generating gradation voltage signals to be supplied to each of the m×n pixel portions based on the video data signals, wherein m and n are integers of 2 or more, the source driver comprising:

a data latch unit that sequentially inputs the n pixel data pieces from the video data signal at a predetermined cycle, and sequentially outputs the m pixel data pieces included in the input pixel data pieces from m output terminals corresponding to the m source lines;

a gradation voltage conversion unit that sequentially introduces the m pieces of pixel data outputted from the data latch unit and converts the m pieces of pixel data into m gradation voltages;

an output unit that amplifies the m gradation voltages and outputs the amplified m gradation voltages to the m source lines; and

a timing control section for controlling the timing of the output of the m pieces of pixel data from the data latch section,

Each of the n pixel data pieces is a pixel data piece corresponding to a gradation voltage signal to be supplied, each of n pixel columns including pixel portions arranged along each of the n gate lines,

the timing control unit controls the timing of the output of the data latch unit so that a timing difference between the timing of the input of the data latch unit of the pixel data piece group corresponding to the gradation voltage signal to be supplied to the pixel column and the timing of the output of the data latch unit of the m pixel data pieces constituting the pixel data piece group becomes smaller as the length of the source line from the source driver to the pixel column becomes longer.

2. The source driver according to claim 1, wherein the timing control unit controls the timing of the output of the data latch unit so that a difference between the timing of the output of 1 pixel data piece corresponding to the gradation voltage signal to be supplied to 1 pixel unit constituting the pixel column and the timing of the output of another pixel data piece corresponding to the gradation voltage signal to be supplied to another pixel unit constituting the pixel column and adjacent to the 1 pixel unit increases as the length of the gate line from the gate driver to each pixel unit of the pixel column increases.

3. The source driver according to claim 1 or 2, wherein,

a gate driver supplying gate signals to each of the m x n pixel parts via the n gate lines is connected to the display panel,

the timing control unit controls the timing of the output of the data latch unit so that a timing difference between the timing of the input of the data latch unit of the pixel data piece corresponding to the gradation voltage signal to be supplied to the pixel unit and the timing of the output of the data latch unit of the m pixel data pieces constituting the pixel data piece group becomes larger as the length of the gate line from the gate driver to each of the m pixel units constituting the pixel column becomes longer.

4. A source driver according to any one of claim 1 to 3,

the timing control section has a counter that counts the n pieces of pixel data for each 1 piece of pixel data corresponding to each of the n gate lines and controls timing of output of the m pieces of pixel data by the data latch section based on a counter value of the counter.

5. A display device, comprising:

a display panel having m source lines, n gate lines, and m×n pixel portions disposed in a matrix at each of intersections of the m source lines and the n gate lines, wherein m and n are integers of 2 or more;

a display controller outputting a video data signal formed by a plurality of continuous pixel data pieces;

a gate driver for supplying gate signals to the m×n pixel units via the n gate lines; and

a plurality of source drivers provided for each predetermined number of the m source lines, receiving the video data signal from the display controller, outputting gradation voltage signals based on the video data signal to the predetermined number of source lines in accordance with timing of the supply of the gate signal from the gate driver,

each of the plurality of source drivers has:

a data latch unit that sequentially inputs, for each predetermined number of pieces of pixel data, pieces of pixel data included in the video data signal at a predetermined period, and outputs the pieces of pixel data from output terminals corresponding to the predetermined number of source lines;

A gradation voltage conversion unit that sequentially introduces the predetermined number of pieces of pixel data outputted from the data latch unit and converts the predetermined number of pieces of pixel data into the predetermined number of gradation voltage signals;

an output unit that amplifies the predetermined number of gradation voltage signals and outputs the amplified predetermined number of gradation voltage signals to the predetermined number of source lines; and

a timing control section for controlling timing of output of the pixel data piece from the data latch section,

the timing control unit includes:

a first output delay setting unit that sets a first delay time such that a time interval from the input to the output of the data latch unit of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel units becomes longer as a length of the gate line from the gate driver to each of a predetermined number of pixel units becomes longer; and

a second output delay setting unit that sets a second delay time such that a time interval from the input to the output of the data latch unit for a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel units becomes smaller as a distance from the source driver to each of the gate lines allocated to each of the predetermined number of pixel units becomes longer,

The timing of the output of the pixel data piece from the data latch section is controlled based on an output delay time determined by the first delay time and the second delay time.

6. The display device according to claim 5, wherein the second output delay setting section sets the second delay time so that the second delay time is changed stepwise for each of the plurality of gate lines for the gate signals of the sequentially selected gate lines.

7. The display device according to claim 5 or 6, wherein the first output delay setting section of each of the plurality of source drivers sets the first delay time in such a manner that the first delay time includes at least a delay time of a leading ch and a delay time that varies stepwise between ch for each source driver.

8. The display device according to any one of claims 5 to 7, wherein,

the timing control section further includes a setting storage section that stores setting information supplied from the display controller to each of the plurality of source drivers at a predetermined timing,

The setting information includes setting information of a delay time with respect to a predetermined timing corresponding to the supply of the gate signal,

the delay time setting information includes at least delay time setting information of the front ch of each source driver, delay time setting information between the ch corresponding to the gate signal delay, delay time of each predetermined gate line corresponding to the source signal delay, and step number setting information showing what stage the delay time is changed to,

the first output delay setting section sets the first delay time based on the delay time of the leading ch and the setting information of the delay time between the ch from the setting storage section,

the second output delay setting section sets the second delay time based on the delay time for each of the predetermined gate lines and the setting information of the number of steps from the setting storage section.

9. The display device according to claim 8, wherein the setting information of the delay time further includes setting information adjusted in such a manner that output timings of a final ch of a source driver adjacent to the source driver and a front ch of the source driver are smoothly continuous.

10. A source driver connected to a display panel having m source lines and n gate lines, and m×n pixel portions provided in a matrix at each of intersections of the m source lines and the n gate lines, the source driver receiving video data signals formed by a plurality of consecutive pieces of pixel data, generating gradation voltage signals for supplying a predetermined number of the m source lines based on the video data signals, and outputting the gradation voltage signals to the predetermined number of source lines in correspondence with timing of supply of gate signals from the gate driver connected to the n gate lines to the plurality of pixel portions, wherein m and n are integers of 2 or more, the source driver comprising:

the timing control unit includes:

a first output delay setting unit that sets a first delay time such that a time interval from the input to the output of the data latch unit of a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the pixel units becomes longer as a length of the gate line from the gate driver to each of a predetermined number of pixel units becomes longer;

a second output delay setting unit that sets a second delay time such that a time interval from the input to the output of the data latch unit for a pixel data piece corresponding to a gradation voltage signal to be supplied to each of the predetermined number of pixel units becomes smaller as a distance from the source driver to the gate line to which each of the predetermined number of pixel units is assigned becomes longer,

11. The source driver according to claim 10, wherein the second output delay setting section sets the second delay time so that the second delay time is changed stepwise for each of the plurality of gate lines for the gate signals of the sequentially selected gate lines.

12. The source driver according to claim 10 or 11, wherein,

the timing control unit further includes a setting storage unit that stores setting information supplied from outside the source driver,

the delay time setting information includes at least delay time setting information of a front ch of the source driver, delay time setting information between ch corresponding to gate signal delay, delay time of each predetermined gate line corresponding to source signal delay, and step number setting information showing a stage to which the delay time is changed,

13. The source driver according to claim 12, wherein the setting information of the delay time further includes setting information adjusted in such a manner that output timings of a final ch of a source driver adjacent to the source driver and a front ch of the source driver are smoothly continuous.