CN113064042A - Junction temperature extraction method of power semiconductor device - Google Patents
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Abstract
The invention relates to a junction temperature extraction method of a power semiconductor device, which is characterized in that a double-pulse experimental circuit is built through simulation software, a SiC MOSFET is taken as an example, the SiC MOSFET is selected as a switching tube, and the drain-source voltage v of the power device is measureddsThe voltage peak and the junction temperature of the power semiconductor are analyzed to find out the causes of the voltage peak, including transconductance coefficient, gate threshold voltage and gate-drain capacitance, and the influencing factors are also influenced by the junction temperature, and the junction temperature and the turn-off voltage peak have negative corresponding relation through simulation experiment. The method has good shielding effect on voltage fluctuation at two ends of the switching tube, and only needs to measure the drain-source voltage vdsThe junction temperature can be obtained through the peak, and compared with other junction temperature extraction methods, the method has the advantages that the reading is easier and the accuracy is higher in the measurement process.
Description
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a junction temperature extraction method of a power semiconductor device.
Background
Power semiconductor devices are widely used in many fields such as communications, traffic, and electric power, and are being developed in the direction of high voltage, high frequency, and high power. The high safety requirements of the above systems have increased the reliability requirements of the power devices. One of the main sources of failure of power converters is failure of the power devices, which is mainly from thermal stress. The higher the working junction temperature of the device is, the smaller the safe operation margin is; the larger the junction temperature fluctuation, the shorter the thermal cycle life. In the normal working temperature range, the failure rate of the device is doubled when the junction temperature of the device rises by 10 ℃. Therefore, monitoring the operating junction temperature of the power device is critical for failure mechanism analysis and life prediction. In addition, junction temperature monitoring provides data support for state monitoring, reliability evaluation and thermal balance control of the power device, and therefore the power device is possible.
At present, a heat sensor method, an infrared thermal imaging method, a thermal sensitive electrical parameter method and an RC thermal resistance network method are provided by research, wherein the thermal sensitive electrical parameter method is distinguished by different thermal sensitive electrical parameters, the method taking voltage change rate as the thermal sensitive electrical parameter is easily affected by disturbance, the method taking conduction voltage drop as the thermal sensitive electrical parameter is difficult to ensure precision, the method taking threshold voltage as the thermal sensitive electrical parameter is difficult to ensure precision, the method taking maximum current change rate as the thermal sensitive electrical parameter is difficult to integrate measurement, and a systematic comprehensive thermal sensitive electrical parameter method is not provided.
The problems that accuracy is difficult to guarantee due to low sensitivity of temperature-sensitive electrical parameters, integration of measuring devices is difficult due to high measuring difficulty, results are easily affected by disturbance due to selection of inappropriate temperature-sensitive electrical parameters, and the like, are urgently needed to be solved by technical personnel in the field, and therefore, a junction temperature extraction method designed for a power semiconductor device is very necessary.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a junction temperature extraction method of a power semiconductor device. The invention designs from the direction of software, measures the peak of the turn-off voltage, finds the corresponding relation between the peak of the turn-off voltage and the junction temperature through a simulation experiment, and further achieves the purpose of extracting the junction temperature. The measurement of the turn-off voltage spike can effectively avoid measurement errors caused by drain-source voltage fluctuation, and the measurement process is simple in reading and high in accuracy.
The invention analyzes the relation between the cut-off voltage peak and the extracted junction temperature through simulation software, and analyzes the relation between the extracted junction temperature and the transconductance coefficient, the threshold voltage and the gate-drain capacitance.
With the increase of the junction temperature of the semiconductor device, the transconductance coefficient is reduced, the threshold voltage is reduced, and the gate-drain capacitance is increased, the variation of the four intermediate quantities finally causes the peak of the turn-off voltage to be reduced, and the relation between the junction temperature and the peak of the turn-off voltage can be obtained according to the relation.
And (3) under the condition of considering different junction temperatures of the semiconductor device, combining a double-pulse test circuit and designing simulation software to carry out experiments.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
a double pulse test circuit comprising: DC power supply UsDouble pulse generator, support capacitor CoHollow inductor L0A silicon carbide MOSFET power cell and a negative voltage source DC,
the silicon carbide MOSFET power cell comprises an upper tube and a lower tube;
the DC power supply UsPositive electrode and supporting capacitor CoIs connected with the DC power supply UsNegative electrode of and supporting capacitor CoIs connected at the other endSupporting capacitor CoOne end of the capacitor is connected with the drain electrode of the upper tube to support the capacitor CoThe other end of the lower tube is connected with the source electrode of the lower tube;
the hollow inductor L0In parallel with the lower tube;
the double-pulse generator is connected with the grid of the upper tube;
the negative electrode of the negative voltage source DC is connected with the grid electrode of the lower tube, and the positive electrode of the negative voltage source DC is connected with the source electrode of the lower tube.
On the basis of the above scheme, the equivalent circuit of the upper tube is the same as that of the lower tube, and the equivalent circuit of the upper tube comprises: drive resistor RgGate inductance LgGate-drain capacitor CgdGate source capacitance CgsA drain electrode inductance LdDrain-source capacitance CdsMOSFET and source electrode inductance Ls；
The driving resistor RgAnd gate inductance LgIs connected to the gate inductance LgThe other end of the MOSFET is connected with the grid electrode of the MOSFET, and a grid leakage capacitor C is arranged between the grid electrode and the drain electrode of the MOSFETgdA gate-source capacitor C is arranged between the gate and the source of the MOSFETgsA drain-source capacitor C is arranged between the drain electrode and the source electrode of the MOSFETdsThe drain electrode of the MOSFET is also connected with a drain electrode inductor LdThe source electrode of the MOSFET is also connected with a source electrode inductor Ls。
On the basis of the scheme, the double-pulse generator and the driving resistor RgConnection, drain inductance LdAnd a support capacitor CoIs connected to the source electrode inductance LsConnected to the drain of the lower tube.
A junction temperature extraction method of a power semiconductor device applies the double-pulse test circuit and comprises the following steps:
before the measurement is started, 5V negative pressure is provided for a grid electrode of the lower tube, and the turn-off of the lower tube is ensured;
sending double pulse signals to the upper tube, observing the current i flowing through the upper tube by an oscilloscopedAnd an upper pipeVoltage v acrossdsThe waveform of (a);
step 2, after reading the turn-off voltage peak, analyzing according to a formula (1);
wherein igRepresents the drive current, CgsRepresenting gate-source capacitance, vgsRepresenting the gate-source voltage, CgdIndicating gate-drain capacitance, vdsRepresenting the drain-source voltage, VPLIndicating driving negative pressure, RgDenotes the drive resistance, LsRepresents the source inductance, igsIndicating the flow through the gate-source capacitance CgsCurrent of (i)dDenotes the drain current, VDCRepresenting a direct voltage, LloopRepresenting power loop inductance, gfsRepresenting the transconductance coefficient;
the formula of the current transformation rate is derived from the formula (1):
wherein, VmWhich is a representation of the voltage of the miller voltage,
the turn-off voltage spike Δ V is derived from equation (2)dsThe formula:
wherein ILRepresenting the load current, VthWhich is indicative of the threshold voltage of the transistor,
this equation shows that the turn-off voltage spike is subject to a threshold voltage VthGate-drain capacitor CgdAnd a transconductance coefficient gfsThe influence of (c).
The formula [ Delta ] V is obtained from the formula (3)ds＝f(gfs,Cgd,Vth) And f represents a functional relationship,
by analyzing the internal working process of the MOSFET, the following results are obtained: threshold voltage VthTransconductance coefficient gfsHaving a negative temperature coefficient, gate-drain capacitance CgdHaving a positive temperature coefficient, threshold voltage VthTransconductance coefficient gfsReduced sum-gate-drain capacitance CgdBoth increases cause a reduction in the off-voltage spike;
thus, the junction temperature TjThe rise will result in Δ VdsDecrease;
for off peak voltage Δ Vds＝f(gfs,Cgd,Vth)＝g(Tj) Is transformed to obtain Tj＝h(gfs,Cgd,Vth)＝k(ΔVds)，TjRepresenting a functional relation of g, h and k for the junction temperature of the semiconductor device;
step 3, after the measurement is finished, releasing the support capacitor C to ensure the safety of the working personneloTo the energy of (c).
The invention has the beneficial effects that:
1. the technical scheme has simple measurement and convenient data acquisition;
2. the method has good shielding effect on voltage fluctuation at two ends when the switching tube is turned off;
3. the selected thermosensitive electrical parameters have good sensitivity and high accuracy;
4. a plurality of intermediate variables are considered in a single thermosensitive electrical parameter, so that the system performance is better, and the accuracy is high;
5. and a plurality of intermediate variables are not required to be measured, so that the measurement cost is reduced.
Drawings
The invention has the following drawings:
FIG. 1 is a schematic diagram of a test circuit of the present invention;
FIG. 2 is a diagram of an equivalent circuit of a SiC MOSFET tested in accordance with the present invention;
FIG. 3 is an idealized overall process waveform diagram of the test circuit of the present invention;
FIG. 4 is a graph of drain-source voltage waveforms at different temperatures for the test circuit of the present invention;
FIG. 5 is a schematic diagram of the turn-off voltage spike and its influencing factors of the present invention;
fig. 6 is a plot of junction temperature versus turn-off voltage spike for the present invention.
Detailed Description
The invention is described in further detail below with reference to figures 1-6.
The embodiment of the invention provides a junction temperature extraction method of a power semiconductor device, which comprises the following steps: the corresponding relation between the turn-off voltage peak and the junction temperature is found through simulation experiments, and the purpose of extracting the junction temperature is further achieved. The measurement of the turn-off voltage spike can effectively avoid measurement errors caused by drain-source voltage fluctuation, and the measurement process is simple in reading and high in accuracy.
Firstly, the relation between a turn-off voltage peak and the extracted junction temperature is analyzed through simulation software, and the relation between the extracted junction temperature and a transconductance coefficient, a threshold voltage and a gate-drain capacitance is analyzed, wherein fig. 1 is a double-pulse test circuit built in a verification experiment of the method. The test circuit includes: DC power supply UsDouble pulse generator, support capacitor CoHollow inductor L0A silicon carbide MOSFET power cell and a negative voltage source DC,
the silicon carbide MOSFET power cell comprises an upper tube and a lower tube;
the DC power supply UsPositive electrode and supporting capacitor CoIs connected with the DC power supply UsNegative electrode of and supporting capacitor CoIs connected with the other end of the supporting capacitor CoOne end of the capacitor is connected with the drain electrode of the upper tube to support the capacitor CoThe other end of the lower tube is connected with the source electrode of the lower tube;
the hollow inductor L0In parallel with the lower tube;
the double-pulse generator is connected with the grid of the upper tube;
the negative electrode of the negative voltage source DC is connected with the grid electrode of the lower tube, and the positive electrode of the negative voltage source DC is connected with the source electrode of the lower tube.
On the basis of the above scheme, the equivalent circuit of the upper tube is the same as that of the lower tube, and as shown in fig. 2, the equivalent circuit of the upper tube includes: drive resistor RgGate inductance LgGate-drain capacitor CgdGate source capacitance CgsA drain electrode inductance LdDrain-source capacitance CdsMOSFET and source electrode inductance Ls；
The driving resistor RgAnd gate inductance LgIs connected to the gate inductance LgThe other end of the MOSFET is connected with the grid electrode of the MOSFET, and a grid leakage capacitor C is arranged between the grid electrode and the drain electrode of the MOSFETgdA gate-source capacitor C is arranged between the gate and the source of the MOSFETgsA drain-source capacitor C is arranged between the drain electrode and the source electrode of the MOSFETdsThe drain electrode of the MOSFET is also connected with a drain electrode inductor LdThe source electrode of the MOSFET is also connected with a source electrode inductor Ls。
On the basis of the scheme, the double-pulse generator and the driving resistor RgConnection, drain inductance LdAnd a support capacitor CoIs connected to the source electrode inductance LsConnected to the drain of the lower tube.
With the increase of the junction temperature of the semiconductor device, the transconductance coefficient is reduced, the threshold voltage is reduced, and the gate-drain capacitance is increased, the variation of the four intermediate quantities finally causes the peak of the turn-off voltage to be reduced, and the relation between the junction temperature and the peak of the turn-off voltage can be obtained according to the relation.
And (3) under the condition of considering different junction temperatures of the semiconductor device, combining a double-pulse test circuit and designing simulation software to carry out experiments.
The test method is a method for analyzing the relation between the junction temperature of a semiconductor and a turn-off voltage peak through simulation experiment test and further determining the junction temperature through the turn-off voltage peak, and specifically comprises the following steps of:
before the measurement is started, 5V negative pressure is provided for a grid electrode of the lower tube, and the turn-off of the lower tube is ensured;
sending double pulse signals to the upper tube, observing the current i flowing through the lower tube by an oscilloscopedAnd the voltage v across the lower tubedsThe waveform of (a);
hollow inductor L0Freewheeling through a schottky freewheeling diode in the lower tube;
in the testing process, the tube is reliably turned off, and a Schottky freewheeling diode in the tube plays a freewheeling role;
FIG. 3 is an idealized overall process waveform diagram of the test circuit of the present invention;
the circuit working process can be divided into three stages, as shown in fig. 3;
t0at the moment, the grid of the upper tube Q1 receives the first pulse, Q1 is in saturated conduction, and the capacitor C is supportedoThe voltage U is applied to the hollow inductor L0Two-terminal, air-core inductor L0Current (sum i) ofdIs the same current) rises linearly;
t1tube Q1 is turned off at any moment, and air core inductor L0The current on the inductor is follow current of a Q2 parallel diode and an air core inductor L0The current above decays slowly, as t in fig. 31And t2I measured as a dashed line between timesdThen decay to 0 soon;
t2at the moment the tube Q1 is turned on again, the diode of Q2 enters reverse recovery, which will pass through Q1, resulting in a current i of Q1dA sharp rise, as shown in fig. 3;
t3at the moment, the tube is turned off again, and because the current of the Q1 turned off at the moment is large, v of the Q1 can be caused due to the existence of stray inductance of the busdsGenerating a voltage spike;
step 2, after the off-voltage peak is read by an oscilloscope, analyzing according to a formula (1);
the formula of the current change rate can be obtained by the formula (1)
Formula (2) can be used to derive the formula of the turn-off voltage spike
This equation shows that the turn-off voltage spike is subject to a threshold voltage VthGate-drain capacitor CgdAnd a transconductance coefficient gfsThe influence of (c).
The formula [ Delta ] V is obtained from the formula (3)ds＝f(gfs,Cgd,Vth) And f represents a functional relationship.
Obtained by analyzing the internal working process of the MOSFET, Vth、gfsHaving a negative temperature coefficient and a gate-drain capacitance CgdHaving a positive temperature coefficient, i.e. Vth、gfsDecrease and CgdThe increase will cause a reduction in the off-voltage spike.
Thus, the junction temperature TjThe rise will result in Δ VdsAnd decreases.
For off peak voltage Δ Vds＝f(gfs,Cgd,Vth)＝g(Tj) Is transformed to obtain Tj＝h(gfs,Cgd,Vth)＝k(ΔVds)，TjRepresenting a functional relation of g, h and k for the junction temperature of the semiconductor device;
step 3, after the measurement is finished, releasing the support capacitor C to ensure the safety of the working personneloTo the energy of (c).
FIG. 4 is a drain-source voltage waveform at different temperatures for the test circuit of the present invention;
the graph shows that the turn-off voltage spike gradually decreases with increasing junction temperature, validating the present invention.
FIG. 5 is a schematic diagram of the turn-off voltage spike and its influencing factors of the present invention;
the graph shows that the increase in junction temperature affects the threshold voltage, the gate-drain capacitance, and the transconductance coefficient, which all affect the turn-off voltage spike drop.
FIG. 6 is a plot of junction temperature versus turn-off voltage spike quantification of the present invention;
example 1
The method of the invention is carried out on SiC MOSFET under the drain-source voltage current level of 700V/300ATesting when the junction temperature is 25-150 ℃, processing data by a linear regression method to obtain the junction temperature TjThe relationship to the off-voltage spike is as follows:
Tj＝-9.212ΔVds+3332.76 (4)
the negative linear relationship between the junction temperature and the drain-source voltage displayed after data processing illustrates the effectiveness of the method provided by the invention.
It should be noted that the above-described embodiments are not intended to limit the scope of the present invention, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein, including but not limited to SiC MOSFETs and Si IGBTs.
Those not described in detail in this specification are within the skill of the art.
Claims (4)
1. A double pulse test circuit, comprising: DC power supply UsDouble pulse generator, support capacitor CoHollow inductor L0A silicon carbide MOSFET power cell and a negative voltage source DC,
the silicon carbide MOSFET power cell comprises an upper tube and a lower tube;
the DC power supply UsPositive electrode and supporting capacitor CoIs connected with the DC power supply UsNegative electrode of and supporting capacitor CoIs connected with the other end of the supporting capacitor CoOne end of the capacitor is connected with the drain electrode of the upper tube to support the capacitor CoThe other end of the lower tube is connected with the source electrode of the lower tube;
the hollow inductor L0In parallel with the lower tube;
the double-pulse generator is connected with the grid of the upper tube;
the negative electrode of the negative voltage source DC is connected with the grid electrode of the lower tube, and the positive electrode of the negative voltage source DC is connected with the source electrode of the lower tube.
2. The double-pulse test circuit of claim 1, wherein the equivalent circuit of the top tube is the same as the equivalent circuit of the bottom tube, the equivalent circuit of the top tube comprising: driving deviceDynamic resistor RgGate inductance LgGate-drain capacitor CgdGate source capacitance CgsA drain electrode inductance LdDrain-source capacitance CdsMOSFET and source electrode inductance Ls；
The driving resistor RgAnd gate inductance LgIs connected to the gate inductance LgThe other end of the MOSFET is connected with the grid electrode of the MOSFET, and a grid leakage capacitor C is arranged between the grid electrode and the drain electrode of the MOSFETgdA gate-source capacitor C is arranged between the gate and the source of the MOSFETgsA drain-source capacitor C is arranged between the drain electrode and the source electrode of the MOSFETdsThe drain electrode of the MOSFET is also connected with a drain electrode inductor LdThe source electrode of the MOSFET is also connected with a source electrode inductor Ls。
3. The double-pulse test circuit of claim 2, wherein the double-pulse generator and the drive resistor RgConnection, drain inductance LdAnd a support capacitor CoIs connected to the source electrode inductance LsConnected to the drain of the lower tube.
4. A junction temperature extraction method for a power semiconductor device, which applies the double-pulse test circuit as claimed in any one of the claims 1 to 3, and is characterized by comprising the following steps:
step 1, building a double-pulse test circuit by using Simplorer simulation software;
before the measurement is started, 5V negative pressure is provided for a grid electrode of the lower tube, and the turn-off of the lower tube is ensured;
sending double pulse signals to the upper tube, observing the current i flowing through the upper tube by an oscilloscopedAnd voltage v across the upper tubedsThe waveform of (a);
step 2, after reading the turn-off voltage peak, analyzing according to a formula (1);
wherein igRepresents the drive current, CgsRepresenting gate-source capacitance, vgsRepresenting the gate-source voltage, CgdIndicating gate-drain capacitance, vdsRepresenting the drain-source voltage, VPLIndicating driving negative pressure, RgDenotes the drive resistance, LsRepresents the source inductance, igsIndicating the flow through the gate-source capacitance CgsCurrent of (i)dDenotes the drain current, VDCRepresenting a direct voltage, LloopRepresenting power loop inductance, gfsRepresenting the transconductance coefficient;
the formula of the current transformation rate is derived from the formula (1):
wherein, VmWhich is a representation of the voltage of the miller voltage,
the turn-off voltage spike Δ V is derived from equation (2)dsThe formula:
wherein ILRepresenting the load current, VthWhich is indicative of the threshold voltage of the transistor,
equation (3) shows that the turn-off voltage spike is subjected to a threshold voltage VthGate-drain capacitor CgdAnd a transconductance coefficient gfsThe influence of (a);
the formula [ Delta ] V is obtained from the formula (3)ds＝f(gfs,Cgd,Vth) And f represents a functional relationship,
by analyzing the internal working process of the MOSFET, the following results are obtained: threshold voltage VthTransconductance coefficient gfsHaving a negative temperature coefficient, gate-drain capacitance CgdHaving a positive temperature coefficient, threshold voltage VthTransconductance coefficient gfsReduced sum-gate-drain capacitance CgdBoth increases cause a reduction in the off-voltage spike;
thus, the junction temperature TjThe rise will result in Δ VdsDecrease;
for off peak voltage Δ Vds＝f(gfs,Cgd,Vth)＝g(Tj) Is transformed to obtain Tj＝h(gfs,Cgd,Vth)＝k(ΔVds)，TjRepresenting a functional relation of g, h and k for the junction temperature of the semiconductor device;
step 3, after the measurement is finished, releasing the support capacitor C to ensure the safety of the working personneloTo the energy of (c).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325292A (en) * | 2021-07-09 | 2021-08-31 | 华北电力大学 | Power semiconductor device gate oxide performance parameter measuring circuit and measuring method thereof |
| CN115951192A (en) * | 2023-03-09 | 2023-04-11 | 长沙丹芬瑞电气技术有限公司 | Junction temperature detection device, method and medium of power device |
| CN116466155A (en) * | 2023-03-24 | 2023-07-21 | 浙江伊控动力系统有限公司 | Method for reducing high-temperature voltage stress of SiC module by dividing Bin |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008054098A (en) * | 2006-08-25 | 2008-03-06 | Nissan Motor Co Ltd | Driving circuit of voltage driving element |
| CN109444706A (en) * | 2018-11-16 | 2019-03-08 | 国网江苏省电力有限公司盐城供电分公司 | A kind of power electronic devices dynamic switching characteristic test method |
| CN109557828A (en) * | 2018-10-31 | 2019-04-02 | 西安理工大学 | A kind of SiCMOSFET simulation circuit model parameters precision bearing calibration |
| US20190376850A1 (en) * | 2018-06-07 | 2019-12-12 | General Electric Company | Systems and methods for monitoring junction temperature of a semiconductor switch |
| CN111460748A (en) * | 2020-03-24 | 2020-07-28 | 北京交通大学 | Method for establishing SiC MOSFET short circuit simulation model |
| CN112001127A (en) * | 2020-08-28 | 2020-11-27 | 河北工业大学 | IGBT junction temperature prediction method |
-
2021
- 2021-02-01 CN CN202110134810.6A patent/CN113064042B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008054098A (en) * | 2006-08-25 | 2008-03-06 | Nissan Motor Co Ltd | Driving circuit of voltage driving element |
| US20190376850A1 (en) * | 2018-06-07 | 2019-12-12 | General Electric Company | Systems and methods for monitoring junction temperature of a semiconductor switch |
| CN109557828A (en) * | 2018-10-31 | 2019-04-02 | 西安理工大学 | A kind of SiCMOSFET simulation circuit model parameters precision bearing calibration |
| CN109444706A (en) * | 2018-11-16 | 2019-03-08 | 国网江苏省电力有限公司盐城供电分公司 | A kind of power electronic devices dynamic switching characteristic test method |
| CN111460748A (en) * | 2020-03-24 | 2020-07-28 | 北京交通大学 | Method for establishing SiC MOSFET short circuit simulation model |
| CN112001127A (en) * | 2020-08-28 | 2020-11-27 | 河北工业大学 | IGBT junction temperature prediction method |
Non-Patent Citations (3)
| Title |
|---|
| DAN ZHENG等: "Monitoring of SiC MOSFET Junction Temperature with On-state Voltage at High Currents", 《CHINESE JOURNAL OF ELECTRICAL ENGINEERING》 * |
| HUI LI等: "Analysis of Voltage Variation in Silicon Carbide MOSFETs during Turn-On and Turn-Off", 《ENERGIES》 * |
| 任磊等: "电力电子电路中功率晶体管结温在线测量技术研究现状", 《电工技术学报》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325292A (en) * | 2021-07-09 | 2021-08-31 | 华北电力大学 | Power semiconductor device gate oxide performance parameter measuring circuit and measuring method thereof |
| CN115951192A (en) * | 2023-03-09 | 2023-04-11 | 长沙丹芬瑞电气技术有限公司 | Junction temperature detection device, method and medium of power device |
| CN116466155A (en) * | 2023-03-24 | 2023-07-21 | 浙江伊控动力系统有限公司 | Method for reducing high-temperature voltage stress of SiC module by dividing Bin |
| CN116466155B (en) * | 2023-03-24 | 2024-05-07 | 浙江伊控动力系统有限公司 | Method for reducing high-temperature voltage stress of SiC module by dividing Bin |
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