CN113053293A - Shifting register unit, grid driving circuit and display panel - Google Patents
Shifting register unit, grid driving circuit and display panel Download PDFInfo
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- CN113053293A CN113053293A CN202110371494.4A CN202110371494A CN113053293A CN 113053293 A CN113053293 A CN 113053293A CN 202110371494 A CN202110371494 A CN 202110371494A CN 113053293 A CN113053293 A CN 113053293A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The disclosure relates to the technical field of display, and provides a shift register unit, a gate drive circuit and a display panel. The shift register unit includes: the input circuit is connected with the signal input end, the first node, the first clock signal end, the second node and the third node; the first control circuit is connected with the first power supply end, the third node, the signal input end and the second clock signal end; the second control circuit is connected with the first power supply end, the first node, the second node and the fourth node; the output circuit is connected with the fourth node, the second node, the signal output end, the first power supply end and the second power supply end; the coupling circuit is connected between the first clock signal end and the third node; the first storage circuit is connected with the fourth node; the second storage circuit is connected to the second node. The shift register unit has a stable output.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to a shift register unit, a gate driving circuit and a display panel.
Background
In a display panel, a pixel driving circuit generally requires a gate driving circuit to provide a gate driving signal, the gate driving circuit may be composed of a plurality of cascaded shift register units, and the plurality of shift register units may sequentially output a shift signal to form the gate driving signal. However, in the prior art, the shift signal output by the shift register unit is not stable, thereby causing abnormal driving of the pixel driving circuit.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
According to an aspect of the present disclosure, there is provided a shift register unit, wherein the shift register unit includes: the input circuit is connected with a signal input end, a first node, a first clock signal end, a second node and a third node, and is used for responding to a signal of the first clock signal end to transmit a signal of the signal input end to the first node and responding to a signal of the third node to transmit a signal of the first clock signal end to the second node; the first control circuit is connected with the first power supply end, the third node, the signal input end and the second clock signal end and is used for responding to the signal of at least one of the signal input end and the second clock signal end to transmit the signal of the first power supply end to the third node; a second control circuit connected to a first power source terminal, a first node, a second node, and a fourth node, for transmitting a signal of the first power source terminal to the second node in response to a signal of the first node, and for transmitting a signal of the first power source terminal to the fourth node in response to a signal of the second node, wherein the first node and the fourth node are connected; the output circuit is connected with a fourth node, a second node, a signal output end, a first power supply end and a second power supply end, and is used for responding to the signal of the fourth node, transmitting the signal of the second power supply end to the signal output end and responding to the signal of the second node, transmitting the signal of the first power supply end to the signal output end; a coupling circuit connected between the first clock signal terminal and the third node for coupling a signal of the first clock signal terminal to the third node; the first storage circuit is connected with the fourth node; the second storage circuit is connected to the second node.
In an exemplary embodiment of the present disclosure, the method further includes: and the third control circuit is connected with the signal input end, the second node, the second clock signal end and the second power supply end and is used for responding to the signals of the signal input end and the second clock signal end and transmitting the signal of the second power supply to the second node.
In an exemplary embodiment of the present disclosure, the method further includes: and the isolation circuit is connected to the first node, the fourth node and the second power end and used for responding to the second power end signal to conduct the first node and the fourth node.
In one exemplary embodiment of the present disclosure, the input circuit includes: the first pole of the first switch transistor is connected with the signal input end, the second pole of the first switch transistor is connected with the first node, and the grid of the first switch transistor is connected with the first clock signal end; the first pole of the second switch transistor is connected with the first clock signal end, the second pole of the second switch transistor is connected with the second node, and the grid of the second switch transistor is connected with the third node.
In one exemplary embodiment of the present disclosure, the first control circuit includes: the first pole of the third switching transistor is connected with the first power supply end, the second pole of the third switching transistor is connected with the third node, and the grid of the third switching transistor is connected with the signal input end; and the fourth switching transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the second clock signal terminal.
In an exemplary embodiment of the present disclosure, the second control circuit includes: a fifth switching transistor having a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the first node; a sixth switching transistor has a first terminal connected to the first power terminal, a second terminal connected to the fourth node, and a gate connected to the second node.
In an exemplary embodiment of the present disclosure, the output circuit includes: a seventh switching transistor, an eighth switching transistor, a first electrode of the seventh switching transistor being connected to the second power supply terminal, a second electrode of the seventh switching transistor being connected to the signal output terminal, and a gate of the seventh switching transistor being connected to the fourth node; the eighth switch transistor has a first electrode connected to the first power terminal, a second electrode connected to the signal output terminal, and a gate connected to the second node.
In an exemplary embodiment of the present disclosure, the coupling circuit includes: the first capacitor is connected between the first clock signal end and the third node; the first storage circuit includes: a second capacitor connected between the fourth node and the signal output terminal; the second storage circuit includes: a third capacitor connected between the second node and the first power supply terminal.
In one exemplary embodiment of the present disclosure, the third control circuit includes: a ninth switching transistor, a tenth switching transistor, a first electrode of the ninth switching transistor being connected to the second power supply terminal, and a gate thereof being connected to the signal input terminal; and the first pole of the tenth switching transistor is connected with the second pole of the ninth switching transistor, the second pole of the tenth switching transistor is connected with the second node, and the grid of the tenth switching transistor is connected with the second clock signal end.
In an exemplary embodiment of the present disclosure, the isolation circuit includes: and the first pole of the eleventh switching transistor is connected with the first node, the second pole of the eleventh switching transistor is connected with the fourth node, and the grid of the eleventh switching transistor is connected with the second power supply end.
According to an aspect of the present disclosure, there is provided a shift register unit driving method for driving the shift register unit, the driving method including:
in the first stage, inputting effective level signals to a second clock signal end and a signal input end, and inputting invalid level signals to a first clock signal end;
in the second stage, inputting effective level signals to the first clock signal end and the signal input end, and inputting ineffective level signals to the second clock signal end;
in the third stage, inputting an invalid level signal to the first clock signal end and the signal input end, and inputting an effective level signal to the second clock signal end;
in the fourth stage, an invalid level signal is input to the second clock signal terminal and the signal input terminal, and an effective level signal is input to the first clock signal terminal.
According to an aspect of the present disclosure, there is provided a gate driving circuit, including: a plurality of cascaded shift register units.
According to an aspect of the present disclosure, a display panel is provided, which includes the gate driving circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram of an exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 2 is a timing diagram of nodes of the shift register unit of FIG. 1;
FIG. 3 is a state diagram of the shift register unit of FIG. 1 at a first stage;
FIG. 4 is a state diagram of the shift register unit of FIG. 1 at a second stage;
FIG. 5 is a state diagram of the shift register unit of FIG. 1 at a third stage;
FIG. 6 is a state diagram of the shift register unit of FIG. 1 at a fourth stage;
FIG. 7 is a schematic diagram of another exemplary embodiment of a shift register cell according to the present disclosure;
FIG. 8 is a state diagram of the shift register cell of FIG. 7 at a first stage;
FIG. 9 is a state diagram of the shift register unit of FIG. 7 at a second stage;
FIG. 10 is a state diagram of the shift register unit of FIG. 7 at a third stage;
FIG. 11 is a state diagram of the shift register unit of FIG. 7 at a fourth stage.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
The present exemplary embodiment first provides a shift register unit, as shown in fig. 1, which is a schematic structural diagram of an exemplary embodiment of the shift register unit of the present disclosure. Wherein, the shift register unit may include: the circuit includes an input circuit 1, a first control circuit 2, a second control circuit 3, an output circuit 4, a coupling circuit 5, a first storage circuit 6, and a second storage circuit 7. The input circuit 1 may be connected to a signal input terminal IN, a first node N1, a first clock signal terminal CK, a second node N2, a third node N3, for transmitting a signal of the signal input terminal IN to the first node N1 IN response to a signal of the first clock signal terminal CK, and for transmitting a signal of the first clock signal terminal CK to the second node N2 IN response to a signal of the third node N3; the first control circuit 2 may be connected to the first power source terminal VGL, the third node N3, the signal input terminal IN, and the second clock signal terminal CB, for transmitting a signal of the first power source terminal VGL to the third node N3 IN response to a signal of at least one of the signal input terminal IN and the second clock signal terminal CB; the second control circuit 3 may be connected to a first power source terminal VGL, a first node N1, a second node N2, a fourth node N4, for transmitting a signal of the first power source terminal VGL to the second node N2 in response to a signal of the first node N1, and for transmitting a signal of the first power source terminal VGL to the fourth node N4 in response to a signal of the second node N2, wherein the first node N1 and the fourth node N4 are connected; the output circuit 4 may be connected to a fourth node N4, a second node N2, a signal output terminal OUT, a first power source terminal VGL, a second power source terminal VGH, for transmitting a signal of the second power source terminal VGH to the signal output terminal OUT in response to a signal of the fourth node N4, and for transmitting a signal of the first power source terminal VGL to the signal output terminal OUT in response to a signal of the second node N2; the coupling circuit 5 may be connected between the first clock signal terminal CK and the third node N3 for coupling the signal of the first clock signal terminal CK to the third node N3; the first memory circuit 6 may be connected to said fourth node N4; the second storage circuit 7 may be connected to said second node N2. The first node N1 and the fourth node N4 are connected, and it is understood that the first node N1 and the fourth node N4 are directly connected or indirectly connected.
In the present exemplary embodiment, the first power source terminal VGL may continuously output the inactive level, and the second power source terminal VGH may continuously output the active level. The driving method of the shift register unit can comprise four stages: the first stage, the second stage, the third stage and the fourth stage. In the first stage: it is possible to input an active level signal to the second clock signal terminal CB, the signal input terminal IN, and an inactive level signal to the first clock signal terminal CK, the first control circuit 2 transmits the inactive level of the first power source terminal VGL to the third node by the active level of the signal input terminal IN, the input circuit 1 is turned off by the inactive level of the first clock signal terminal CK, the third node N3, the fourth node N4 maintains the inactive level of the previous stage (fourth stage), the second node N2 maintains the active level of the previous stage, and the output circuit 4 transmits the inactive level of the first power source terminal to the signal output terminal OUT IN response to the active level of the second node N2. In the second stage: the active level signal is input to the first clock signal terminal CK, the signal input terminal IN, the inactive level signal is input to the second clock signal terminal CB, the input circuit 1 transmits the active level of the signal input terminal IN to the first node N1 and the fourth node N4 IN response to the active level of the first clock signal terminal CK, the second control circuit 3 transmits the inactive level of the first power source terminal to the second node IN response to the active level of the first node N1, and the output circuit 4 transmits the active level of the second power source terminal to the signal output terminal OUT IN response to the active level of the fourth node. In the third stage: the first node N1 and the fourth node N4 maintain the active level of the previous stage under the action of the first storage circuit 6, the second node maintains the inactive level of the previous stage under the action of the second storage circuit 7, and the signal output terminal OUT still outputs the active level. In a fourth phase: the input circuit 1 transmits the invalid level of the signal input terminal IN to the first node and the fourth node IN response to the valid level of the first clock signal terminal CK, the third node jumps to the valid level by the action of the coupling circuit 5, the input circuit transmits the valid level of the first clock signal terminal CK to the second node IN response to the valid level of the third node, and the output circuit 4 transmits the invalid level of the first power terminal to the signal output terminal OUT IN response to the valid level of the second node. Therefore, the shift register unit can stably output the shift signal under the control of the first clock signal end, the second clock signal end and the signal input end. Note that the active level is a level at which the driver circuit can operate, for example, as shown in fig. 1, the input circuit may include the first switching transistor T1 of an N-type, and the active level is a high level.
In the present exemplary embodiment, as shown in fig. 1, the input circuit 1 may include: a first switch transistor T1, a second switch transistor T2, a first electrode of the first switch transistor T1 is connected to the signal input terminal IN, a second electrode is connected to the first node N1, and a gate is connected to the first clock signal terminal CK; the second switching transistor T2 has a first electrode connected to the first clock signal terminal CK, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3.
In the present exemplary embodiment, as shown in fig. 1, the first control circuit 2 may include: a third switching transistor T3, a fourth switching transistor T4, a first electrode of the third switching transistor T3 is connected to the first power source terminal VGL, a second electrode is connected to the third node N3, and a gate is connected to the signal input terminal IN; the fourth switching transistor T4 has a first electrode connected to the first power terminal VGL, a second electrode connected to the third node N3, and a gate connected to the second clock signal terminal CB.
In the present exemplary embodiment, as shown in fig. 1, the second control circuit 3 may include: a fifth switching transistor T5, a sixth switching transistor T6, a fifth switching transistor T5 having a first electrode connected to the first power source terminal VGL, a second electrode connected to the second node N2, and a gate connected to the first node N1; the sixth switching transistor T6 has a first terminal connected to the first power source terminal VGL, a second terminal connected to the fourth node N4, and a gate connected to the second node N2.
In the present exemplary embodiment, as shown in fig. 1, the output circuit 4 may include: a seventh switching transistor T7, an eighth switching transistor T8, a first electrode of the seventh switching transistor T7 being connected to the second power source terminal VGH, a second electrode thereof being connected to the signal output terminal OUT, and a gate thereof being connected to the fourth node N4; the eighth switching transistor T8 has a first terminal connected to the first power terminal VGL, a second terminal connected to the signal output terminal OUT, and a gate connected to the second node N2.
In the present exemplary embodiment, as shown in fig. 1, the coupling circuit 5 may include: a first capacitor C1 and a first capacitor C1 are connected between the first clock signal terminal CK and the third node N3. The first memory circuit 6 may be connected between the fourth node N4 and the signal output terminal OUT, and the first memory circuit 6 may include: a second capacitor C2 and a second capacitor C2 are connected between the fourth node N4 and the signal output terminal OUT. The second memory circuit 7 may be connected between the second node N2 and the first power source terminal VGL, and the second memory circuit 7 may include: a third capacitor C3 and a third capacitor C3 are connected between the second node N2 and the first power source terminal VGL.
In the present exemplary embodiment, as shown in fig. 1, the shift register unit may further include: and an isolation circuit 8, the isolation circuit 8 being connectable to the first node N1, the fourth node N4, and the second power source terminal VGH for turning on the first node N1 and the fourth node N4 in response to the second power source terminal VGH signal. The isolation circuit 8 can isolate the fourth node N4 from the first node N1 when the voltage of the fourth node N4 is excessive.
In the present exemplary embodiment, as shown in fig. 1, the isolation circuit 8 may include: and an eleventh switching transistor T11, wherein a first electrode of the eleventh switching transistor T11 is connected to the first node N1, a second electrode thereof is connected to the fourth node N4, and a gate thereof is connected to the second power source terminal VGH.
It should be understood that, in other exemplary embodiments, the input circuit 1, the first control circuit 2, the second control circuit 3, the output circuit 4, the coupling circuit 5, the first storage circuit 6, the second storage circuit 7, and the isolation circuit 8 may have other structures, the shift register unit may not include the isolation circuit, and the first node and the fourth node may be directly connected. All falling within the scope of the present disclosure.
In the present exemplary embodiment, as shown in fig. 1, the switching transistor may be an N-type switching transistor, the first power source terminal VGL may be a low-level signal terminal, and the second power source terminal VGH may be a high-level signal terminal. It should be understood that, in other exemplary embodiments, the switching transistor may be a P-type transistor, and accordingly, the first power source terminal VGL may be a high-level signal terminal and the second power source terminal VGH may be a low-level signal terminal.
As shown IN fig. 2, fig. 2 is a timing diagram of each node of the shift register unit IN fig. 1, where CK represents the timing of the first clock signal terminal, CB represents the timing of the second clock signal terminal, IN represents the timing of the signal input terminal, and OUT represents the timing of the signal output terminal. The driving method of the shift register unit can comprise four stages: a first stage t1, a second stage t2, a third stage t3 and a fourth stage t 4. It should be noted that the timing diagram of each node in fig. 2 is an ideal timing diagram, and actually, the timing diagram of each node has a rising edge and a falling edge with a certain duration.
Fig. 3 shows a state diagram of the shift register unit in fig. 1 at a first stage t1, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the first stage t1, the second clock signal terminal CB and the signal input terminal IN output high level signals, and the first clock signal terminal CK outputs low level signals. The first switching transistor T1 is turned off, the first node N1 and the fourth node N4 maintain the low level signal of the previous stage (fourth stage), and the seventh switching transistor T7 is turned off; the third switching transistor T3 and the fourth switching transistor T4 are turned on, the first power supply terminal VGL inputs a low level signal to the third node, the second switching transistor T2 is turned off, the second node maintains a high level signal of the previous stage, the eighth switching transistor T8 is turned on, and the first power supply terminal VGL outputs a low level signal to the signal output terminal OUT through the eighth switching transistor T8.
Fig. 4 shows a state diagram of the shift register unit in fig. 1 at a second stage t2, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the second stage t2, the first clock signal terminal CK and the signal input terminal IN output high level signals, and the second clock signal terminal CB outputs low level signals. The first switching transistor T1 is turned on, the signal input terminal IN inputs a high level signal to the first node N1, the eleventh switching transistor T11 is turned on, the first node N1 inputs a high level signal to the fourth node N4, the seventh switching transistor T7 is turned on, the second power supply terminal VGH inputs a high level signal to the signal output terminal OUT through the seventh switching transistor T7, when the signal output terminal OUT outputs a high level signal, the fourth node N4 (the source of the eleventh switching transistor) is boosted by the coupling of the second capacitor C2, the voltage difference between the gate and the source of the eleventh switching transistor T11 is smaller than the threshold voltage thereof, and the eleventh switching transistor is turned off; meanwhile, the fifth switching transistor T5 is turned on, the first power source terminal VGL inputs a low level signal to the second node, and the eighth switching transistor T8 is turned off. The eleventh switching transistor T11 isolating the first node N1 and the fourth node N4 may prevent the first switching transistor T1 from being turned off due to the voltage of the first node N1 being too high. When the first switching transistor T1 is turned off, the first node N1 is in a floating state, and the voltage thereof is unstable.
Fig. 5 shows a state diagram of the shift register unit in fig. 1 at a third stage t3, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the third stage, the first clock signal terminal CK and the signal input terminal IN output low level signals, and the second clock signal terminal CB outputs high level signals. The first switching transistor T1 is turned off, the first node N1 and the fourth node N4 maintain the high level signal of the previous stage, the seventh switching transistor T7 is turned on, the second power source terminal VGH inputs the high level signal to the signal output terminal OUT, and the eleventh switching transistor is turned off continuously; the fifth switching transistor T5 is turned on continuously, the second node N2 is a low signal, and the eighth switching transistor T8 is turned off.
Fig. 6 shows a state diagram of the shift register unit in fig. 1 at a fourth stage t4, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the fourth phase t4, the second clock signal terminal CB and the signal input terminal IN output low level signals, and the first clock signal terminal CK outputs high level signals. The first switching transistor T1 is turned on, the signal input terminal IN inputs a low level signal to the first node N1 and the fourth node N4, and the seventh switching transistor T7 is turned off; the first clock signal terminal CK changes from a low level to a high level, the voltage of the third node N3 changes to a high level under the coupling action of the first capacitor C1, the second switching transistor T2 is turned on, the first clock signal terminal CK inputs a high level signal to the second node N2, the eighth switching transistor T8 is turned on, and the first power supply terminal VGL inputs a low level signal to the signal output terminal OUT.
The shift register unit not only can stably output the shift signal, but also has a simpler structure and lower cost.
Fig. 7 is a schematic structural diagram of another exemplary embodiment of a shift register unit according to the present disclosure. Compared to the shift register unit shown in fig. 1, the shift register unit further includes: a third control circuit 9, the third control circuit 9 may include: a ninth switching transistor T9, a tenth switching transistor T10, a first electrode of the ninth switching transistor T9 being connected to the second power source terminal VGH, and a gate thereof being connected to the signal input terminal IN; a tenth switching transistor has a first pole connected to the second pole of the ninth switching transistor, a second pole connected to the second node N2, and a gate connected to the second clock signal terminal CB.
The driving method of the shift register unit shown in fig. 7 may also include four stages, wherein the timing of each node in the shift register unit at each stage may be as shown in fig. 2.
Fig. 8 shows a state diagram of the shift register unit in fig. 7 at a first stage t1, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the first stage t1, the second clock signal terminal CB and the signal input terminal IN output high level signals, and the first clock signal terminal CK outputs low level signals. The first switching transistor T1 is turned off, the first node N1 and the fourth node N4 maintain the low level signal of the previous stage (fourth stage), and the seventh switching transistor T7 is turned off; the third switching transistor T3 and the fourth switching transistor T4 are turned on, the first power supply terminal VGL inputs a low level signal to the third node, the second switching transistor T2 is turned off, the ninth switching transistor T9 and the tenth switching transistor T10 are turned on, the second power supply terminal VGH inputs a high level signal to the second node N2, the eighth switching transistor T8 is turned on, and the first power supply terminal VGL outputs a low level signal to the signal output terminal OUT through the eighth switching transistor T8.
Fig. 9 shows a state diagram of the shift register unit in fig. 7 at a second stage t2, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the second stage t2, the first clock signal terminal CK and the signal input terminal IN output high level signals, and the second clock signal terminal CB outputs low level signals. The first switching transistor T1 is turned on, the signal input terminal IN inputs a high level signal to the first node N1, the eleventh switching transistor T11 is turned on, the first node N1 inputs a high level signal to the fourth node N4, the seventh switching transistor T7 is turned on, the second power supply terminal VGH inputs a high level signal to the signal output terminal OUT through the seventh switching transistor T7, when the signal output terminal OUT outputs a high level signal, the fourth node N4 (the source of the eleventh switching transistor) is boosted by the coupling of the second capacitor C2, the voltage difference between the gate and the source of the eleventh switching transistor T11 is smaller than the threshold voltage thereof, and the eleventh switching transistor is turned off; meanwhile, the fifth switching transistor T5 is turned on, the first power source terminal VGL inputs a low level signal to the second node, and the eighth switching transistor T8 is turned off.
Fig. 10 shows a state diagram of the shift register unit in fig. 7 at a third stage t3, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the third stage, the first clock signal terminal CK and the signal input terminal IN output low level signals, and the second clock signal terminal CB outputs high level signals. The first switching transistor T1 is turned off, the first node N1 and the fourth node N4 maintain the high level signal of the previous stage, the seventh switching transistor T7 is turned on, the second power source terminal VGH inputs the high level signal to the signal output terminal OUT, and the eleventh switching transistor is turned off continuously; the fifth switching transistor T5 is turned on continuously, the second node N2 is a low signal, and the eighth switching transistor T8 is turned off.
Fig. 11 shows a state diagram of the shift register unit in fig. 7 at a fourth stage t4, in which the crossed switch transistors are turned off and the non-crossed switch transistors are turned on. IN the fourth phase t4, the second clock signal terminal CB and the signal input terminal IN output low level signals, and the first clock signal terminal CK outputs high level signals. The first switching transistor T1 is turned on, the signal input terminal IN inputs a low level signal to the first node N1 and the fourth node N4, and the seventh switching transistor T7 is turned off; the first clock signal terminal CK changes from a low level to a high level, the voltage of the third node N3 changes to a high level under the coupling action of the first capacitor C1, the second switching transistor T2 is turned on, the first clock signal terminal CK inputs a high level signal to the second node N2, the eighth switching transistor T8 is turned on, and the first power supply terminal VGL inputs a low level signal to the signal output terminal OUT.
The shift register cell shown in fig. 7 can input a high-level signal to the second node N2 in the first stage compared to the shift register cell shown in fig. 1, so that the eighth switching transistor T8 can be sufficiently turned on in the first stage.
The present exemplary embodiment further provides a shift register unit driving method, for driving the shift register unit, where the driving method includes:
in the first stage, inputting effective level signals to a second clock signal end and a signal input end, and inputting invalid level signals to a first clock signal end;
in the second stage, inputting effective level signals to the first clock signal end and the signal input end, and inputting ineffective level signals to the second clock signal end;
in the third stage, inputting an invalid level signal to the first clock signal end and the signal input end, and inputting an effective level signal to the second clock signal end;
in the fourth stage, an invalid level signal is input to the second clock signal terminal and the signal input terminal, and an effective level signal is input to the first clock signal terminal.
The driving method has been described in detail in the above, and is not described herein again.
The present exemplary embodiment also provides a gate driving circuit, including: a plurality of cascaded shift register units. The signal output end of the shift register unit of the previous stage can be connected with the signal input end of the shift register unit of the next stage.
The present exemplary embodiment also provides a display panel including the gate driving circuit described above. The display panel can be used for forming display devices such as mobile phones and tablet computers.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.
Claims (13)
1. A shift register cell, comprising:
an input circuit connected to a signal input terminal, a first node, a first clock signal terminal, a second node, and a third node, for transmitting a signal of the signal input terminal to the first node in response to a signal of the first clock signal terminal, and for transmitting a signal of the first clock signal terminal to the second node in response to a signal of the third node;
the first control circuit is connected with the first power supply end, the third node, the signal input end and the second clock signal end and is used for responding to the signal of at least one of the signal input end and the second clock signal end to transmit the signal of the first power supply end to the third node;
a second control circuit connected to a first power source terminal, a first node, a second node, and a fourth node, for transmitting a signal of the first power source terminal to the second node in response to a signal of the first node, and for transmitting a signal of the first power source terminal to the fourth node in response to a signal of the second node, wherein the first node and the fourth node are connected;
an output circuit connected to a fourth node, a second node, a signal output terminal, a first power terminal, and a second power terminal, for transmitting a signal of the second power terminal to the signal output terminal in response to a signal of the fourth node, and for transmitting a signal of the first power terminal to the signal output terminal in response to a signal of the second node;
a coupling circuit connected between the first clock signal terminal and the third node, for coupling a signal of the first clock signal terminal to the third node;
a first storage circuit connected to the fourth node;
and the second storage circuit is connected with the second node.
2. The shift register cell of claim 1, further comprising:
and the third control circuit is connected with the signal input end, the second node, the second clock signal end and the second power end and is used for responding the signals of the signal input end and the second clock signal end and transmitting the signal of the second power supply to the second node.
3. The shift register cell of claim 1 or 2, wherein the first storage circuit is connected between the fourth node and the signal output terminal, the shift register cell further comprising:
and the isolation circuit is connected to the first node, the fourth node and the second power end and used for responding to the second power end signal to conduct the first node and the fourth node.
4. The shift register cell of claim 1, wherein the input circuit comprises:
a first switch transistor, a first pole of which is connected with a signal input end, a second pole of which is connected with the first node, and a grid of which is connected with the first clock signal end;
and the first pole of the second switching transistor is connected with the first clock signal end, the second pole of the second switching transistor is connected with the second node, and the grid of the second switching transistor is connected with the third node.
5. The shift register cell of claim 1, wherein the first control circuit comprises:
a third switching transistor having a first terminal connected to the first power terminal, a second terminal connected to the third node, and a gate connected to the signal input terminal;
and a fourth switching transistor, wherein a first electrode of the fourth switching transistor is connected with the first power supply end, a second electrode of the fourth switching transistor is connected with the third node, and a grid electrode of the fourth switching transistor is connected with the second clock signal end.
6. The shift register cell of claim 1, wherein the second control circuit comprises:
a fifth switching transistor having a first terminal connected to the first power terminal, a second terminal connected to the second node, and a gate connected to the first node;
and a sixth switching transistor having a first electrode connected to the first power source terminal, a second electrode connected to the fourth node, and a gate connected to the second node.
7. The shift register cell of claim 1, wherein the output circuit comprises:
a seventh switching transistor having a first terminal connected to the second power terminal, a second terminal connected to the signal output terminal, and a gate connected to the fourth node;
and the eighth switching transistor has a first electrode connected with the first power supply end, a second electrode connected with the signal output end and a grid electrode connected with the second node.
8. The shift register cell of claim 1,
the coupling circuit includes:
a first capacitor connected between the first clock signal terminal and the third node;
the first storage circuit includes:
a second capacitor connected between the fourth node and the signal output terminal;
the second storage circuit includes:
and a third capacitor connected between the second node and the first power supply terminal.
9. The shift register cell of claim 2, wherein the third control circuit comprises:
a ninth switching transistor, having a first electrode connected to the second power terminal and a gate connected to the signal input terminal;
and a tenth switching transistor, wherein the first pole of the tenth switching transistor is connected with the second pole of the ninth switching transistor, the second pole of the tenth switching transistor is connected with the second node, and the grid of the tenth switching transistor is connected with the second clock signal end.
10. The shift register cell of claim 3, wherein the isolation circuit comprises:
and the eleventh switching transistor has a first electrode connected with the first node, a second electrode connected with the fourth node, and a grid electrode connected with the second power supply end.
11. A shift register cell driving method for driving the shift register cell according to any one of claims 1 to 10, the driving method comprising:
in the first stage, inputting effective level signals to a second clock signal end and a signal input end, and inputting invalid level signals to a first clock signal end;
in the second stage, inputting effective level signals to the first clock signal end and the signal input end, and inputting ineffective level signals to the second clock signal end;
in the third stage, inputting an invalid level signal to the first clock signal end and the signal input end, and inputting an effective level signal to the second clock signal end;
in the fourth stage, an invalid level signal is input to the second clock signal terminal and the signal input terminal, and an effective level signal is input to the first clock signal terminal.
12. A gate drive circuit, comprising: a plurality of cascaded shift register cells as claimed in any one of claims 1 to 10.
13. A display panel comprising the gate driving circuit of claim 12.
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| CN113053293B (en) | 2022-07-19 |
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