CN115294916A

CN115294916A - Shifting register unit and driving method thereof, grid driving circuit and display panel

Info

Publication number: CN115294916A
Application number: CN202211116957.3A
Authority: CN
Inventors: 程鸿飞
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2022-09-14
Filing date: 2022-09-14
Publication date: 2022-11-04

Abstract

The disclosure relates to the technical field of display, and provides a shift register unit, a driving method thereof, a gate driving circuit and a display panel. The shift register unit includes: the circuit comprises a first input circuit, a second input circuit, a first storage circuit, a second storage circuit, a first pull-down circuit, a second pull-down circuit, a first output circuit, a second output circuit and a third storage circuit. The first input circuit is used for inputting an effective level to the second node; the second input circuit is used for inputting an effective level to the third node; the first storage circuit is used for storing the voltage between a first node and a first clock signal end; the second storage circuit is used for storing the voltage between the second node and the second clock signal terminal; the first pull-down circuit is used for pulling down the first node; the second pull-down circuit is used for pulling down the second node; the first output circuit and the second output circuit are used for outputting signals; the third storage circuit is used for storing the voltage of the third node. The shift register unit has a simple structure.

Description

Shifting register unit and driving method thereof, grid driving circuit and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display panel.

Background

The display panel usually provides the enable signal to the pixel driving circuit through the gate driving circuit, and in the related art, the structure of the gate driving circuit is complex and the cost is high.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a shift register unit including: the circuit comprises a first input circuit, a second input circuit, a first storage circuit, a second storage circuit, a first pull-down circuit, a second pull-down circuit, a first output circuit, a second output circuit and a third storage circuit. The first input circuit is connected with a first clock signal end, a first node and a second node and is used for responding to the signal of the first node and transmitting the signal of the first clock signal end to the second node; the second input circuit is connected with a signal input end, a third node and a first clock signal end and is used for responding to the signal of the first clock signal end and transmitting the signal of the signal input end to the third node; a first storage circuit connected between the first clock signal terminal and the first node for storing a voltage between the first node and the first clock signal terminal; the second storage circuit is connected between a second clock signal end and the second node and used for storing the voltage between the second node and the second clock signal end; the first pull-down circuit is connected with the signal input end, a first power end and a first node and is used for responding to the signal of the signal input end and transmitting the signal of the first power end to the first node; a second pull-down circuit connected to the first power source terminal, a third node, and a second node, for transmitting a signal of the first power source terminal to the second node in response to a signal of the third node; the first output circuit is connected with the second node, the first power supply end and the signal output end and is used for responding to the signal of the second node and transmitting the signal of the first power supply end to the signal output end; the second output circuit is connected with the third node, a second power supply end and a signal output end and is used for responding to the signal of the third node and transmitting the signal of the second power supply end to the signal output end; the third storage circuit is connected to the third node and used for storing the voltage of the third node.

In one exemplary embodiment of the present disclosure, the shift register unit further includes: and the third pull-down circuit is connected with the second node, the third node, the first power supply end and the second clock signal end and is used for responding to the signals of the second node and the second clock signal end and transmitting the signal of the first power supply end to the third node.

In one exemplary embodiment of the present disclosure, the first input circuit includes: a first transistor, wherein a first pole of the first transistor is connected with a first clock signal end, a second pole of the first transistor is connected with the second node, and a grid of the first transistor is connected with the first node; the second input circuit includes: and a third transistor, wherein a first pole of the third transistor is connected with the signal input end, a second pole of the third transistor is connected with the third node, and a grid electrode of the third transistor is connected with the first clock signal end.

In one exemplary embodiment of the present disclosure, the first storage circuit includes: a first electrode of the first capacitor is connected with the first clock signal end, and a second electrode of the first capacitor is connected with the first node; the second storage circuit includes: a first electrode of the second capacitor is connected with the second clock signal end, and a second electrode of the second capacitor is connected with the second node; the third storage circuit includes: and a first electrode of the third capacitor is connected with the third node, and a second electrode of the third capacitor is connected with the second power supply end.

In one exemplary embodiment of the present disclosure, the first pull-down circuit includes: a second transistor, wherein a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the first power terminal, and a gate of the second transistor is connected to the signal input terminal; the second pull-down circuit includes: and a fourth transistor, wherein a first electrode of the fourth transistor is connected with the second node of the book search, a second electrode of the fourth transistor is connected with the first power supply end, and a grid of the fourth transistor is connected with the third node.

In one exemplary embodiment of the present disclosure, the first output circuit includes: a fifth transistor, a first electrode of which is connected to the first power terminal, a second electrode of which is connected to the signal output terminal, and a gate of which is connected to the second node; the second output circuit includes: and a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second power supply terminal, a second electrode of the sixth transistor is connected to the signal output terminal, and a gate of the sixth transistor is connected to the third node.

In an exemplary embodiment of the present disclosure, the third pull-down circuit includes: a seventh transistor and an eighth transistor, wherein a first electrode of the seventh transistor is connected to the first power supply terminal, and a gate of the seventh transistor is connected to the second node; and the first pole of the eighth transistor is connected with the second pole of the seventh transistor, the second pole of the eighth transistor is connected with the third node, and the grid of the eighth transistor is connected with the second clock signal end.

According to an aspect of the present disclosure, there is provided a shift register unit driving method, the driving method including:

in the first stage: inputting an invalid level signal to the signal input end and the first clock signal end, and inputting an effective level signal to the second clock signal end;

in a second stage: inputting an invalid level signal to a signal input end and a second clock signal end, and inputting an effective level signal to the first clock signal end;

in the third stage: inputting an invalid level signal to the first clock signal end, and inputting an effective level signal to the signal input end and the second clock signal end;

in a fourth phase: and inputting an invalid level signal to the second clock signal end, and inputting an effective level signal to the signal input end and the first clock signal end.

According to an aspect of the present disclosure, a gate driving circuit is provided, which includes the shift register unit described above.

According to an aspect of the present disclosure, a display panel is provided, which includes the gate driving circuit described above.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a schematic diagram of an exemplary embodiment of a shift register cell according to the present disclosure;

FIG. 2 is a timing diagram of various control signals in an exemplary embodiment of the shift register cell of FIG. 1;

FIG. 3 is a state diagram of the shift register unit shown in FIG. 1 at a first buffering stage;

FIG. 4 is a state diagram of the shift register cell of FIG. 1 at a first stage;

FIG. 5 is a state diagram of the shift register unit shown in FIG. 1 at a second stage;

FIG. 6 is a state diagram of the shift register unit shown in FIG. 1 at a second buffering stage;

FIG. 7 is a state diagram of the shift register unit shown in FIG. 1 at a third stage;

FIG. 8 is a state diagram of the shift register unit shown in FIG. 1 at a fourth stage;

FIG. 9 is a schematic diagram of another exemplary embodiment of a shift register cell according to the present disclosure;

FIG. 10 is a state diagram of the shift register unit of FIG. 9 in a first buffering stage;

FIG. 11 is a state diagram of the shift register cell of FIG. 9 in a first stage;

FIG. 12 is a state diagram of the shift register cell of FIG. 9 in a second stage;

FIG. 13 is a state diagram of the shift register cell of FIG. 9 at a second buffering stage;

FIG. 14 is a state diagram of the shift register unit of FIG. 9 at a third stage;

FIG. 15 is a state diagram of the shift register cell of FIG. 9 at a fourth stage.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a detailed description thereof will be omitted.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

The present exemplary embodiment first provides a shift register unit, as shown in fig. 1, which is a schematic structural diagram of an exemplary embodiment of the shift register unit of the present disclosure. The shift register unit may include: the first input circuit 11, the second input circuit 12, the first memory circuit 21, the second memory circuit 22, the first pull-down circuit 31, the second pull-down circuit 32, the first output circuit 41, the second output circuit 42, and the third memory circuit 23. The first input circuit 11 is connected to a first clock signal terminal CK, a first node N1, and a second node N2, and is configured to transmit a signal of the first clock signal terminal CK to the second node N2 in response to a signal of the first node N1; the second input circuit 12 is connected to a signal input terminal IN, a third node N3, and a first clock signal terminal CK, and is configured to transmit a signal of the signal input terminal IN to the third node N3 IN response to a signal of the first clock signal terminal CK; the first storage circuit 21 is connected between the first clock signal terminal CK and the first node N1, and is configured to store a voltage between the first node N1 and the first clock signal terminal CK; the second storage circuit 22 is connected between a second clock signal terminal CB and the second node N2, and is configured to store a voltage between the second node N2 and the second clock signal terminal CB; the first pull-down circuit 31 is connected to the signal input terminal IN, the first power terminal VGL, and the first node N1, and is configured to transmit a signal of the first power terminal VGL to the first node N1 IN response to a signal of the signal input terminal IN; the second pull-down circuit 32 is connected to the first power source terminal VGL, a third node N3, and a second node N2, and is configured to transmit a signal of the first power source terminal VGL to the second node N2 in response to a signal of the third node N3; the first output circuit 41 is connected to the second node N2, the first power terminal VGL, and the signal output terminal OUT, and is configured to transmit a signal of the first power terminal VGL to the signal output terminal OUT in response to a signal of the second node N2; the second output circuit 42 is connected to the third node N3, the second power source terminal VGH, and the signal output terminal OUT, and is configured to transmit the signal of the second power source terminal VGH to the signal output terminal OUT in response to the signal of the third node N3; the third storage circuit 23 is connected to the third node N3, and is configured to store a voltage of the third node N3.

In the present exemplary embodiment, the first power source terminal VGL may output an inactive level, and the second power source terminal VGH may output an active level. The active level is a level capable of driving the target circuit to normally operate, the inactive level is a level for turning off the target circuit, for example, when the target circuit is an N-type transistor, the active level is a high level, and the inactive level is a low level.

The driving method of the shift register unit may include: the method comprises a first buffering stage, a first stage, a second buffering stage, a third stage and a fourth stage. IN the first buffering stage, the inactive level may be input to the first clock signal terminal CK, the active level may be input to the signal input terminal IN, the second clock signal terminal CB, the third node N3 maintains the active level of the previous stage (the fourth stage), the second pull-down circuit 32 transmits the inactive level of the first power source terminal VGL to the second node N2, the first output circuit 41 is turned off by the inactive level of the second node N2, the second output circuit 42 transmits the active level of the second power source terminal VGH to the signal output terminal OUT by the active level of the third node N3, and simultaneously, the first pull-down circuit 31 is turned on by the signal input terminal IN to transmit the inactive level of the first power source terminal VGL to the first node N1, and the first input circuit 11 and the second input circuit 12 are turned off. In the first stage: an inactive level signal may be input to the signal input terminal IN, the first clock signal terminal CK, an active level signal may be input to the second clock signal terminal CB, the third node N3 maintains an active level of a previous stage (a first buffer stage), the second pull-down circuit 32 transmits the inactive level of the first power source terminal VGL to the second node N2, the first output circuit 41 is turned off by the inactive level of the second node N2, and the second output circuit 42 transmits the active level of the second power source terminal VGH to the signal output terminal OUT by the active level of the third node N3. Meanwhile, the second input circuit 12 is turned off, the first node N1 maintains the inactive level of the previous stage (first buffering stage), and the first input circuit 11 is turned off. In the second stage: it is possible to input the disable level signal to the signal input terminal IN, the second clock signal terminal CB, input the active level signal to the first clock signal terminal CK, the first memory circuit 21 couples the active level of the first clock signal terminal CK to the first node N1, the first input circuit 11 transmits the active level of the first clock signal terminal CK to the second node N2, the first output circuit 41 transmits the disable level of the first power source terminal VGL to the signal output terminal OUT under the action of the second node N2, and at the same time, the second input circuit 12 transmits the disable level of the signal input terminal IN to the third node N3, and the second output circuit 42, the second pull-down circuit 32 are turned off. IN the second buffering stage, the inactive level may be input to the signal input terminal IN and the first clock signal terminal CK, the active level may be input to the second clock signal terminal CB, the first storage circuit 21 couples the inactive level of the first clock signal terminal CK to the first node N1, the first input circuit 11 and the second input circuit 12 are turned off, the second storage circuit 22 couples the active level of the second clock signal terminal CB to the second node N2, the first output circuit 41 transmits the inactive level of the first power terminal VGL to the signal output terminal OUT under the action of the second node N2, the third node N3 maintains the inactive level of the previous stage (second stage), and the second output circuit 42 is turned off. In a third stage: the first pull-down circuit 31 transmits the disable level of the first power terminal to the first node N1 under the action of the signal input terminal IN, the first input circuit 11 is turned off, the second node N2 maintains the enable level of the previous stage (IN the second buffer stage), the first output circuit 41 continuously transmits the disable level of the first power terminal VGL to the signal output terminal OUT under the action of the second node N2, and simultaneously, the third node N3 maintains the disable level of the previous stage (IN the second buffer stage), and the second output circuit 42 is turned off. In a fourth phase: an inactive level signal is input to the second clock signal terminal CB, an active level signal is input to the signal input terminal IN and the first clock signal terminal CK, the first pull-down circuit 31 transmits the inactive level of the first power supply terminal VGL to the first node N1, the first input circuit 11 is turned off, the second input circuit 12 transmits the active level of the signal input terminal IN to the third node N3, the second output circuit 42 transmits the active level of the second power supply terminal VGH to the signal output terminal OUT under the action of the third node N3, and simultaneously, the second pull-down circuit 32 transmits the inactive level of the first power supply terminal VGL to the second node N2, and the first output circuit 41 is turned off. The shift register unit can output an enable signal required by the pixel driving circuit.

It should be understood that in other exemplary embodiments, the driving method of the shift register unit may not include the first buffer stage and the second buffer stage.

In the present exemplary embodiment, the first input circuit 11 may include: a first transistor T1, a first pole of the first transistor T1 being connected to the first clock signal terminal CK, a second pole being connected to the second node N2, and a gate being connected to the first node N1; the second input circuit 12 may include: and a third transistor T3, wherein a first pole of the third transistor T3 is connected to the signal input terminal IN, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to the first clock signal terminal CK.

In the present exemplary embodiment, the first storage circuit 21 may include: a first electrode of the first capacitor C1 is connected to the first clock signal terminal CK, and a second electrode of the first capacitor C1 is connected to the first node N1; the second storage circuit 22 may include: a first electrode of the second capacitor C2 is connected to the second clock signal terminal CB, and a second electrode of the second capacitor C2 is connected to the second node N2; the third storage circuit 23 may include: and a first electrode of the third capacitor C3 is connected to the third node N3, and a second electrode of the third capacitor C3 is connected to the second power supply terminal VGH.

In the present exemplary embodiment, the first pull-down circuit 31 may include: a second transistor T2, wherein a first electrode of the second transistor T2 is connected to the first node N1, a second electrode is connected to the first power source terminal VGL, and a gate is connected to the signal input terminal IN; the second pull-down circuit 32 may include: and a fourth transistor T4, wherein a first pole of the fourth transistor T4 is connected to the second node N2, a second pole is connected to the first power source terminal VGL, and a gate is connected to the third node N3.

In the present exemplary embodiment, the first output circuit 41 may include: a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is connected to the first power terminal VGL, a second electrode of the fifth transistor T5 is connected to the signal output terminal OUT, and a gate of the fifth transistor T5 is connected to the second node N2; the second output circuit 42 may include: and a sixth transistor T6, wherein a first pole of the sixth transistor T6 is connected to the second power supply terminal VGH, a second pole of the sixth transistor T6 is connected to the signal output terminal OUT, and a gate of the sixth transistor T6 is connected to the third node N3.

In the present exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be N-type transistors. It should be understood that in other exemplary embodiments, the transistors may also be P-type transistors.

Fig. 2 is a timing diagram of various control signals in an exemplary embodiment of the shift register cell of fig. 1. Wherein, CK represents a timing diagram of the first clock signal terminal, CB represents a timing diagram of the second clock signal terminal, IN represents a timing diagram of the signal input terminal, and OUT represents a timing diagram of the signal output terminal.

As shown in fig. 2, the driving method of the shift register unit may include: a first buffer stage t11, a first stage t1, a second stage t2, a second buffer stage t31, a third stage t3, and a fourth stage t4.

IN the first buffering stage t11, a low level signal may be input to the first clock signal terminal CK, and a high level signal may be input to the signal input terminal IN and the second clock signal terminal CB. As shown in fig. 3, a state diagram of the shift register unit shown in fig. 1 in the first buffering stage is shown, where in the present exemplary embodiment, the transistors that are hatched are off transistors, and the transistors that are not hatched are on transistors. As shown IN fig. 3, the third node N3 maintains the high level of the previous stage (the fourth stage), the fourth transistor T4 is turned on, the fourth transistor T4 transmits the low level signal of the first power source terminal VGL to the second node N2, the fifth transistor T5 is turned off by the low level signal of the second node N2, the sixth transistor T6 is turned on by the high level signal of the third node N3 to transmit the high level signal of the second power source terminal VGH to the signal output terminal OUT, and the second transistor T2 is turned on by the signal input terminal IN to transmit the low level signal of the first power source terminal VGL to the first node N1, and the first transistor T1 and the third transistor T3 are turned off.

In the first phase t1: a low level signal can be input to the signal input terminal IN, the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, as shown IN fig. 4, which is a state diagram of the shift register unit shown IN fig. 1 at the first stage. The third node N3 maintains the high level of the previous stage (the first buffer stage), the fourth transistor T4 is turned on to transmit the low level signal of the first power source terminal VGL to the second node N2, the fifth transistor T5 is turned off under the action of the low level signal of the second node N2, the sixth transistor T6 transmits the high level of the second power source terminal VGH to the signal output terminal OUT under the action of the high level signal of the third node N3, the first node N1 maintains the low level of the previous stage (the first buffer stage), and the first transistor T1 and the third transistor T3 are turned off.

In the second stage t2: a low level signal may be input to the signal input terminal IN, the second clock signal terminal CB, and a high level signal may be input to the first clock signal terminal CK. Fig. 5 is a state diagram of the shift register unit shown in fig. 1 at the second stage. The first capacitor C1 couples the high level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 is turned on to transmit the high level signal of the first clock signal terminal CK to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low level signal of the first power terminal VGL to the signal output terminal OUT, and simultaneously, the third transistor T3 is turned on to transmit the low level signal of the signal input terminal IN to the third node N3, and the sixth transistor T6 and the fourth transistor T4 are turned off.

IN the second buffering stage t31, a low level signal can be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, as shown IN fig. 6, which is a state diagram of the shift register unit shown IN fig. 1 IN the second buffering stage. The first capacitor C1 couples the low level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 and the third transistor T3 are turned off, the second capacitor C2 couples the high level signal of the second clock signal terminal CB to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low level of the first power terminal VGL to the signal output terminal OUT, the third node N3 maintains the low level of the previous stage (the second stage), and the sixth transistor T6 is turned off.

In a third stage: as shown IN fig. 7, a state diagram of the shift register unit shown IN fig. 1 at the third stage is shown, IN which a low level signal is input to the first clock signal terminal CK, and a high level signal is input to the signal input terminal IN and the second clock signal terminal CB. The second transistor T2 is turned on by the signal input terminal IN to transmit the low level signal of the first power terminal to the first node N1, the first transistor T1 is turned off, the second node N2 maintains the high level of the previous stage (the second buffer stage), the fifth transistor T5 is continuously turned on by the second node N2 to transmit the low level signal of the first power terminal VGL to the signal output terminal OUT, meanwhile, the third node N3 maintains the low level of the previous stage (the second buffer stage), and the sixth transistor T6 is turned off.

In a fourth phase: as shown IN fig. 8, a state diagram of the shift register unit shown IN fig. 1 at the fourth stage is shown, IN which a low level signal is input to the second clock signal terminal CB, and a high level signal is input to the signal input terminal IN and the first clock signal terminal CK. The second transistor T2 is turned on to transmit the low-level signal of the first power source terminal VGL to the first node N1, the first transistor T1 is turned off, the third transistor T3 is turned on to transmit the high-level signal of the signal input terminal IN to the third node N3, the sixth transistor T6 is turned on by the third node N3 to transmit the high-level signal of the second power source terminal VGH to the signal output terminal OUT, the fourth transistor T4 is turned on to transmit the low-level signal of the first power source terminal VGH to the second node N2, and the fifth transistor T5 is turned off.

Fig. 9 is a schematic structural diagram of another exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit may further include: a third pull-down circuit 33, the third pull-down circuit 33 being connectable to the second node N2, the third node N3, the first power terminal VGL, the second clock terminal CB, for transmitting the signal of the first power terminal VGL to the third node N3 in response to the signals of the second node N2 and the second clock terminal CB.

In the present exemplary embodiment, the third pull-down circuit 33 includes: a seventh transistor T7 and an eighth transistor T8, wherein a first electrode of the seventh transistor T7 is connected to the first power supply terminal VGL, and a gate thereof is connected to the second node N2; a first pole of the eighth transistor T8 is connected to a second pole of the seventh transistor T7, a second pole is connected to the third node N3, and a gate is connected to the second clock signal terminal CB. The seventh transistor T7 and the eighth transistor T8 may be N-type transistors.

Timing diagrams of the various control signals in an exemplary embodiment of the shift register cell can be seen in fig. 2. The driving method of the shift register unit can also comprise the following steps: a first buffer stage t11, a first stage t1, a second stage t2, a second buffer stage t31, a third stage t3, and a fourth stage t4.

IN the first buffering period t11, a low level signal may be input to the first clock signal terminal CK, and a high level signal may be input to the signal input terminal IN and the second clock signal terminal CB. As shown in fig. 10, a state diagram of the shift register unit shown in fig. 9 in the first buffering stage is shown, where in the present exemplary embodiment, the transistors that are hatched are off transistors, and the transistors that are not hatched are on transistors. As shown IN fig. 10, the third node N3 maintains the high level of the previous stage (the fourth stage), the fourth transistor T4 is turned on, the fourth transistor T4 transmits the low level signal of the first power source terminal VGL to the second node N2, the fifth and seventh transistors T5 and T7 are turned off by the low level signal of the second node N2, the sixth transistor T6 is turned on by the high level signal of the third node N3 to transmit the high level signal of the second power source terminal VGH to the signal output terminal OUT, and simultaneously the second transistor T2 is turned on by the signal input terminal IN to transmit the low level signal of the first power source terminal VGL to the first node N1, the first transistor T1 and the third transistor T3 are turned off, and the eighth transistor T8 is turned on.

In the first phase t1: a low level signal can be input to the signal input terminal IN, the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, as shown IN fig. 11, which is a state diagram of the shift register unit shown IN fig. 9 at the first stage. The third node N3 maintains the high level of the previous stage (the first buffer stage), the fourth transistor T4 is turned on to transmit the low level signal of the first power source terminal VGL to the second node N2, the fifth transistor T5 and the seventh transistor T7 are turned off under the action of the low level signal of the second node N2, the sixth transistor T6 transmits the high level of the second power source terminal VGH to the signal output terminal OUT under the action of the high level signal of the third node N3, the first node N1 maintains the low level of the previous stage (the first buffer stage), the first transistor T1 and the third transistor T3 are turned off, and the eighth transistor T8 is turned on.

In the second stage t2: a low level signal may be input to the signal input terminal IN, the second clock signal terminal CB, and a high level signal may be input to the first clock signal terminal CK. FIG. 12 is a state diagram of the shift register unit of FIG. 9 in the second stage. The first capacitor C1 couples the high level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 is turned on to transmit the high level signal of the first clock signal terminal CK to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low level signal of the first power terminal VGL to the signal output terminal OUT, and at the same time, the third transistor T3 is turned on to transmit the low level signal of the signal input terminal IN to the third node N3, the sixth transistor T6, the fourth transistor T4, the eighth transistor T8 are turned off, and the seventh transistor is turned on.

IN the second buffering stage t31, a low level signal can be input to the signal input terminal IN and the first clock signal terminal CK, and a high level signal can be input to the second clock signal terminal CB, as shown IN fig. 13, which is a state diagram of the shift register unit shown IN fig. 9 IN the second buffering stage. The first capacitor C1 couples the low level signal of the first clock signal terminal CK to the first node N1, the first transistor T1 and the third transistor T3 are turned off, the second capacitor C2 couples the high level signal of the second clock signal terminal CB to the second node N2, the fifth transistor T5 is turned on by the second node N2 to transmit the low level signal of the first power terminal VGL to the signal output terminal OUT, the seventh transistor T7 and the eighth transistor T8 are turned on to transmit the low level signal of the first power terminal VGL to the third node N3, and the sixth transistor T6 is turned off.

In the third stage: as shown IN fig. 14, a state diagram of the shift register unit IN the third stage shown IN fig. 9 is shown, IN which a low level signal is input to the first clock signal terminal CK, and a high level signal is input to the signal input terminal IN and the second clock signal terminal CB. The second transistor T2 is turned on by the signal input terminal IN to transmit the low level signal of the first power source terminal VGL to the first node N1, the first transistor T1 is turned off, the second node N2 maintains the high level of the previous stage (the second buffer stage), the fifth transistor T5 is continuously turned on by the second node N2 to transmit the low level signal of the first power source terminal VGL to the signal output terminal OUT, and meanwhile, the seventh transistor T7 and the eighth transistor T8 are turned on to transmit the low level signal of the first power source terminal VGL to the third node N3, and the sixth transistor T6 is turned off.

In a fourth phase: as shown IN fig. 15, a state diagram of the shift register unit shown IN fig. 9 at the fourth stage is shown, IN which a low level signal is input to the second clock signal terminal CB, and a high level signal is input to the signal input terminal IN and the first clock signal terminal CK. The second transistor T2 is turned on to transmit the low level signal of the first power source terminal VGL to the first node N1, the first transistor T1 is turned off, the third transistor T3 is turned on to transmit the high level signal of the signal input terminal IN to the third node N3, the sixth transistor T6 is turned on by the third node N3 to transmit the high level signal of the second power source terminal VGH to the signal output terminal OUT, the fourth transistor T4 is turned on to transmit the low level signal of the first power source terminal to the second node N2, and the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.

The present exemplary embodiment also provides a shift register unit driving method, including:

in the first stage: inputting an invalid level signal to the signal input terminal IN and the first clock signal terminal CK, and inputting a valid level signal to the second clock signal terminal CB;

in the second stage: inputting an invalid level signal to a signal input end IN and a second clock signal end CB, and inputting an effective level signal to a first clock signal end CK;

in the third stage: inputting an invalid level signal to the first clock signal terminal CK, and inputting a valid level signal to the signal input terminal IN and the second clock signal terminal CB;

in a fourth phase: an inactive level signal is input to the second clock signal terminal CB, and an active level signal is input to the signal input terminal IN and the first clock signal terminal CK.

The exemplary embodiment further provides a gate driving circuit, where the gate driving circuit includes a plurality of shift register units, the shift register units may be sequentially cascaded, and a signal output end of a shift register unit at a previous stage may be connected to a signal input end of a shift register unit at a next stage. The gate driving circuit may provide a gate driving signal or an enable signal to the pixel driving circuit.

The present exemplary embodiment also provides a display panel including the gate driving circuit described above. The display panel can be applied to display devices such as mobile phones, tablet computers and televisions.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.

Claims

1. A shift register cell, comprising:

the first input circuit is connected with a first clock signal end, a first node and a second node and is used for responding to the signal of the first node and transmitting the signal of the first clock signal end to the second node;

the second input circuit is connected with a signal input end, a third node and a first clock signal end and is used for responding to a signal of the first clock signal end to transmit a signal of the signal input end to the third node;

a first storage circuit connected between the first clock signal terminal and the first node, for storing a voltage between the first node and the first clock signal terminal;

a second storage circuit connected between a second clock signal terminal and the second node, for storing a voltage between the second node and the second clock signal terminal;

a first pull-down circuit connected to the signal input terminal, a first power terminal, and a first node, for transmitting a signal of the first power terminal to the first node in response to a signal of the signal input terminal;

a second pull-down circuit, connected to the first power terminal, a third node, and a second node, for transmitting the signal of the first power terminal to the second node in response to the signal of the third node;

a first output circuit, connected to said second node, a first power supply terminal, and a signal output terminal, for transmitting a signal of said first power supply terminal to said signal output terminal in response to a signal of said second node;

the second output circuit is connected with the third node, a second power supply end and a signal output end and is used for responding to the signal of the third node and transmitting the signal of the second power supply end to the signal output end;

and the third storage circuit is connected to the third node and used for storing the voltage of the third node.

2. The shift register cell of claim 1, further comprising:

and the third pull-down circuit is connected with the second node, the third node, the first power supply end and the second clock signal end and is used for responding to the signals of the second node and the second clock signal end and transmitting the signal of the first power supply end to the third node.

3. The shift register cell of claim 1, wherein the first input circuit comprises:

a first transistor, wherein a first pole of the first transistor is connected with a first clock signal end, a second pole of the first transistor is connected with the second node, and a grid of the first transistor is connected with the first node;

the second input circuit includes:

and a third transistor, wherein a first pole of the third transistor is connected with the signal input end, a second pole of the third transistor is connected with the third node, and a grid electrode of the third transistor is connected with the first clock signal end.

4. The shift register cell of claim 1, wherein the first storage circuit comprises:

a first electrode of the first capacitor is connected with the first clock signal end, and a second electrode of the first capacitor is connected with the first node;

the second storage circuit includes:

a first electrode of the first capacitor is connected with the first clock signal end, and a second electrode of the first capacitor is connected with the second node;

the third storage circuit includes:

and a third capacitor, wherein the first electrode is connected with the third node, and the second electrode is connected with the second power supply end.

5. The shift register cell of claim 1, wherein the first pull-down circuit comprises:

a second transistor, having a first electrode connected to the first node, a second electrode connected to the first power terminal, and a gate connected to the signal input terminal;

the second pull-down circuit includes:

and a first electrode of the fourth transistor is connected with the second node of the search book, a second electrode of the fourth transistor is connected with the first power supply end, and a grid electrode of the fourth transistor is connected with the third node.

6. The shift register cell of claim 1, wherein the first output circuit comprises:

a fifth transistor, having a first electrode connected to the first power terminal, a second electrode connected to the signal output terminal, and a gate connected to the second node;

the second output circuit includes:

and a sixth transistor having a first electrode connected to the second power terminal, a second electrode connected to the signal output terminal, and a gate connected to the third node.

7. The shift register cell of claim 2, wherein the third pull-down circuit comprises:

a seventh transistor having a first electrode connected to the first power supply terminal and a gate connected to the second node;

and the first pole of the eighth transistor is connected with the second pole of the seventh transistor, the second pole of the eighth transistor is connected with the third node, and the grid of the eighth transistor is connected with the second clock signal end.

8. A driving method of a shift register unit is characterized by comprising the following steps:

in the first stage: inputting invalid level signals to a signal input end and a first clock signal end, and inputting valid level signals to a second clock signal end;

in the second stage: inputting an invalid level signal to a signal input end and a second clock signal end, and inputting an effective level signal to the first clock signal end;

9. A gate drive circuit, characterized in that the gate drive circuit comprises a shift register cell according to any one of claims 1 to 7.

10. A display panel comprising the gate driver circuit according to claim 9.