CN113037508B - A power-off control circuit and a power-off control method - Google Patents

Abstract

The power-off control circuit and the power-off control method provided by the application acquire the current of the PSE power supply through the current detection circuit and convert the current into the voltage, and control the second PSE chip through the second overcurrent comparison circuit according to the voltage, so that the power-on and power-off of the PD corresponding to the second PSE chip are controlled. After the corresponding PD of second PSE chip is electrified, the output of second overcurrent comparison circuit passes through voltage control circuit and will fit comparative voltage input to the second input of first overcurrent comparison circuit for first overcurrent comparison circuit can be according to the first PSE chip of this voltage control, thereby control and power up and down with the corresponding PD of first PSE chip. Therefore, the power-off control method and the power-off control device can firstly power off part of the PDs, and then control the power on and off of the other part of the PDs after the power off of the part of the PDs, so that the power off of the PDs is controlled in a grading manner, when the load is changed, the power off of unimportant PDs can be controlled, the important PDs are controlled finally, and the influence is reduced.

Description

A power-off control circuit and a power-off control method

technical field

The embodiments of the present application relate to the technical field of circuit power supply, and in particular, to a power-off control circuit and a power-off control method.

Background technique

With the development of modern technology, the application of power over Ethernet (PoE) is becoming more and more extensive, and more and more devices support PoE. These PoE-enabled devices can obtain power through PoE and do not need an external power supply. convenient. PoE refers to the power supply for some terminals (such as IP phones, wireless LAN access points (APs), Network cameras, etc.) while transmitting data signals, it can also provide DC power supply technology for such devices. PoE is also known as power over LAN (PoL) or active Ethernet, and is sometimes referred to simply as Power over Ethernet. The equipment that provides power is a power sourcing equipment (PSE), and the equipment that receives power is a powered device (PD).

When a PSE supplies power to multiple PDs, if the current power consumption of the multiple PDs exceeds the power output power of the PSE, the PSE will stop supplying power due to power overcurrent, and all PDs connected to the PSE will be powered off together. affect the application.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a power-off control circuit and a power-off control method, which can enable some PDs to be powered off first, and some PDs to be powered off later, so as to reduce the negative impact caused by the power-off.

In a first aspect, an embodiment of the present application provides a power-off control circuit, including: a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit, and a voltage control circuit;

The input terminal of the current detection circuit is coupled to the power supply of the power supply equipment PSE, and the output terminal of the current detection circuit is connected to the first input terminal of the first overcurrent comparison circuit and the first input of the second overcurrent comparison circuit. end coupling;

The output end of the first overcurrent comparison circuit is coupled to the control end of the first PSE chip of the PSE;

The output end of the second overcurrent comparison circuit is coupled with the control end of the second PSE chip of the PSE;

The input end of the voltage control circuit is coupled with the output end of the second overcurrent comparison circuit, and the output end of the voltage control circuit is coupled with the second input end of the first overcurrent comparison circuit;

The voltage control circuit includes a voltage divider power supply, a first resistor and a second resistor;

The first resistor is coupled between the voltage dividing power supply and the output end of the voltage control circuit;

The second resistor is coupled between the output terminal of the voltage control circuit and the input terminal of the voltage control circuit.

In a possible implementation manner, the second resistor is connected in parallel with the first capacitor.

In a possible implementation manner, the enable terminal of the first PSE chip is capacitively coupled to ground.

In a possible implementation manner, the circuit further includes a signal amplifying circuit;

The output end of the current detection circuit is coupled with the input end of the signal amplifying circuit, and the output end of the signal amplifying circuit is connected with the first input end of the first overcurrent comparison circuit and the second overcurrent comparison circuit coupled to the first input; or

The output end of the current detection circuit is coupled with the input ends of the two signal amplifying circuits, the output end of one signal amplifying circuit is coupled with the first input end of the first overcurrent comparison circuit, and the other The output terminal of the signal amplification circuit is coupled to the first input terminal of the second overcurrent comparison circuit.

In a possible implementation manner, the second input terminal of the second overcurrent comparison circuit is coupled to the output terminal of the voltage regulator circuit;

The voltage-stabilizing circuit includes a voltage-stabilizing power supply and a voltage dividing resistor;

The output end of the regulated power supply is grounded through the voltage dividing resistor;

The output end of the voltage regulator circuit is coupled between the voltage dividing resistors.

In a possible implementation manner, the current detection circuit includes a sampling resistor and an operational amplifier;

Both ends of the sampling resistor are coupled to the PSE power supply;

Both ends of the sampling resistor are also coupled to the input end of the operational amplifier;

The output of the operational amplifier is coupled to the input of the operational amplifier.

In a possible implementation manner, a switch circuit is coupled between the input end of the first PSE chip and the output end of the first PSE chip;

The control terminal of the first PSE chip is coupled to the switch circuit, and is used to control the conduction and disconnection between the input terminal of the first PSE chip and the output terminal of the first PSE chip.

In a second aspect, an embodiment of the present application provides a power-off control method, which is applied to a power-off control circuit, where the power-off control circuit includes a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit, and a voltage A control circuit, the method comprising:

Outputting the first voltage according to the power supply current of the power supply device PSE through the current detection circuit, and the PSE is powered by the first PSE chip and the second PSE chip;

comparing the first voltage with the second voltage by the second overcurrent comparison circuit;

When the first voltage is lower than the second voltage, the second overcurrent comparison circuit outputs a high level to control the power supply of the second PSE chip;

When the first voltage is greater than the second voltage, the second overcurrent comparison circuit outputs a low level to control the second PSE chip to stop power supply;

Generate a third voltage by the voltage control circuit according to the low level output by the second overcurrent comparison circuit;

comparing the first voltage with the third voltage by the first overcurrent comparison circuit;

When the first voltage is lower than the third voltage, the first overcurrent comparison circuit outputs a high level to control the power supply of the first PSE chip;

When the first voltage is greater than the third voltage, the first overcurrent comparison circuit outputs a low level to control the first PSE chip to stop supplying power.

In a possible implementation manner, before the comparing the first voltage with the third voltage by the first overcurrent comparison circuit, the method further includes:

The first time is delayed by the first capacitor.

In a possible implementation manner, after the outputting a low level through the first overcurrent comparison circuit, and before the controlling the first PSE chip to stop power supply, the method further includes:

The second time is delayed by a grounded capacitor.

In a possible implementation manner, after the current detection circuit outputs the first voltage according to the power supply current of the power supply equipment PSE, the second overcurrent comparison circuit compares the first voltage with the second voltage Before the voltage comparison, the method further includes:

The first voltage is amplified by a signal amplification circuit.

In a possible implementation, the method further includes:

The second voltage is output through a voltage regulator circuit.

In a possible implementation manner, the controlling the power supply of the first PSE chip specifically includes:

The power supply of the first PSE chip is controlled by a switch circuit according to the high level output by the first overcurrent comparison circuit.

The controlling the first PSE chip to stop power supply specifically includes:

The switch circuit controls the first PSE chip to stop power supply according to the low level output by the first overcurrent comparison circuit.

As can be seen from the above technical solutions, the embodiments of the present application have the following advantages:

The power-off control circuit provided by the present application obtains the current of the PSE power supply through the current detection circuit and converts it into a voltage, and controls the second PSE chip through the second overcurrent comparison circuit according to the voltage, thereby controlling the power-on and power-off of the PD corresponding to the second PSE chip . When the PD corresponding to the second PSE chip is powered off, the output terminal of the second overcurrent comparison circuit inputs an appropriate comparison voltage to the second input terminal of the first overcurrent comparison circuit through the voltage control circuit, so that the first overcurrent comparison circuit The first PSE chip can be controlled according to the voltage, thereby controlling the power-on and power-off of the PD corresponding to the first PSE chip. Therefore, the present application can power off some PDs first, and then control another part of the PDs to power on and off after the partial PDs are powered off, so as to realize the hierarchical control of the power off of the PDs. When the load changes, the present application can control the unimportant PDs. Power off first, and let important PDs be controlled last to reduce the impact.

Description of drawings

FIG. 1 is an example of a system model of PSE and PD in an embodiment of the application;

FIG. 2 is an example diagram inside the PSE in the embodiment of the application;

FIG. 3 is an example diagram of a power-off control circuit in an embodiment of the present application;

FIG. 4 is an exemplary diagram of a current detection circuit in an embodiment of the present application;

FIG. 5 is an exemplary diagram of a voltage control circuit in an embodiment of the present application;

6 is another exemplary diagram of a power-off control circuit in an embodiment of the present application;

FIG. 7 is another exemplary diagram of a power-off control circuit in an embodiment of the present application;

FIG. 8 is another exemplary diagram of a power-off control circuit in an embodiment of the present application;

FIG. 9 is another exemplary diagram of a power-off control circuit in an embodiment of the present application;

10 is an example diagram of a signal amplification circuit and an overcurrent comparison circuit in an embodiment of the present application;

FIG. 11 is an exemplary diagram of a switch circuit in an embodiment of the application;

FIG. 12 is an exemplary diagram of a power-off control method in an embodiment of the present application.

Detailed ways

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that the embodiments of the application described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "corresponding to", and any variations thereof, are intended to cover non-exclusive inclusion, eg, a process, method, system, product or device comprising a series of steps or units not necessarily limited to those expressly listed but may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

In order to describe the following embodiments clearly and concisely, a brief introduction of the related technology is given first:

FIG. 1 is an example of a system model of a PSE and a PD in an embodiment of the present application. In the embodiment of the present application, the PSE and the PD may be connected through an RJ-45 twisted pair cable. In practical applications, they may also be connected through other suitable cables, which are not limited in the embodiment of the present application.

Table 1

Table 1 is an example of the parameters of the connection between the PSE and the PD in this embodiment of the present application. It can be seen that the connection between the PSE and the PD needs to meet the relevant parameters. If the relevant parameters are not met, a connection abnormality will occur. The following will introduce the general steps for connecting the PSE and the PD.

1. Check whether there is a device connected.

In this embodiment of the present application, the PSE can detect whether the RJ-45 twisted pair has a PD connection. If there is a PD connection, the RJ-45 twisted pair can have corresponding signal feedback.

2. Check whether the other party is a standard PD.

In this embodiment of the present application, the PSE may send a signal to the PD through the RJ-45 twisted pair, so that the PD feeds back information to the PSE, and the information may indicate whether the PD is a standard PD. In some embodiments, the information may also represent standards such as 802.3af, 802.3at, etc. in Table 1.

3. Detect the receiving power level of the other party.

In this embodiment of the present application, the PSE may send a signal to the PD through the RJ-45 twisted pair cable, so that the PD feeds back information to the PSE, and the information may indicate the power level of the PD. It can be understood that the received power levels may be the classifications in Table 1.

4. Power supply according to power.

It can be understood that, in this embodiment of the present application, the PSE is generally powered by an RJ-45 twisted pair cable.

5. Detect whether the other party leaves or short-circuits and other abnormal conditions.

In some embodiments, the PSE may require the PD to return a heartbeat signal at regular intervals. If the PD does not return the heartbeat signal on time, the PSE may determine that the PD has left or is abnormal. In other embodiments, an abnormality can also be determined as the abnormality occurs in the connection parameters between the PSE and the PD. For example, the voltage range of some ports in the RJ-45 twisted pair exceeds a limited range, etc., which is not limited in this embodiment of the present application.

6. Turn off the power supply and go back to the first step (step 1).

In this embodiment of the present application, when the PD is abnormal, the PSE stops supplying power to the PD. When the PD returns to normal, the PSE can repeat step 1 to power on the PD again.

In this embodiment of the present application, power-on means that the PSE supplies power to the PD, and power-down means that the PSE stops supplying power to the PD.

FIG. 2 is an example diagram of the interior of the PSE in the embodiment of the present application. It can be seen that the PSE may include multiple PSE chips, for example, PSE_0, PSE_1, PSE_2...PSE_n. Each PSE chip can be connected to multiple PDs. The PSE can control each PSE chip through a micro controller unit (MCU). A PSE chip generally has a control terminal (also called an enable terminal). In some embodiments, when the input of the control terminal is at a high level, the PSE chip controls the PD connected to it to supply power normally, and when the input of the control terminal turns to a low level, the PSE chip controls the PD connected to it to power off. In practical applications, the high level may also cause the PSE chip to control the PD connected to it to power off, which is not limited in this embodiment of the present application.

When there are many PDs installed in the PSE as shown in Figure 2, for example, the PSE supplies power to 24 PDs at the same time, and each PD needs 30W of power supply, then the PSE device reserves enough power supply capacity for each PD device according to the standard requirements, then The total power output power W=24*30W+PSE equipment itself power consumption>720W. This solution ensures that each port has sufficient power. However, although this solution can ensure that each port has sufficient power supply, in fact, the use efficiency of the power supply is very low, which adds a lot of cost waste to the networking.

In practical applications, since the PSE is not necessarily installed with 24 PDs, and each PD does not necessarily operate at a power consumption of 30W, the power consumption of a PD is generally only a few W, so the power consumption of the PSE generally does not reach 720W. Therefore, in practical applications, in order to reduce costs, the total power of the PSE that supplies power to 24 PDs is generally set at about 380W. When the load changes, for example, the power of each PD increases, so that the total power of each PD is greater than 380W, the PSE power supply will appear in the verification overcurrent state, and due to the power supply overcurrent, the equipment will be powered off and so on. , which affects the application.

In order to solve the technical problem of powering off the above equipment, an embodiment of the present application provides a power-off control circuit, as shown in FIG. 3 , including: a current detection circuit 301 , a first overcurrent comparison circuit 302 , and a second overcurrent comparison circuit 303 and the voltage control circuit 304.

The input terminal of the current detection circuit 301 is coupled with the power supply of the PSE, and is used to detect the current of the power supply of the PSE and convert it into a voltage parameter. The embodiments of the present application may use various circuits to implement the above functions. The embodiments of the present application do not limit the specific implementation of the current detection circuit 301 , but one example provided by the embodiments of the present application is shown in FIG. 4 .

FIG. 4 is an exemplary diagram of a current detection circuit in an embodiment of the present application. The current detection circuit includes a sampling resistor R1 and an operational amplifier. Both ends of the sampling resistor R1 are coupled with the PSE power supply, specifically between the positive pole RTN_POE of the PSE power supply and the negative pole -48V_POE of the PSE power supply. The size of the sampling resistor R1 may be 0.05 ohms, and the embodiment of the present application does not limit the size of the sampling resistor R1. The first terminal of the operational amplifier is grounded, the second terminal and the third section are coupled to the sampling resistor R1, the fourth terminal and the seventh terminal are coupled to the power supply, the fifth terminal is grounded, and the sixth terminal is the output terminal V0 of the current detection circuit. According to the circuit principle, the output terminal of the current detection circuit V0=R1*Is. Some resistors may be coupled at appropriate positions in the current detection circuit, which is not limited in this embodiment of the present application. In this embodiment of the present application, the output terminal of the current detection circuit 301 is coupled to the first input terminal of the first overcurrent comparison circuit 302 , and the output terminal of the current detection circuit 301 is also connected to the first input terminal of the second overcurrent comparison circuit 303 . The terminals are coupled to transmit the converted voltage to the first overcurrent comparison circuit 302 or the second overcurrent comparison circuit 303 for voltage comparison.

The output end of the first overcurrent comparison circuit 302 is coupled with the control end of the first PSE chip inside the PSE, and is used to control the first PSE chip according to the voltage comparison condition, so that the PD coupled with the first PSE chip is powered on or off;

The output end of the second overcurrent comparison circuit 303 is coupled with the control end of the second PSE chip inside the PSE, and is used to control the second PSE chip according to the voltage comparison condition, so that the PD coupled with the second PSE chip is powered on or off;

The input terminal of the voltage control circuit 304 is coupled with the output terminal of the second overcurrent comparison circuit 303, and the output terminal of the voltage control circuit 304 is coupled with the second input terminal of the first overcurrent comparison circuit 302 for comparing according to the second overcurrent The voltage comparison condition of the circuit 303 controls the voltage comparison of the first overcurrent comparison circuit 302 . Specifically, in some embodiments, the interior of the voltage control circuit 304 is shown in FIG. 5 .

FIG. 5 is an exemplary diagram of the voltage control circuit 304 in the embodiment of the present application. The voltage control circuit includes at least a power supply V33, a resistor R1 and a resistor R2. The voltage of the output terminal of the second overcurrent comparison circuit 303 is V _{PSE2_EN} , and the voltage of the second input terminal of the first overcurrent comparison circuit 302 is Vref1. From the circuit principle, it can be known that:

Vref1=(V33-V _{PSE2_EN} )*R2/(R1+R2)+V _{PSE2_EN} ;

According to the above formula, when the voltage of the output terminal of the second overcurrent comparison circuit 303 changes, the voltage of the second input terminal of the first overcurrent comparison circuit 302 also changes accordingly. The second overcurrent comparison circuit 303 performs proper voltage detection only when the power supply load exceeds the limit. In practical applications, the resistor R1, the resistor R2 and the power supply V33 can be set to appropriate values to achieve hierarchical control.

In order to clearly describe the implementation process of the embodiments of the present application, the embodiments of the present application provide two circuit design processes. One of the circuit design processes is:

Set the power supply V33 to 3.3V, the resistance R1 to 2.1K ohms, and the resistance R2 to be 1.2K ohms, then when the output voltage of the second overcurrent comparison circuit is 0V, according to the circuit principle, the first overcurrent comparison circuit 302 The second input terminal voltage Vref1=(V33-V _{PSE2_EN} )*R2/(R1+R2)+V _{PSE2_EN} =(3.3-0)*1.2K/(2.1K+1.2K)+0=1.2V. When the output terminal voltage of the two overcurrent comparison circuits is 3.3V, according to the circuit principle, the second input terminal voltage of the first overcurrent comparison circuit 302 is Vref1=(V33-V _{PSE2_EN} )*R2/(R1+R2)+V _{PSE2_EN} =(3.3-3.3)*1.2K/(2.1K+1.2K)+3.3=3.3V. And the second input terminal voltage Vref2 of the second overcurrent comparison circuit 303 is set to 1.2V.

Therefore, when the PSE power supply operates normally, the output terminal voltage of the current detection circuit 301 is less than 1.2V, the second overcurrent comparison circuit 303 outputs 3.3V, the PSE_2 chip works normally, and the PD connected to the PSE_2 chip does not need to be powered off. And according to the circuit principle, the voltage of the second input terminal of the first overcurrent comparison circuit 302 is Vref1=3.3V, even if the PSE power supply load changes suddenly, the output terminal voltage of the current detection circuit 301 is suddenly greater than 1.2V, and under normal circumstances it will not be greater than 1.2V. 3.3V, so it can be considered that the first overcurrent comparison circuit 302 constantly outputs a high level, the PSE_1 chip works normally, and the PD connected to the PSE_1 chip does not need to be powered off.

When the PSE power supply changes from normal operation to overload, the output voltage of the current detection circuit 301 exceeds 1.2V. After the comparison by the second overcurrent comparison circuit 303, the output voltage of the second overcurrent comparison circuit 303 outputs 0V, so that The PSE_2 chip controls the power-off of the PD connected to it. And because the voltage of the output terminal of the second overcurrent comparison circuit 303 changes to 0V, according to the circuit principle, the voltage Vref1 of the second input terminal of the first overcurrent comparison circuit 302 also changes to 1.2V successively. Therefore, the first overcurrent comparison circuit 302 can continue to detect the output terminal voltage of the current detection circuit 301 after the PD connected to the PSE_2 chip is powered off. If the output terminal voltage of the current detection circuit 301 still exceeds 1.2V, the output of the first overcurrent comparison circuit 302 is low. level, so that the PD connected to the PSE_1 chip is powered off.

Another design process is to first set the current detection circuit 301 so that when the output voltage of the current detection circuit 301 is greater than 1.2V, it means that the PSE power supply current exceeds the load limit, and some PDs need to be powered off. When the output terminal voltage of the current detection circuit 301 is less than 1.2V, it indicates that the PSE power supply current is within a suitable load range, and it is not necessary to power off the PD. Therefore, the first overcurrent comparison circuit 302 and the second overcurrent comparison circuit 303 need to compare the voltage of the output terminal of the current detection circuit 301, and the voltage used for the voltage comparison should be set to 1.2V. The voltage Vref2 of the second input terminal of the second overcurrent comparison circuit 303 can be directly connected to a 1.2V power supply or a stable 1.2V voltage can be obtained by dividing the power supply. However, the first overcurrent comparison circuit 302 needs to perform proper detection only after the second overcurrent comparison circuit 303 detects that the voltage of the output terminal of the current detection circuit 301 exceeds 1.2V. In the embodiment of the present application, after the second overcurrent comparison circuit 303 detects that the output terminal voltage of the current detection circuit 301 exceeds 1.2V, the output terminal output voltage V _{PSE2_EN} of the second overcurrent comparison circuit 303 is 0V, and the first If the voltage Vref1 of the second input terminal of the overcurrent comparison circuit 302 should be 1.2V, the output voltage of the power supply V33 can be set to 3.3V, the resistance R1 is 2.1K ohm, and the resistance R2 is 1.2K ohm. According to the circuit principle, it can be calculated that Vref1=(V33-V _{PSE2_EN} )*R2/(R1+R2)+V _{PSE2_EN} =(3.3-0)*1.2K/(2.1K+1.2K)+0=1.2V.

In some embodiments, the resistor R2 may also be connected with a capacitor C1 in parallel, so that when the output voltage V _{PSE2_EN} of the second overcurrent comparison circuit 303 is converted, due to the charging process of the capacitor C1, the second overcurrent comparison circuit 302 The input terminal voltage Vref1 reaches an appropriate voltage after a delay time. This delay design allows the PD connected to the PSE_2 chip to be powered off for a period of time before detecting the voltage of the output terminal of the current detection circuit 301 . For example, when the output voltage V _{PSE2_EN} of the second overcurrent comparison circuit 303 is converted from 3.3V to 0V, the second input voltage Vref1 of the first overcurrent comparison circuit 302 reaches 1.2V after a delay time.

In practical applications, different overcurrent comparison circuits can be set to use different comparison voltages. For example, the voltage Vref1 of the second input terminal of the first overcurrent comparison circuit 302 is set to 2V, and the voltage Vref2 of the second input terminal of the second overcurrent comparison circuit 303 is set to 1.2V, which is not limited in this embodiment of the present application .

As shown in FIG. 6 , in some embodiments, the embodiments of the present application are further provided with more overcurrent comparison circuits, wherein the first additional overcurrent comparison circuit (in FIG. 6 is the third overcurrent comparison circuit) The first input terminal of the current detection circuit 301 can be coupled with the output terminal, and its second input terminal can be coupled with the output terminal of the first overcurrent comparison circuit 302 through a voltage control circuit similar to the voltage control circuit 304, and its output terminal can be Coupled with the control terminal of the PSE chip. The first input of the second additional overcurrent comparison circuit may be coupled to the output of the current detection circuit 301 , and its second input may be compared with the previous additional overcurrent through a voltage control circuit similar to the voltage control circuit 304 . The output end of the circuit is coupled, and the output end of the circuit can be coupled with the control end of the PSE chip. By analogy, the embodiment of the present application may additionally set a number of overcurrent comparison circuits according to the actual situation, which is not limited in the embodiment of the present application.

In practical applications, a regulated power supply can be set to couple with the control terminal of a certain PSE chip, so that the PD connected to the PSE chip will not be powered off under the control of the regulated power supply. As shown in Figure 6, the regulated power supply VCC is connected to the PSE_0 chip, and the PD controlled by the PSE_0 chip will generally not be powered off. Staff can connect particularly important PDs to the PSE_0 chip to ensure stable power supply.

In some embodiments, the output terminal of the current detection circuit 301 is specifically coupled to the first input terminal of the first overcurrent comparison circuit 302 and the first input terminal of the second overcurrent comparison circuit 303 through a signal amplification circuit. FIG. 7 is an exemplary diagram of a power-off control circuit in an embodiment of the present application. It can be seen that the output end of the current detection circuit 301 is coupled to the input end of the signal amplifying circuit 305 , and the output end of the signal amplifying circuit 305 is connected to the first input end of the first overcurrent comparison circuit 302 and the first input end of the second overcurrent comparison circuit 303 . input coupling. In the embodiment of the present application, the signal amplifying circuit is used to amplify the voltage, so that the load condition of the PSE power supply can be judged more accurately.

In another embodiment, the output end of the current detection circuit 301 is specifically coupled to the first input end of the first overcurrent comparison circuit 302 and the first input end of the second overcurrent comparison circuit 303 through two signal amplification circuits, respectively. . FIG. 8 is another exemplary diagram of the power-off control circuit in the embodiment of the present application. It can be seen that the output end of the current detection circuit 301 is coupled to the input end of the signal amplifying circuit 3051 and the input end of the signal amplifying circuit 3052, respectively. The output terminal of the signal amplification circuit 3051 is coupled to the first input terminal of the first overcurrent comparison circuit 302 . The output terminal of the signal amplification circuit 3052 is coupled to the first input terminal of the second overcurrent comparison circuit 303 .

FIG. 9 is another exemplary diagram of a power-off control circuit in an embodiment of the present application. When multiple signal amplification circuits are used in the embodiment of the present application, the multiple signal amplification circuits may use different amplification factors, and the corresponding overcurrent detection circuits may use different detection voltages, that is, the second input terminal of the overcurrent detection circuit may be Set different voltages.

The embodiment of the present application implements hierarchical control through a plurality of overcurrent comparison circuits. After the second overcurrent comparison circuit 303 detects an overcurrent, the first overcurrent comparison circuit 302 is used for comparison, thereby realizing the hierarchical control and capable of controlling part of the PDs are powered off according to the preset sequence. The embodiment of the present application uses a hardware circuit to perform power-off control, which is faster than the MCU control method, and can achieve an ns-level response.

FIG. 10 is an example diagram of a signal amplifying circuit and an overcurrent comparison circuit in an embodiment of the present application. There are two signal amplifying circuits in Fig. 10, and the input voltages of the two signal amplifying circuits are both V0. After the input voltage V0 is amplified by the signal amplifying circuit, the output voltages are respectively V1=(R10/R18)*V0, V2=(R20/R28)*V0. The amplification factor of the signal amplification circuit can be realized by setting the values of R10, R18, R20, and R28, and the embodiment of the present application does not limit the amplification factor of the signal amplification circuit. Among them, the regulated power supply V33 is divided by R22, R23 and R24 to stabilize the output voltage of 1.2V, then the output voltage V2 is compared with the voltage of 1.2V through the second overcurrent comparison circuit.

When the output voltage V2 is less than 1.2V, the second overcurrent comparison circuit outputs a high level, PORT_EN_PSE2=3.3V, so that PSE2 supplies power. Vref1=V33=PORT_EN_PSE2=3.3V. At this time, in the first overcurrent comparison circuit, V1 is always smaller than Vref1, and the first overcurrent comparison circuit outputs a high level, so that the PSE1 is powered.

When the output voltage V2 is greater than 1.2V, the second overcurrent comparison circuit outputs a low level, PORT_EN_PSE2=0V, so that PSE2 stops power supply. In the example of the power-off control circuit in Figure 10, the resistor R26=1.2K ohm, and the resistor R27=2.1K ohm, so Vref1=V33*R26/(R27+R26)=3.3V*1.2k/(2.1k+1.2k )=1.2V. In the first overcurrent comparison circuit, the output voltage V1 is compared with Vref1=1.2V. When the output voltage V1 is less than 1.2V, the first overcurrent comparison circuit outputs a high level, so that the PSE1 supplies power. When the output voltage V1 is greater than 1.2V, the first overcurrent comparison circuit outputs a low level, so that the PSE1 stops supplying power.

The circuit shown in Figure 10 is also provided with a capacitor C21. The capacitor C21 enables the charging process of the capacitor when the output PORT_EN_PSE2 of the second overcurrent comparison circuit changes from 3.3V to 1.2V, so that Vref1 gradually changes from 3.3V to 1.2V V instead of instantaneously changing to 1.2V. Therefore, after the PSE2 stops supplying power for a period of time, the first overcurrent comparison circuit compares the output voltage V1 with the 1.2V voltage. Therefore, it can be ensured that when the PSE power supply is overloaded, PSE2 and PSE1 can stop power supply in sequence.

The circuit shown in Figure 10 is also provided with C20, and the capacitor C20 can cooperate with the capacitor C21, so that when the output PORT_EN_PSE2 of the second overcurrent comparison circuit changes from 3.3V to 1.2V, the capacitor C20 discharges, and the second overcurrent comparison circuit discharges The output of PORT_EN_PSE2 gradually changes from 3.3V to 1.2V, instead of instantaneously changing from 3.3V to 1.2V. Similarly, other capacitors in the circuit also have similar functions, which will not be repeated here.

In a possible embodiment, a switch circuit is coupled between the input end of the first PSE chip and the output end of the first PSE chip; the control end of the first PSE chip is coupled to the switch circuit for controlling the first PSE chip On and off between the input terminal of the first PSE chip and the output terminal of the first PSE chip. FIG. 11 is an exemplary diagram of a switch circuit in an embodiment of the present application. Wherein, PORT_EN_PSE is the control terminal of the first PSE chip, RTN_PSE is the power terminal of the PSE chip, and RTN_PSE_OUT is the output terminal of the PSE chip. When PORT_EN_PSE is high, the chip Q2 is turned on, so that RTN_PSE can be output to RTN_PSE_OUT, and the corresponding PD can be powered. When PORT_EN_PSE is low, the chip Q2 is disconnected, so that RTN_PSE cannot be output to RTN_PSE_OUT, and the corresponding PD stops receiving power. In practical applications, the switch circuit may also implement the switch function through other electronic components, which is not limited in the embodiment of the present application.

FIG. 12 is an exemplary diagram of a power-off control method in an embodiment of the present application. The method is applied to the power-off control circuit as shown in FIG. 3 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 or FIG. 9 . The method includes:

1201. Output a first voltage according to the power supply current of the power supply equipment PSE through the current detection circuit.

In this embodiment of the present application, the current detection circuit may acquire the current of the PSE power supply, and convert the current of the PSE power supply into the first voltage (ie, the output voltage of the current detection circuit). This process is similar to the description of the current detection circuit in the foregoing embodiment, and will not be repeated here.

1202. Compare the first voltage with the second voltage through the second overcurrent comparison circuit.

In this embodiment of the present application, the second overcurrent comparison circuit may be a circuit that compares two voltages, such as a comparator, where the second voltage may be a voltage output by a voltage regulator circuit, for example, 1.2V. The voltage comparison performed by the second overcurrent comparison circuit is similar to the description of the second overcurrent comparison circuit in the foregoing embodiment, and details are not repeated here.

1203. When the first voltage is lower than the second voltage, output a high level through the second overcurrent comparison circuit to control the power supply of the second PSE chip.

In the embodiment of the present application, when the first voltage is lower than the second voltage, the second overcurrent comparison circuit outputs a high level. The high level may be a voltage greater than or equal to 1, such as 1V, 3.3V, etc., and is generally 3.3V in this embodiment of the present application. This embodiment of the present application does not limit the specific voltage of the high level.

After a high level is input to the control terminal of the second PSE chip (or the enable terminal of the second PSE chip), the second PSE chip can supply power according to the high level. Generally, a plurality of PDs are connected to the second PSE chip, and the second PSE chip actually supplies power to the plurality of PDs connected to it.

Other situations in step 1203 are similar to the descriptions related to the second overcurrent comparison circuit and the second PSE chip in the foregoing embodiment, and are not repeated here.

1204. When the first voltage is greater than the second voltage, output a low level through the second overcurrent comparison circuit, and control the second PSE chip to stop supplying power.

In this embodiment of the present application, when the first voltage is greater than the second voltage, the second overcurrent comparison circuit outputs a low level. The low level is generally 0V, which is not limited in this embodiment of the present application.

After a low level is input to the control terminal of the second PSE chip (or the enable terminal of the second PSE chip), the second PSE chip can stop power supply according to the low level, that is, stop supplying power to multiple PDs connected to it.

Other situations in step 1204 are similar to the descriptions related to the second overcurrent comparison circuit and the second PSE chip in the foregoing embodiment, and are not repeated here.

1205. Generate a third voltage according to the low level output by the second overcurrent comparison circuit through the voltage control circuit.

In this embodiment of the present application, when the first voltage is greater than the second voltage, and the second overcurrent comparison circuit outputs a low level, step 1205 may be executed, and the voltage control circuit may use the voltage control circuit according to the low level outputted by the second overcurrent comparison circuit. A third voltage is generated.

In a possible embodiment, the voltage control circuit may be a voltage regulation circuit, which provides a power supply and a resistor, etc., and increases the low level output by the second overcurrent comparison circuit to a suitable voltage as the third voltage. For example, the voltage control circuit can increase the 0V voltage output by the second overcurrent comparison circuit to 1.2V. For details of the voltage control circuit, reference may be made to the descriptions in the foregoing embodiments, which will not be repeated here.

1206. Compare the first voltage with the third voltage through the first overcurrent comparison circuit.

In this embodiment of the present application, the first voltage and the third voltage may be input to the first overcurrent comparison circuit. The first overcurrent comparison circuit may be a comparator, which compares the first voltage with the third voltage. If the first voltage is less than the third voltage, the first overcurrent comparison circuit outputs a high level. If the first voltage is greater than the third voltage, the first overcurrent comparison circuit outputs a high level. With three voltages, the first overcurrent comparison circuit outputs a low level. For details of the first overcurrent comparison circuit, reference may be made to the descriptions in the foregoing embodiments, which will not be repeated here.

1207. When the first voltage is lower than the third voltage, output a high level through the first overcurrent comparison circuit to control the power supply of the first PSE chip.

In this embodiment of the present application, when the first voltage is lower than the third voltage, the first overcurrent comparison circuit outputs a high level. A high level is input to the control terminal or enable terminal of the first PSE chip, so that the first PSE chip supplies power to multiple PDs connected to it. For details, reference may be made to the descriptions of the first overcurrent comparison circuit and the first PSE chip in the foregoing embodiments, which are not repeated in this embodiment of the present application.

1208. When the first voltage is greater than the third voltage, output a low level through the first overcurrent comparison circuit, and control the first PSE chip to stop supplying power.

In this embodiment of the present application, when the first voltage is greater than the third voltage, the first overcurrent comparison circuit outputs a low level. A low level is input to the control terminal or enable terminal of the first PSE chip, so that the first PSE chip stops supplying power to a plurality of PDs connected to it. For details, reference may be made to the descriptions of the first overcurrent comparison circuit and the first PSE chip in the foregoing embodiments, which are not repeated in this embodiment of the present application.

In the embodiment of the present application, the power-down control circuit first compares the first voltage with the second voltage through the second overcurrent comparison circuit. When the first voltage is greater than the second voltage, the power-down control circuit may compare the first voltage with the third voltage through the first overcurrent comparison circuit. Therefore, after the second overcurrent comparison circuit stops the power supply of the second PSE chip, the power-off control circuit determines whether the power supply of the first PSE chip needs to be stopped, so that when the PSE power supply is overloaded, a part of PDs can be powered off first. Power off another part of the PD to reduce the negative impact caused by the power off of the PD.

In a possible embodiment, the method may further include: delaying the first time by the first capacitor. Correspondingly, in the power-off control circuit, the first capacitor, such as the capacitor C1 corresponding to FIG. 5 , can be set at an appropriate position to delay for a period of time. The first time may be related to a parameter of the first capacitor, which is not limited in this embodiment of the present application.

In a possible embodiment, the method may further include: delaying the second time by a grounding capacitor. Correspondingly, in the power-off control circuit, a ground capacitor, such as capacitor C20 and capacitor C10 corresponding to FIG. 10 , can be added to the output end of the first overcurrent comparison circuit or the second overcurrent comparison circuit to delay the second time. The length of the second time may be related to the parameter of the ground capacitance, which is not limited in this embodiment of the present application.

In a possible embodiment, the method may further include amplifying the first voltage through a signal amplifying circuit. Correspondingly, in the power-off control circuit, a signal amplification circuit can be set between the current detection circuit and the first overcurrent comparison circuit, or between the current detection circuit and the second overcurrent comparison circuit, as shown in FIG. 7 , FIG. 8 or FIG. 9 . shown to amplify the first voltage. The embodiment of the present application does not limit the amplification factor of the signal amplification circuit.

In a possible embodiment, the method may further include outputting the second voltage through a voltage regulator circuit. Correspondingly, in the power-down control circuit, the input terminal Vref2 of the second overcurrent comparison circuit may be connected to a voltage stabilizing circuit, and the voltage stabilizing circuit outputs a second voltage, for example, a voltage of 1.2V. This embodiment of the present application does not limit this.

In a possible embodiment, the method may further include controlling the power supply of the first PSE chip according to the high level output by the first overcurrent comparison circuit through the switch circuit, and using the switch circuit according to the low level outputted by the first overcurrent comparison circuit Ping controls the first PSE chip to stop power supply. The switch circuit is similar to the embodiment corresponding to the aforementioned FIG. 11 , and details are not repeated here.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

Claims (13)

1. A power-off control circuit, comprising: a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit, and a voltage control circuit; The input terminal of the current detection circuit is coupled to the power supply of the power supply equipment PSE, and the output terminal of the current detection circuit is connected to the first input terminal of the first overcurrent comparison circuit and the first input of the second overcurrent comparison circuit. end coupling; The output end of the first overcurrent comparison circuit is coupled to the control end of the first PSE chip of the PSE; The output end of the second overcurrent comparison circuit is coupled with the control end of the second PSE chip of the PSE; The input end of the voltage control circuit is coupled with the output end of the second overcurrent comparison circuit, and the output end of the voltage control circuit is coupled with the second input end of the first overcurrent comparison circuit; The voltage control circuit includes a voltage divider power supply, a first resistor and a second resistor; The first resistor is coupled between the voltage dividing power supply and the output end of the voltage control circuit; The second resistor is coupled between the output terminal of the voltage control circuit and the input terminal of the voltage control circuit. 2 . The circuit of claim 1 , wherein the second resistor is connected in parallel with a first capacitor. 3 . 3 . The circuit according to claim 1 , wherein the enable terminal of the first PSE chip is capacitively coupled to ground. 4 . 4. The circuit according to any one of claims 1 to 2, characterized in that, further comprising a signal amplifying circuit; The output end of the current detection circuit is coupled with the input end of the signal amplifying circuit, and the output end of the signal amplifying circuit is connected with the first input end of the first overcurrent comparison circuit and the second overcurrent comparison circuit coupled to the first input; or The output end of the current detection circuit is coupled with the input ends of the two signal amplifying circuits, the output end of one signal amplifying circuit is coupled with the first input end of the first overcurrent comparison circuit, and the other The output terminal of the signal amplification circuit is coupled to the first input terminal of the second overcurrent comparison circuit. 5. The circuit according to any one of claims 1 to 2, wherein the second input terminal of the second overcurrent comparison circuit is coupled to the output terminal of the voltage regulator circuit; The voltage-stabilizing circuit includes a voltage-stabilizing power supply and a voltage dividing resistor; The output end of the regulated power supply is grounded through the voltage dividing resistor; The output end of the voltage regulator circuit is coupled between the voltage dividing resistors. 6. The circuit according to any one of claims 1 to 2, wherein the current detection circuit comprises a sampling resistor and an operational amplifier; Both ends of the sampling resistor are coupled to the PSE power supply; Both ends of the sampling resistor are also coupled to the input end of the operational amplifier; The output of the operational amplifier is coupled to the input of the operational amplifier. 7. The circuit according to any one of claims 1 to 2, wherein a switch circuit is coupled between the input end of the first PSE chip and the output end of the first PSE chip; The control terminal of the first PSE chip is coupled to the switch circuit, and is used to control the conduction and disconnection between the input terminal of the first PSE chip and the output terminal of the first PSE chip. 8. A power-off control method, characterized in that it is applied to a power-off control circuit, wherein the power-off control circuit comprises a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit and a voltage control circuit, so The methods described include: Outputting the first voltage according to the power supply current of the power supply device PSE through the current detection circuit, and the PSE is powered by the first PSE chip and the second PSE chip; comparing the first voltage with a second voltage by the second overcurrent comparison circuit, where the second voltage includes the output voltage of the voltage stabilizing circuit; When the first voltage is lower than the second voltage, the second overcurrent comparison circuit outputs a high level to control the power supply of the second PSE chip; When the first voltage is greater than the second voltage, the second overcurrent comparison circuit outputs a low level to control the second PSE chip to stop power supply; Generate a third voltage by the voltage control circuit according to the low level output by the second overcurrent comparison circuit; comparing the first voltage with the third voltage by the first overcurrent comparison circuit; When the first voltage is lower than the third voltage, the first overcurrent comparison circuit outputs a high level to control the power supply of the first PSE chip; When the first voltage is greater than the third voltage, the first overcurrent comparison circuit outputs a low level to control the first PSE chip to stop supplying power. 9 . The method according to claim 8 , wherein before comparing the first voltage with the third voltage by the first overcurrent comparison circuit, the method further comprises: 10 . The first time is delayed by the first capacitor. 10. The method according to claim 8 or 9, wherein after the first overcurrent comparison circuit outputs a low level and before the control of the first PSE chip to stop power supply, the method Also includes: The second time is delayed by a grounded capacitor. 11. The method according to claim 8 or 9, wherein after the current detection circuit outputs the first voltage according to the power supply current of the power supply equipment PSE, the second overcurrent comparison circuit Before comparing the first voltage with the second voltage, the method further includes: The first voltage is amplified by a signal amplification circuit. 12. The method according to claim 8 or 9, wherein the method further comprises: The second voltage is output through the voltage regulator circuit. 13. The method according to claim 8 or 9, wherein the controlling the power supply of the first PSE chip specifically comprises: Control the power supply of the first PSE chip according to the high level output by the first overcurrent comparison circuit through a switch circuit; The controlling the first PSE chip to stop power supply specifically includes: The switch circuit controls the first PSE chip to stop power supply according to the low level output by the first overcurrent comparison circuit.

Images