CN113037508A

CN113037508A - Power-down control circuit and power-down control method

Info

Publication number: CN113037508A
Application number: CN201911387123.4A
Authority: CN
Inventors: 季桂荣; 顾超
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2021-06-25
Anticipated expiration: 2039-12-24
Also published as: CN113037508B

Abstract

The power-off control circuit and the power-off control method provided by the application acquire the current of the PSE power supply through the current detection circuit and convert the current into the voltage, and control the second PSE chip through the second overcurrent comparison circuit according to the voltage, so that the power-on and power-off of the PD corresponding to the second PSE chip are controlled. After the corresponding PD of second PSE chip is electrified, the output of second overcurrent comparison circuit passes through voltage control circuit and will fit comparative voltage input to the second input of first overcurrent comparison circuit for first overcurrent comparison circuit can be according to the first PSE chip of this voltage control, thereby control and power up and down with the corresponding PD of first PSE chip. Therefore, the power-off control method and the power-off control device can firstly power off part of the PDs, and then control the power on and off of the other part of the PDs after the power off of the part of the PDs, so that the power off of the PDs is controlled in a grading manner, when the load is changed, the power off of unimportant PDs can be controlled, the important PDs are controlled finally, and the influence is reduced.

Description

Power-down control circuit and power-down control method

Technical Field

The embodiment of the application relates to the technical field of circuit power supply, in particular to a power-down control circuit and a power-down control method.

Background

With the development of modern technology, the application of power over Ethernet (PoE) is more and more extensive, and more devices support PoE, and these devices supporting PoE can obtain electric energy through PoE, do not need external power supply again, and are very convenient. PoE refers to a technology that, without any change in the existing ethernet type five (cat.5) wiring infrastructure, can provide dc power for some terminals (such as IP phones, wireless local area network Access Points (APs), network cameras, etc.) while transmitting data signals. PoE is also known as power over LAN (PoL) or active Ethernet (active Ethernet), and is sometimes referred to simply as power over Ethernet. The device providing power supply is a Power Sourcing Equipment (PSE), and the device receiving power supply is a Powered Device (PD).

When one PSE supplies power to a plurality of PDs, if the current power consumption of the plurality of PDs is added to exceed the power output power of the PSE, the PSE can stop supplying power due to power overcurrent, all the PDs connected with the PSE are powered off together, and application is affected.

Disclosure of Invention

The embodiment of the application provides a power-down control circuit and a power-down control method, which can enable a part of PDs to be powered down firstly and a part of PDs to be powered down later, and reduce negative effects caused by power-down.

In a first aspect, an embodiment of the present application provides a power down control circuit, including: the overcurrent protection circuit comprises a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit and a voltage control circuit;

the input end of the current detection circuit is coupled with a power supply unit (PSE), and the output end of the current detection circuit is coupled with the first input end of the first over-current comparison circuit and the first input end of the second over-current comparison circuit;

the output end of the first overcurrent comparison circuit is coupled with the control end of a first PSE chip of the PSE;

the output end of the second overcurrent comparison circuit is coupled with the control end of a second PSE chip of the PSE;

the input end of the voltage control circuit is coupled with the output end of the second overcurrent comparison circuit, and the output end of the voltage control circuit is coupled with the second input end of the first overcurrent comparison circuit;

the voltage control circuit comprises a voltage division power supply, a first resistor and a second resistor;

the first resistor is coupled between the voltage division power supply and the output end of the voltage control circuit;

the second resistor is coupled between the output end of the voltage control circuit and the input end of the voltage control circuit.

In one possible implementation, the second resistor is connected in parallel with the first capacitor.

In one possible implementation, the enable terminal of the first PSE chip is coupled with a capacitance to ground.

In one possible implementation, the circuit further includes a signal amplification circuit;

the output end of the current detection circuit is coupled with the input end of the signal amplification circuit, and the output end of the signal amplification circuit is coupled with the first input end of the first over-current comparison circuit and the first input end of the second over-current comparison circuit; or

The output end of the current detection circuit is coupled with the input ends of the two signal amplification circuits, the output end of one signal amplification circuit is coupled with the first input end of the first overcurrent comparison circuit, and the output end of the other signal amplification circuit is coupled with the first input end of the second overcurrent comparison circuit.

In a possible implementation manner, a second input terminal of the second over-current comparison circuit is coupled with an output terminal of the voltage stabilizing circuit;

the voltage stabilizing circuit comprises a voltage stabilizing power supply and a voltage dividing resistor;

the output end of the voltage-stabilized power supply is grounded through the voltage-dividing resistor;

the output end of the voltage stabilizing circuit is coupled between the divider resistors.

In one possible implementation, the current detection circuit includes a sampling resistor, an operational amplifier;

both ends of the sampling resistor are coupled with the PSE power supply;

the two ends of the sampling resistor are also coupled with the input end of the operational amplifier;

an output of the operational amplifier is coupled to an input of the operational amplifier.

In one possible implementation, a switch circuit is coupled between an input terminal of the first PSE chip and an output terminal of the first PSE chip;

the control terminal of the first PSE chip is coupled with the switching circuit and used for controlling the connection and disconnection between the input terminal of the first PSE chip and the output terminal of the first PSE chip.

In a second aspect, an embodiment of the present application provides a power-down control method, which is applied to a power-down control circuit that includes a current detection circuit, a first over-current comparison circuit, a second over-current comparison circuit, and a voltage control circuit, and the method includes:

outputting a first voltage according to power supply current of Power Supply Equipment (PSE) through the current detection circuit, wherein the PSE supplies power through a first PSE chip and a second PSE chip;

comparing, by the second over-current comparison circuit, the first voltage with a second voltage;

when the first voltage is lower than the second voltage, outputting a high level through the second overcurrent comparison circuit to control the second PSE chip to supply power;

when the first voltage is larger than the second voltage, outputting a low level through the second overcurrent comparison circuit, and controlling the second PSE chip to stop supplying power;

generating a third voltage according to the low level output by the second overcurrent comparison circuit through the voltage control circuit;

comparing, by the first over-current comparison circuit, the first voltage with the third voltage;

when the first voltage is smaller than the third voltage, outputting a high level through the first overcurrent comparison circuit to control the first PSE chip to supply power;

and when the first voltage is greater than the third voltage, outputting a low level through the first overcurrent comparison circuit, and controlling the first PSE chip to stop supplying power.

In one possible implementation, before the comparing the first voltage with the third voltage by the first over-current comparison circuit, the method further includes:

a first time is delayed by a first capacitance.

In a possible implementation manner, after the outputting of the low level by the first over-current comparison circuit and before the controlling of the first PSE chip to stop supplying power, the method further includes:

the second time is delayed by the grounded capacitance.

In a possible implementation manner, after the outputting, by the current detection circuit, the first voltage according to the power supply current of the power supply equipment PSE, and before the comparing, by the second over-current comparison circuit, the first voltage with the second voltage, the method further includes:

the first voltage is amplified by a signal amplification circuit.

In one possible implementation, the method further includes:

and outputting the second voltage through a voltage stabilizing circuit.

In a possible implementation manner, the controlling the power supply of the first PSE chip specifically includes:

and controlling the first PSE chip to supply power through a switching circuit according to the high level output by the first over-current comparison circuit.

The controlling the first PSE chip to stop supplying power specifically includes:

and controlling the first PSE chip to stop supplying power according to the low level output by the first overcurrent comparison circuit through the switch circuit.

According to the technical scheme, the embodiment of the application has the following advantages:

the application provides a control circuit under passes through the current detection circuit and obtains the electric current of PSE power and convert voltage into, and pass through second overcurrent comparison circuit control second PSE chip according to this voltage to the control is electrified from top to bottom with the PD that second PSE chip corresponds. After the corresponding PD of second PSE chip is electrified, the output of second overcurrent comparison circuit passes through voltage control circuit and will fit comparative voltage input to the second input of first overcurrent comparison circuit for first overcurrent comparison circuit can be according to the first PSE chip of this voltage control, thereby control and power up and down with the corresponding PD of first PSE chip. Therefore, the power-off control method and the power-off control device can firstly power off part of the PDs, and then control the power on and off of the other part of the PDs after the power off of the part of the PDs, so that the power off of the PDs is controlled in a grading manner, when the load is changed, the power off of unimportant PDs can be controlled, the important PDs are controlled finally, and the influence is reduced.

Drawings

FIG. 1 is an example of a system model of a PSE and a PD in an embodiment of the present application;

FIG. 2 is an exemplary diagram of the PSE internal in an embodiment of the present application;

FIG. 3 is an exemplary diagram of a power down control circuit in an embodiment of the present application;

FIG. 4 is a diagram illustrating an exemplary current detection circuit according to an embodiment of the present application;

FIG. 5 is a diagram of an example of a voltage control circuit in an embodiment of the present application;

FIG. 6 is a diagram of another example of a power down control circuit in an embodiment of the present application;

FIG. 7 is a diagram of another example of a power down control circuit in an embodiment of the present application;

FIG. 8 is a diagram of another example of a power down control circuit in an embodiment of the present application;

FIG. 9 is a diagram of another example of a power down control circuit in an embodiment of the present application;

FIG. 10 is a diagram illustrating a signal amplifying circuit and an over-current comparing circuit according to an embodiment of the present disclosure;

FIG. 11 is a diagram illustrating an exemplary switching circuit according to an embodiment of the present application;

fig. 12 is an exemplary diagram of a power-down control method in an embodiment of the present application.

Detailed Description

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "corresponding" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

For clarity and conciseness of the following descriptions of the various embodiments, a brief introduction to the related art is first given:

fig. 1 is a system model example of a PSE and a PD in the embodiment of the present application. In this embodiment of the present application, the PSE and the PD may be connected by an RJ-45 twisted pair, and in practical applications, may also be connected by another suitable cable, which is not limited in this embodiment of the present application.

TABLE 1

Table 1 shows an example of parameters of the PSE and PD connection in the embodiment of the present application. It can be seen that the PSE and the PD need to conform to the relevant parameters when they are connected, and if they do not conform to the relevant parameters, a connection exception occurs, and the following will describe the general steps of the PSE and the PD connection.

1. It is detected whether a device is connected.

In an embodiment of the present application, the PSE may detect whether a PD is connected to the RJ-45 twisted pair. If there is a PD connection, the RJ-45 twisted pair can have corresponding signal feedback.

2. It is detected whether the partner is a standard PD.

In an embodiment of the present application, the PSE may send a signal to the PD over the RJ-45 twisted pair, causing the PD to feed back information to the PSE, which may indicate whether the PD is a standard PD. In some embodiments, this information may also represent standards such as 802.3af, 802.3at, etc. in table 1.

3. The received power level of the other party is detected.

In an embodiment of the present application, the PSE may send a signal to the PD over the RJ-45 twisted pair, causing the PD to feed back information to the PSE, which may be indicative of the received power level of the PD. It is understood that the received power level may be a classification in table 1.

4. The power is supplied according to the power.

It will be appreciated that in the embodiments of the present application, the PSE is typically powered by RJ-45 twisted pairs.

5. Whether the other party is separated or short-circuited or not is detected.

In some embodiments, the PSE may request the PD to return a heartbeat signal at intervals, and if the PD does not return a heartbeat signal on time, the PSE may determine that the PD is away or abnormal. In other embodiments, an abnormal condition may be determined to occur when an abnormality occurs in a parameter of the connection between the PSE and the PD. For example, the voltage range of some ports in the RJ-45 twisted pair exceeds a limited range, and the like, which is not limited in the embodiments of the present application.

6. The power supply is stopped and the process returns to the first step (step 1).

In the embodiment of the application, when the PD has an abnormal condition, the PSE stops supplying power to the PD. When the PD returns to normal, the PSE may resume step 1 to power up the PD again.

In the embodiment of the present application, power-up refers to the PSE supplying power to the PD, and power-down refers to the PSE stopping supplying power to the PD.

FIG. 2 is an exemplary diagram of the PSE internal in the embodiment of the present application. It can be seen that multiple PSE chips may be included in a PSE, e.g., PSE _0, PSE _1, PSE _2 … PSE _ n. Multiple PDs may be connected to each PSE chip. The PSE may control each PSE chip through a Micro Controller Unit (MCU). PSE chips typically have a control terminal (also referred to as an enable terminal). In some embodiments, when the input of the control terminal is high level, the PSE chip controls the PD connected thereto to normally supply power, and when the input of the control terminal is low level, the PSE chip controls the PD connected thereto to power down. In practical applications, it may also be a high level, so that the PSE chip controls the PD connected thereto to power down, which is not limited in this embodiment of the application.

When more PDs are installed, for example, the PSE supplies power to 24 PDs simultaneously, each PD needs 30W of power, the PSE device reserves sufficient power supply capacity for each PD device according to the standard requirement, and the total power output W is 24 × 30W + the power consumption of the PSE device itself is > 720W. This arrangement ensures that each port has sufficient power. However, although this solution can ensure sufficient power supply to each port, it adds a large cost waste to the networking because the power supply is actually used inefficiently.

In practical applications, since the PSE is not always fully loaded with 24 PDs, and each PD is not always operated with a power consumption of 30W, the power consumption of a general PD is only about a few W, so that the power consumption of the PSE does not reach 720W in practice. Therefore, in practical applications, the total power of the PSE powering 24 PDs is generally set to be around 380W in order to reduce the cost. When the load varies, for example, the power of each PD increases, so that the total power of each PD is more than 380W, the PSE power supply may have a verification overcurrent state, and due to the overcurrent of the power supply, the power of the device may be turned off, and the like, which affects the application.

In order to solve the technical problem of powering down the above device, an embodiment of the present application provides a power down control circuit, as shown in fig. 3, including: a current detection circuit 301, a first over-current comparison circuit 302, a second over-current comparison circuit 303 and a voltage control circuit 304.

The input terminal of the current detection circuit 301 is coupled to the power supply of the PSE, and is configured to detect the current of the power supply of the PSE and convert the current into a voltage parameter. Various circuits can be adopted in the embodiment of the present application to realize the above functions, and the embodiment of the present application does not limit the specific implementation manner of the current detection circuit 301, but one example of the implementation manner is provided in the embodiment of the present application and is shown in fig. 4.

Fig. 4 is an exemplary diagram of a current detection circuit in an embodiment of the present application. The current detection circuit includes a sampling resistor R1 and an operational amplifier. The two ends of the sampling resistor R1 are coupled with the PSE power supply, specifically between the positive pole RTN _ POE of the PSE power supply and the negative pole-48V _ POE of the PSE power supply. The size of the sampling resistor R1 may be 0.05 ohm, and the size of the sampling resistor R1 is not limited in this embodiment of the application. The first end of the operational amplifier is grounded, the second end and the third section of the operational amplifier are coupled with the sampling resistor R1, the fourth end and the seventh end of the operational amplifier are coupled with the power supply, the fifth end of the operational amplifier is grounded, and the sixth end of the operational amplifier is an output end V0 of the current detection circuit. According to the circuit principle, the output terminal V0 of the current detection circuit Is R1 Is. Some resistors may be coupled at appropriate positions in the current detection circuit, which is not limited in this application. In this embodiment, an output terminal of the current detection circuit 301 is coupled to a first input terminal of the first over-current comparison circuit 302, and an output terminal of the current detection circuit 301 is further coupled to a first input terminal of the second over-current comparison circuit 303, so as to transmit the converted voltage to the first over-current comparison circuit 302 or the second over-current comparison circuit 303 for voltage comparison.

The output end of the first overcurrent comparison circuit 302 is coupled with the control end of a first PSE chip in the PSE and is used for controlling the first PSE chip according to the voltage comparison condition, so that a PD coupled with the first PSE chip is powered on or powered off;

the output end of the second overcurrent comparison circuit 303 is coupled with the control end of a second PSE chip in the PSE, and is used for controlling the second PSE chip according to the voltage comparison condition, so that the PD coupled with the second PSE chip is powered on or powered off;

an input end of the voltage control circuit 304 is coupled to an output end of the second over-current comparison circuit 303, and an output end of the voltage control circuit 304 is coupled to a second input end of the first over-current comparison circuit 302, for controlling the voltage comparison of the first over-current comparison circuit 302 according to the voltage comparison condition of the second over-current comparison circuit 303. Specifically, in some embodiments, the voltage control circuit 304 is internal as shown in FIG. 5.

FIG. 5 shows voltages in the examples of the present applicationAn exemplary diagram of control circuitry 304. The voltage control circuit at least comprises a power supply V33, a resistor R1 and a resistor R2. The voltage at the output terminal of the second over-current comparison circuit 303 is V_{PSE2_EN}If the voltage at the second input terminal of the first over-current comparing circuit 302 is Vref1, the circuit principle shows that:

Vref1＝(V33-V_{PSE2_EN})*R2/(R1+R2)+V_{PSE2_EN}；

according to the above formula, when the voltage at the output terminal of the second over-current comparison circuit 303 changes, the voltage at the second input terminal of the first over-current comparison circuit 302 also changes, so that the first over-current comparison circuit 302 can perform appropriate voltage detection only when the second over-current comparison circuit 303 detects that the power load exceeds the limit. In practical applications, the resistor R1, the resistor R2 and the power supply V33 are set to appropriate values to realize the hierarchical control.

For clarity of description of the implementation process of the embodiment of the present application, two circuit design processes are given in the embodiment of the present application. One of the circuit design processes is:

setting the power supply V33 to be 3.3V power supply, the resistor R1 to be 2.1K ohm, and the resistor R2 to be 1.2K ohm, when the output terminal voltage of the second over-current comparison circuit is 0V, the second input terminal voltage Vref1 of the first over-current comparison circuit 302 is equal to (V33-V) according to the circuit principle_{PSE2_EN})*R2/(R1+R2)+V_{PSE2_EN}1.2K/(2.1K +1.2K) + 0-1.2V. When the output voltage of the over-current comparison circuit is 3.3V, the second input voltage Vref1 of the over-current comparison circuit 302 is equal to (V33-V) according to the circuit principle_{PSE2_EN})*R2/(R1+R2)+V_{PSE2_EN}(3.3-3.3) × 1.2K/(2.1K +1.2K) +3.3 ═ 3.3V. And the second input voltage Vref2 of the second overcurrent comparing circuit 303 is set to 1.2V.

Therefore, when the PSE power supply operates normally, the voltage at the output terminal of the current detection circuit 301 is less than 1.2V, the second over-current comparison circuit 303 outputs 3.3V, the PSE _2 chip operates normally, and the PD connected to the PSE _2 chip is not powered down. And according to the circuit principle, the voltage Vref1 at the second input end of the first overcurrent comparison circuit 302 is 3.3V, even if the PSE power supply load suddenly changes, the voltage at the output end of the current detection circuit 301 is suddenly greater than 1.2V, and is generally not greater than 3.3V, so that the first overcurrent comparison circuit 302 can be considered to constantly output a high level, the PSE _1 chip normally operates, and the PD connected with the PSE _1 chip does not need to be powered down.

When the PSE power supply changes from normal operation to excess load, the voltage of the output end of the current detection circuit 301 exceeds 1.2V, and after comparison by the second overcurrent comparison circuit 303, the voltage of the output end of the second overcurrent comparison circuit 303 outputs 0V, so that the PSE _2 chip controls the power-down of the PD connected with the PSE _2 chip. Since the voltage of the output terminal of the second over-current comparison circuit 303 changes to 0V, and the voltage Vref1 of the second input terminal of the first over-current comparison circuit 302 also changes to 1.2V successively according to the circuit principle, the first over-current comparison circuit 302 can continue to detect the voltage of the output terminal of the current detection circuit 301 after the PD connected with the PSE _2 chip is powered off, and if the voltage of the output terminal of the current detection circuit 301 still exceeds 1.2V, the first over-current comparison circuit 302 outputs a low level, so that the PD connected with the PSE _1 chip is powered off.

Another design procedure is to first set the current detection circuit 301 so that when the voltage at the output of the current detection circuit 301 is greater than 1.2V, it indicates that the PSE power supply current exceeds the load limit and a power down needs to be given to a part of the PD. When the voltage at the output of the current detection circuit 301 is less than 1.2V, it indicates that the PSE power supply current is within the proper load range and the PD does not need to be powered down. Therefore, the first overcurrent comparing circuit 302 and the second overcurrent comparing circuit 303 need to perform voltage comparison on the voltage at the output terminal of the current detecting circuit 301, and the voltages used for the voltage comparison should be set to 1.2V. The voltage Vref2 at the second input terminal of the second over-current comparison circuit 303 can be directly connected to a 1.2V power supply or can obtain a stable 1.2V voltage through power supply voltage division. The first over-current comparison circuit 302 needs to start proper detection after the second over-current comparison circuit 303 detects that the voltage at the output terminal of the current detection circuit 301 exceeds 1.2V. In the embodiment of the present application, when the second over-current comparing circuit 303 detects that the voltage at the output terminal of the current detecting circuit 301 exceeds 1.2V, the output terminal of the second over-current comparing circuit 303 outputs the voltage V_{PSE2_EN}At 0V, the voltage Vref1 at the second input terminal of the first over-current comparison circuit 302 should be 12V, the output voltage of the power supply V33 can be set to 3.3V, the resistor R1 to 2.1K ohm, and the resistor R2 to 1.2K ohm. The Vref1 ═ (V33-V) can be calculated according to circuit principles_{PSE2_EN})*R2/(R1+R2)+V_{PSE2_EN}＝(3.3-0)*1.2K/(2.1K+1.2K)+0＝1.2V。

In some embodiments, the resistor R2 may be further connected in parallel with a capacitor C1, so that the output end of the second over-current comparison circuit 303 outputs a voltage V_{PSE2_EN}During switching, the voltage Vref1 at the second input terminal of the first over-current comparison circuit 302 reaches a proper voltage after a delay time due to the charging process of the capacitor C1. The time delay design can enable the PD connected with the PSE _2 chip to be powered off for a period of time, and then detect the voltage at the output end of the current detection circuit 301. For example, when the output terminal of the second over-current comparison circuit 303 outputs the voltage V_{PSE2_EN}When the voltage is converted from 3.3V to 0V, the voltage Vref1 at the second input terminal of the first over-current comparison circuit 302 reaches 1.2V after a delay time.

In practical application, different overcurrent comparison circuits can be set to adopt different comparison voltages. For example, the voltage Vref1 at the second input terminal of the first over-current comparison circuit 302 is set to 2V, and the voltage Vref2 at the second input terminal of the second over-current comparison circuit 303 is set to 1.2V, which is not limited in the embodiment of the present application.

As shown in fig. 6, in some embodiments, the present application is further provided with more over-current comparison circuits, wherein a first input terminal of a first additional over-current comparison circuit (in fig. 6, a third over-current comparison circuit) may be coupled to an output terminal of the current detection circuit 301, a second input terminal thereof may be coupled to an output terminal of the first over-current comparison circuit 302 through a voltage control circuit similar to the voltage control circuit 304, and an output terminal thereof may be coupled to a control terminal of the PSE chip. A first input of a second additional over-current comparison circuit may be coupled to an output of the current detection circuit 301, a second input thereof may be coupled to an output of a previous additional over-current comparison circuit via a voltage control circuit similar to the voltage control circuit 304, and an output thereof may be coupled to a control terminal of the PSE chip. In this way, a plurality of overcurrent comparison circuits can be additionally arranged according to actual conditions in the embodiment of the present application, and the embodiment of the present application does not limit the number of the overcurrent comparison circuits.

In practical application, a regulated power supply can be arranged to be coupled with a control terminal of a certain PSE chip, so that a PD connected with the PSE chip is controlled by the regulated power supply and cannot be powered off. If the PSE _0 chip is connected to regulated power VCC in FIG. 6, the PD controlled by the PSE _0 chip will not normally be powered down. The worker can connect a particularly important PD to the PSE _0 chip to ensure that its power supply is stable.

In some embodiments, the output terminal of the current detection circuit 301 is coupled to a first input terminal of the first over-current comparison circuit 302 and a first input terminal of the second over-current comparison circuit 303 through a signal amplification circuit. Fig. 7 is an exemplary diagram of a power-down control circuit in the embodiment of the present application. It can be seen that the output of the current detection circuit 301 is coupled to the input of the signal amplification circuit 305, and the output of the signal amplification circuit 305 is coupled to a first input of the first over-current comparison circuit 302 and a first input of the second over-current comparison circuit 303. The embodiment of the application adopts the signal amplification circuit to amplify the voltage, so that the load condition of the PSE power supply can be more accurately judged.

In another embodiment, the output terminal of the current detection circuit 301 is coupled to the first input terminal of the first over-current comparison circuit 302 and the first input terminal of the second over-current comparison circuit 303 through two signal amplification circuits, respectively. Fig. 8 is another exemplary diagram of a power down control circuit in the embodiment of the present application. It can be seen that the output terminal of the current detection circuit 301 is coupled to the input terminal of the signal amplification circuit 3051 and the input terminal of the signal amplification circuit 3052, respectively. An output terminal of the signal amplification circuit 3051 is coupled to a first input terminal of the first over-current comparison circuit 302. An output terminal of the signal amplification circuit 3052 is coupled to a first input terminal of the second over-current comparison circuit 303.

Fig. 9 is another exemplary diagram of a power down control circuit in the embodiment of the present application. When the plurality of signal amplifying circuits are adopted in the embodiment of the application, the plurality of signal amplifying circuits can adopt different amplification factors, and the corresponding over-current detecting circuit can adopt different detection voltages, namely, different voltages can be set at the second input end of the over-current detecting circuit.

According to the embodiment of the application, the hierarchical control is realized through the plurality of overcurrent comparison circuits, when the second overcurrent comparison circuit 303 detects overcurrent, the first overcurrent comparison circuit 302 is adopted for comparison, the hierarchical control is realized, and partial PDs can be controlled to be powered off according to a preset sequence. The embodiment of the application adopts a hardware circuit mode to carry out power-off control, is quicker compared with a mode of MCU control, and can achieve ns-level response.

Fig. 10 is an exemplary diagram of a signal amplifying circuit and an over-current comparing circuit in the embodiment of the present application. Fig. 10 includes two signal amplification circuits, and both of the input voltages of the two signal amplification circuits are V0. After the input voltage V0 is amplified by the signal amplification circuit, the output voltage is V1 ═ V0 (R10/R18), and V2 ═ V0 (R20/R28). The amplification factor of the signal amplification circuit can be realized by setting the values of R10, R18, R20 and R28, and the amplification factor of the signal amplification circuit is not limited in the embodiment of the present application. The regulated power supply V33 outputs a regulated output voltage of 1.2V after voltage division by R22, R23 and R24, and the output voltage V2 is compared with the voltage of 1.2V through the second overcurrent comparison circuit.

When the output voltage V2 is less than 1.2V, the second over-current comparison circuit outputs a high level, PORT _ EN _ PSE2 is 3.3V, so that PSE2 supplies power. Vref 1-V33-PORT _ EN _ PSE 2-3.3V. At this time, in the first over-current comparison circuit, V1 is constantly less than Vref1, and the first over-current comparison circuit outputs a high level, so that PSE1 supplies power.

When the output voltage V2 is greater than 1.2V, the second over-current comparison circuit outputs a low level, and PORT _ EN _ PSE2 is 0V, so that PSE2 stops supplying power. As in the example of the lower electronic control circuit of fig. 10, the resistance R26 is 1.2K ohms, and the resistance R27 is 2.1K ohms, so that Vref1 is V33R 26/(R27+ R26) 3.3V 1.2K/(2.1K +1.2K) 1.2V. In the first overcurrent comparison circuit, the output voltage V1 is compared with Vref1, which is 1.2V. When the output voltage V1 is less than 1.2V, the first over-current comparison circuit outputs a high level, so that the PSE1 supplies power. When the output voltage V1 is greater than 1.2V, the first over-current comparison circuit outputs a low level, so that the PSE1 stops supplying power.

A capacitor C21 is further provided in the circuit shown in fig. 10, and the capacitor C21 makes the output PORT _ EN _ PSE2 of the second overcurrent comparison circuit go through the charging process of the capacitor when changing from 3.3V to 1.2V, so that Vref1 gradually changes from 3.3V to 1.2V instead of instantaneously changing to 1.2V. So that the output voltage V1 is compared with the 1.2V voltage by the first over-current comparison circuit after a time delay after the PSE2 stops supplying power. It can therefore be ensured that PSE2 and PSE1 can stop supplying power in order when the PSE power supply is overloaded.

The circuit shown in fig. 10 is further provided with C20, and the capacitor C20 can cooperate with the capacitor C21, so that when the output PORT _ EN _ PSE2 of the second overcurrent comparison circuit changes from 3.3V to 1.2V, the capacitor C20 discharges, and the output PORT _ EN _ PSE2 of the second overcurrent comparison circuit gradually changes from 3.3V to 1.2V, rather than instantaneously changing from 3.3V to 1.2V. Similarly, other capacitors in the circuit have similar functions, and are not described herein again.

In one possible embodiment, a switching circuit is coupled between an input of the first PSE chip and an output of the first PSE chip; the control terminal of the first PSE chip is coupled to the switching circuit for controlling the connection and disconnection between the input terminal of the first PSE chip and the output terminal of the first PSE chip. Fig. 11 is an exemplary diagram of a switch circuit in an embodiment of the present application. Wherein, PORT _ EN _ PSE is the control terminal of first PSE chip, and RTN _ PSE is the power supply end of PSE chip, and RTN _ PSE _ OUT is the output of PSE chip. When PORT _ EN _ PSE is high, chip Q2 is turned on so that RTN _ PSE can output to RTN _ PSE _ OUT and the corresponding PD can receive power. When PORT _ EN _ PSE is low, chip Q2 is turned off so that RTN _ PSE cannot output to RTN _ PSE _ OUT and the corresponding PD stops receiving power. In practical application, the switching circuit can also realize a switching function through other electronic components, and the embodiment of the application does not limit the switching function.

Fig. 12 is an exemplary diagram of a power-down control method in an embodiment of the present application. The method is applied to a power down control circuit as shown in fig. 3, fig. 5, fig. 6, fig. 7, fig. 8 or fig. 9. The method comprises the following steps:

1201. the first voltage is output by a current detection circuit depending on the power supply current of the power supply equipment PSE.

In an embodiment of the present application, the current detection circuit may obtain a current of the PSE power supply and convert the current of the PSE power supply into a first voltage (i.e., an output voltage of the current detection circuit). The process is similar to the description of the current detection circuit in the previous embodiment, and is not repeated here.

1202. The first voltage is compared with the second voltage by a second over-current comparison circuit.

In the embodiment of the present application, the second over-current comparing circuit may be a comparator or the like that compares two voltages, where the second voltage may be a voltage output by the voltage stabilizing circuit, for example, 1.2V. The voltage comparison performed by the second over-current comparison circuit is similar to that described in the foregoing embodiment, and is not repeated here.

1203. And when the first voltage is smaller than the second voltage, outputting a high level through a second overcurrent comparison circuit, and controlling a second PSE chip to supply power.

In the embodiment of the present application, when the first voltage is less than the second voltage, the second over-current comparison circuit outputs a high level. The high level may be a voltage greater than or equal to 1, such as 1V, 3.3V, etc., and is typically 3.3V in the embodiments of the present application. The embodiment of the present application does not limit the specific voltage of the high level.

After the high level is input to the control terminal of the second PSE chip (or the enable terminal of the second PSE chip), the second PSE chip may supply power according to the high level. The second PSE chip typically has multiple PDs connected to it, and is actually powered by the multiple PDs connected to it.

The other conditions of step 1203 are similar to the descriptions related to the second over-current comparison circuit and the second PSE chip in the foregoing embodiment, and are not described herein again.

1204. When the first voltage is larger than the second voltage, a low level is output through the second overcurrent comparison circuit, and the second PSE chip is controlled to stop supplying power.

In the embodiment of the present application, when the first voltage is greater than the second voltage, the second over-current comparison circuit outputs a low level. The low level is generally 0V, which is not limited in the embodiments of the present application.

After the low level is inputted to the control terminal of the second PSE chip (or the enable terminal of the second PSE chip), the second PSE chip may stop supplying power according to the low level, that is, stop supplying power to the plurality of PDs connected thereto.

The other conditions of step 1204 are similar to those described in the foregoing embodiment regarding the second over-current comparison circuit and the second PSE chip, and are not described herein again.

1205. And generating a third voltage according to the low level output by the second overcurrent comparison circuit through a voltage control circuit.

In this embodiment of the application, when the first voltage is greater than the second voltage, and the second over-current comparison circuit outputs a low level, step 1205 may be executed to generate, by the voltage control circuit, a third voltage according to the low level output by the second over-current comparison circuit.

In one possible embodiment, the voltage control circuit may be a voltage regulator circuit, which provides a power supply and a resistor, etc. to raise the low level output by the second over-current comparison circuit to a suitable voltage as the third voltage. For example, the voltage control circuit may increase the voltage of 0V output from the second overcurrent comparing circuit to 1.2V. The voltage control circuit may specifically refer to the description in the foregoing embodiments, and is not described herein again.

1206. The first voltage is compared with the third voltage by a first over-current comparison circuit.

In the embodiment of the present application, the first voltage and the third voltage may be input to the first over current comparison circuit. The first over-current comparison circuit may be a comparator, and compares the first voltage with the third voltage, and outputs a high level if the first voltage is less than the third voltage, and outputs a low level if the first voltage is greater than the third voltage. The first over-current comparison circuit can refer to the description in the foregoing embodiments, and is not described herein again.

1207. When the first voltage is smaller than the third voltage, a high level is output through the first overcurrent comparison circuit, and the first PSE chip is controlled to supply power.

In the embodiment of the present application, when the first voltage is less than the third voltage, the first over-current comparison circuit outputs a high level. The high level is input into a control terminal or an enabling terminal of the first PSE chip, so that the first PSE chip supplies power to a plurality of PDs connected with the first PSE chip. Specifically, reference may be made to the descriptions of the first over-current comparison circuit and the first PSE chip in the foregoing embodiments, which are not described in detail in this application embodiment.

1208. When the first voltage is larger than the third voltage, the first overcurrent comparison circuit outputs a low level to control the first PSE chip to stop supplying power.

In the embodiment of the present application, when the first voltage is greater than the third voltage, the first over-current comparison circuit outputs a low level. The low level is input into a control terminal or an enabling terminal of the first PSE chip, so that the first PSE chip stops supplying power to a plurality of PDs connected with the first PSE chip. Specifically, reference may be made to the descriptions of the first over-current comparison circuit and the first PSE chip in the foregoing embodiments, which are not described in detail in this application embodiment.

In the embodiment of the application, the power-off control circuit compares the first voltage with the second voltage through the second overcurrent comparison circuit. When the first voltage is greater than the second voltage, the power-down control circuit may compare the first voltage with the third voltage through the first over-current comparison circuit. Therefore, after the second overcurrent comparison circuit enables the second PSE chip to stop supplying power, the power-down control circuit judges whether the first PSE chip needs to stop supplying power or not, and can realize that when the PSE power supply is overloaded, one part of the PDs are powered down firstly, and then the other part of the PDs are powered down, so that the negative influence caused by the power-down of the PDs is reduced.

In one possible embodiment, the method may further comprise: a first time is delayed by a first capacitance. Correspondingly, in the power-down control circuit, a first capacitor, such as the capacitor C1 corresponding to fig. 5, may be provided at a suitable position to delay for a period of time. The first time may be related to a parameter of the first capacitor, which is not limited in this application.

In one possible embodiment, the method may further comprise: the second time is delayed by the grounded capacitance. Correspondingly, in the power-down control circuit, a grounded capacitor, such as the capacitor C20 and the capacitor C10 corresponding to fig. 10, can be added at the output end of the first overcurrent comparison circuit or the second overcurrent comparison circuit to delay the second time. The length of the second time may be related to a parameter of the ground capacitor, which is not limited in this embodiment of the application.

In one possible embodiment, the method may further include amplifying the first voltage by a signal amplification circuit. Correspondingly, in the power-down control circuit, a signal amplifying circuit may be disposed between the current detecting circuit and the first overcurrent comparing circuit, or between the current detecting circuit and the second overcurrent comparing circuit, as shown in fig. 7, 8 or 9, to amplify the first voltage. The embodiment of the present application does not limit the amplification factor of the signal amplification circuit.

In one possible embodiment, the method may further include outputting the second voltage through a voltage regulation circuit. Correspondingly, in the power-down control circuit, the input terminal Vref2 of the second over-current comparison circuit may be connected to a voltage stabilizing circuit, which outputs a second voltage, for example, a voltage of 1.2V. The embodiment of the present application does not limit this.

In a possible embodiment, the method may further include controlling, by the switching circuit, the first PSE chip to be powered according to a high level output by the first over-current comparison circuit, and controlling, by the switching circuit, the first PSE chip to be powered down according to a low level output by the first over-current comparison circuit. The switch circuit is similar to the embodiment shown in fig. 11 and will not be described herein again.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

Claims

1. A power down control circuit, comprising: the overcurrent protection circuit comprises a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit and a voltage control circuit;

2. The circuit of claim 1, wherein the second resistor is connected in parallel with a first capacitor.

3. The circuit of any of claims 1-2, wherein an enable terminal of the first PSE chip is coupled with a capacitance to ground.

4. The circuit of any one of claims 1 to 3, further comprising a signal amplification circuit;

5. The circuit of any of claims 1 to 4, wherein a second input of the second over-current comparison circuit is coupled to an output of a voltage regulation circuit;

6. The circuit of any one of claims 1 to 5, wherein the current detection circuit comprises a sampling resistor, an operational amplifier;

both ends of the sampling resistor are coupled with the PSE power supply;

7. The circuit of any one of claims 1-6, wherein a switching circuit is coupled between an input of the first PSE chip and an output of the first PSE chip;

8. A power-down control method is applied to a power-down control circuit which comprises a current detection circuit, a first overcurrent comparison circuit, a second overcurrent comparison circuit and a voltage control circuit, and comprises the following steps:

9. The method of claim 8, wherein prior to comparing the first voltage with the third voltage by the first over-current comparison circuit, the method further comprises:

a first time is delayed by a first capacitance.

10. The method of claim 8 or 9, wherein after the outputting of the low level by the first over-current comparison circuit and before the controlling of the first PSE chip to stop supplying power, the method further comprises:

the second time is delayed by the grounded capacitance.

11. The method according to any one of claims 8 to 10, wherein after the first voltage is output by the current detection circuit according to the power supply current of the power supply equipment PSE and before the first voltage is compared with the second voltage by the second overcurrent comparison circuit, the method further comprises:

the first voltage is amplified by a signal amplification circuit.

12. The method according to any one of claims 8 to 11, further comprising:

and outputting the second voltage through a voltage stabilizing circuit.

13. The method according to any one of claims 8 to 12, wherein the controlling the first PSE chip to supply power specifically comprises: