CN116781435A - Power supply device and power supply control method - Google Patents
Power supply device and power supply control method Download PDFInfo
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- CN116781435A CN116781435A CN202210231610.7A CN202210231610A CN116781435A CN 116781435 A CN116781435 A CN 116781435A CN 202210231610 A CN202210231610 A CN 202210231610A CN 116781435 A CN116781435 A CN 116781435A
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- 239000003990 capacitor Substances 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 6
- 238000012358 sourcing Methods 0.000 description 5
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- 230000004075 alteration Effects 0.000 description 1
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Abstract
The application provides a power supply device for supplying power to a power receiving device in a power over ethernet system. The power supply device comprises a first port, a second port and a control circuit. The first port is used for classifying power of the powered device in a first stage and outputting a first voltage across the powered device. The second port is used for outputting a second cross voltage to the powered device in a second stage. The control circuit is used for disabling the second port in the first stage and controlling the second port to output the second voltage across and increase the first voltage across in the second stage.
Description
Technical Field
The present application relates to a power supply device and a power supply control method, and more particularly, to a single-channel power supply device and a power supply control method.
Background
In the power over ethernet system (power over Ethernet), when the power sourcing device (power sourcing equipment) spends too long performing the power classification (power classification) on the powered device (powered device), the powered device may not be verified successfully, such that the power sourcing device may not be able to power the powered device normally. Therefore, the efficiency of performing power classification has become one of the concerns in the art.
Disclosure of Invention
The application provides an electric device for supplying power to a powered device in a power over ethernet system. The power supply device comprises a first port, a second port and a control circuit. The first port is used for classifying power of the powered device in a first stage and outputting a first voltage across the powered device. The second port is used for outputting a second cross voltage to the powered device in a second stage. The control circuit is used for disabling the second port in the first stage and controlling the second port to output the second voltage across and increase the first voltage across in the second stage.
The application provides a power supply control method which is used for controlling a power supply device to supply power to a power receiving device in an Ethernet power supply system. The power supply control method comprises the following steps: the power classification is carried out on the power receiving device in the first stage of the power supply control method, and a first port of the power supply device is controlled to output a first cross voltage to the power receiving device; disabling the second port of the power device during the first phase; controlling a second port to output a second voltage across the power receiving device in a second stage of the power supply control method; and increasing the first crossover pressure in the second stage.
The power supply device and the power supply control method of the application increase the speed of charging the capacitor in the power supply device by current in a voltage regulation mode so as to accelerate the time for executing power classification.
Drawings
Various embodiments of the application can be best understood from the following detailed description and the accompanying drawings. It should be noted that the various features of the drawings are not drawn to scale in accordance with standard practice in the art. Indeed, the dimensions of some features may be exaggerated or reduced on purpose for clarity of description.
Fig. 1 is a schematic diagram of a power over ethernet system according to some embodiments of the present application.
Fig. 2 is a schematic diagram of a power supply device and a power receiving device according to some embodiments of the application.
Fig. 3 is a waveform diagram illustrating voltages within a power supply device according to some embodiments of the present application.
Reference numerals illustrate:
PoE-Ethernet power supply PSE-power supply device PD-power receiving device system
PA-converter CRT-control circuit P1-first port
P2-second port PP 1-positive terminal PN 1-negative terminal
PP 2-positive terminal PN 2-negative terminal C1-capacitor
C2-capacitor CN-capacitor R-resistor
L-load M1-transistor M2-transistor
OP-amplifier S-switch FB-feedback controller
VDD-supply voltage VSS-supply voltage V1-voltage
V2-Voltage VC-control Voltage VP 1-Cross Voltage
VP 2-voltage-across VPD-voltage-across BR 1-bridge rectifier
BR 2-bridge rectifier T1-first stage T2-second stage
Detailed Description
Fig. 1 is a schematic diagram of a power over ethernet system (power over Ethernet, hereinafter PoE) according to some embodiments of the present application. PoE includes a power sourcing equipment (power sourcing equipment, hereinafter PSE), a Powered Device (PD), and a converter (PA).
In PoE, the PSE provides power over the wire to the PD in addition to transmitting ethernet signals, eliminating the need for the remote PD to receive additional power. In some embodiments, the power consumption required by the PD is high, and the PSE may not be enough to use only one port to transfer power. In this case, the PSE uses a single signature mode (also referred to as a single feature application) to power the PD. Specifically, in single channel mode, the PSE uses two (or more) ports to transfer power to the PD. For ease of illustration, the application is explained in terms of a PSE using two ports to provide power to a PD. The present application is not limited in this regard and it is within the contemplation and scope of the application to use various numbers of ports to power the PD.
The PA is used to provide supply voltages VDD and VSS to the PSE, for example, to provide a dc voltage of 48V between the supply voltage VDD and the supply voltage VSS. The PSE uses the supply voltages VDD, VSS to supply power to the PD.
Reference is made to fig. 2. Fig. 2 is a schematic diagram of a PSE and PD according to some embodiments of the application. The PSE comprises a plurality of ports and control circuitry CRT, only the first port P1 and the second port P2 are discussed in the present application, wherein the first port P1 and the second port P2 may be any two of these ports in the PSE. The control circuit CRT is coupled to the first port P1 and the second port P2 for controlling the power supply of the first port P1 and the second port P2 to the PD. The first port P1 and the second port P2 are coupled to the PD through the network cable, respectively.
The operation of the PSE may be divided into two phases T1 and T2 before the PSE is to provide power to the PD, with the PSE and PD being power classified (also referred to as power detection) first in the first phase T1. During the first phase T1, the PSE detects with the PD through the first port P1, and enters the second phase T2 if the PD is verified successfully.
The first port P1 and the second port P2 are respectively configured to provide the cross-voltage VP1 and the cross-voltage VP2 to the PD. The first port P1 includes a positive terminal PP1 and a negative terminal PN1, wherein the positive terminal PP1 is configured to receive the supply voltage VDD and transmit it to the PD, and the negative terminal PN1 is configured to receive the voltage V1 from the PD. The second port P2 includes a positive terminal PP2 and a negative terminal PN2, wherein the positive terminal PP2 is configured to receive the supply voltage VDD and transmit it to the PD, and the negative terminal PN2 is configured to receive the voltage V2 from the PD. The voltage difference between the supply voltage VDD and the voltage V1 is the voltage across VP1, and the voltage difference between the supply voltage VDD and the voltage V2 is the voltage across VP2.
The control circuit CRT includes a capacitor C1, a capacitor C2, a transistor M1, a transistor M2, an amplifier OP, a feedback controller FB and a switch S. The capacitor C1 is coupled between the supply voltage VDD and the first terminal of the transistor M1; the feedback controller FB is coupled between the positive input terminal of the amplifier OP and the first terminal of the transistor M1; the negative input end of the amplifier OP is used for receiving a reference voltage VREF; the output end of the amplifier OP is coupled with the control end of the transistor M1; the second terminal of the transistor M1 is coupled to the supply voltage VSS; the capacitor C2 is coupled between the supply voltage VDD and the first terminal of the transistor M2; the output end of the amplifier OP is also coupled with the control end of the transistor M2 through a switch S; the second terminal of the transistor M2 is coupled to the supply voltage VSS. The first terminal of the transistor M1 is coupled to the negative terminal PN1 for receiving the voltage V1, and the first terminal of the transistor M2 is coupled to the negative terminal PN2 for receiving the voltage V2.
In some embodiments, the PD includes a bridge rectifier BR1 and a bridge rectifier BR2 connected across the load L. For ease of understanding, load L is represented by an RC circuit consisting of a capacitance CN and a resistance R. The bridge rectifier BR1 is used for receiving the supply voltage VDD and outputting a first voltage; the bridge rectifier BR2 is used for receiving the supply voltage VDD and outputting a second voltage. When the first port P1 supplies power to the PD, the voltage across the load L VPD is equal to the voltage across VP1. Similarly, when the second port P2 powers the PD, the voltage across the load L VPD is equal to the voltage across VP2. When the PSE utilizes the first port P1 and the second port P2 to supply power to the PD to reach a steady state, the cross voltages VP1, VP2, VPD are equal.
In the first phase T1, the switch S is turned off, the transistor M2 is thus turned off, and the voltage across the capacitor C2 VP2 is 0, so that the second port P2 is disabled (disabled). The supply voltage VDD is transferred from the positive terminal PP1 of the first port P1 to PD and generates a voltage across the load L VPD. Next, the voltage V1 (=vdd-VPD) is transmitted from the bridge rectifier BR1 to the first terminal of the transistor M1 through the negative terminal PN1 of the first port P1. The feedback controller FB is configured to directly transmit the voltage V1 to the positive receiving terminal of the amplifier OP.
In the present application, the voltage V1 is greater than the reference voltage VREF, and the amplifier OP generates the control voltage VC greater than 0, so the transistor M1 is turned on. Referring to fig. 3, fig. 3 is a waveform diagram of voltage V1 and voltage V2 according to some embodiments of the application. When the transistor M1 is turned on, an on-current is generated and transmitted from the first segment of the transistor M1 to the second end coupled to the supply voltage VSS, so that the voltage V1 at the first end of the transistor M1 is pulled down. Next, the first terminal of the transistor M1 (coupled to the capacitor C1) gradually accumulates charge until the voltage across the capacitor C1 is equal to the predetermined voltage across VP1 (as shown in the region of the first stage T1 in fig. 3).
In the second phase T2, the switch S is turned on, and the transistor M2 is thereby turned on, so that the second port P2 is enabled (enabled). The supply voltage VDD is transferred from the positive terminal PP2 of the second port P2 to PD and generates a voltage across the load L VPD. Next, the voltage V2 (=vdd-VPD) is transmitted from the bridge rectifier BR2 to the first terminal of the transistor M2 through the negative terminal PN2 of the second port P2. Similarly, when the transistor M2 is just turned on, the transistor M2 generates a current to be transferred to the supply voltage VSS terminal, and thus the voltage V2 at the first terminal of the transistor M2 is pulled down. Next, the first terminal of the transistor M2 (coupled to the capacitor C2) gradually accumulates charge to a voltage across the capacitor C2 equal to the predetermined voltage across VP2 (as shown in the region of the second stage T2 in fig. 3).
In some embodiments, the feedback controller FB directly transmits the voltage V1 to the positive receiving terminal of the amplifier OP in the second phase T2. The amplifier OP generates a control voltage VC greater than 0, so the transistors M1 and M2 are turned on. Meanwhile, the control circuit CRT is configured to change the reference voltage VREF in the second stage T2, so that the voltage V1 at the first terminal of the transistor M1 decreases, thereby causing the instantaneous increase of the voltage across VP1 (voltage across VPD). In this case, the current flowing through the load L becomes large as the voltage across VPD becomes large. In some embodiments, the transistor M1 and the transistor M2 have the same size and specification, so that when the switch S is turned on, the current flowing through the transistor M1 can be mirrored to the transistor M2.
Since the second port P2 has just been enabled and the bridge rectifier BR2 in the PD is not yet on, the equivalent impedance from the load L to the bridge rectifier BR1 is relatively low, so the proportion of current on the load L that is transferred to the first terminal of the transistor M2 is small. Therefore, the time required for the control circuit CRT to accumulate the charge on the first terminal of the transistor M2 to the voltage across the capacitor C2 equal to the voltage across VP2 is short. However, by momentarily increasing the voltage across VP1 (i.e., decreasing the voltage V1), additional mirror current can be generated on the transistor M2, increasing the rate at which charge is accumulated at the first terminal of the transistor M2, reducing the time required for operation.
In some embodiments, the control circuit CRT increases the reference voltage VREF to increase the voltage across VP1 during the second phase T2. However, the present application is not limited thereto, and the control circuit CRT can also decrease the reference voltage VREF to increase the voltage VP1 in the second stage T2 according to the different types of transistors M1 and/or the amplifier OP.
In other embodiments, the control circuit CRT does not adjust the reference voltage VREF in the second stage, but rather steps up the voltage V1 to the voltage V3 by the feedback controller FB and transmits the voltage V3 to the positive receiving terminal of the amplifier OP. Similar to the embodiment of adjusting the reference voltage VREF, the control circuit CRT decreases the voltage V3 to the voltage V1 and transmits the voltage V1 to the positive receiving terminal of the amplifier OP to decrease the voltage V1 at the first terminal of the transistor M1 to momentarily increase the current flowing through the transistor M1 and thus the current flowing through the transistor M2.
When the first terminal of the transistor M2 accumulates enough charge to make the voltage across the capacitor C2 reach the predetermined VP2, the second stage T2 is completed and reaches the steady state, and the voltage across VP1, VP2, and VPD are equal.
The foregoing description briefly sets forth features of certain embodiments of the application in order to provide a more thorough understanding of the various embodiments of the present disclosure to those skilled in the art to which the present application pertains. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments herein. Those skilled in the art to which the application pertains will appreciate that such equivalent embodiments are within the spirit and scope of the disclosure and that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure.
Claims (10)
1. A power supply apparatus for powering a powered device in a power over ethernet system, comprising:
the first port is used for carrying out power classification on the powered device in a first stage and outputting a first cross voltage to the powered device;
the second port is used for outputting a second cross voltage to the powered device in a second stage; and
and the control circuit is used for disabling the second port in the first stage and controlling the second port to output the second voltage across and increase the first voltage across in the second stage.
2. The power supply of claim 1, wherein the first port has a first positive terminal and a first negative terminal, wherein during the first phase the first positive terminal is configured to output a first supply voltage to the powered device and the first negative terminal is configured to receive a first voltage from the powered device, wherein the first supply voltage and the first voltage form the first voltage across the first positive terminal and the first negative terminal.
3. The power supply of claim 2, wherein the second port has a second positive terminal and a second negative terminal, wherein during the second phase the second positive terminal is configured to output the first supply voltage to the powered device and the second negative terminal is configured to receive a second voltage from the powered device, wherein the first supply voltage and the second voltage form the second voltage across the first positive terminal and the first negative terminal.
4. A power supply according to claim 3, wherein the control circuit comprises:
a first capacitor;
a first transistor; and
an amplifier having a positive receiving terminal, a negative receiving terminal and an output terminal,
wherein the first capacitor is coupled between the first supply voltage and a first terminal of the first transistor, the output terminal is coupled to a control terminal of the first transistor, and a second terminal of the first transistor is coupled to a second supply voltage,
wherein the first end of the first transistor is for receiving the first voltage.
5. The power supply of claim 4, wherein the control circuit further comprises:
a second capacitor; and
a second transistor is provided, which is connected to the first transistor,
wherein the second capacitor is coupled between the first supply voltage and a first terminal of the second transistor, and a second terminal of the second transistor is coupled to the second supply voltage,
wherein the first end of the second transistor is for receiving the second voltage.
6. The power supply of claim 4, wherein the positive receiving terminal is configured to receive the first voltage, and the negative receiving terminal is configured to receive a first reference voltage during the first phase and a second reference voltage during the second phase, wherein the second reference voltage is greater than the first reference voltage.
7. The power supply of claim 4, wherein the control circuit further comprises a feedback controller coupled between the positive receiving terminal and the first terminal of the first transistor, wherein the feedback controller is configured to transmit the first voltage directly to the positive receiving terminal during the first phase and to boost the first voltage of the positive receiving terminal to a third voltage during the second phase,
the negative receiving terminal is used for receiving a first reference voltage in the first stage and the second stage.
8. A power supply control method for controlling power supply of a power supply device to a power receiving device in a power over ethernet system, comprising:
performing a power classification on the powered device at a first stage of the power supply control method, and controlling a first port of the power supply device to output a first voltage across the powered device;
disabling a second port of the power supply device during the first phase;
controlling the second port to output a second voltage across the power receiving device in a second stage of the power supply control method; and
the first crossover pressure is increased in the second stage.
9. The power supply control method according to claim 8, wherein controlling the first port of the power supply device to output the first voltage across to the power receiving device comprises:
transmitting a first supply voltage to the powered device through a first positive terminal of the first port; and
a first voltage is received from the powered device through a first negative terminal of the first port,
wherein the first supply voltage and the first voltage form the first voltage across the first positive terminal and the first negative terminal, wherein controlling the second port to output the second voltage across the powered device comprises:
transmitting the first supply voltage to the powered device through a second positive terminal of the second port; and
receiving a second voltage from the powered device through a second negative terminal of the second port,
wherein the first supply voltage and the second voltage form the second voltage across the second positive terminal and the second negative terminal.
10. The power supply control method according to claim 9, wherein increasing the first voltage across in the second stage includes:
the first voltage is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210231610.7A CN116781435A (en) | 2022-03-10 | 2022-03-10 | Power supply device and power supply control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210231610.7A CN116781435A (en) | 2022-03-10 | 2022-03-10 | Power supply device and power supply control method |
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| Publication Number | Publication Date |
|---|---|
| CN116781435A true CN116781435A (en) | 2023-09-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210231610.7A Pending CN116781435A (en) | 2022-03-10 | 2022-03-10 | Power supply device and power supply control method |
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| CN (1) | CN116781435A (en) |
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- 2022-03-10 CN CN202210231610.7A patent/CN116781435A/en active Pending
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