CN113036012B - High light-emitting rate integrated unit diode chip - Google Patents

High light-emitting rate integrated unit diode chip Download PDF

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CN113036012B
CN113036012B CN201911356240.4A CN201911356240A CN113036012B CN 113036012 B CN113036012 B CN 113036012B CN 201911356240 A CN201911356240 A CN 201911356240A CN 113036012 B CN113036012 B CN 113036012B
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diode
type electrode
conductive type
integrated unit
diode chip
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CN113036012A (en
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闫春辉
蒋振宇
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Naweilang Technology Shenzhen Co ltd
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Shenzhen Third Generation Semiconductor Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides an integrated unit diode chip with high light extraction rate, which comprises a first conductive type electrode, a second conductive type electrode and a plurality of diode mesa structures and groove structures, wherein the side, far away from the first conductive type electrode, of the integrated unit diode chip forms n diode mesa structures and groove structures; the second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the direction vertical to the table top. The invention solves the problems of the prior art that the thickness of the transparent electrode limits the transverse current diffusion and the luminous efficiency of the LED, improves the lumen output of the unit diode chip per unit area and reduces the lumen cost.

Description

High light-emitting rate integrated unit diode chip
Technical Field
The invention relates to the field of semiconductor material and device process, in particular to a semiconductor photoelectric device, and more particularly relates to an integrated unit diode chip with high light extraction rate.
Background
The conventional forward-mounted integrated unit diode chip has uneven current diffusion, which causes the loss of luminous efficiency, the heat dissipation of the diode unit diode chip under the existing structure is realized by a sapphire substrate, and the heat dissipation is poor, so that the efficiency and the stability of the unit diode chip are influenced, therefore, the main application field of the forward-mounted light-emitting diode unit diode chip is the market of medium-small power unit diode chips below 0.5 watt, and the forward-mounted light-emitting diode chip cannot provide a product with high lumen output per unit area. The non-uniformity of current diffusion, the non-uniformity of heat diffusion and the non-uniformity of light extraction cause the LED to have great limitations on three important parameters of lumen efficiency, lumen density output and lumen cost, and the forward-mounted diode technology in the current market cannot provide an effective solution.
One prior art is U.S. patent application publication No. US6614056B1, shown in fig. 1, 21/23 being an N-type electrode and 19/20ab being a P-type electrode. The mechanism of current diffusion is as follows: after ITO (indium tin oxide) and P-type gallium nitride form ohmic contact, 19/20ab metal is deposited on the ITO, holes are diffused to the P-type gallium nitride in an electrode wire mode and reach a quantum well active region, electrons diffused from the quantum well active region and a 21/22N-type electrode emit light through radiation recombination, and a light-emitting LED device is obtained. By adopting ITO transparent conductive ohmic contact and a current diffusion mode of a metal lead, the total current diffusion is very uneven because the ITO resistivity is high and the conductivity of the P-type gallium nitride material is poor. And considering the problem of absorption of light by ITO, the thickness of the ITO layer cannot be too large, which also limits the overall current spreading. In addition, because the current diffusion length of the LED unit diode chip is inversely proportional to the square root of the current density, the current diffusion length is shorter under the injection of large current, so that the current diffusion of the unit diode chip is more uneven, the efficiency is lower, and the heat dissipation is more difficult.
The non-uniformity of current spreading of the diode chip of the forward integrated unit results in a loss of luminous efficiency. The heat dissipation of the diode unit diode chip under the existing structure is realized by the sapphire substrate, and the heat dissipation is poor, so that the efficiency and the stability of the diode unit chip are affected, and therefore, the main application field of the normally installed light emitting diode unit chip is the market of medium and small power unit diode chips below 0.5 watt, and a product with high lumen output per unit area cannot be provided. The non-uniformity of current diffusion, the non-uniformity of heat diffusion and the non-uniformity of light extraction cause the current to have great limitations on three important parameters of lumen efficiency, lumen density output and lumen cost, and the forward-mounted light-emitting diode technology in the current market cannot provide an effective solution.
Second prior art conference paper of SPIE Vol.10021100210X-12016, as shown in FIG. 2, the near-field analysis diagram (upper) and the normalized current distribution diagram (lower) on the middle line of the LED chip being mounted, the size of the chip is 1.2mm × 1.2 mm. The light intensity distribution in the near-field analysis chart is proportional to the distribution of current spreading. It can be seen that the concentration is 7A/cm 2 When the current is small, the current density in some edge regions is less than 80% of that in the middle region, and when the current is increased by 70A/cm 2 When this occurs, the current density in some regions of the edge is less than 50% even of the middle region. Therefore, the luminous efficiency, heat dissipation and stability of the LED under large current are severely limited.
The thickness of a transparent conductive film ITO (transparent electrode) in the current LED design is generally about 60-120 nanometers, and the thicker ITO absorbs light more, so that the light emitting efficiency of the LED is reduced. And the thinner the ITO thickness is, the larger the sheet resistance is, resulting in the poorer lateral current spreading efficiency. Therefore, the thickness of ITO in the existing LED design is usually limited to a process window of 60-120 nm.
Disclosure of Invention
The invention provides an integrated unit diode chip with high light-emitting rate, which has small unit size and thin transparent electrode, and aims to solve the problem that the thickness of a transparent electrode has overlarge influence on the light-emitting efficiency and current diffusion of an LED chip in the prior art.
To achieve the above object, the chip has a length, width and height of X, Y and Z, respectively, the length, width and height of the mesa size of each unit are represented by a, b and c, and the units are arranged and distributed according to a unit of J multiplied by K.
The invention provides an integrated unit diode chip with high light extraction rate, comprising:
the diode comprises a first conductive type electrode, a second conductive type electrode and n diode unit mesa structures and a groove structure, wherein the n diode unit mesa structures and the groove structure are formed on one side far away from the first conductive type electrode, the second conductive type electrode wire extends along the groove on the second conductive type layer, the n diode unit mesa structures are formed between the extended second conductive type electrode wires, n is larger than or equal to 2, and the distance between the first conductive type electrode and the second conductive type electrode of each unit in the direction vertical to the extending direction of the electrode wires is determined according to the current diffusion length;
the existing LED structure faces the problem of lateral current diffusion from a P electrode to a quantum well active region and from an N electrode to the quantum well active region, and the current lateral diffusion cannot achieve 100% of current uniform distribution in physical nature. The current diffusion length is related to an LED epitaxial structure and a chip structure, is not a fixed value, and is usually about 80 micrometers under a small current, while in most LED chip designs on the market, the distance from an n electrode lead to a p electrode lead is usually about 100 micrometers, so that the current middle-power and small-power LED chips generally have the problem of relatively serious uneven current distribution. Meanwhile, the current diffusion length is also a function of the current density, and the current diffusion length is reduced along with the increase of the current density, so that the current diffusion under large current is more uneven, the current density of a local area is overlarge, and the efficiency is reduced. Meanwhile, the high current density area is also a heat collection area, so that the stability of the chip is influenced, the service life of the chip is shortened, and higher requirements on the packaging heat dissipation technology and the cost are provided.
The same problem exists in the above aspects, and the lateral current diffusion cannot achieve 100% uniform current distribution in a physical nature. The current spreading length is defined by J (0) exp (-x/Lx), which is related to the LED epitaxial structure and the chip structure, and is not a fixed value, and is usually about 80 microns at a small current, while in most LED chip designs on the market, the distance from the N electrode lead to the P electrode lead is usually about 100 microns, so that the current medium and small power LED chips generally have a relatively serious problem of non-uniform current distribution. Meanwhile, the current diffusion length is also a function of the current density, and the current diffusion length is reduced along with the increase of the current density, so that the current diffusion under large current is more uneven, the current density of a local area is overlarge, and the efficiency is reduced. Meanwhile, the high current density area is also a heat collection area, so that the stability of the chip is influenced, the service life of the chip is shortened, and higher requirements on the packaging heat dissipation technology and the cost are provided.
As a further preference, the length of the current diffusion is in particular the lateral critical current diffusion length;
the lateral critical current diffusion length is a current diffusion length corresponding to an inflection point on a "working Voltage (VF) -cell size" curve of the light emitting diode cell. When the threshold value is less than the critical value, the performance of the chip is greatly improved.
Preferably, the dimensions of the mesa structure are specifically selected as follows: a distance between the first conductivity type electrode and the second conductivity type electrode of each of the cells in a direction perpendicular to an extending direction of the electrode lines.
Preferably, the lateral critical current diffusion length is less than 70 microns.
The n diode units comprise an insulating medium layer, a transparent electrode and a second conductive type electrode, wherein the insulating medium layer is positioned on the first conductive type layer and partially covers the second conductive type layer; the second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the direction vertical to the table board.
Preferably, the n diode cells comprise quantum well active regions; the quantum well active region is located between the first conductivity type layer and the second conductivity type layer.
Preferably, the chip comprises a trench structure, the trench structure being located between the diode units.
Preferably, the insulating medium layer, the transparent electrode and the second conductive type electrode are arranged in the groove structure.
Preferably, the thickness of the transparent electrode is 60 to 120 nanometers, or 1 to 60 nanometers.
Preferably, the chip includes a first conductive type pad and a second conductive type pad, the first conductive type electrode is connected to the first conductive type pad, and the second conductive type electrode is connected to the second conductive type pad.
Preferably, the first conductive type electrode and the second conductive type electrode are a first conductive type electrode line and a second conductive type electrode line, respectively.
Preferably, the first conductive type electrode line and the second conductive type electrode line are line-shaped electrode lines; the width of the linear electrode line is 0.001-20 microns, and the thickness is 0.001-10 microns.
Preferably, the insulating dielectric layer material is silicon dioxide, aluminum oxide, silicon nitride.
Preferably, the diode unit is connected in a manner that: parallel connection, series connection or series-parallel connection mixing with set proportion.
Preferably, the diode unit is shaped as follows: triangle, square, rectangle, pentagon, hexagon, circle, arbitrary self-defined shape.
Preferably, the number of the diode units is 2 to 1000 hundred million.
Preferably, the length of the diode unit along the direction perpendicular to the extension direction of the electrode wire is 0.001-200 microns.
Preferably, the layout mode of the line-type electrode line is as follows: the layout that more than 1 first conduction type electrode wire surrounds the chip plane; or more than 1 second conductive type electrode wires surround the planar layout of the chip; or the first conductive type electrode wires and the second conductive type electrode wires are distributed in equal quantity; or the first conductive type electrode wires and the second conductive type electrode wires are parallel and are in insulated overlapping layout in a vertical space, and insulating medium materials are arranged between the overlapping parts of the different conductive type electrode wires; or the first conductive type electrode wires and the second conductive type electrode wires are in insulated vertical crossing layout, and insulating medium materials are arranged between crossing parts of the different conductive type electrode wires; or the first conductive type electrode wires and the second conductive type electrode wires are partially or completely designed in a non-linear layout.
Preferably, the non-linear layout includes a broken line layout and a curve layout.
Preferably, the line-shaped electrode wire is made of a line-shaped metal and/or an indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
Preferably, the diode mesa structure comprises a hole structure.
Preferably, the substrate is located on a mirror. The reflector material is silver, aluminum or distributed Bragg reflector.
The integrated unit diode chip with high light extraction rate breaks through the limitation of the existing upright LED technology in three aspects of light, electricity and heat through the nanometer and micron size structure effect. The second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the direction vertical to the table top, so that the transverse diffusion of current is promoted; the reduction of the size of the integrated unit diode chip brings larger side wall heat dissipation area, has better heat dissipation performance, and can allow the injection of super-high current density without influencing the stability of the integrated unit diode chip. The transparent electrode is small in thickness and weak in light absorption capacity, so that the light emitting efficiency of the LED is enhanced, and the bottleneck of the thickness of the transparent electrode in the prior art is solved. The size design of the unit diode chip is controlled within the current diffusion length, and the geometric optimization design mode with higher degree of freedom can simultaneously solve the problem of uneven current diffusion of an N electrode and a P electrode which troubles the design of the LED unit diode chip, thereby obtaining higher photoelectric conversion efficiency/lumen efficiency; the nano-micro structure of each diode unit and the hole structure in the table top can increase the light-emitting area of the side wall, thereby improving the light extraction efficiency.
Drawings
Fig. 1 is a diagram of a prior art diode cell structure.
Fig. 2 is a structure diagram of a diode cell of the prior art.
Fig. 3 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 1 of the present invention.
Fig. 4 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 1 of the present invention.
Fig. 5 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 1 of the present invention.
Fig. 6 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 2 of the present invention.
Fig. 7 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 2 of the present invention.
Fig. 8 is a top view of a mesa structure of a diode chip with a high light extraction efficiency provided in embodiment 2 of the present invention.
Fig. 9 is a cross-sectional view of a high light extraction efficiency integrated unit diode chip provided in embodiment 2 of the present invention.
Fig. 10 is a cross-sectional view of a high light extraction efficiency integrated unit diode chip provided in embodiment 2 of the present invention.
FIG. 11 is a graph of operating voltage VF versus cell size
FIG. 12 is a diagram illustrating the VF reduction effect achieved by the present invention
FIG. 13 is a schematic diagram of the preferred diode cell mesa dimension definition of the present invention
The LED comprises an N-type electrode wire 1, a P-type electrode wire 2, a transparent electrode 3, an insulating medium layer 4, a P-type gallium nitride layer 5, a quantum well active region (MQWs)6, an N-type gallium nitride layer 7, an intrinsic GaN layer 8, a substrate 9, a reflector 10, an N-type welding disk 11, a P-type welding disk 12, an integral table-board structure 13, a diode unit 14, a groove structure 15, a hole structure 16 and a groove and table-board uncovered region 17.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of the present invention.
In view of the great limitations of the three important parameters of the existing diode structure, namely, the lumen efficiency, the lumen density output and the lumen cost, the embodiment of the invention provides a forward-mounted integrated unit diode with high lumen efficiency and high lumen density output, and the invention is described in detail below with reference to the attached drawings.
A high extraction integrated unit diode chip comprising:
the diode comprises a first conductive type electrode, a second conductive type electrode and n diode unit mesa structures positioned between the first conductive type electrode and the second conductive type electrode, wherein n is more than or equal to 2, and the distance between the first conductive type electrode and the second conductive type electrode of each diode unit in the direction perpendicular to the extension direction of an electrode wire is less than the diffusion length of transverse critical current;
the n diode units comprise an insulating medium layer, a transparent electrode and a second conductive type electrode, wherein the insulating medium layer is positioned on the first conductive type layer and partially covers the second conductive type layer; the second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the direction vertical to the table board.
The n diode cells include a quantum well active region; the quantum well active region is located between the first conductivity type layer and the second conductivity type layer. The chip further comprises a groove structure, the groove structure is located between the diode units, the width of the groove is 0.0005 microns-10 microns, and the depth of the groove is 0.0005 microns-10 microns. The insulating medium layer, the transparent electrode and the second conductive type electrode are arranged in the groove structure.
The chip comprises a first conduction type bonding pad and a second conduction type bonding pad, wherein the first conduction type electrode is connected with the first conduction type bonding pad, and the second conduction type electrode is connected with the second conduction type bonding pad. The first conductivity type electrode and the second conductivity type electrode are a first conductivity type electrode line and a second conductivity type electrode line, respectively. The first conductive type electrode wire and the second conductive type electrode wire are line type electrode wires; the width of the linear electrode line is 0.001-20 microns, and the thickness is 0.001-10 microns. The first conductive type electrode is an N-type electrode wire, the second conductive type electrode is a P-type electrode wire, the first conductive type bonding pad is an N-type bonding pad, the second conductive type is a P-type bonding pad, the first conductive type layer is an N-type gallium nitride layer, and the second conductive type layer is a P-type gallium nitride layer.
The layout mode of the linear electrode wires is as follows: more than 1N-type electrode wires surround the surface of the chip; or more than 1P-type electrode wire surrounds the surface layout of the chip; or the N-type electrode wires and the P-type electrode wires are distributed in equal number; or the N-type electrode wires and the P-type electrode wires are parallel and are in insulation overlapping layout in a vertical space, and insulating dielectric materials are arranged between the overlapping parts of the electrode wires with different conductive types; or the N-type electrode wires and the P-type electrode wires are in insulated vertical crossing arrangement, and insulating medium materials are arranged between crossing parts of the electrode wires with different conductive types; or the N-type electrode wire and the P-type electrode wire are partially or completely designed in a non-linear layout manner; the non-linear layout includes a broken line layout and a curve layout. The line-shaped electrode wire is made of line-shaped metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
The thickness of the transparent electrode is 60-120 nm, or 1-60 nm, and the insulating dielectric layer is made of silicon dioxide, aluminum oxide, and silicon nitride.
The connection mode of the diode unit is as follows: parallel connection, series connection or series-parallel connection mixing with set proportion. The diode unit shape is: triangle, square, rectangle, pentagon, hexagon, circle, any custom shape. The number of the diode units is 2-1000 hundred million. The length of the diode unit along the direction vertical to the extension direction of the electrode wire is 0.001-200 microns.
The diode mesa structure comprises a hole structure, an intrinsic gallium nitride layer is arranged between the diode mesa structure and a substrate, the substrate is positioned on a reflector, and the reflector is made of silver, aluminum or a distributed Bragg reflector.
Example 1
The present embodiment provides an integrated unit diode chip with high light extraction efficiency, as shown in fig. 3, including: the diode comprises an N-type electrode wire 1, a P-type electrode wire 2, an N-type welding disk 11, a P-type welding disk 12, an integral structure 13 consisting of diode unit table boards, diode units 14 and a groove structure 15, wherein the width of a groove is 0.1 micrometer, the depth of the groove is 0.01 micrometer, and the groove structure is positioned among the diode units. The chip comprises 6 rows of 52 square diode units 16 which are uniformly distributed in equal size, and the length of each diode unit along the direction perpendicular to the extension direction of the electrode wires is 40 micrometers. The diode mesa structure adopts the square arrangement, and the first conductivity type electrode of each diode unit is less than horizontal critical current diffusion length with the second conductivity type inter-electrode perpendicular to electrode line extension distance. The diode units are in a shape of a positive rectangle and are distributed according to uniform symmetrical arrangement. As shown in fig. 4, the trench in the chip plane and the top of the diode unit are laid with a transparent electrode 3, which completely covers the trench structure and occupies most of the chip plane structure.
In some preferred embodiments, the length of the diode unit along the direction perpendicular to the extension direction of the electrode line is 100 nanometers, the width of the groove is 0.01 micrometer, and the depth is 0.001 micrometer; in other preferred embodiments, the length of the diode unit along the direction perpendicular to the extension direction of the electrode lines is 10 nanometers, the width of the groove is 0.001 micrometer, and the depth is 0.0001 micrometer.
The N-type electrode wire 1 and the P-type electrode wire 2 are line-type electrode wires, the width of each line-type electrode wire is 0.001-20 micrometers, the thickness of each line-type electrode wire is 0.001-10 micrometers, the electrode wires are made of indium tin oxide materials, and the line layout design is adopted. The N-type bonding pad 11 and the P-type bonding pad 12 are in the shape of an arc irregular polygon, the number of the bonding pads is 1, and the bonding pads are located on the edge of the chip. The groove structure 17 is cross-shaped, the cross section is rectangular, and the electrode wires are uniformly distributed in the extending direction.
As shown in fig. 5, each diode unit is further provided with a pore structure 16, the pore structure comprises 2 pore units, and the diameter of each pore unit is 1 nm-20 microns. The hole units are arranged symmetrically, asymmetrically, periodically, non-periodically or randomly. The cell shape may also be triangular, square, rectangular, pentagonal, hexagonal, circular, and any other arbitrarily defined shape, and is not limited to the shape shown in fig. 5.
Example 2
The present embodiment provides a mesa structure of a diode chip with high light extraction efficiency, as shown in fig. 6, including: the diode comprises an N-type electrode wire 1, a P-type electrode wire 2, an N-type welding disc 11, a P-type welding disc 12, an integral table-board structure 13 consisting of diode unit table boards, a diode unit 14 and a groove structure 15, wherein the width of a groove is 1 micrometer, and the depth of the groove structure is 0.1 micrometer, and the groove structure is positioned among the diode units. The diode mesa comprises 6 rows of 6 equal sized elongate diode cells 16 having a length of 80 microns in a direction perpendicular to the extension of the electrode lines. The diode mesa structure is arranged in a rectangle, and the extension distance between the first conduction type electrode and the second conduction type electrode of each diode unit, which is vertical to the electrode wire, is less than the transverse critical current diffusion length. As shown in fig. 7, the trench in the diode mesa and the top of the diode cell are laid with a transparent electrode 3 that completely covers the trench structure and occupies most of the chip plane.
Fig. 9 is a cross-sectional view of a diode chip with a trench structure completely covered by a transparent electrode, which includes an N-type electrode line 1, a P-type electrode line 2, a transparent electrode 3, an insulating dielectric layer 4, an N-type gallium nitride layer 7, a P-type gallium nitride layer 5, a quantum well active region 6, an intrinsic gallium nitride layer (u-GaN) layer 8, a substrate 9, and a reflector 10. The quantum well active region 6 is located between the N-type gallium nitride layer 7 and the P-type gallium nitride layer 5. The insulating medium layer 4 is positioned on the N-type gallium nitride layer 7 and partially covers the P-type gallium nitride layer 5, and the transparent electrode 3 is positioned on the P-type gallium nitride layer 5 and completely covers the insulating medium layer 4 on the N-type gallium nitride layer 7; the P-type electrode wire 2, the transparent electrode 3 and the P-type gallium nitride layer 5 are not communicated in the direction vertical to the table top; the insulating medium layer 4, the transparent electrode 3 and the P-type electrode wire 2 are arranged in the groove structure. The depth of the groove of the diode unit is up to the N-type gallium nitride layer.
As shown in fig. 8, the transparent electrode may also partially cover the trench structure, leaving a portion of the trench and the mesa uncovered region 17, the uncovered region being shown in cross-section in fig. 10. The GaN-based solar cell comprises an N-type electrode wire 1, a P-type electrode wire 2, a transparent electrode 3, an insulating medium layer 4, an N-type gallium nitride layer 7, a P-type gallium nitride layer 5, a quantum well active region 6, an intrinsic gallium nitride layer (u-GaN) layer 8, a substrate 9 and a reflector 10. The quantum well active region 6 is located between the N-type gallium nitride layer 7 and the P-type gallium nitride layer 5. The insulating medium layer 4 is positioned on the N-type gallium nitride layer 7 and partially covers the P-type gallium nitride layer 5, and the transparent electrode 3 is positioned on the P-type gallium nitride layer 5 and partially covers the insulating medium layer 4 at the top of the unit; the P-type electrode wire 2, the transparent electrode 3 and the P-type gallium nitride layer 5 are not communicated in the direction vertical to the table top; the insulating medium layer 4 and the P-type electrode wire 2 are arranged in the groove structure. The depth of the groove of the diode unit is up to the N-type gallium nitride layer.
In some preferred embodiments, the length of the diode unit along the direction perpendicular to the extension direction of the electrode lines is 100 micrometers, the width of the groove is 5 micrometers, and the depth is 2 micrometers; in other preferred embodiments, the length of the diode unit along the direction perpendicular to the extension direction of the electrode lines is 10 micrometers; in other preferred embodiments, the length of the diode cell in the direction perpendicular to the extension direction of the electrode lines is 1 micrometer, the width of the trench is 8 micrometers, and the depth is 1.5 micrometers.
The N-type electrode wire 1 and the P-type electrode wire 2 are line-type electrode wires, the width of each line-type electrode wire is 0.001-20 micrometers, the thickness of each line-type electrode wire is 0.001-10 micrometers, the electrode wires are made of indium tin oxide materials, and the line layout design is adopted. The N-type bonding pads 11 and the P-type bonding pads 12 are in the shape of an arc irregular polygon, the number of the bonding pads is 1, and the bonding pads are located on the edge of the table-board structure. The groove structure 17 is cross-shaped, the cross section is rectangular, and the electrode wires are uniformly distributed in the extending direction.
The diode chip provided by the embodiment can effectively block the diffusion of current in the vertical direction, and promotes the uniform and transverse diffusion of the current, so that the light is emitted more uniformly, and the light emitting efficiency is higher. The design of the structure that the groove is partially covered by the transparent electrode ensures that current is uniformly and transversely diffused, saves the cost of electrode materials and has the advantages of economy and environmental protection.
The conventional forward-mounted integrated unit light-emitting diode product of 0.5W has the driving current of 150mA and the driving current density of 70A/cm 2 Left and right. In the invention, because the size of each unit is smaller than the diffusion length of current and the ultra-uniform current distribution design is adopted, the driving current of the normally-installed integrated unit LED of 0.5W can be 150A/cm 2 In the above, each led unit can bear a current density more than 2 times that of a conventional front-mounted led product. For example, when the driving current exceeds 150mA, the voltage VF of the normally-mounted LED chip rises sharply due to the non-uniform current diffusion, and the thermal effect is very significant, so that the chip cannot bear the driving of a large current; the driving current of the corresponding light emitting diode chip of the integrated unit can be increased to more than 600mA, and meanwhile, the increase of the contrast voltage VF is small. The integrated unit LEDs can therefore withstand current densities several times higher than the forward mounted LEDs, bringing the advantages of enormous lumen density and lumen cost.
The advantages of the large lumen density and the lumen cost of the integrated unit LED chip are illustrated here with 0.5W LED chips. In addition, the point to be emphasized is that the normally installed LED chip can only be used for 0.5W output products due to the difficulty of current diffusion and heat dissipation. However, the integrated unit light emitting diode product with the same size can drive the current of more than 600mA, and actually reaches the driving power of 2W, so the lumen output of the chip can be more than 4 times of that of a forward-mounted product, and the ultrahigh lumen density output which is not possessed by the forward-mounted medium-small power LED product is realized.
In a preferred embodiment, the length of the current diffusion is in particular the lateral critical current diffusion length;
the transverse critical current diffusion length is a current diffusion length corresponding to an inflection point on a working Voltage (VF) -cell size curve of the light-emitting diode cell. When the threshold value is less than the critical value, the performance of the chip is greatly improved.
As shown in fig. 13, the chip and the diode cells are defined to include dimensions, the length, width, and height of the chip are XYZ, and the cell size is abc. The specific principle is shown in fig. 11, the cell size of 100 μm refers to a conventional LED chip structure in the market, and the cell size refers to the spacing between N-P electrodes: x is 72, 60, 50,40,30 μm. The curves of different colors represent different drive currents. Since the operating voltage of the LED chip is usually required to be VF <3.3V in the market, the conventional LED chip can satisfy the condition only under the driving current of 150 mA. Since VF starts to decrease rapidly below 72 μm as the lateral current diffusion length decreases, we can define 72 μm as the critical lateral current diffusion length in the design, and when it is less than this critical value, the performance of the chip starts to increase dramatically. For example, to a size of 50 microns, the driving current VF is less than 3.3V at 300mA, so the new design can allow driving current exceeding that of the current conventional chip (over driving 100%), thereby greatly improving the lumen density of the chip.
Fig. 12 shows the improved effect of the above arrangement on VF, thereby defining a critical current spreading length, L <72 μm, under which design, due to the reduction of VF, a more energy efficient LED chip can be obtained; due to the reduction of VF, the energy conversion efficiency is improved, and meanwhile, the heat effect is reduced, so that a chip with better stability is obtained; and due to the improvement of the current diffusion uniformity, the chip can bear higher driving current, so that the lumen density of the chip is greatly improved.
Preferably, the dimensions of the mesa structure are specifically selected as follows: the distance between the first conductivity type electrode and the second conductivity type electrode of each of the cells in the direction in which the electrode line extends is as shown in fig. 13.
Preferably, the lateral critical current diffusion length is less than 70 microns.
The high light-extraction-rate integrated unit diode chip provided by the embodiment of the invention has the following beneficial effects:
(1) the length design of the diode unit is controlled within the current diffusion length, the optimized geometric design with certain degree of freedom can further improve the light emitting efficiency, and the problem of uneven current diffusion of an N-type electrode and a P-type electrode which troubles the design of an LED unit diode chip can be solved, so that higher photoelectric conversion efficiency/lumen efficiency is obtained.
(2) The length of the diode unit can be far less than the current diffusion length, so that the thickness of the transparent electrode can be greatly reduced, the absorption of the transparent electrode to light is greatly reduced, and the light extraction efficiency of the chip is improved.
(3) The design of the current blocking layer structure can reduce the current aggregation and light absorption effect and improve the light extraction efficiency of the chip.
(4) The micro-nano structure of each diode unit increases the light emitting area of the side wall, so that the light extraction efficiency is improved.
(5) The size of the integrated unit diode chip is optimized, so that a larger side wall heat dissipation area is brought, the integrated unit diode chip has better heat dissipation performance, injection of super-large current density is allowed without influencing the stability of the integrated unit diode chip, the lumen output of the unit diode chip in unit area is greatly improved, and the lumen cost is reduced.
(6) The design of the integrated unit diode chip can realize ultra-uniform current injection, thereby obtaining higher efficiency, better wavelength uniformity, narrower half-height width of a light-emitting spectrum, better heat dissipation uniformity and better device stability, and the current injection uniformity is far more than about 50 percent of the current injection uniformity of the normal device.
(7) The integrated unit diode chip is suitable for LED products of various color systems such as UVC, UVA, UVB, purple light, blue light, green light, yellow light, red light, infrared light and the like, and can be used in the application fields of LED illumination, backlight, display, plant illumination, medical treatment and other semiconductor light-emitting devices.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (15)

1. A high light extraction rate integrated unit diode chip, comprising: a first conductive type electrode line, a second conductive type electrode line, and a diode mesa structure between the first conductive type electrode line and the second conductive type electrode line, the diode mesa structure comprises n diode units, n is more than or equal to 2, the n diode units are arranged in a row-column array, a first groove is arranged between the diode units arranged in adjacent rows, a second groove is arranged between the diode units arranged in adjacent columns, the first conductive type electrode wire and the second conductive type electrode wire are respectively positioned in the first groove, the first conduction type electrode wire is positioned on the first conduction type layer, the second conduction type electrode wire is positioned on the second conduction type layer, and the distance between the first conduction type electrode wire and the second conduction type electrode wire of each unit in the direction vertical to the extension direction of the electrode wires is determined according to the current diffusion length; the n diode units comprise an insulating medium layer, a transparent electrode and a second conductive type electrode wire, wherein the insulating medium layer is positioned on the first conductive type layer and partially covers the second conductive type layer; the second conductive type electrode wire, the transparent electrode and the second conductive type layer are communicated in the direction vertical to the table top;
the length of current diffusion is specifically the transverse critical current diffusion length; wherein, the transverse critical current diffusion length is the current diffusion length corresponding to the inflection point on the curve of the working Voltage (VF) -cell size of the light-emitting diode cell;
the distance between the first conductive type electrode wire and the second conductive type electrode wire of each unit in the direction perpendicular to the extension direction of the electrode wires is smaller than the transverse critical current diffusion length;
the lateral critical current diffusion length is less than 70 microns.
2. The high extraction integrated unit diode chip of claim 1, wherein said n diode units comprise quantum well active regions; the quantum well active region is located between the first conductivity type layer and the second conductivity type layer.
3. The high extraction efficiency integrated unit diode chip of claim 2, wherein the insulating dielectric layer, the transparent electrode and the second conductive type electrode line are disposed in the first trench.
4. The high extraction efficiency integrated unit diode chip of claim 3, wherein the transparent electrode has a thickness of 60 nm to 120 nm.
5. An integrated unit diode chip with high light extraction efficiency as claimed in claim 4, characterized in that said chip comprises pads of the first conductivity type and pads of the second conductivity type, the electrode lines of the first conductivity type being connected to the pads of the first conductivity type, and the electrode lines of the second conductivity type being connected to the pads of the second conductivity type.
6. The high extraction efficiency integrated unit diode chip of claim 5, wherein the first conductivity type electrode wires and the second conductivity type electrode wires are line type electrode wires; the width of the linear electrode line is 0.001-20 microns, and the thickness is 0.001-10 microns.
7. The high-extraction-efficiency integrated unit diode chip as claimed in claim 6, wherein the insulating dielectric layer is made of silicon dioxide, aluminum oxide or silicon nitride.
8. The high-extraction-efficiency integrated unit diode chip as claimed in claim 7, wherein the diode unit is connected in a manner that: parallel connection, series connection or series-parallel connection mixing with set proportion.
9. The high extraction efficiency integrated unit diode chip of claim 8, wherein the diode unit is shaped as: triangle, square, rectangle, pentagon, hexagon, circle.
10. A high extraction efficiency integrated unit diode chip as claimed in claim 9, wherein the number of said diode units is 2-1000 hundred million.
11. The high extraction efficiency integrated unit diode chip of claim 10, wherein the length of the diode unit in the direction perpendicular to the extension direction of the electrode lines is 0.001 to 200 μm.
12. The high extraction efficiency integrated unit diode chip of claim 11, wherein the non-linear layout comprises a polygonal line layout and a curved line layout.
13. The high-extraction-ratio integrated unit diode chip of claim 12, wherein the linear electrode wires are made of linear metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.
14. A high extraction efficiency integrated unit diode chip as claimed in claim 13, wherein said diode mesa structure comprises a hole structure.
15. The high extraction efficiency integrated unit diode chip of claim 14, wherein the substrate is on a mirror, the mirror is a distributed bragg mirror, and the mirror material is silver or aluminum.
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