CN113035713B - Memory structure and manufacturing method thereof - Google Patents
Memory structure and manufacturing method thereof Download PDFInfo
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- CN113035713B CN113035713B CN201911346306.1A CN201911346306A CN113035713B CN 113035713 B CN113035713 B CN 113035713B CN 201911346306 A CN201911346306 A CN 201911346306A CN 113035713 B CN113035713 B CN 113035713B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 98
- 125000006850 spacer group Chemical group 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 39
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 261
- 239000000758 substrate Substances 0.000 claims description 25
- 239000003989 dielectric material Substances 0.000 claims description 17
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000006073 displacement reaction Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 18
- 230000000873 masking effect Effects 0.000 abstract description 14
- 230000002411 adverse Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000002161 passivation Methods 0.000 description 10
- 230000002829 reductive effect Effects 0.000 description 9
- 238000003860 storage Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 239000013256 coordination polymer Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention provides a manufacturing method of a memory structure, which comprises the following steps. A spacer layer is formed on sidewalls of the gate stack. Forming a protective material layer covering the spacer layer and the gate stack. A masking material layer is formed on the protective material layer. The mask material layer has a hole between two adjacent gate stacks. The first distance between the top of the protective material layer and the top of the masking material layer directly above the gate stack is greater than the sum of the second distance between the top of the hole and the top of the masking material layer directly above the hole and the third distance between the bottom of the hole and the bottom of the masking material layer directly below the hole. An etching process is performed on the mask material layer to form a plurality of first mask layers separated from each other. The manufacturing method of the memory structure can effectively reduce the adverse effect of ions on the memory operation.
Description
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a memory structure and a method for fabricating the same.
Background
Nonvolatile memory devices (e.g., flash memory devices) have become one of the dominant technologies for storage media in recent years. However, in the manufacturing process of the nonvolatile memory device, some ions are inevitably generated, and these ions adversely affect the memory operation, thereby reducing the reliability of the memory device.
Disclosure of Invention
The invention provides a memory structure and a manufacturing method thereof, which can effectively reduce adverse effects of ions on memory operation.
The invention provides a manufacturing method of a memory structure, which comprises the following steps. A plurality of gate stack structures are formed on a substrate. A spacer layer is formed on sidewalls of the gate stack. The spacer layer is connected between two adjacent gate stack structures. Forming a protective material layer covering the spacer layer and the gate stack. A masking material layer is formed on the protective material layer. The mask material layer has a hole between two adjacent gate stacks. The first distance between the top of the protective material layer and the top of the masking material layer directly above the gate stack is greater than the sum of the second distance between the top of the hole and the top of the masking material layer directly above the hole and the third distance between the bottom of the hole and the bottom of the masking material layer directly below the hole. An etching process is performed on the mask material layer to form a plurality of first mask layers separated from each other. The first mask layer covers the protective material layer on the gate stack structures and exposes a portion of the protective material layer between the bottoms of two adjacent gate stack structures. And removing part of the protective material layer exposed by the first mask layer to form a plurality of protective layers separated from each other.
The invention provides a memory structure, which comprises a substrate, a grid stacking structure, a gap wall and a protective layer. The gate stack structure is disposed on the substrate. The spacer is disposed on the sidewall of the gate stack. The spacer has a stepped structure adjacent to the substrate. The stair-step structure includes a first step and a second step connected to each other. The first step is located between the gate stack and the second step. The first step is higher than the second step and lower than the top of the spacer. The protection layer covers the gate stack structure and the spacer.
In view of the above, in the method for manufacturing a memory structure according to the present invention, the protection layer covers the spacer layer and the gate stack structure, so that ions can be blocked from entering the spacer layer and the gate stack structure by the protection layer. Therefore, adverse effects caused by ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved. In addition, the mask material layer has a hole between two adjacent gate stack structures, and a first distance between a top of the protective material layer and a top of the mask material layer directly above the gate stack structures is greater than a sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between a bottom of the hole and a bottom of the mask material layer directly below the hole. In this way, in the etching process of the mask material layer, a plurality of first mask layers separated from each other can be formed by a self-aligned manner, so that the complexity and the cost of the process can be reduced.
In addition, in the memory structure according to the present invention, since the passivation layer covers the spacer and the gate stack structure, ions can be blocked from entering the spacer and the gate stack structure by the passivation layer. In addition, the protective layer only exposes the side wall of the second step with lower height in the step structure of the spacer, so that the channel of ions entering the spacer can be effectively reduced, and the quantity of ions entering the spacer can be further reduced. Therefore, adverse effects caused by ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1L are cross-sectional views illustrating a manufacturing process of a memory structure according to an embodiment of the invention.
Reference numerals illustrate:
10: memory structure
100: substrate
102: gate stack structure
104: charge storage layer
106: grid electrode
108. 110, 122a, 122b: dielectric layer
112: conductor layer
114. 114a, 114b: top cover layer
116: spacer material layer
116a: spacer layer
116b: spacer wall
118: protective material layer
118a: protective layer
120: mask material cover
120a: curtain layer
122: dielectric material layer
124: amorphous silicon layer
124a, 126: polysilicon layer
128: replacement layer
130: mask layer
132: contact window
CP: central portion
D1, D2, D3: distance of
OP1, OP2: an opening
S1: first order of
S2: second order
SP: side portion
SS: ladder structure
V1: holes and holes
Detailed Description
Referring to fig. 1A, a plurality of gate stack structures 102 are formed on a substrate 100. The substrate 100 is, for example, a semiconductor substrate such as a silicon substrate. The gate stack 102 may include a charge storage layer 104 and a gate 106 isolated from each other. The charge storage layer 104 is located between the gate 106 and the substrate 100. The charge storage layer 104 may be a floating gate (floating gate) or a charge trapping layer (charge trapping layer). The material of the floating gate is, for example, doped polysilicon or undoped polysilicon. The material of the charge trapping layer is, for example, silicon nitride. In the present embodiment, the charge storage layer 104 is illustrated as a floating gate, but the invention is not limited thereto. Further, there may be an opening OP1 between two adjacent gate stack structures 102.
In addition, the gate stack 102 may further include at least one of a dielectric layer 108, a dielectric layer 110, a conductor layer 112, and a cap layer 114. A dielectric layer 108 is located between the charge storage layer 104 and the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. Dielectric layer 110 is located between gate 106 and charge storage layer 104, whereby charge storage layer 104 and gate 106 may be isolated from each other. The material of the dielectric layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. In the present embodiment, the dielectric layer 110 is exemplified by a composite layer of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO), but the invention is not limited thereto. A conductor layer 112 is located on the gate 106. The material of the conductor layer 112 is, for example, metal (e.g., tungsten) or metal silicide (e.g., cobalt silicide or nickel silicide). A cap layer 114 is located on the conductor layer 112. The cap layer 114 may be a single layer structure or a multi-layer structure. In the present embodiment, the capping layer 114 is illustrated as a multi-layer structure. For example, the cap layer 114 may include a cap layer 114a and a cap layer 114b. The capping layer 114a is located between the capping layer 114b and the conductor layer 112. The material of the cap layer 114a is, for example, silicon nitride. The material of the cap layer 114b is, for example, silicon oxide.
In addition, the gate stack 102 may be formed by a deposition process and a patterning process, but the invention is not limited thereto.
Next, a spacer material layer 116 is formed overlying the gate stack 102. The material of the spacer material layer 116 is, for example, an oxide material such as silicon oxide. The spacer material layer 116 is formed by thermal oxidation or chemical vapor deposition.
Referring to fig. 1B, an etching process (e.g., a dry etching process) is performed on the spacer material layer 116, and a spacer layer 116a is formed on the sidewalls of the gate stack structures 102, wherein the spacer layer 116a is connected between two adjacent gate stack structures 102. The spacer layer 116a may expose the top of the gate stack 102. In some embodiments, during the dry etching process, polymer may accumulate at corners of the spacer material layer 116 adjacent to the substrate 100, whereby the spacer layer 116a may have a stepped structure SS adjacent to the substrate 100. The step structure SS may include a first step S1 and a second step S2 connected to each other. The first step S1 is located between the gate stack 102 and the second step S2. The first level S1 may be higher than the second level S2 and may be lower than the top of the spacer layer 116a. The connection surface between the first step S1 and the second step S2 may include a vertical surface, an inclined surface or a curved surface. In the present embodiment, the connection surface between the first step S1 and the second step S2 is described by taking a vertical surface as an example. In addition, although the method of forming the spacer layer 116a is exemplified by the above method, the present invention is not limited thereto.
Referring to fig. 1C, a protective material layer 118 is formed to cover the spacer layer 116a and the gate stack 102. The material of the protective material layer 118 is, for example, a nitride material such as silicon nitride. The protective material layer 118 is formed by, for example, chemical vapor deposition.
Referring to fig. 1D, a masking material layer 120 is formed on the protective material layer 118. The masking material layer 120 has a hole V1 between two adjacent gate stacks 102. The distance D1 between the top of the protective material layer 118 and the top of the masking material layer 120 directly above the gate stack 102 is greater than the sum of the distance D2 between the top of the hole V1 and the top of the masking material layer 120 directly above the hole V1 and the distance D3 between the bottom of the hole V1 and the bottom of the masking material layer 120 directly below the hole V1. The material of the mask material layer 120 is, for example, an oxide material such as silicon oxide. The mask material layer 120 is formed by chemical vapor deposition, for example.
Referring to fig. 1E, an etching process (e.g., a dry etching process) is performed on the mask material layer 120 to form a plurality of mask layers 120a separated from each other. The mask layer 120a covers the protective material layer 118 on the gate stack 102 and exposes a portion of the protective material layer 118 between the bottoms of two adjacent gate stacks 102. Since the distance D1 is greater than the sum of the distance D2 and the distance D3 (fig. 1D), the mask layers 120a separated from each other can be formed by self-alignment during the dry etching process of the mask material layer 120, so as to reduce the process complexity and the manufacturing cost.
Referring to fig. 1F, a portion of the protective material layer 118 exposed by the mask layer 120a is removed, so as to form protective layers 118a separated from each other. The passivation layer 118a may cover the top surface of the gate stack 102 and the spacer layer 116a on the sidewalls of the gate stack 102. In addition, the passivation layer 118a may expose a portion of the spacer layer 116a between two adjacent gate stack structures 102. The method of removing a portion of the protective material layer 118 is, for example, dry etching.
In some embodiments, the mask layer 120a may be removed after removing a portion of the protective material layer 118. For example, during the removal of a portion of the protective material layer 118, a portion of the mask layer 120a may be consumed. Next, after removing a portion of the protective material layer 118, the mask layer 120a may be removed by a subsequent cleaning process. In some embodiments, the mask layer 120a may be removed simultaneously during the removal of a portion of the protective material layer 118.
Referring to fig. 1G, a dielectric material layer 122 covering the passivation layer 118a and the spacer layer 116a may be formed. The material of the dielectric material layer 122 is, for example, an oxide material such as silicon oxide. The dielectric material layer 122 is formed by chemical vapor deposition, for example.
An amorphous silicon layer 124 may then be formed on the dielectric material layer 122. The amorphous silicon layer 124 is formed by, for example, chemical vapor deposition.
Referring to fig. 1H, an annealing process may be performed on the amorphous silicon layer 124 to form a polysilicon layer 124a. The polysilicon layer 124a may be used as a seed layer (seed layer).
Then, a polysilicon layer 126 may be deposited on the polysilicon layer 124a. The material of the polysilicon layer 126 may be doped polysilicon or undoped polysilicon. In the case where the material of the polysilicon layer 126 is doped polysilicon, the polysilicon layer 126 may have a better hole filling capability.
Thereby, the displacement layer 128 may be formed on the dielectric material layer 122. The replacement layer 128 may include the polysilicon layer 124a and the polysilicon layer 126. The displacement layer 128 fills the opening OP1 between two adjacent gate stack structures 102. In the case of forming the replacement layer 128 by the above method, the replacement layer 128 may have a better hole filling capability, but the material and the forming method of the replacement layer 128 are not limited thereto. In the present embodiment, the replacement layer 128 is exemplified by a two-layer structure, but the invention is not limited thereto. In other embodiments, the displacing layer 128 may be a single layer structure or a structure with more than three layers.
Referring to fig. 1I, a portion of the replacement layer 128 above the top surface of the gate stack 102 may be removed to form a plurality of openings OP2 exposing a portion of the dielectric material layer 122. The opening OP2 is formed by patterning the exchange layer 128, for example, by photolithography and etching Cheng Duizhi. In addition, during the process of forming the opening OP2, a portion of the dielectric material layer 122 may be removed.
Referring to fig. 1J, a mask layer 130 may be formed in the opening OP2. The material of the mask layer 130 is, for example, a nitride material such as silicon nitride. The method for forming the mask layer 130 may include the following steps, but the invention is not limited thereto. First, a layer of masking material (not shown) may be formed to fill the opening OP2 by a deposition process. Then, the mask material layer outside the opening OP2 may be removed by chemical mechanical polishing to form the mask layer 130.
Referring to fig. 1K, the replacement layer 128 may be removed. The removing method for removing the replacement layer 128 is, for example, wet etching or dry etching.
Next, the mask layer 130 may be used as a mask to remove a portion of the dielectric material layer 122 and a portion of the spacer layer 116a between the bottoms of two adjacent gate stack structures 102, thereby forming a spacer 116b on the sidewall of each gate stack structure 102 and exposing the substrate 100. The partial dielectric material layer 122 and the partial spacer layer 116a are removed by, for example, wet etching or dry etching. In some embodiments, during the step of forming the spacers 116b, a portion of the mask layer 130 may be consumed, such that the cross-sectional shape of the mask layer 130 approximates a rounded triangle with two curved sides.
In addition, in the step of forming the spacers 116b, a portion of the dielectric material layer 122 located between the tops of the adjacent two gate stack structures 102 may be removed, and a dielectric layer 122a and a dielectric layer 122b may be formed over the top and side surfaces of each gate stack structure 102, respectively, and the dielectric layer 122a and the dielectric layer 122b may be separated from each other. The dielectric layer 122a may include a central portion CP and two side portions SP connected to both sides of the central portion CP. The thickness of the two side portions SP may be greater than the thickness of the center portion CP. As such, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape.
In addition, since a portion of the dielectric material layer 122 and a portion of the spacer layer 116a are removed by using the mask layer 130 as a mask, the spacers 116b, the dielectric layer 122a and the dielectric layer 122b can be formed by self-aligned method, so as to reduce the complexity and the cost of the process.
Referring to fig. 1L, a contact 132 may be formed in the opening OP1 between two adjacent gate stacks 102. The contact 132 may be connected to the substrate 100. The material of the contact 132 is, for example, tungsten or other metal. The method for forming the contact 132 may include the following steps, but the invention is not limited thereto. First, a contact material layer (not shown) filling the opening OP1 may be formed through a deposition process. Then, the contact window 132 may be formed by removing the contact window material layer outside the opening OP1 through a chemical mechanical polishing process. In the chemical mechanical polishing process, a portion of the mask layer 130 may be removed, so that the cross-sectional shape of the mask layer 130 is a trapezoid with two curved sides.
In addition, in the above method for manufacturing the memory structure 10, a desired doped region (not shown) may be formed in the substrate 100 according to the requirement. The formation of the desired doped regions in the substrate 100 is not described herein, as it is a technique well known to those skilled in the art.
As can be seen from the above embodiments, in the method 10 for manufacturing a memory structure, the protection layer 118a covers the spacer layer 116a and the gate stack structure 102, so that the protection layer 118a can block ions from entering the spacer layer 116a and the gate stack structure 102. Therefore, adverse effects caused by ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved. In addition, the mask material layer 120 has a hole V1 between two adjacent gate stacks 102, and the distance D1 is greater than the sum of the distance D2 and the distance D3 (fig. 1D). In this way, in the dry etching process performed on the mask material layer 120, a plurality of mask layers 120a (fig. 1E) separated from each other can be formed by self-alignment, so as to reduce the complexity and cost of the process.
The memory structure 10 of the present embodiment is described below with reference to fig. 1L. In addition, although the method of forming the memory structure 10 is described above as an example, the present invention is not limited thereto.
Referring to fig. 1L, the memory structure 10 includes a substrate 100, a gate stack 102, a spacer 116b and a passivation layer 118a. In the present embodiment, the memory structure 10 may be a NOR flash memory (flash memory), but the invention is not limited thereto. The gate stack 102 is disposed on the substrate 100. The details of the gate stack 102 are described in the above embodiments, and are not described here. Spacers 116b are disposed on sidewalls of the gate stack 102. The spacer 116b has a stepped structure SS adjacent to the substrate 100. The step structure SS includes a first step S1 and a second step S2 connected to each other. The first step S1 is located between the gate stack 102 and the second step S2. The first step S1 is higher than the second step S2 and lower than the top of the spacer 116 b. The connection surface between the first step S1 and the second step S2 may include a vertical surface, an inclined surface or a curved surface. Spacers 116b may expose the top surface of gate stack 102. The passivation layer 118a covers the gate stack 102 and the spacer 116b, and exposes the sidewall of the second step S2. The protective layer 118a may cover the top surface of the gate stack 102.
In addition, the memory structure 10 may further include at least one of a dielectric layer 122a, a dielectric layer 122b, a mask layer 130 and a contact 132. A dielectric layer 122a is disposed on the protective layer 118a over the top surface of the gate stack 102. A dielectric layer 122b is disposed on the protective layer 118a over the sides of the gate stack 102. The dielectric layer 122a and the dielectric layer 122b may be separated from each other. The dielectric layer 122a may include a central portion CP and two side portions SP connected to both sides of the central portion CP. The thickness of the two side portions SP may be greater than the thickness of the center portion CP. As such, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape. The mask layer 130 is disposed on the dielectric layer 122 a. The cross-sectional shape of the mask layer 130 is, for example, a trapezoid with two curved sides, but the invention is not limited thereto. The contact 132 is disposed on the substrate 100 at one side of the gate stack 102. The contact 132 and the gate stack 102 may be isolated from each other. The contact may be connected to the substrate 100.
In addition, the materials, forming methods and functions of the components in the memory structure 10 are described in detail in the above embodiments, and will not be repeated here.
As can be seen from the above embodiments, in the memory structure 10, since the passivation layer 118a covers the spacer 116b and the gate stack 102, ions can be blocked from entering the spacer 116b and the gate stack 102 by the passivation layer 118a. In addition, since the passivation layer 118a only exposes the sidewall of the second step S2 with a lower height in the step structure SS of the spacer 116b, the channel of the ions into the spacer 116b can be effectively reduced, thereby reducing the number of ions entering the spacer 116 b. Therefore, adverse effects caused by ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved.
In summary, in the memory structure and the method for manufacturing the same in the above embodiments, the protection layer can block ions, so that adverse effects of ions on the memory operation can be effectively reduced, and the reliability of the memory device can be improved.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and practiced by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (6)
1. A method of manufacturing a memory structure, comprising:
forming a plurality of gate stack structures on a substrate;
forming a spacer layer on sidewalls of the plurality of gate stack structures, wherein the spacer layer is connected between two adjacent gate stack structures;
forming a protective material layer covering the spacer layer and the gate stack structures;
forming a mask material layer on the protective material layer, wherein the mask material layer has a hole between two adjacent gate stack structures, and a first distance between a top of the protective material layer and a top of the mask material layer directly above the plurality of gate stack structures is greater than a sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between a bottom of the hole and a bottom of the mask material layer directly below the hole;
etching the mask material layer to form a plurality of first mask layers which are separated from each other, wherein the plurality of first mask layers cover the protection material layers on the plurality of gate stack structures and expose a part of the protection material layers between the bottoms of two adjacent gate stack structures; and
and removing part of the protective material layer exposed by the first mask layers to form a plurality of protective layers separated from each other.
2. The method of claim 1, wherein the spacer layer has a stair-step structure adjacent to the substrate, the stair-step structure comprising first and second steps connected to each other, the first step being between the gate stack and the second step, and the first step being higher than the second step and lower than a top of the spacer layer.
3. The method of claim 1, wherein the plurality of first mask layers are removed after or during removing portions of the protective material layer.
4. The method of manufacturing a memory structure of claim 1, further comprising:
forming a dielectric material layer covering the plurality of protection layers and the spacer layer;
forming a replacement layer on the dielectric material layer, wherein the replacement layer fills a first opening between two adjacent gate stack structures;
removing a portion of the replacement layer above top surfaces of the plurality of gate stack structures to form a plurality of second openings exposing a portion of the dielectric material layer; and
a plurality of second mask layers are formed in the plurality of second openings.
5. The method of manufacturing a memory structure of claim 4, further comprising:
removing the displacement layer; and
and removing part of the dielectric material layer and part of the gap wall layer which are positioned between the bottoms of the two adjacent grid stacking structures by using the second mask layers as masks, forming gap walls on the side walls of each grid stacking structure, and exposing the substrate.
6. The method of claim 5, wherein in forming the spacers, portions of the dielectric material layer between tops of two adjacent gate stack structures are removed, and a first dielectric layer and a second dielectric layer are formed over top and side surfaces of each gate stack structure, respectively, and the first dielectric layer and the second dielectric layer are separated from each other.
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| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| KR20060104025A (en) * | 2005-03-29 | 2006-10-09 | 매그나칩 반도체 유한회사 | Method for manufacturing a non-volatile memory device |
| US7375392B1 (en) * | 2001-08-10 | 2008-05-20 | Integrated Device Technology, Inc. | Gate structures having sidewall spacers formed using selective deposition |
| JP2010147410A (en) * | 2008-12-22 | 2010-07-01 | Toshiba Corp | Nonvolatile semiconductor memory device and method of manufacturing the same |
| CN103515216A (en) * | 2012-06-27 | 2014-01-15 | 力晶科技股份有限公司 | Method for manufacturing semiconductor element |
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| US8664102B2 (en) * | 2010-03-31 | 2014-03-04 | Tokyo Electron Limited | Dual sidewall spacer for seam protection of a patterned structure |
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| US7375392B1 (en) * | 2001-08-10 | 2008-05-20 | Integrated Device Technology, Inc. | Gate structures having sidewall spacers formed using selective deposition |
| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| KR20060104025A (en) * | 2005-03-29 | 2006-10-09 | 매그나칩 반도체 유한회사 | Method for manufacturing a non-volatile memory device |
| JP2010147410A (en) * | 2008-12-22 | 2010-07-01 | Toshiba Corp | Nonvolatile semiconductor memory device and method of manufacturing the same |
| CN103515216A (en) * | 2012-06-27 | 2014-01-15 | 力晶科技股份有限公司 | Method for manufacturing semiconductor element |
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