CN113035713A - Memory structure and manufacturing method thereof - Google Patents

Memory structure and manufacturing method thereof Download PDF

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Publication number
CN113035713A
CN113035713A CN201911346306.1A CN201911346306A CN113035713A CN 113035713 A CN113035713 A CN 113035713A CN 201911346306 A CN201911346306 A CN 201911346306A CN 113035713 A CN113035713 A CN 113035713A
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Prior art keywords
layer
gate stack
material layer
spacer
mask
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CN201911346306.1A
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CN113035713B (en
Inventor
许哲睿
吕俊昇
童盈辅
廖振伟
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN201911346306.1A priority Critical patent/CN113035713B/en
Priority to CN202311252467.0A priority patent/CN117080270A/en
Publication of CN113035713A publication Critical patent/CN113035713A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

The invention provides a manufacturing method of a memory structure, which comprises the following steps. A spacer layer is formed on sidewalls of the gate stack structure. And forming a protective material layer covering the spacer layer and the gate stack structure. A masking material layer is formed on the protective material layer. The masking material layer has a hole between two adjacent gate stacks. A first distance between the top of the protective material layer directly above the gate stack and the top of the mask material layer is greater than a sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole. An etching process is performed on the mask material layer to form a plurality of first mask layers separated from each other. The manufacturing method of the memory structure can effectively reduce the adverse effect of ions on the operation of the memory.

Description

Memory structure and manufacturing method thereof
Technical Field
The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to a memory structure and a method of fabricating the same.
Background
Non-volatile memory devices (e.g., flash memory devices) have become one of the mainstream technologies for storage media in recent years. However, in the fabrication of the non-volatile memory device, some ions are inevitably generated and adversely affect the memory operation, thereby reducing the reliability of the memory device.
Disclosure of Invention
The invention provides a memory structure and a manufacturing method thereof, which can effectively reduce the adverse effect of ions on the operation of a memory.
The invention provides a manufacturing method of a memory structure, which comprises the following steps. A plurality of gate stack structures are formed on a substrate. A spacer layer is formed on sidewalls of the gate stack structure. The spacer layer is connected between two adjacent gate stack structures. And forming a protective material layer covering the spacer layer and the gate stack structure. A masking material layer is formed on the protective material layer. The masking material layer has a hole between two adjacent gate stacks. A first distance between the top of the protective material layer directly above the gate stack and the top of the mask material layer is greater than a sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole. An etching process is performed on the mask material layer to form a plurality of first mask layers separated from each other. The first mask layer covers the protective material layer on the gate stack structures and exposes a part of the protective material layer between the bottoms of two adjacent gate stack structures. Removing the exposed portion of the protective material layer to form a plurality of protective layers separated from each other.
The invention provides a memory structure, which comprises a substrate, a gate stack structure, a spacer and a protective layer. The gate stack structure is disposed on the substrate. The spacer is disposed on a sidewall of the gate stack structure. The spacer has a stepped structure adjacent to the substrate. The stepped structure includes a first step and a second step connected to each other. The first level is located between the gate stack structure and the second level. The first step is higher than the second step and lower than the top of the spacer. The protective layer covers the gate stack structure and the spacer.
In view of the above, in the method for manufacturing a memory structure provided by the present invention, since the protection layer covers the spacer layer and the gate stack structure, ions can be blocked from entering the spacer layer and the gate stack structure by the protection layer. Therefore, the adverse effect of ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved. In addition, the mask material layer has a hole between two adjacent gate stack structures, and a first distance between the top of the protection material layer directly above the gate stack structures and the top of the mask material layer is greater than a sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole. Therefore, in the etching process of the mask material layer, a plurality of first mask layers separated from each other can be formed in a self-aligned manner, and the process complexity and the manufacturing cost can be further reduced.
In addition, in the memory structure provided by the invention, since the protective layer covers the spacer and the gate stack structure, ions can be blocked from entering the spacer and the gate stack structure through the protective layer. In addition, the protective layer only exposes the side wall of the second step with lower height in the stepped structure of the gap wall, so that the channel of ions entering the gap wall can be effectively reduced, and the quantity of the ions entering the gap wall is further reduced. Therefore, the adverse effect of ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1L are cross-sectional views illustrating a manufacturing process of a memory structure according to an embodiment of the invention.
The reference numbers illustrate:
10: memory structure
100: substrate
102: gate stack structure
104: charge storage layer
106: grid electrode
108. 110, 122a, 122 b: dielectric layer
112: conductive layer
114. 114a, 114 b: top cover layer
116: spacer material layer
116 a: spacer layer
116 b: spacer wall
118: layer of protective material
118 a: protective layer
120: mask material cover
120 a: curtain layer
122: dielectric material layer
124: amorphous silicon layer
124a, 126: polycrystalline silicon layer
128: replacement layer
130: mask layer
132: contact window
And (3) CP: center part
D1, D2, D3: distance between two adjacent plates
OP1, OP 2: opening of the container
S1: first order
S2: second stage
SP: side part
And SS: step structure
V1: hole(s)
Detailed Description
Referring to fig. 1A, a plurality of gate stack structures 102 are formed on a substrate 100. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. The gate stack structure 102 may include a charge storage layer 104 and a gate 106 isolated from each other. The charge storage layer 104 is located between the gate 106 and the substrate 100. The charge storage layer 104 may be a floating gate (floating gate) or a charge trapping layer (charge trapping layer). The material of the floating gate is, for example, doped polysilicon or undoped polysilicon. The material of the charge trapping layer is, for example, silicon nitride. In the present embodiment, the charge storage layer 104 is illustrated as a floating gate, but the invention is not limited thereto. In addition, there may be an opening OP1 between two adjacent gate stack structures 102.
In addition, the gate stack structure 102 may further include at least one of a dielectric layer 108, a dielectric layer 110, a conductive layer 112 and a cap layer 114. The dielectric layer 108 is located between the charge storage layer 104 and the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. A dielectric layer 110 is located between the gate 106 and the charge storage layer 104, whereby the charge storage layer 104 and the gate 106 may be isolated from each other. The material of the dielectric layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. In the present embodiment, the dielectric layer 110 is a composite layer of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO), but the invention is not limited thereto. A conductor layer 112 is located on the gate 106. The material of the conductive layer 112 is, for example, metal (e.g., tungsten) or metal silicide (e.g., cobalt silicide or nickel silicide). A cap layer 114 is located on the conductive layer 112. Cap layer 114 may be a single layer structure or a multi-layer structure. In the present embodiment, the cap layer 114 is illustrated as a multi-layer structure. For example, cap layer 114 may include cap layer 114a and cap layer 114 b. Capping layer 114a is located between capping layer 114b and conductive layer 112. The material of the cap layer 114a is, for example, silicon nitride. The material of the cap layer 114b is, for example, silicon oxide.
In addition, the gate stack structure 102 may be formed by a deposition process and a patterning process, but the invention is not limited thereto.
Next, a spacer material layer 116 is formed to cover the gate stack structure 102. The material of the spacer material layer 116 is, for example, an oxide material such as silicon oxide. The spacer material layer 116 is formed by a thermal oxidation method or a chemical vapor deposition method.
Referring to fig. 1B, an etching process (e.g., a dry etching process) is performed on the spacer material layer 116 to form a spacer layer 116a on the sidewalls of the gate stack structures 102, wherein the spacer layer 116a is connected between two adjacent gate stack structures 102. The spacer layer 116a may expose the top of the gate stack structure 102. In some embodiments, during the dry etching process, polymer may accumulate at the corners of the spacer material layer 116 adjacent to the substrate 100, so that the spacer layer 116a may have a step structure SS adjacent to the substrate 100. The step structure SS may include a first step S1 and a second step S2 connected to each other. The first level S1 is located between the gate stack structure 102 and the second level S2. The first step S1 may be higher than the second step S2 and may be lower than the top of the spacer layer 116 a. The connection surface between the first step S1 and the second step S2 may include a vertical surface, an inclined surface, or a curved surface. In the present embodiment, the connection surface between the first step S1 and the second step S2 is a vertical surface. In addition, although the method for forming the spacer layer 116a is described above as an example, the invention is not limited thereto.
Referring to fig. 1C, a protective material layer 118 is formed to cover the spacer layer 116a and the gate stack structure 102. The material of the protective material layer 118 is, for example, a nitride material such as silicon nitride. The protective material layer 118 is formed by, for example, chemical vapor deposition.
Referring to fig. 1D, a mask material layer 120 is formed on the protection material layer 118. The masking material layer 120 has a hole V1 between two adjacent gate stacks 102. The distance D1 between the top of the protection material layer 118 and the top of the mask material layer 120 directly above the gate stack 102 is greater than the sum of the distance D2 between the top of the hole V1 and the top of the mask material layer 120 directly above the hole V1 and the distance D3 between the bottom of the hole V1 and the bottom of the mask material layer 120 directly below the hole V1. The material of the masking material layer 120 is, for example, an oxide material such as silicon oxide. The masking material layer 120 is formed by a chemical vapor deposition method, for example.
Referring to fig. 1E, an etching process (e.g., a dry etching process) is performed on the mask material layer 120 to form a plurality of mask layers 120a separated from each other. The mask layer 120a covers the protective material layer 118 on the gate stack structures 102 and exposes a portion of the protective material layer 118 between the bottoms of two adjacent gate stack structures 102. Since the distance D1 is greater than the sum of the distance D2 and the distance D3 (fig. 1D), the mask layers 120a can be formed in a self-aligned manner during the dry etching process performed on the mask material layer 120, thereby reducing the process complexity and the manufacturing cost.
Referring to fig. 1F, a portion of the protective material layer 118 exposed by the mask layer 120a is removed to form a protective layer 118a separated from each other. The protection layer 118a may cover the top surface of the gate stack structure 102 and the spacer layer 116a on the sidewall of the gate stack structure 102. In addition, the passivation layer 118a may expose a portion of the spacer layer 116a between two adjacent gate stack structures 102. The method for removing the portion of the protective material layer 118 is, for example, a dry etching method.
In some embodiments, the mask layer 120a may be removed after removing a portion of the protective material layer 118. For example, during the process of removing a portion of the protective material layer 118, a portion of the mask layer 120a may be consumed. Then, after removing a portion of the protective material layer 118, the mask layer 120a may be removed by a cleaning process performed subsequently. In some embodiments, the mask layer 120a may be removed simultaneously during the removal of the portion of the protective material layer 118.
Referring to fig. 1G, a dielectric material layer 122 may be formed to cover the passivation layer 118a and the spacer layer 116 a. The material of the dielectric material layer 122 is, for example, an oxide material such as silicon oxide. The dielectric material layer 122 is formed by a chemical vapor deposition method, for example.
Next, an amorphous silicon layer 124 may be formed on the dielectric material layer 122. The amorphous silicon layer 124 is formed by, for example, chemical vapor deposition.
Referring to fig. 1H, an annealing process may be performed on the amorphous silicon layer 124 to form a polysilicon layer 124 a. The polysilicon layer 124a may be used as a seed layer.
A polysilicon layer 126 may then be deposited over polysilicon layer 124 a. The material of the polysilicon layer 126 may be doped polysilicon or undoped polysilicon. In the case where the material of the polysilicon layer 126 is doped polysilicon, the polysilicon layer 126 may have better hole-filling capability.
Thereby, a displacement layer 128 may be formed on the dielectric material layer 122. The displacement layer 128 may include a polysilicon layer 124a and a polysilicon layer 126. The replacement layer 128 fills the opening OP1 between two adjacent gate stack structures 102. In the case of forming the replacement layer 128 by the above method, the replacement layer 128 may have a better hole filling capability, but the material and the forming method of the replacement layer 128 of the present invention are not limited thereto. In the embodiment, the replacement layer 128 is a two-layer structure, but the invention is not limited thereto. In other embodiments, the displacement layer 128 may have a single-layer structure or a structure with more than three layers.
Referring to fig. 1I, a portion of the replacement layer 128 above the top surface of the gate stack 102 may be removed to form a plurality of openings OP2 exposing a portion of the dielectric material layer 122. The opening OP2 is formed by patterning the displacement layer 128 by, for example, a photolithography process and an etching process. In addition, in the process of forming the opening OP2, a portion of the dielectric material layer 122 may be removed.
Referring to fig. 1J, a mask layer 130 may be formed in the opening OP 2. The material of the mask layer 130 is, for example, a nitride material such as silicon nitride. The method for forming the mask layer 130 may include the following steps, but the invention is not limited thereto. First, a mask material layer (not shown) filling the opening OP2 may be formed by a deposition process. Then, the mask layer 130 may be formed by removing the mask material layer outside the opening OP2 by chemical mechanical polishing.
Referring to fig. 1K, the replacement layer 128 may be removed. The replacement layer 128 is removed by, for example, wet etching or dry etching.
Next, a portion of the dielectric material layer 122 and a portion of the spacer layer 116a between the bottoms of two adjacent gate stack structures 102 are removed by using the mask layer 130 as a mask, so as to form a spacer 116b on the sidewall of each gate stack structure 102 and expose the substrate 100. The dielectric material layer 122 and the spacer 116a are removed by a wet etching method or a dry etching method. In some embodiments, during the step of forming the spacers 116b, a portion of the mask layer 130 may be consumed, such that the cross-sectional shape of the mask layer 130 approximates to a rounded triangle with two curved sides.
In addition, in the step of forming the spacers 116b, a portion of the dielectric material layer 122 between the tops of two adjacent gate stack structures 102 may be removed, and a dielectric layer 122a and a dielectric layer 122b may be formed over the top surface and the side surface of each gate stack structure 102, respectively, and the dielectric layer 122a and the dielectric layer 122b may be separated from each other. The dielectric layer 122a may include a central portion CP and two side portions SP connected to both sides of the central portion CP. The thickness of the two side portions SP may be greater than that of the central portion CP. As such, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape.
In addition, since a portion of the dielectric material layer 122 and a portion of the spacer layer 116a are removed by using the mask layer 130 as a mask, the spacers 116b, the dielectric layer 122a and the dielectric layer 122b can be formed in a self-aligned manner, thereby reducing the process complexity and the manufacturing cost.
Referring to fig. 1L, a contact 132 may be formed in the opening OP1 between two adjacent gate stack structures 102. The contact 132 may be connected to the substrate 100. The material of the contact 132 is, for example, a metal such as tungsten. The method for forming the contact 132 may include the following steps, but the invention is not limited thereto. First, a contact material layer (not shown) filling the opening OP1 may be formed by a deposition process. The contact 132 may then be formed by removing the contact material layer outside the opening OP1 by a chemical mechanical polishing process. In the chemical mechanical polishing process, a portion of the mask layer 130 may be removed, so that the cross-sectional shape of the mask layer 130 is a trapezoid with two arc-shaped sides.
In addition, in the manufacturing method of the memory structure 10, a desired doped region (not shown) may be formed in the substrate 100 according to requirements. Since the formation of the desired doped regions in the substrate 100 is well known to those skilled in the art, it will not be described herein.
Based on the above embodiments, in the method 10 for manufacturing a memory structure, since the protection layer 118a covers the spacer layer 116a and the gate stack structure 102, ions can be blocked from entering the spacer layer 116a and the gate stack structure 102 by the protection layer 118 a. Therefore, the adverse effect of ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved. In addition, the masking material layer 120 has a hole V1 between two adjacent gate stack structures 102, and the distance D1 is greater than the sum of the distances D2 and D3 (fig. 1D). Thus, in the dry etching process performed on the mask material layer 120, a plurality of mask layers 120a (fig. 1E) separated from each other can be formed in a self-aligned manner, thereby reducing the process complexity and the manufacturing cost.
Hereinafter, the memory structure 10 of the present embodiment will be described with reference to fig. 1L. In addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the invention is not limited thereto.
Referring to fig. 1L, the memory structure 10 includes a substrate 100, a gate stack structure 102, a spacer 116b and a protection layer 118 a. In the present embodiment, the memory structure 10 can be an NOR flash memory (NOR flash memory), but the invention is not limited thereto. The gate stack structure 102 is disposed on the substrate 100. The details of the gate stack structure 102 are already described in the above embodiments and will not be described herein. Spacers 116b are disposed on sidewalls of the gate stack structure 102. The spacer 116b has a step structure SS adjacent to the substrate 100. The step structure SS includes a first step S1 and a second step S2 connected to each other. The first level S1 is located between the gate stack structure 102 and the second level S2. The first step S1 is higher than the second step S2 and lower than the top of the spacer 116 b. The connection surface between the first step S1 and the second step S2 may include a vertical surface, an inclined surface, or a curved surface. The spacers 116b may expose the top surface of the gate stack structure 102. The protection layer 118a covers the gate stack structure 102 and the spacer 116b, and exposes the sidewall of the second step S2. The protection layer 118a may cover a top surface of the gate stack structure 102.
In addition, the memory structure 10 may further include at least one of a dielectric layer 122a, a dielectric layer 122b, a mask layer 130 and a contact 132. A dielectric layer 122a is disposed on the protection layer 118a over the top surface of the gate stack structure 102. A dielectric layer 122b is disposed on the protection layer 118a over the sides of the gate stack structure 102. The dielectric layer 122a and the dielectric layer 122b may be separated from each other. The dielectric layer 122a may include a central portion CP and two side portions SP connected to both sides of the central portion CP. The thickness of the two side portions SP may be greater than that of the central portion CP. As such, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape. The mask layer 130 is disposed on the dielectric layer 122 a. The cross-sectional shape of the mask layer 130 is, for example, a trapezoid with two arc-shaped sides, but the invention is not limited thereto. The contact window 132 is disposed on the substrate 100 at one side of the gate stack structure 102. The contact 132 and the gate stack 102 may be isolated from each other. The contact window may be connected to the substrate 100.
In addition, the materials, forming methods and functions of the components in the memory structure 10 have been described in detail in the above embodiments, and will not be repeated herein.
Based on the above embodiments, in the memory structure 10, since the protection layer 118a covers the spacers 116b and the gate stack structure 102, the protection layer 118a can block ions from entering the spacers 116b and the gate stack structure 102. In addition, since the protection layer 118a only exposes the sidewall of the lower second level S2 in the step structure SS of the spacer 116b, the passage of ions into the spacer 116b can be effectively reduced, thereby reducing the amount of ions entering the spacer 116 b. Therefore, the adverse effect of ions on the operation of the memory can be effectively reduced, and the reliability of the memory element can be further improved.
In summary, in the memory structure and the manufacturing method thereof of the above embodiments, the protective layer can block ions, so that adverse effects of the ions on the memory operation can be effectively reduced, and the reliability of the memory device can be further improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (13)

1. A method of fabricating a memory structure, comprising:
forming a plurality of gate stack structures on a substrate;
forming a spacer layer on sidewalls of the plurality of gate stack structures, wherein the spacer layer is connected between two adjacent gate stack structures;
forming a protective material layer covering the spacer layer and the plurality of gate stack structures;
forming a mask material layer on the protective material layer, wherein the mask material layer has a hole between two adjacent gate stack structures, and a first distance between the top of the protective material layer directly above the plurality of gate stack structures and the top of the mask material layer is greater than the sum of a second distance between the top of the hole and the top of the mask material layer directly above the hole and a third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole;
performing an etching process on the masking material layer to form a plurality of first masking layers separated from each other, wherein the plurality of first masking layers cover the protective material layer on the plurality of gate stack structures and expose a portion of the protective material layer between bottoms of two adjacent gate stack structures; and
removing the exposed part of the protective material layer by the first mask layers to form a plurality of protective layers separated from each other.
2. The method of manufacturing a memory structure according to claim 1, wherein the spacer layer has a stepped structure adjacent to the substrate, the stepped structure includes a first step and a second step connected to each other, the first step is located between the gate stack structure and the second step, and the first step is higher than the second step and lower than a top of the spacer layer.
3. The method of claim 1, wherein the plurality of first masking layers are removed after or during removing a portion of the protective material layer.
4. The method of manufacturing a memory structure of claim 1, further comprising:
forming a dielectric material layer covering the plurality of protective layers and the gap wall layer;
forming a replacement layer on the dielectric material layer, wherein the replacement layer fills the first opening between two adjacent gate stack structures;
removing a portion of the replacement layer above top surfaces of the plurality of gate stack structures to form a plurality of second openings exposing a portion of the dielectric material layer; and
and forming a plurality of second mask layers in the plurality of second openings.
5. The method of manufacturing a memory structure of claim 4, further comprising:
removing the replacement layer; and
and removing part of the dielectric material layer and part of the gap wall layer positioned between the bottoms of the two adjacent grid stacking structures by using the plurality of second mask layers as masks, and forming a gap wall on the side wall of each grid stacking structure and exposing the substrate.
6. The method for manufacturing a memory structure according to claim 5, wherein in the step of forming the spacer, a portion of the dielectric material layer between the tops of two adjacent gate stack structures is removed, and a first dielectric layer and a second dielectric layer are respectively formed over the top surface and the side surface of each gate stack structure, and the first dielectric layer and the second dielectric layer are separated from each other.
7. A memory structure, comprising:
a substrate;
a gate stack structure disposed on the substrate;
a spacer disposed on a sidewall of the gate stack structure, wherein the spacer has a step structure adjacent to the substrate, the step structure includes a first step and a second step connected to each other, the first step is located between the gate stack structure and the second step, and the first step is higher than the second step and lower than a top of the spacer; and
and the protective layer covers the gate stack structure and the gap wall.
8. The memory structure of claim 7, wherein the spacer exposes a top surface of the gate stack structure and the protective layer covers the top surface of the gate stack structure.
9. The memory structure of claim 7, wherein a connection surface of the first level and the second level comprises a vertical surface, a sloped surface, or a curved surface.
10. The memory structure of claim 7, further comprising:
a first dielectric layer disposed on the protective layer over a top surface of the gate stack structure; and
a second dielectric layer disposed on the protective layer over a side of the gate stack structure, wherein the first and second dielectric layers are separated from each other.
11. The memory structure of claim 10, wherein the first dielectric layer comprises a central portion and two side portions connected to both sides of the central portion, and the two side portions have a thickness greater than a thickness of the central portion.
12. The memory structure of claim 10, further comprising:
and the mask layer is arranged on the first dielectric layer, wherein the cross section of the mask layer has a trapezoid shape, and two side edges of the trapezoid shape are arc-shaped.
13. The memory structure of claim 7, wherein the protective layer exposes sidewalls of the second level.
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