TWI721690B - Memory structure and manufacturing method therefore - Google Patents

Abstract

A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer directly located above the gate stack structures and a top of the mask material layer directly located above the gate stack structures. A second distance is between a top of the void and a top of the mask material layer directly located above the void. A third distance is between a bottom of the void and a bottom of the mask material layer located directly below the void. The first distance is greater than a sum of the second distance and the third distance. An etching process is performed on the mask material layer to form first mask layers separated from each other.

Description

Memory structure and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory structure and a manufacturing method thereof.

Non-volatile memory devices (such as flash memory devices) have gradually become one of the mainstream technologies for storage media in recent years. However, during the manufacturing process of the non-volatile memory device, some ions are inevitably generated, and these ions will adversely affect the operation of the memory device, thereby reducing the reliability of the memory device.

The invention provides a memory structure and a manufacturing method thereof, which can effectively reduce the adverse effects of ions on the operation of the memory.

The present invention provides a method for manufacturing a memory structure, which includes the following steps. A plurality of gate stack structures are formed on the substrate. On the sidewall of the gate stack structure Form the spacer layer. The spacer layer is connected between two adjacent gate stack structures. A protective material layer covering the stacked structure of the spacer layer and the gate electrode is formed. A mask material layer is formed on the protective material layer. The mask material layer has holes between two adjacent gate stack structures. The first distance between the top of the protective material layer directly above the gate stack structure and the top of the mask material layer is greater than the second distance between the top of the hole and the top of the mask material layer directly above the hole and the hole The sum of the third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole. An etching process is performed on the mask material layer to form a plurality of first mask layers separated from each other. The first mask layer covers the protective material layer located on the gate stack structure, and exposes a part of the protective material layer located between the bottoms of two adjacent gate stack structures. A part of the protective material layer exposed by the first mask layer is removed to form a plurality of protective layers separated from each other.

The present invention provides a memory structure including a substrate, a gate stack structure, a spacer and a protective layer. The gate stack structure is arranged on the substrate. The spacer is arranged on the side wall of the gate stack structure. The spacer has a stepped structure adjacent to the base. The stepped structure includes a first step and a second step connected to each other. The first stage is located between the gate stack structure and the second stage. The first step is higher than the second step and lower than the top of the spacer. The protective layer covers the gate stack structure and the spacer.

Based on the above, in the manufacturing method of the memory structure proposed in the present invention, since the protective layer covers the spacer layer and the gate stack structure, the protective layer can block ions from entering the spacer layer and the gate stack structure. In this way, the adverse effects of ions on the operation of the memory can be effectively reduced, and the reliability of the memory device can be improved. In addition, the mask material layer has holes between two adjacent gate stack structures Hole, and the first distance between the top of the protective material layer directly above the gate stack structure and the top of the mask material layer is greater than the second distance between the top of the hole and the top of the mask material layer directly above the hole The sum of the distance and the third distance between the bottom of the hole and the bottom of the mask material layer directly below the hole. In this way, in the etching process of the mask material layer, a plurality of first mask layers separated from each other can be formed in a self-aligned manner, thereby reducing the process complexity and manufacturing cost.

In addition, in the memory structure proposed in the present invention, since the protective layer covers the spacer and the gate stack structure, the protective layer can block ions from entering the spacer and the gate stack structure. In addition, since the protective layer only exposes the side walls of the second step with a lower height in the stepped structure of the spacer, it can effectively reduce the passage of ions into the spacer, thereby reducing the number of ions entering the spacer. In this way, the adverse effects of ions on the operation of the memory can be effectively reduced, and the reliability of the memory device can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Memory structure

100: base

102: Gate stack structure

104: charge storage layer

106: Gate

108, 110, 122a, 122b: dielectric layer

112: Conductor layer

114, 114a, 114b: top cover layer

116: spacer material layer

116a: spacer layer

116b: Clearance wall

118: Protective material layer

118a: protective layer

120: mask material cover

120a: curtain layer

122: Dielectric material layer

124: Amorphous silicon layer

124a, 126: polysilicon layer

128: displacement layer

130: mask layer

132: contact window

CP: Central Department

D1, D2, D3: distance

OP1, OP2: opening

S1: First order

S2: second order

SP: side

SS: Ladder structure

V1: Hole

1A to 1L are cross-sectional views of a manufacturing process of a memory structure according to an embodiment of the invention.

1A, a plurality of gate stack structures 102 are formed on the substrate 100. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. The gate stack structure 102 may include a charge storage layer 104 and a gate electrode 106 that are isolated from each other. The charge storage layer 104 is located between the gate 106 and the substrate 100. The charge storage layer 104 may be a floating gate or a charge trapping layer. The material of the floating gate is, for example, doped polysilicon or undoped polysilicon. The material of the charge trapping layer is, for example, silicon nitride. In this embodiment, the charge storage layer 104 is described as an example of a floating gate, but the invention is not limited to this. In addition, there may be an opening OP1 between two adjacent gate stack structures 102.

In addition, the gate stack structure 102 may further include at least one of a dielectric layer 108, a dielectric layer 110, a conductive layer 112, and a cap layer 114. The dielectric layer 108 is located between the charge storage layer 104 and the substrate 100. The material of the dielectric layer 108 is silicon oxide, for example. The dielectric layer 110 is located between the gate 106 and the charge storage layer 104, so that the charge storage layer 104 and the gate 106 can be isolated from each other. The material of the dielectric layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. In this embodiment, the dielectric layer 110 is described with a composite layer of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO) as an example, but the invention is not limited to this. The conductor layer 112 is located on the gate electrode 106. The material of the conductor layer 112 is, for example, metal (eg, tungsten) or metal silicide (eg, cobalt silicide or nickel silicide). The cap layer 114 is located on the conductor layer 112. The cap layer 114 may be a single-layer structure or a multi-layer structure. In this embodiment, the top cover layer 114 is described with a multilayer structure as an example. For example, the cap layer 114 may include a cap layer 114a and a cap layer 114b. The cap layer 114 a is located between the cap layer 114 b and the conductor layer 112. The material of the cap layer 114a is, for example, nitrided Silicon. The material of the cap layer 114b is, for example, silicon oxide.

In addition, the gate stack structure 102 can be formed by a deposition process and a patterning process, but the invention is not limited to this.

Next, a spacer material layer 116 covering the gate stack structure 102 is formed. The material of the spacer material layer 116 is, for example, an oxide material, such as silicon oxide. The formation method of the spacer material layer 116 is, for example, a thermal oxidation method or a chemical vapor deposition method.

1B, an etching process (eg, dry etching process) is performed on the spacer material layer 116, and a spacer layer 116a is formed on the sidewall of the gate stack structure 102, wherein the spacer layer 116a is connected to two adjacent gates. Between the pole stack structure 102. The spacer layer 116a may expose the top of the gate stack structure 102. In some embodiments, during the above dry etching process, polymer will accumulate in the corners of the spacer material layer 116 adjacent to the substrate 100, whereby the spacer layer 116a may have a step adjacent to the substrate 100. Structure SS. The step structure SS may include a first step S1 and a second step S2 connected to each other. The first stage S1 is located between the gate stack structure 102 and the second stage S2. The first step S1 may be higher than the second step S2 and may be lower than the top of the spacer layer 116a. The connecting surface of the first step S1 and the second step S2 may include a vertical surface, an inclined surface or a curved surface. In this embodiment, the connection surface of the first step S1 and the second step S2 is described by taking a vertical surface as an example. In addition, although the formation method of the spacer layer 116a is based on the above-mentioned method as an example, the present invention is not limited to this.

1C, a protective material layer 118 covering the spacer layer 116a and the gate stack structure 102 is formed. The material of the protective material layer 118 is, for example, a nitride material, such as silicon nitride. The method of forming the protective material layer 118 is, for example, a chemical vapor deposition method.

1D, a mask material layer 120 is formed on the protective material layer 118. The mask material layer 120 has a hole V1 between two adjacent gate stack structures 102. The distance D1 between the top of the protective material layer 118 directly above the gate stack structure 102 and the top of the mask material layer 120 is greater than the distance between the top of the hole V1 and the top of the mask material layer 120 directly above the hole V1. The sum of the distance D2 and the distance D3 between the bottom of the hole V1 and the bottom of the mask material layer 120 directly below the hole V1. The material of the mask material layer 120 is, for example, an oxide material, such as silicon oxide. The method for forming the mask material layer 120 is, for example, a chemical vapor deposition method.

1E, the mask material layer 120 is subjected to an etching process (for example, a dry etching process) to form a plurality of mask layers 120a separated from each other. The mask layer 120 a covers the protective material layer 118 located on the gate stack structure 102 and exposes a part of the protective material layer 118 located between the bottoms of two adjacent gate stack structures 102. Since the distance D1 is greater than the sum of the distance D2 and the distance D3 (FIG. 1D), in the dry etching process of the mask material layer 120, the mask layers 120a separated from each other can be formed in a self-aligned manner, so Reduce process complexity and manufacturing cost.

1F, a part of the protective material layer 118 exposed by the mask layer 120a is removed to form a protective layer 118a separated from each other. The protective layer 118 a can cover the top surface of the gate stack structure 102 and the spacer layer 116 a located on the sidewall of the gate stack structure 102. In addition, the protective layer 118a may expose a part of the spacer layer 116a located between two adjacent gate stack structures 102. The method for removing part of the protective material layer 118 is, for example, a dry etching method.

In some embodiments, after removing part of the protective material layer 118, the mask layer 120a may be removed. For example, in the process of removing part of the protective material layer 118, part of the mask layer 120a may be consumed. Then, after removing part of the protective material layer 118, the mask layer 120a can be removed by a subsequent cleaning process. In some embodiments, the mask layer 120a may be removed at the same time as part of the protective material layer 118 is removed.

1G, a dielectric material layer 122 covering the protective layer 118a and the spacer layer 116a can be formed. The material of the dielectric material layer 122 is, for example, an oxide material, such as silicon oxide. The formation method of the dielectric material layer 122 is, for example, a chemical vapor deposition method.

Next, an amorphous silicon layer 124 can be formed on the dielectric material layer 122. The method for forming the amorphous silicon layer 124 is, for example, a chemical vapor deposition method.

1H, the amorphous silicon layer 124 may be subjected to a tempering process to form a polysilicon layer 124a. The polysilicon layer 124a can be used as a seed layer.

Then, a polysilicon layer 126 may be deposited on the polysilicon layer 124a. The material of the polysilicon layer 126 can be doped polysilicon or undoped polysilicon. In the case where the material of the polysilicon layer 126 is doped polysilicon, the polysilicon layer 126 may have better hole filling ability.

In this way, a replacement layer 128 can be formed on the dielectric material layer 122. The replacement layer 128 may include a polysilicon layer 124a and a polysilicon layer 126. The replacement layer 128 fills the opening OP1 between two adjacent gate stack structures 102. In the case where the replacement layer 128 is formed by the above-mentioned method, the replacement layer 128 may have a better hole-filling ability, but the material and formation method of the replacement layer 128 of the present invention are not limited to this. In this example The replacement layer 128 is an example of a double-layer structure, but the present invention is not limited to this. In other embodiments, the replacement layer 128 may be a single-layer structure or a structure with more than three layers.

1I, the partial replacement layer 128 above the top surface of the gate stack structure 102 can be removed to form a plurality of openings OP2 exposing a portion of the dielectric material layer 122. The method of forming the opening OP2 is, for example, patterning the replacement layer 128 by a photolithography process and an etching process. In addition, during the process of forming the opening OP2, part of the dielectric material layer 122 may be removed.

1J, a mask layer 130 may be formed in the opening OP2. The material of the mask layer 130 is, for example, a nitride material, such as silicon nitride. The method for forming the mask layer 130 may include the following steps, but the present invention is not limited thereto. First, a mask material layer (not shown) that fills the opening OP2 can be formed by a deposition process. Then, the mask layer 130 can be formed by removing the mask material layer outside the opening OP2 by a chemical mechanical polishing method.

Referring to FIG. 1K, the replacement layer 128 can be removed. The removal method for removing the replacement layer 128 is, for example, a wet etching method or a dry etching method.

Then, the mask layer 130 can be used as a mask to remove part of the dielectric material layer 122 and part of the spacer layer 116a located between the bottoms of the two adjacent gate stack structures 102, and in each gate stack A spacer 116b is formed on the sidewall of the structure 102, and the substrate 100 is exposed. The method for removing part of the dielectric material layer 122 and part of the spacer layer 116a is, for example, a wet etching method or a dry etching method. In some embodiments, in the step of forming the spacer 116b, part of the mask layer 130 may be consumed, so that the cross-sectional shape of the mask layer 130 is similar to a rounded triangle with arcs on both sides.

In addition, in the step of forming the spacer 116b, a part of the dielectric material layer 122 located between the tops of two adjacent gate stack structures 102 can be removed, and the top surface of each gate stack structure 102 A dielectric layer 122a and a dielectric layer 122b are respectively formed above the side surface, and the dielectric layer 122a and the dielectric layer 122b can be separated from each other. The dielectric layer 122a may include a central part CP and two side parts SP connected to both sides of the central part CP. The thickness of the two side parts SP may be greater than the thickness of the central part CP. In this way, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape.

In addition, since part of the dielectric material layer 122 and part of the spacer layer 116a are removed using the mask layer 130 as a mask, the spacer 116b, the dielectric layer 122a, and the dielectric layer can be formed in a self-aligned manner. The layer 122b can further reduce the process complexity and manufacturing cost.

1L, a contact window 132 may be formed in the opening OP1 between two adjacent gate stack structures 102. The contact window 132 may be connected to the substrate 100. The material of the contact window 132 is, for example, metal such as tungsten. The method of forming the contact window 132 may include the following steps, but the present invention is not limited thereto. First, a deposition process can be used to form a contact window material layer (not shown) that fills the opening OP1. Then, the contact window 132 can be formed by removing the contact window material layer outside the opening OP1 by a chemical mechanical polishing process. In the above chemical mechanical polishing process, part of the mask layer 130 may be removed, so that the cross-sectional shape of the mask layer 130 is changed to an arc shape on both sides of the trapezoid.

In addition, in the above-mentioned manufacturing method of the memory structure 10, a required doped region (not shown) may be formed in the substrate 100 according to requirements. Due to the formation of the substrate 100 The required doped region is a technology well known to those with ordinary knowledge in the relevant technical field, so it will not be described here.

Based on the above embodiment, in the manufacturing method 10 of the memory structure, since the protective layer 118a covers the spacer layer 116a and the gate stack structure 102, the protective layer 118a can block ions from entering the spacer layer 116a and the gate stack. Structure 102. In this way, the adverse effects of ions on the operation of the memory can be effectively reduced, and the reliability of the memory device can be improved. In addition, the mask material layer 120 has a hole V1 between two adjacent gate stack structures 102, and the distance D1 is greater than the sum of the distance D2 and the distance D3 (FIG. 1D). In this way, in the dry etching process of the mask material layer 120, a plurality of mask layers 120a (FIG. 1E) that are separated from each other can be formed in a self-aligned manner, thereby reducing the process complexity and manufacturing cost. .

Hereinafter, the memory structure 10 of this embodiment will be described with reference to FIG. 1L. In addition, although the method for forming the memory structure 10 is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

1L, the memory structure 10 includes a substrate 100, a gate stack structure 102, a spacer 116b, and a protective layer 118a. In this embodiment, the memory structure 10 may be a NOR flash memory (NOR flash memory), but the invention is not limited thereto. The gate stack structure 102 is disposed on the substrate 100. The detailed content of the gate stack structure 102 has been described in the above-mentioned embodiment, and will not be described here. The spacer 116b is disposed on the sidewall of the gate stack structure 102. The spacer 116b has a stepped structure SS adjacent to the substrate 100. The step structure SS includes a first step S1 and a second step S2 connected to each other. The first stage S1 is located between the gate stack structure 102 and the second stage S2. First order S1 It is higher than the second step S2 and lower than the top of the spacer 116b. The connecting surface of the first step S1 and the second step S2 may include a vertical surface, an inclined surface or a curved surface. The spacer 116b may expose the top surface of the gate stack structure 102. The protective layer 118a covers the gate stack 102 and the spacer 116b, and exposes the sidewall of the second stage S2. The protective layer 118 a may cover the top surface of the gate stack structure 102.

In addition, the memory structure 10 may further include at least one of a dielectric layer 122a, a dielectric layer 122b, a mask layer 130, and a contact window 132. The dielectric layer 122 a is disposed on the protective layer 118 a above the top surface of the gate stack structure 102. The dielectric layer 122 b is disposed on the protective layer 118 a above the side surface of the gate stack structure 102. The dielectric layer 122a and the dielectric layer 122b may be separated from each other. The dielectric layer 122a may include a central part CP and two side parts SP connected to both sides of the central part CP. The thickness of the two side parts SP may be greater than the thickness of the central part CP. In this way, the dielectric layer 122a may have a cross-sectional shape similar to a bat shape. The mask layer 130 is disposed on the dielectric layer 122a. The cross-sectional shape of the mask layer 130 is, for example, the two sides of a trapezoid are changed to an arc shape, but the present invention is not limited to this. The contact window 132 is disposed on the substrate 100 on one side of the gate stack structure 102. The contact window 132 and the gate stack structure 102 may be isolated from each other. The contact window can be connected to the substrate 100.

In addition, the materials, forming methods, and functions of the components in the memory structure 10 have been described in detail in the above-mentioned embodiments, and the description will not be repeated here.

Based on the above embodiment, in the memory structure 10, since the protective layer 118a covers the spacer 116b and the gate stack structure 102, the protective layer 118a can block ions from entering the spacer 116b and the gate stack structure 102. In addition, since the protective layer 118a only exposes the lower height of the stepped structure SS of the spacer 116b The side wall of the second stage S2 can effectively reduce the passage of ions into the spacer 116b, thereby reducing the number of ions entering the spacer 116b. In this way, the adverse effects of ions on the operation of the memory can be effectively reduced, and the reliability of the memory device can be improved.

In summary, in the memory structure and manufacturing method of the above-mentioned embodiment, the protective layer can block ions, so the adverse effects of ions on the operation of the memory can be effectively reduced, and the performance of the memory device can be improved. Reliability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Memory structure

100: base

102: Gate stack structure

104: charge storage layer

106: Gate

108, 110, 122a, 122b: dielectric layer

112: Conductor layer

114, 114a, 114b: top cover layer

116b: Clearance wall

118a: protective layer

130: mask layer

132: contact window

CP: Central Department

OP1: Opening

S1: First order

S2: second order

SP: side

SS: Ladder structure

Claims (13)

A method for manufacturing a memory structure includes: forming a plurality of gate stack structures on a substrate; forming a spacer layer on the sidewalls of the plurality of gate stack structures, wherein the spacer layer is connected to two adjacent ones Between the gate stack structures; forming a protective material layer covering the spacer layer and the plurality of gate stack structures; forming a mask material layer on the protective material layer, wherein the mask material layer is in phase There is a hole between two adjacent gate stack structures, and the first distance between the top of the protective material layer directly above the plurality of gate stack structures and the top of the mask material layer is greater than the first distance The second distance between the top of the hole and the top of the mask material layer directly above the hole and the second distance between the bottom of the hole and the bottom of the mask material layer directly below the hole The sum of the three distances; performing an etching process on the mask material layer to form a plurality of first mask layers separated from each other, wherein the plurality of first mask layers cover the plurality of gate stack structures On the protective material layer, and exposes a part of the protective material layer located between the bottoms of two adjacent gate stack structures; and removes the portion of the protective material layer exposed by the plurality of first mask layers Part of the protective material layer forms a plurality of protective layers separated from each other. The method for manufacturing a memory structure as described in claim 1, wherein the spacer layer has a step structure adjacent to the substrate, and the step structure includes a first step and a second step that are connected to each other, The first stage is at the gate Between the stacked structure and the second stage, and the first stage is higher than the second stage and lower than the top of the spacer layer. According to the method for manufacturing a memory structure as described in claim 1, wherein after removing part of the protective material layer or in the process of removing part of the protective material layer, the plurality of first Mask layer. The manufacturing method of the memory structure according to the first item of the scope of patent application, further includes: forming a dielectric material layer covering the plurality of protective layers and the spacer layer; forming a replacement on the dielectric material layer Layer, wherein the replacement layer fills the first opening between two adjacent gate stack structures; a part of the replacement layer above the top surface of the plurality of gate stack structures is removed to form an exposed portion A plurality of second openings of the dielectric material layer; and a plurality of second mask layers are formed in the plurality of second openings. As described in item 4 of the scope of patent application, the method for manufacturing a memory structure further includes: removing the replacement layer; and using the plurality of second mask layers as masks, and the removal is located at two adjacent ones. Part of the dielectric material layer and part of the spacer layer between the bottom of the gate stack structure are formed on the sidewall of each gate stack structure, and the substrate is exposed. The manufacturing method of the memory structure as described in the 5th item of the scope of patent application, wherein in the step of forming the spacers, removing the stacked junctions located between two adjacent gate electrodes Part of the dielectric material layer between the top of the structure, and a first dielectric layer and a second dielectric layer are respectively formed on the top surface and the side surface of each gate stack structure, and the first dielectric layer And the second dielectric layer are separated from each other. A memory structure includes: a substrate; a gate stack structure arranged on the substrate; a spacer arranged on the side wall of the gate stack structure, wherein the spacer has a step adjacent to the substrate Structure, the stepped structure includes a first step and a second step connected to each other, the first step is located between the gate stack structure and the second step, and the first step is higher than the The second stage is lower than the top of the spacer; and a protective layer covering the gate stack structure and the spacer. The memory structure according to item 7 of the scope of patent application, wherein the spacer exposes the top surface of the gate stack structure, and the protective layer covers the top surface of the gate stack structure. The memory structure according to item 7 of the scope of patent application, wherein the connecting surface of the first step and the second step includes a vertical surface, an inclined surface or a curved surface. The memory structure described in item 7 of the scope of patent application further includes: a first dielectric layer disposed on the protective layer above the top surface of the gate stack structure; and a second dielectric layer disposed On the protective layer above the side surface of the gate stack structure, the first dielectric layer and the second dielectric layer are separated from each other. The memory structure according to claim 10, wherein the first dielectric layer includes a central portion and two side portions connected to both sides of the central portion, and the thickness of the two side portions Greater than the thickness of the central portion. The memory structure as described in item 10 of the scope of patent application further includes: a mask layer disposed on the first dielectric layer, wherein the cross-sectional shape of the mask layer includes a trapezoid, and both sides are changed to arcs Shaped shape. In the memory structure described in item 7 of the scope of patent application, the protective layer exposes the sidewall of the second stage.

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