TW202337002A - Memory device and method of manufacturing the same - Google Patents

Abstract

Provided is a memory device including a substrate, a plurality of stack structures, and a protective layer. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In the cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, that of the control gate and that of the cap layer are substantially equal to each other.

Description

Memory element and manufacturing method thereof

The present invention relates to a memory element and a manufacturing method thereof, and in particular to a memory element including a top cover layer having a multi-layer structure and a manufacturing method thereof.

With the improvement of semiconductor technology, the size of semiconductor memory components is getting smaller and smaller. Among them, flash memory (Flash Memory) has gradually attracted attention due to its advantages such as light weight, small size, and low power. However, in the current manufacturing process of flash memory, it is easy to form protrusions at the corners above the gate. Therefore, when the dummy source contact plugs or dummy drain contact plugs are removed, such as by performing an etching process to form the source or drain contact openings, it is easy to make the The protective layer near the protruding portion is damaged, causing problems such as element leakage current, which reduces the reliability of the semiconductor memory element.

The invention provides a memory element, which includes a plurality of stacked structures and a protective layer. A plurality of stacked structures are arranged on the array area of the substrate along a first direction, and each stacked structure extends along a second direction different from the first direction. In the cross-sectional view of the memory element, each stacked structure includes a charge storage structure, a control gate and a top cover layer in order from the base, and the top cover layer has a multi-layer structure. A protective layer covers the side walls of the stacked structure. The width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the capping layer along the first direction are substantially equal to each other.

The invention provides a method for manufacturing a memory element, the steps of which are as follows. A plurality of stacked structures are formed on the substrate of the array area. The plurality of stacked structures are arranged along a first direction, and each stacked structure extends along a second direction that is different from the first direction. And in the cross-sectional view of the memory element, each stacked structure includes a charge storage structure, a control gate and a top cover layer in order from the base, where the top cover layer has a multi-layer structure. The width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the capping layer along the first direction are substantially equal to each other. Next, a protective layer is formed on the sidewalls of the stacked structure. A conductor layer is formed on the substrate to fill the spaces between the plurality of stacked structures. A planarization process is performed to form multiple conductor strips. At least one conductor strip is patterned to form a plurality of conductor posts. Furthermore, an alternative process is performed to replace the plurality of conductor strips and the plurality of conductor posts with a plurality of contact plugs.

Based on the above, in the present invention, the width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the top capping layer along the first direction are substantially equal to each other, so that the stacked structure has Substantially smooth sidewalls. In this way, the protective layer can be prevented from being damaged by the etching process and its integrity can be maintained to further improve component reliability. On the other hand, in the manufacturing method of the present invention, the top cover layer of the stacked structure can be used as a polishing buffer layer, so the dummy source contact plug can be directly isolated through the planarization process, and only a subsequent patterning process is required. to form a virtual drain contact plug.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Figure 1A, Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 11D, Figure 12A, Figure 12D, Figure 13A, Figure 13C, Figure 14A , Figure 14C, Figure 15A, Figure 15C, Figure 16A, Figure 16C, Figure 17A and Figure 17C are schematic cross-sectional views of the manufacturing process of the array area of the memory element according to an embodiment of the present invention; Figure 1B, Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 11E, Figure 12B, Figure 12E, Figure 13B, Figure 13D, Figure 14B, Figure 14D, Figure 15B, Figure 15D , Figure 16B, Figure 16D, Figure 17B and Figure 17D are schematic cross-sectional views of the manufacturing process of the peripheral area of the memory element according to an embodiment of the present invention; Figure 1C, Figure 11C and Figure 12C are respectively Figure 1A, Figure 11A and Figure 12A Schematic diagram from above. It should be noted that Figure 1A, Figure 11A and Figure 12A are schematic cross-sectional views taken along line II' of Figure 1C, Figure 11C and Figure 12C respectively; Figures 11D and Figure 12D are respectively taken along line II-II' of Figure 11C and Figure 12C Schematic diagram of line section.

First, please refer to FIGS. 1A to 1C to provide a substrate 100 . The substrate 100 includes an array area 102 and a peripheral area 104. As shown in FIG. 1C , the isolation structure 101 is disposed in the substrate 100 to define a plurality of active areas AA on the substrate 100 . The active area AA extends, for example, along the first direction D1. In one embodiment, the substrate 100 is, for example, a silicon substrate. The isolation structure 101 may be a shallow trench isolation (STI) structure. As shown in FIGS. 1A and 1B , the tunnel dielectric layer 106 may be formed on the surface 100 a of the substrate 100 . In one embodiment, the material of the tunnel dielectric layer 106 may include dielectric materials such as silicon oxide.

A plurality of first stacked structures 110 are arranged on the substrate 100 of the array area 102 , and a plurality of second stacked structures 120 are arranged on the substrate 100 of the peripheral area 104 . As shown in FIGS. 1A and 1B , the height of the first stacked structure 110 is, for example, greater than the height of the second stacked structure 120 . As shown in FIG. 1C , the first stacked structure 110 may be a strip structure and cross the active area AA. In other words, the first stacked structure 110 extends along the second direction D2 that is different from the first direction D1. In this embodiment, the second direction D2 is perpendicular or orthogonal to the first direction D1, but the invention is not limited thereto. In addition, although only one second stacked structure 120 is shown in FIGS. 1A and 1B , only five first stacked structures 110 are shown in FIG. 1C . In other embodiments, the number of the first stacked structure 110 and the second stacked structure 120 can be adjusted according to design requirements, and is not limited in the present invention.

In this embodiment, the first stacked structure 110 includes a charge storage structure 112, a barrier layer BL, a control gate (Control Gate) CG, and a top cap layer CL in order from bottom to top. In the cross-sectional view 1A, the side wall 110b of the first stacked structure 110 is substantially in a straight line. Specifically, the sidewalls of the charge storage structure 112 , the control gate CG and the capping layer CL on the same side are, for example, located on the same straight line parallel to the normal vector of the substrate 100 . In other words, the width of the charge storage structure 112 along the first direction D1 , the width of the control gate CG along the first direction D1 and the width of the capping layer CL along the first direction D1 are substantially equal to each other. In this way, the first stacked structure 110 can have substantially smooth sidewalls 110b. Therefore, when the protective layer is formed on the sidewalls 110b of the first stacked structure 110 in subsequent processes, protrusions can be avoided, thereby ensuring that the protective layer is positioned on the sidewalls. The protective layer on 110b has a smooth surface. In one embodiment, the barrier layer BL can be regarded as an inter-gate dielectric layer, which can be a composite layer composed of oxide/nitride/oxide (Oxide-Nitride-Oxide, ONO). The material of the control gate CG includes a conductor material, which may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof.

In this embodiment, the charge storage structure 112 is suitable for storing charges. In one embodiment, the charge storage structure 112 may include a floating gate, but the invention is not limited thereto. The material of the floating gate includes a conductor material, which may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof.

In this embodiment, the capping layer CL has a multi-layer structure. For example, the capping layer CL may include a dielectric layer 114 and a hard mask layer 116 . The dielectric layer 114 is, for example, disposed between the control gate CG and the hard mask layer 116 . The width of the dielectric layer 114 along the first direction D1 is substantially equal to the width of the hard mask layer 116 along the first direction D1. In this way, it is ensured that a smooth surface can be maintained even when a protective layer or the like is formed on the sidewall of the capping layer CL in subsequent processes. In this embodiment, the thickness of the hard mask layer 116 is, for example, 100 nm to 150 nm. In addition, the material of the hard mask layer 116 is, for example, silicon nitride, but the present invention is not limited thereto. In other embodiments, the hard mask layer 116 can also use other suitable thicknesses and/or hard mask materials, as long as it can block grinding during chemical mechanical polishing processes and other steps. In one embodiment, the material of the dielectric layer 114 may include dielectric materials such as silicon oxide.

In this embodiment, the second stacked structure 120 includes a gate electrode 122 and a dielectric layer 124 in order from bottom to top. In one embodiment, the material of the gate electrode 122 includes a conductive material, which may be, for example, doped polysilicon, non-doped polysilicon, or a combination thereof. The material of the dielectric layer 124 is, for example, silicon oxide.

Next, please refer to FIGS. 2A and 2B simultaneously. The spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A are formed sequentially on the substrate 100, the first stacked structure 110, and the second stacked structure 120, for example. For example, in the array region 102, the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A sequentially and conformally cover the surface 100a of the substrate 100, and the top surface 110a of the first stack structure 110. Sidewall 110b; in the peripheral area 104, the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A sequentially conformally cover the surface 100a of the substrate 100, and the top surface 120a and sidewalls of the second stacked structure 120 120b. In one embodiment, a method of forming the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A is, for example, a deposition method. The material of the spacer material layer 131A may be silicon oxide or the like. The material of the spacer material layer 132A may be silicon nitride or the like. The material of the spacer material layer 133A may be silicon oxide or the like.

Then, please refer to FIGS. 3A and 3B simultaneously to remove part of the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A to expose the top surface 110a of the first stacked structure 110 and the second stacked structure. 120 and a portion of the tunnel dielectric layer 106, and spacer layers 131, 132 and 133 are formed on the sidewalls 110b of the first stacked structure 110 and the sidewalls 120b of the second stacked structure 120. (Hereinafter collectively referred to as the spacer layer 130). In one embodiment, a method for removing part of the spacer material layer 131A, the spacer material layer 132A, and the spacer material layer 133A is, for example, an anisotropic etching process, but the invention is not limited thereto.

Then, please refer to FIGS. 4A and 4B simultaneously, the protective layer 136 is conformally formed on the substrate 100 . In this embodiment, the first stacked structure 110 has substantially smooth sidewalls 110b, thus ensuring that the protective layer 136 formed on the sidewalls 110b has a substantially smooth surface. In one embodiment, the protective layer 136 is formed by a deposition method, for example. The material of the protective layer 136 may be silicon nitride or the like.

After that, please refer to FIG. 5A and FIG. 5B simultaneously, the conductor layer 138 is disposed on the protective layer 136 . In this embodiment, the height of the conductor layer 138 is greater than the height of the first stacked structure 110 and the height of the second stacked structure 120 . In this embodiment, the height of the conductor layer 138 located in the array area 102 is, for example, greater than the height of the conductor layer 138 located in the peripheral area 104 . Next, a hard mask layer 140 is formed on the conductor layer 138 . In one embodiment, the material of the conductor layer 138 may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof. The material of the hard mask layer 140 may be suitable material such as silicon nitride.

Next, please refer to FIGS. 6A and 6B simultaneously, spacers 142 are formed on the sidewalls 120b of the second stacked structure 120 . The method of forming the spacer 142 includes, for example, the following steps, but the present invention is not limited thereto. First, a photoresist pattern layer (not shown) is formed on the hard mask layer 140 located in the array area 102, and an etching process is performed using the photoresist pattern layer as a mask to remove the conductor layer 138 located in the peripheral area 104. and the hard mask layer 140 to expose the second stacked structure 120 . In one embodiment, the etching process may be a dry etching process using different etching gases, such as a reactive ion etching (RIE) process. Next, the photoresist pattern layer is removed, a spacer material (not shown) such as silicon oxide is blanket-deposited on the substrate 100 , and the spacer material is etched to form spacers 142 . In this embodiment, part of the protective layer 136 is also removed.

Then, please refer to FIGS. 7A and 7B at the same time. After forming the spacers 142 , it may also include forming a plurality of silicide layers 144 on the substrate 100 and the second stacked structure 120 . In one embodiment, the material of the silicide layer 144 may be, for example, titanium silicide, cobalt silicide, nickel silicide, or a combination thereof. Then, a liner layer 146 is conformally deposited on the substrate 100 . In one embodiment, the material of the lining layer 146 may be silicon nitride or the like.

Afterwards, please refer to FIGS. 8A and 8B simultaneously to form an oxide layer 148 blanketingly on the substrate 100 . In this embodiment, the height of the oxide layer 148 located in the array region 102 is, for example, greater than the height of the oxide layer 148 located in the peripheral region 104 . In one embodiment, the material of the oxide layer 148 may be silicon oxide or the like.

Next, referring to FIGS. 9A and 9B , for example, a wet etching process is performed to remove part of the oxide layer 148 and the liner layer 146 and the remaining hard mask layer 140 to expose the conductor layer 138 . In this embodiment, taking a surface of the substrate 100 as a reference plane, the horizontal height of the top surface 150 a of the oxide layer 150 is, for example, lower than the horizontal height of the top surface 138 a of the conductor layer 138 . In addition, the horizontal height of the top surface 150 a of the oxide layer 150 is, for example, higher than the horizontal height of the top surface 110 a of the first stacked structure 110 . In other words, the level of the top surface 150 a of the oxide layer 150 is between the level of the top surface 138 a of the conductor layer 138 and the level of the top surface 110 a of the first stacked structure 110 .

Then, please refer to FIG. 10A and FIG. 10B simultaneously, using the hard mask layer 116 as a grinding buffer layer, a planarization process is performed on the conductor layer 138 until the highest top surface 136 a of the protective layer 136 is exposed to obtain the conductor strip 152 . In this embodiment, the conductor strip 152 is located between two adjacent first stack structures 110 . Taking a surface of the substrate 100 as a reference plane, the horizontal height of the highest top surface 136 a of the protective layer 136 is substantially equal to the horizontal height of the top surface 152 a of the conductor bar 152 . In other words, the highest top surface 136a of the protective layer 136 and the top surface 152a of the conductor bar 152 are substantially coplanar. In contrast, in the prior art, a conductor layer with a certain height is usually reserved, for example, the height is greater than the height of the first stack structure, and a spin-coated carbon layer or a photoresist layer is formed on the conductor layer; and then the The conductor layer undergoes a patterning process to obtain multiple conductor strips. However, the present invention uses the hard mask layer 116 in the first stacked structure 110 as a polishing buffer layer, which can directly form the conductor strip 152 through the planarization process and also isolate the source contact plugs scheduled to be formed later. area (that is, to form a virtual source contact plug), so it is only necessary to subsequently perform a patterning process on at least one of the plurality of conductor strips 152 to form a conductor pillar (that is, to form a virtual drain contact plug), Details are explained later. In one embodiment, the planarization process is, for example, a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof.

On the other hand, during the step of forming the conductor strip 152, a planarization process may also be performed on the oxide layer 150 to reduce the horizontal height of the top surface 150a of the oxide layer 150. In this embodiment, taking a surface of the substrate 100 as a reference plane, the horizontal height of the top surface 150 a of the oxide layer 150 is substantially equal to the horizontal height of the top surface 152 a of the conductor strip 152 . In other words, the top surface 150a of the oxide layer 150 and the top surface 152a of the conductor strip 152 are substantially coplanar.

Then, referring to FIGS. 11A to 11E , a mask pattern PR is formed on the substrate 100 . The mask pattern PR has a plurality of first openings OP1 corresponding to the conductor bars 152 on one side of the first stacked structure 110 . That is to say, the first opening OP1 is located directly above the conductor bar 152 on one side of the first stacked structure 110 but not directly above the conductor bar 152 on the other side of the first stacked structure 110 . In addition, as can be seen from FIGS. 11A, 11C, and 11D, the first opening OP1 is located directly above the conductor strip 152 on the isolation structure 101, but not directly above the conductor strip 152 on the active area AA. As shown in FIG. 11A and FIG. 11C , the width W of the first opening OP1 along the second direction D2 is, for example, 120 nm, and exposes part of the protective layer 136 and the corresponding conductor strip 152 . In one embodiment, the material of the mask pattern PR includes suitable materials such as carbon and photoresist materials.

After that, please refer to FIGS. 12A to 12E to pattern the conductor strips 152 into a plurality of conductor posts 154 . Specifically, using the mask pattern PR as a mask, the conductor bars 152 exposed by the first opening OP1 are removed to form a plurality of conductor posts 154 and the second opening OP2. The second opening OP2 exposes the protective layer 136 on the surface 100a of the substrate 100. In addition, as shown in FIG. 12C , the conductive pillars 154 are respectively arranged on the active area AA, and are alternately arranged along the second direction D2. In more detail, FIG. 12A is a schematic cross-sectional view along line I-I' of FIG. 12C. Therefore, after the above patterning process is performed, the conductor strip 152 in FIG. 12A will be removed. On the other hand, FIG. 12D is a schematic cross-sectional view taken along line II-II' in FIG. 12C. Therefore, after the above patterning process is performed, the conductor strips 152 in FIG. 12D will not be removed to form the conductor posts 154. In one embodiment, the method for removing the conductor strip 152 may be a dry etching process, such as a reactive ion etching (RIE) process, but the invention is not limited thereto.

In this embodiment, as shown in FIGS. 12A, 12C, and 12D, the conductor bar 152 can be regarded as a virtual source contact plug, and the conductor post 154 can be regarded as a virtual drain contact plug. Here, the so-called "dummy" refers to structures that will be removed by subsequent replacement processes. The position of the dummy source/drain contact plug is replaced by the subsequently formed source/drain contact plug.

Next, please refer to FIGS. 13A to 13D , 14A to 14D , 15A to 15D , 16A to 16D , and 17A to 17D to perform a replacement process to connect the conductor bar 152 with the conductor post. 154 is replaced by a plurality of contact plugs 162 and 164 . Specifically, referring to FIGS. 13A to 13D , a nitride layer 156 and an oxide layer 158 can be sequentially formed on the substrate 100 . The nitride layer 156 conformally covers the substrate 100 . The oxide layer 158 fills the second opening OP2 and blanket covers the nitride layer 156 . In one embodiment, nitride layer 156 may be silicon nitride. Oxide layer 158 may be silicon oxide.

Then, referring to FIGS. 14A to 14D , a planarization process is performed on the oxide layer 158 to expose the nitride layer 156 outside the second opening OP2. In this case, the highest top surface 156a of the nitride layer 156 and the top surface 160a of the oxide layer 160 can be considered to be coplanar. In one embodiment, the planarization process may be, for example, a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof.

Then, please refer to FIGS. 15A to 15D to remove part of the nitride layer 156 , the conductor bars 152 and the conductor pillars 154 to form a plurality of third openings OP3 and fourth openings OP4 . A plurality of third openings OP3 and fourth openings OP4 are respectively formed between the first stack structures 110 and expose the protective layer 136 . Here, since the first stacked structure 110 of this embodiment has smooth sidewalls 110b without protrusions, when removing the conductor strips 152 and the conductor posts 154, it is possible to avoid contact with the sidewalls 110b of the first stacked structure 110. The protective layer 136 on the semiconductor memory device causes damage, thereby avoiding problems such as device leakage current and improving the reliability of the semiconductor memory device. In this embodiment, the third opening OP3 may be a strip-shaped opening extending along the second direction D2. The fourth openings OP4 may be island-shaped or columnar openings, which are alternately arranged along the second direction D2. In one embodiment, a method for removing portions of the nitride layer 156, the conductor strips 152, and the conductor pillars 154 may be, for example, a dry etching process using different etching gases, such as a reactive ion etching (RIE) process.

After that, please refer to FIG. 16A to FIG. 16D to perform an etching process to remove the protective layer 136 and the tunnel dielectric layer 106 under the third opening OP3 and the fourth opening OP4, so as to separate the third opening OP3 and the fourth opening OP4 respectively. OP4 extends downward, thereby exposing the substrate 100 . During the etching process, the protective layer 136 on the top surface 110a of the first stacked structure 110 is also removed, so that the top surface 110a of the first stacked structure 110 and the top surface 160a of its adjacent oxide layer 160 are the same. flat. In one embodiment, the etching process may include a dry etching process, such as a reactive ion etching (RIE) process. In this embodiment, the hard mask layer 116 can further protect the first stacked structure 110 from damage during the etching process.

Next, referring to FIGS. 17A to 17D , a conductive material is formed in the third opening OP3 and the fourth opening OP4 to form a plurality of contact plugs 162 and 164 to complete the memory element 10 of this embodiment. In this embodiment, the contact plug 162 can be regarded as a source contact plug, and the contact plug 164 can be regarded as a drain contact plug. In one embodiment, the contact plug 162 may be strip-shaped in the plan view direction of the memory element 10 and extend along the second direction D2. In another embodiment, the contact plugs 164 may be island-shaped in the plan view direction of the memory element 10 and alternately arranged along the second direction D2. In one embodiment, the memory element 10 is, for example, a flash memory element, but the invention is not limited thereto. In one embodiment, the conductor material includes a metal material (such as W, Cu, AlCu, etc.), a barrier metal (such as Ti, TiN, Ta, TaN, etc.) or a combination thereof. The formation method may be electroplating, physical Suitable formation methods such as vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (CVD), etc.

Hereinafter, the memory element of this embodiment will be described with reference to FIGS. 17A to 17D. It should be noted that although the manufacturing method of the memory element in this embodiment is based on the above manufacturing method as an example, the manufacturing method of the memory element in this embodiment is not limited to this.

Referring to FIGS. 17A to 17D , the memory element 10 of this embodiment includes a substrate 100 , a plurality of first stack structures 110 , a plurality of second stack structures 120 , a protective layer 136 and a plurality of contact plugs 162 and 164 . The protective layer 136 covers the sidewalls 110b of the first stack structure 110. The plurality of first stacked structures 110 are arranged on the substrate 100 of the array area 102 along the first direction D1, and each first stacked structure 110 extends along the second direction D2. As shown in cross-sectional views 17A and 17C, the first stacked structure 110 includes a charge storage structure 112, a barrier layer BL, a control gate CG and a top capping layer CL in order from the substrate 100. Specifically, the width of the charge storage structure 112 along the first direction D1 , the width of the control gate CG along the first direction D1 and the width of the capping layer CL along the first direction D1 are substantially equal to each other. That is to say, the first stacked structure 110 has substantially smooth sidewalls 110b, which can prevent the protective layer 136 from being damaged by the etching process and maintain its integrity to further improve reliability.

In this embodiment, the cap layer CL is, for example, a multi-layer structure including a dielectric layer 114 and a hard mask layer 116 . The dielectric layer 114 is disposed between the control gate CG and the hard mask layer 116 . The width of the dielectric layer 114 along the first direction D1 is substantially equal to the width of the hard mask layer 116 along the first direction D1. In this way, the first stacked structure 110 can maintain a smooth surface and ensure the integrity of the protective layer 136 on the sidewall 110b.

As shown in FIGS. 17A to 17D , a plurality of contact plugs 162 and 164 are respectively arranged on the substrate 100 between a plurality of first stack structures 110 . In this embodiment, the contact plug 162 can be regarded as a source contact plug, and the contact plug 164 can be regarded as a drain contact plug. In one embodiment, the contact plug 162 may be strip-shaped in the plan view direction of the memory element 10 and extend along the second direction D2. In another embodiment, the contact plugs 164 may be island-shaped in the plan view direction of the memory element 10 and alternately arranged along the second direction D2. In this embodiment, the top surfaces 162 a of the contact plugs 162 , the top surfaces 164 a of the contact plugs 164 , and the top surface 110 a of the first stacked structure 110 are substantially coplanar with each other.

To sum up, the width of the charge storage structure of the present invention along the first direction, the width of the control gate along the first direction and the width of the top capping layer along the first direction are substantially equal to each other, so that the first stacked structure Having substantially smooth sidewalls can prevent the protective layer from being damaged by etching processes and maintain its integrity to further improve reliability. On the other hand, in the manufacturing method of the present invention, the hard mask layer of the first stacked structure can be used as a grinding buffer layer, so the dummy source contact plugs can be directly isolated through the planarization process, and only subsequent patterning is required. The process can be modified to form a virtual drain contact plug.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10:Memory component 100:Base 100a: Surface 101: Isolation structure 102:Array area 104: Surrounding area 106: Tunneling dielectric layer 110: First stack structure 110a, 120a, 138a, 150a, 152a, 160a: top surface 110b, 120b: side wall 112:Charge storage structure 114:Dielectric layer 116, 140: Hard curtain layer 120: Second stack structure 122: Gate electrode 124:Dielectric layer 130, 131, 132, 133: gap wall layer 131A, 132A, 133A: Spacer material layer 136:Protective layer 136a, 156a: highest top surface 138: Conductor layer 142: Gap wall 144:Silicide layer 146: Lining 148, 150, 158, 160: Oxide layer 152: Conductor strip 154: Conductor post 156:Nitride layer 162, 164: Contact plug AA: active area BL: barrier layer CG: control gate CL: top cover D1: first direction D2: second direction PR:Cover pattern OP1: First opening OP2: Second opening OP3: The third opening OP4: The fourth opening

Figure 1A, Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 11D, Figure 12A, Figure 12D, Figure 13A, Figure 13C, Figure 14A 14C, 15A, 15C, 16A, 16C, 17A and 17C are cross-sectional schematic diagrams of the manufacturing process of the array area of the memory element according to an embodiment of the present invention. Figure 1B, Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 11E, Figure 12B, Figure 12E, Figure 13B, Figure 13D, Figure 14B 14D, 15B, 15D, 16B, 16D, 17B and 17D are schematic cross-sectional views of the manufacturing process of the peripheral area of the memory element according to an embodiment of the present invention. 1C, 11C and 12C are schematic top views of FIGS. 1A, 11A and 12A respectively.

10:Memory component

100:Base

100a: Surface

102:Array area

106: Tunneling dielectric layer

110: First stack structure

110a:Top surface

110b:Side wall

112:Charge storage structure

114:Dielectric layer

116:Hard curtain layer

131, 132, 133: gap wall layer

136:Protective layer

156:Nitride layer

160:Oxide layer

162:Contact plug

BL: barrier layer

CG: control gate

CL: top cover

D1: first direction

OP2: Second opening

OP3: The third opening

Claims (10)

A memory element including: A plurality of stacked structures are arranged on the array area of the substrate along a first direction, and each stacked structure extends along a second direction different from the first direction. In the cross-sectional view of the memory element, each stacked structure One of the stacked structures includes a charge storage structure, a control gate and a top cover layer in sequence from the base, and the top cover layer has a multi-layer structure; and a protective layer covering the side walls of the stacked structure, The width of the charge storage structure along the first direction, the width of the control gate along the first direction, and the width of the capping layer along the first direction are substantially equal to each other. The memory element of claim 1, wherein the top cover layer includes a dielectric layer and a hard mask layer, the dielectric layer is disposed between the control gate and the hard mask layer, and the The width of the dielectric layer along the first direction is substantially equal to the width of the hard mask layer along the first direction. The memory element according to claim 2, wherein the material of the hard mask layer is silicon nitride. The memory component as described in claim 1 further includes: A plurality of contact plugs are respectively arranged on the base between the plurality of stacked structures, and the top surface of the contact plugs relative to the base and the top surface of the stacked structure relative to the base The top surfaces are substantially coplanar. The memory element of claim 4, wherein the plurality of contact plugs include: A plurality of source contact plugs, the plurality of source contact plugs are strip-shaped in the plan view direction of the memory element and extend along the second direction; and A plurality of drain contact plugs are island-shaped in a plan view direction of the memory element and are alternately arranged along the second direction. A method of manufacturing a memory element, including: A plurality of stacked structures are formed on the base of the array area, the plurality of stacked structures are arranged along a first direction, and each stacked structure extends along a second direction different from the first direction, in the In the cross-sectional view of the memory element, each of the stacked structures includes a charge storage structure, a control gate and a top cover layer in sequence from the base, and the top cover layer has a multi-layer structure, wherein the charge storage structure is along the The width in the first direction, the width of the control gate along the first direction, and the width of the top cover layer along the first direction are substantially equal to each other; forming a protective layer on the side walls of the stacked structure; forming a conductor layer on the substrate to fill the space between the plurality of stacked structures; Perform a planarization process to form multiple conductor strips; Patterning at least one of the conductor strips to form a plurality of conductor posts; and An alternative process is performed to replace the plurality of conductor strips and the plurality of conductor posts with a plurality of contact plugs. The method of manufacturing a memory element according to claim 6, wherein the top cover layer includes a dielectric layer and a hard mask layer, and the dielectric layer is disposed between the control gate and the hard mask layer. , and the width of the dielectric layer along the first direction is substantially equal to the width of the hard mask layer along the first direction. The method of manufacturing a memory element according to claim 7, wherein the material of the hard mask layer is silicon nitride. The method of manufacturing a memory element according to claim 6, wherein a top surface of the contact plug relative to the base and a top surface of the stacked structure relative to the base are substantially coplanar. The manufacturing method of memory element according to claim 6, wherein the alternative process includes: removing the plurality of conductor strips and the plurality of conductor posts to respectively form a plurality of openings between the plurality of stacked structures, wherein the plurality of openings expose the substrate; and Conductor material is filled into the plurality of openings to form the plurality of contact plugs.

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